RT8855 4/3/2/1-Phase PWM Controller for AMD AM2/AM2+ CPUs General Description Features The RT8855 is a 4/3/2/1-phase synchronous buck controller with two integrated MOSFET drivers for CPU power application and a single-phase buck with integrated MOSFET driver for North-Bridge (NB) chipset.The RT8855 uses differential inductor DCR current sense to achieve phase current balance and active voltage positioning. Other features include adjustable operating frequency, power good indication, external error-amp compensation, over voltage protection, over current protection and enable/ shutdown for various applications. The RT8855 comes to a small footprint with WQFN-48L 7x7 package. z 12V Power Supply Voltage z 4/3/2/1-Phase Power Conversion for VCORE Power 3 Embedded MOSFET Drivers (2 for CPU and 1 for NB) Internal Regulated 5V Output Support AMD AM2 6-bit Parallel and AM2+ 7-bit Serial VID Tables Continuous Differential Inductor DCR Current Sense Adjustable Frequency (Typically at 300kHz) Selectable 1 or 2 Phase in Power-Saving (PS) Mode Phase-Interleaving for VCORE and NB Controller Power Good Indication Adjustable Over Current Protection Over Voltage Protection Small 48-Lead WQFN Package RoHS Compliant and Halogen Free z z z z z z z z z z z Pin Configurations Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. UGATE_NB PHASE_NB LGATE_NB VID5 Note : PGOOD EN Lead Plating System G : Green (Halogen Free and Pb Free) VCC12_NB (TOP VIEW) Package Type QW : WQFN-48L 7x7 (W-Type) VID0/VFIXEN RT8855 VID1/PVI Ordering Information VID2/SVD z Desktop CPU Core Power Low Voltage, High Current DC/ DC Converter VID3/SVC z z VID4 Applications 48 47 46 45 44 43 42 41 40 39 38 37 PWROK RT FBRTN FBRTN_NB FB_NB COMP_NB ISP_NB ISN_NB ADJ OFS COMP FB 1 36 2 35 3 34 4 33 5 32 31 6 GND 7 30 8 29 9 28 10 27 49 26 11 25 12 BOOT_NB BOOT1 UGATE1 PHASE1 LGATE1 VCC12 LGATE2 PHASE2 UGATE2 BOOT2 PWM3 PWM4 VCC5 PS ISP4 ISN4 ISN3 ISP3 ISN2 ISP2 ISP1 ISN1 IMAX IMAX_NB 13 14 15 16 17 18 19 20 21 22 23 24 WQFN-48L 7x7 DS8855-01 April 2011 www.richtek.com 1 www.richtek.com 2 L2 L2 12V 12V BOOT VCC 12V PWM GND PWM GND VCC ROFS LGATE RT9619 PHASE UGATE BOOT LGATE RT9619 PHASE UGATE ISP4 PWM4 EN 13 IMAX_NB PWROK 47 PGOOD 2 RT 14 IMAX 1 48 VID[5:0] 21 ISN4 10 OFS 22 25 46 to 41 12V PWM3 20 ISP3 19 ISN3 26 VCC5 33 23 18 FBRTN 3 17 ISN2 FB 12 11 COMP ISP2 PHASE2 29 30 LGATE2 BOOT2 27 UGATE2 28 PS ISP1 16 15 ISN1 LGATE1 32 PHASE1 BOOT1 35 UGATE1 34 COMP_NB 6 4 FBRTN_NB ISP_NB 7 8 ISN_NB FB_NB 5 PHASE_NB 38 LGATE_NB 39 BOOT_NB 36 UGATE_NB 37 40 VCC12_NB 12V 24 31 VCC12 12V 9 ADJ RT8855 12V 12V 12V L2 L2 L1 NTC LOAD LOAD RT8855 Typical Application Circuit DS8855-01 April 2011 RT8855 Table 1. 7-bit VID Code Table for AM2+ CPU (Serial) SVID[6:0] Voltage SVID[6:0] Voltage SVID[6:0] Voltage SVID[6:0] Voltage 0000000 1.5500 0100000 1.1500 1000000 0.7500 1100000 0.3500 0000001 1.5375 0100001 1.1375 1000001 0.7375 1100001 0.3375 0000010 1.5250 0100010 1.1250 1000010 0.7250 1100010 0.3250 0000011 1.5125 0100011 1.1125 1000011 0.7125 1100011 0.3125 0000100 1.5000 0100100 1.1000 1000100 0.7000 1100100 0.3000 0000101 1.4875 0100101 1.0875 1000101 0.6875 1100101 0.2875 0000110 1.4750 0100110 1.0750 1000110 0.6750 1100110 0.2750 0000111 1.4625 0100111 1.0625 1000111 0.6625 1100111 0.2625 0001000 1.4500 0101000 1.0500 1001000 0.6500 1101000 0.2500 0001001 1.4375 0101001 1.0375 1001001 0.6375 1101001 0.2375 0001010 1.4250 0101010 1.0250 1001010 0.6250 1101010 0.2250 0001011 1.4125 0101011 1.0125 1001011 0.6125 1101011 0.2125 0001100 1.4000 0101100 1.0000 1001100 0.6000 1101100 0.2000 0001101 1.3875 0101101 0.9875 1001101 0.5875 1101101 0.1875 0001110 1.3750 0101110 0.9750 1001110 0.5750 1101110 0.1750 0001111 1.3625 0101111 0.9625 1001111 0.5625 1101111 0.1625 0010000 1.3500 0110000 0.9500 1010000 0.5500 1110000 0.1500 0010001 1.3375 0110001 0.9375 1010001 0.5375 1110001 0.1375 0010010 1.3250 0110010 0.9250 1010010 0.5250 1110010 0.1250 0010011 1.3125 0110011 0.9125 1010011 0.5125 1110011 0.1125 0010100 1.3000 0110100 0.9000 1010100 0.5000 1110100 0.1000 0010101 1.2875 0110101 0.8875 1010101 0.4875 1110101 0.0875 0010110 1.2750 0110110 0.8750 1010110 0.4750 1110110 0.0750 0010111 1.2625 0110111 0.8625 1010111 0.4625 1110111 0.0675 0011000 1.2500 0111000 0.8500 1011000 0.4500 1111000 0.0500 0011001 1.2375 0111001 0.8375 1011001 0.4375 1111001 0.0375 0011010 1.2250 0111010 0.8250 1011010 0.4250 1111010 0.0250 0011011 1.2125 0111011 0.8125 1011011 0.4125 1111011 0.0125 0011100 1.2000 0111100 0.8000 1011100 0.4000 1111100 OFF 0011101 1.1875 0111101 0.7875 1011101 0.3875 1111101 OFF 0011110 1.1750 0111110 0.7750 1011110 0.3750 1111110 OFF 0011111 1.1625 0111111 0.7625 1011111 0.3625 1111111 OFF DS8855-01 April 2011 www.richtek.com 3 RT8855 Table 2. 6-bit VID Code Table for AM2 CPU (Parallel) VID[5:0] Voltage VID[5:0] Voltage VID[5:0] Voltage VID[5:0] Voltage 000000 1.5500 010000 1.1500 100000 0.7625 110000 0.5625 000001 1.5250 010001 1.1250 100001 0.7500 110001 0.5500 000010 1.5000 010010 1.1000 100010 0.7375 110010 0.5375 000011 1.4750 010011 1.0750 100011 0.7250 110011 0.5250 000100 1.4500 010100 1.0500 100100 0.7125 110100 0.5125 000101 1.4250 010101 1.0250 100101 0.7000 110101 0.5000 000110 1.4000 010110 1.0000 100110 0.6875 110110 0.4875 000111 1.3750 010111 0.9750 100111 0.6750 110111 0.4750 001000 1.3500 011000 0.9500 101000 0.6625 111000 0.4625 001001 1.3250 011001 0.9250 101001 0.6500 111001 0.4500 001010 1.3000 011010 0.9000 101010 0.6375 111010 0.4375 001011 1.2750 011011 0.8750 101011 0.6250 111011 0.4250 001100 1.2500 011100 0.8500 101100 0.6125 111100 0.4125 001101 1.2250 011101 0.8250 101101 0.6000 111101 0.4000 001110 1.2000 011110 0.8000 101110 0.5875 111110 0.3875 001111 1.1750 011111 0.7750 101111 0.5750 111111 0.3750 www.richtek.com 4 DS8855-01 April 2011 RT8855 Functional Pin Description Pin No. Pin Name Pin Function 1 PWROK PWROK Input Signal. 2 RT Connect this pin to GND by a resistor to adjust frequency. 3 FBRTN Remote sense ground for CORE. 4 FBRTN_NB Remote sense ground for NB. 5 FB_NB Inverting input of error-amp for NB. 6 COMP_NB Output of error-amp and input of PWM comparator for NB. 7 ISP_NB Positive current sense pin of NB 8 ISN_NB Negative current sense pin of NB 9 ADJ 10 OFS 11 COMP 12 FB Output of error-amp and input of PWM comparator of V CORE . Inverting input of error-amp of V CORE. 13 IMAX_NB Connect this pin to GND by a resistor to set OCP of NB. 14 IMAX Connect this pin to GND by a resistor to set OCP of VCORE. Connect this pin to GND by a resistor to set load line of VCORE. Connect this pin to GND/5VCC by a resistor to set no-load offset voltage of V CORE. 15, 17, 19, 21 ISN1, ISN2, ISN3, ISN4 Negative current sense pin of channel 1, 2, 3 and 4. 16, 18, 20, 22 ISP1, ISP2, ISP3, ISP4 Positive current sense pin of channel 1, 2, 3 and 4. 23 24 25,26 PS VCC5 Power Saving Mode Selection Pin. Output of internal 5V regulator for control circuits power supply. Connect this pin to GND by a ceramic capacitor larger than 1uF. PWM4, PWM3 PWM output for channel 4 and channel 3. 27, 35, 36 BOOT2, BOOT1, BOOT_NB Bootstrap supply for channel 2 and channel 1 and NB. 28, 34, 37 UGATE2, UGATE1, UGATE_NB Upper gate driver for channel 2 and channel 1 and NB. 29, 33, 38 PHASE2, PHASE1, PHASE_NB Switching node of channel 2 and channel 1 and NB. 30, 32, 39 31, 40 LGATE2, LGATE1, LGATE_NB Lower gate driver for channel 2 and channel 1 and NB. VCC12, VCC12_NB IC power supply. Connect this pin to 12V. PVI Mode : Used as voltage identification input for DAC. SVI Mode : Functions as VFIXEN selection input. This pin selects PVI/SVI mode based on the state of this pin prior to EN signal. PVI Mode : Used as voltage identification input for DAC. PVI Mode : Used as voltage identification input for DAC. 41 VID0/VFIXEN 42 VID1/PVI 43 VID2/SVD 44 VID3/SVC 45, 46 VID4, VID5 PVI Mode : Used as voltage identification input for DAC. 47 PGOOD Power Good Indicator (open drain). 48 EN Enable Input Signal. Reference Ground for the IC. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Exposed pad GND (49) DS8855-01 April 2011 SVI Mode : Serial data input. PVI Mode : Used as voltage identification input for DAC. SVI Mode : Serial clock input. www.richtek.com 5 RT8855 Function Block Diagram RAMP_NB Modulator Waveform Generator RT VCC12 Power-On Reset POR 5V Regulator COMP VCC5 EA + FB BOOT1 Offset OFS UGATE1 MOSFET Driver + - PHASE1 LGATE1 + - OV + 1.8V BOOT2 + MOSFET Driver - UGATE2 PHASE2 Transient Response Enhancement LGATE2 + PWM3 - OV OC VIDOFF POR PGOOD PWROK EN Soft Start and Fault Logic CH3_EN Detector + - PWM4 CH4_EN Detector + PS - I_SEN1 + + 1.25V FBRTN_NB + VID Table Generator I_SEN2 + VID5 to VID0 FBRTN - - - - I_SEN3 + OC Detection OC + OC_NB Detection IMAX_NB CH2 Current SENSE ISP1 ISN1 ISP2 ISN2 AVG ADJ IMAX CH1 Current SENSE I_SEN4 OC_NB I_SENNB Transient Response Enhancement CH3 Current SENSE ISP3 ISN3 CH4 Current SENSE ISP4 NB Current SENSE ISP_NB ISN4 ISN_NB VCC12_NB COMP_NB BOOT_NB FB_NB + + - EA + OV_NB + RAMP_NB - MOSFET Driver UGATE_NB PHASE_NB LGATE_NB 1.8V www.richtek.com 6 DS8855-01 April 2011 RT8855 Absolute Maximum Ratings z z z z z z z z z z z (Note 1) Supply Input Voltage ---------------------------------------------------------------------------------------------------BOOTx to PHASEx ----------------------------------------------------------------------------------------------------BOOTx to GND DC --------------------------------------------------------------------------------------------------------------------------<200ns --------------------------------------------------------------------------------------------------------------------PHASEx to GND DC --------------------------------------------------------------------------------------------------------------------------<200ns --------------------------------------------------------------------------------------------------------------------Input/Output Voltage or I/O Voltage ---------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WQFN−48L 7x7 ---------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-48L 7x7, θJA ----------------------------------------------------------------------------------------------------Junction Temperature --------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) --------------------------------------------------------------------------------------------MM (Machine Mode) ---------------------------------------------------------------------------------------------------- Recommended Operating Conditions z z z −0.3V to 15V −0.3V to 15V −0.3V to 30V −0.3V to 42V −2V to 15V −5V to 30V −0.3V to 7V 3.226W 31°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Voltage, VCC12 ------------------------------------------------------------------------------------------------ 12V ± 10% Junction Temperature Range ------------------------------------------------------------------------------------------ −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------------ 0°C to 70°C Electrical Characteristics (VCC12 = 12V, GND = 0V, TA = 25°C, unless otherwise specified) Parameter Min Typ Max Unit V VCC12 IVCC12 10.8 -- 12 10 13.2 -- V mA VCC12_NB Supply Voltage V VCC12_NB 10.8 12 13.2 V VCC12_NB Supply Current IVCC12_NB -- 5 -- mA VCC Supply Input VCC12 Supply Voltage VCC12 Supply Current Symbol Test Conditions VCC5 Power VCC5 Supply Voltage VCC5 Output Sourcing V VCC5 IVCC5 ILOAD = 10mA 4.9 10 5 -- 5.1 -- V mA VCC12 Rising Threshold V VCC12TH VCC12 Rising 9.2 9.6 10 V VCC12 Hysteresis Input Threshold V VCC12HY VCC12 Falling -- 0.9 -- V Enable Input High Threshold Enable Input Low Threshold V ENHI V ENLO EN Rising EN Falling 2 -- --- -0.8 V V Power-On Reset To be continued DS8855-01 April 2011 www.richtek.com 7 RT8855 Parameter Symbol PWROK Input High Threshold V POKHI Test Conditions PWROK Rising Min 2 Typ -- Max -- Unit V PWROK Input Low Threshold V POKLO VID5 to VID0 Rising Threshold V VID 5 to 0 PWROK Falling VID5 to VID0 Rising -0.75 -0.8 0.8 0.85 V V VID5 to VID0 Hysteresis V VID5 to 0 HYS VID5 to VID0 Pull-Down IVID5 to 0 Current Reference Voltage accuracy VID5 to VID0 Falling -- 25 -- mV VVID5 to 0 = 1.5V -- 16 30 uA 1V to 1.55V −0.5 -- +0.5 % 0.8V to 1V −8 -- +8 mV 0.5V to 0.8V −10 -- +10 mV DAC Accuracy Error Amplifier DC Gain A DC No Load -- 80 -- dB Gain-Bandwidth GBW CLOAD = 10pF -- 10 -- MHz Slew Rate SR CLOAD = 10pF 10 -- -- V/us Output Voltage Range V COMP RLOAD = 47kΩ 0.5 -- 3.6 V Over-Voltage Threshold V PGOOD-OV FB Rising VDAC VDAC VDAC +210mV +240mV +270mV V Under-Voltage Threshold V PGOOD-UV FB Falling VDAC VDAC VDAC −330mV −300mV −270mV V Over-Voltage Threshold_NB V PGOOD-OV_NB FB_NB Rising VDAC VDAC VDAC +210mV +240mV +270mV V Under-Voltage Threshold_NB V PGOOD-UV_NB FB_NB Falling Power Good Low Voltage V PGOOD IPGOOD = 4mA Power Good VDAC VDAC VDAC −330mV −300mV −270mV V -- -- 0.4 V 100 -- -- uA −2 0 +2 mV 270 300 330 kHz -- 1.6 -- V Current Sense Amplifier Max Current IGMMAX Input Offset Voltage V OSCS VCSP = 1.3V Sink Current from CSN Oscillator Running Frequency fOSC Ramp Amplitude V RAMP RRT = 40kΩ Soft Start Soft Start Slew Rate SRSS Slew Rate 2.5 3.25 4 mV/us VID change Slew Rate SRVID Slew Rate 2.5 3.25 4 mV/us V OVP Sweep FB Voltage 1.7 1.8 1.9 V V OVP_NB Sweep FB_NB Voltage 1.7 1.8 1.9 V Protection Over-Voltage Threshold To be continued www.richtek.com 8 DS8855-01 April 2011 RT8855 Parameter Symbol Test Conditions Min Typ Max Unit IOCP RIMAX = 40kΩ 68 80 92 uA VIMAX RIMAX = 40kΩ 1.44 1.6 1.76 V IOCP_NB RIMAX_NB = 40kΩ 68 80 92 uA VIMAX_NB RIMAX_NB = 40kΩ 1.44 1.6 1.76 V UGATE Drive Source RUGATEsr BOOT − PHASE = 8V 250mA Source Current -- 1 -- Ω UGATE Drive Sink RUGATEsk BOOT − PHASE = 8V 250mA Sink Current -- 1 -- Ω LGATE Drive Source RLGATEsr VLGATE = 8V -- 1 -- Ω LGATE Drive Sink RLGATEsk 250mA Sink Current -- 0.9 -- Ω Over-Current Threshold Gate Driver Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a effective single layer thermal conductivity test board of JEDEC thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8855-01 April 2011 www.richtek.com 9 RT8855 Application Information The RT8855 is a dual output PWM controller supports hybrid power control of AMD processors which operate from either a 6-bit parallel VID interface (PVI) or a serial VID interface (SVI). One of the outputs is a 4/3/2/1-phase PWM controller with two integrated MOSFET drivers to support CPU core voltage (VDD) and another is a singlephase buck controller with an integrated MOSFET driver to power North-Bridge (NB) chipset (VDDNB) in SVI mode. In PVI mode, only multiphase PWM controller is active for single-plane VDD only processor. Richtek's proprietary Burst Transient Response(BTRTM), provides fastest initial response to high di/dt load transients and less bulk and ceramic output capacitance is required to meet transient regulation specifications. The RT8855 incorporates differential voltage sensing, continuous inductor DCR phase current sensing, programmable loadline voltage positioning and offset voltage to provide high accuracy regulated power for both VDD and VDDNB. While VDDNB is enabled in SVI mode, it will be automatically phase-shifted with respect to the CPU Core phases in order to reduce the total input RMS current amount. CPU_TYPE Detection and System Start-Up At system Start-up, on the rising-edge of EN signal, RT8855 monitors the status of VID1 and latches the PVI mode (VID1 = 1) or SVI mode (VID1 = 0). PVI Mode PVI is a 6-bit-wide parallel interface used to address the CPU Core section reference. According to the selected code, the device sets the Core section reference and regulates its output voltage according to Table 2. In this mode, NB section is kept in high impedance. Furthermore, PWROK information is ignored as well since the signal only applies to the SVI protocol. SVI Mode Figure1. SVI interface also consider two additional signals needed to manage the system start-up. These signals are EN and PWROK. The device asserts a PGOOD signal if the output voltages are in regulation. Start Slave Addressing + W 6 SVC 5 4 3 ACK 0 Data Phase 7 6 ACK SVD ACK Stop 0 ACK 110b Start Slave Addressing (7 Clocks) BUS Driven by RT8855 Write ACK (1Ck) (1Ck) Data Phase (8 Clocks) ACK (1Ck) Stop BUS Driven by Master (CPU) Figure 1. SVI Communication-Send Byte Set VID Command The Set VID Command is defined as the command sequence that the CPU issues on the SVI bus to modify the voltage level of the Core section and NB section, as shown is Figure 1. During a Set VID Command, the processor sends the start (Start) sequence followed by the address of the Section which the Set VID Command applies. The processor then sends the write (WRITE) bit. After the write bit, The Voltage Regulator (VR) sends the acknowledge (ACK) bit. The processor then sends the VID bits code during the data phase. The VR sends the acknowledge (ACK) bit after the data phase. Finally, the processor sends the stop (Stop) sequence. After the VR has detected the stop, it performs an On-the-Fly VID transition for the addressed section(s). Refer to Table 3 for the details of SVI send byte. RT8855 is able to manage individual power off for both VCORE and NB sections. The CPU may issue a serial VID command to power off or power on one section while the other one remains powered. In this case, the PGOOD signal remains asserted. SVI is a two wire, Clock and Data, bus that connect a single master (CPU) to one slave (RT8855). The master initiates and terminates SVI transactions and drives the clock, SVC, and the data, SVD, during a transaction. The slave receives the SVI transactions and acts accordingly. SVI wire protocol is based on fast-mode I2C as shown in www.richtek.com 10 DS8855-01 April 2011 RT8855 Table 3. SVI Send Byte-Address and Data Phase Description / Example bits Description Address Phase 6 : 4 Always 110b 3 Not Applicable, ignored. 2 Not Applicable, ignored. CORE Section. (Note) 1 If set then the following data byte contains the VID code for CORE Section. NB Section. (Note) 0 If set then the following data byte contains the VID code for NB Section. Data Phase PSI_L Flag (Active Low). When asserted, the 7 VR is allowed to enter Power-Saving Mode. 6 : 0 VID Code. Note : Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously. Example : SVI Address Bits [6 : 0] 1100_000 1100_001 1100_110 1100_100 1100_010 1100_111 Table 4. V_FIX Mode and Pre-PWROK Metal VID Output Voltage (V) SVC SVD Pre-PWROK Metal VID V_FIX Mode 0 0 1.1V 1.4V 0 1 1.0V 1.2V 1 0 0.9V 1.0V 1 1 0.8V 0.8V Power Ready Detection During start-up, RT8855 will detect VCC12, VCC5 and EN signal. Figure 2 shows the power ready detection circuit. When VCC12 > 9.6V and VCC5 > 4.6V, POR (Power On Reset) will go high. POR is the internal signal to indicate all input powers are ready to let RT8855 and the companioned MOSFET drivers to work properly. When POR = L, RT8855 will turn off both high side and low side MOSFETs. Description Should be ignored. Set VID on VDDNB. Set VID on VDD0 and VDD1. Set VID on VDD1. Set VID on VDD0 or VDD (uniplane). Set VID on VDDNB, VDD0 and VDD1. PWROK De-assertion PWROK stays low after EN signal is asserted, and the controller regulates all the planes according to the PrePWROK Metal VID. PGOOD is de-asserted as long as Pre-PWROK Metal VID voltage is out of the initial voltage specifications. V_FIX Mode Function Anytime the pin VID0/VFIXEN is pulled high, the controller enters V-FIX mode. When in V_FIX mode, both VCORE and NB section voltages are governed by the information shown in Table 4. Regardless of the state of PWROK, the device will work in SVI mode. SVC and SVD are considered as static VID and the output voltage will be changed according to their status. Dynamic SVC/SVD-change management is provided in this condition. V_FIX mode is intended for system debug only. DS8855-01 April 2011 VCC12 9.6V VCC5 + - + 4.6V CMP CMP POR - Chip Enable EN Figure 2. Circuit for Power Ready Detection Power-Up Sequencing Figure 3 and 4 are the power-up sequencing diagram of RT8855. Once power_on_reset is valid (POR = H), on the rising edge of the EN signal, the RT8855 detects the VID1 pin and determine to operate either in SVI or PVI mode. Figure3 shows the PVI-mode power sequence, the controller stays in T1 state waiting for valid parallel VID code sent by CPU. After receiving valid parallel VID code, VCORE continues ramping up to the specified voltage according to the VID code in T2 state. Figure 4 shows the SVI-mode power sequence, the controller samples the two serial VID pins, SVC and SVD. Then, the controller stores this value as the boot VID that is the so-called “Pre-PWROK Metal VID” in T1 state. After the processor starts with boot VID voltages, PWROK is asserted and the processor initializes the serial VID interface in T2 state. The processor uses the serial VID interface to issue VID commands to move the power planes from the boot VID values to the dual power planes in T3 state. www.richtek.com 11 RT8855 VCC12 9.6V VCC5 4.6V 8.7V POR EN VID(1)/PVI xx PVI mode (6-bits) L DCR RS CS 4.2V CSA: Current Sense Amplifier xx Valid V OFS_CSA IX ISP R CSP ISN R CSN + 235nA + - 235nA VDD PGOOD PWROK T2 Figure 5. Current Sensing Circuit. T1 CORE Section- Phase Detection Figure 3. PVI-Mode Power-sequencing Diagram VCC12 9.6V VCC5 4.6V 8.7V 4.2V POR EN VID(1)/PVI xx SVC SVD xx Valid xx Valid Vboot VDD or VDDNB PGOOD PWROK T1 T2 T3 Figure 4. SVI-Mode Power-sequencing Diagram CORE Section- Output Current Sensing The RT8855 provides a low input offset current-sense amplifier (CSA) to monitor the continuous output current of each phase for VCORE. Output current of CSA (IX[n]) is used for current balance and active voltage position as shown in Figure 5. In this inductor current sensing topology, RS and CS must be set according to the equation below : The number of the operational phases is determined by the internal circuitry that monitors the ISNx voltages during start up. Normally, the RT8855 operates as a 4-phase PWM controller. Pull ISN4 and ISP4 to 5VCC programs 3-phase operation, pull ISN3 and ISP3 to 5VCC programs 2-phase operation, and pull ISN2 and ISP2 to 5VCC programs 1-phase operation. RT8855 detects the voltage of ISN4, ISN3 and ISN2 at rising edge of POR. At the rising edge, RT8855 detects whether the voltage of ISN4, ISN3 and ISN2 are higher than “VCC5-1V” respectively to decide how many phases should be active. Phase detection is only active during start up. Once POR = high, the number of operational phases is determined and latched. CORE Section- Switching Frequency Connect a resistor (RT) from the RT pin to GND can program the switching frequency of each phase. Figure 6 shows the relationship between the resistance and switching frequency. Frequency vs. RRT 1200 L = R ×C S S DCR IX = [IL × DCR − VOFS-CSA + 235nA × (RCSP − RCSN )] RCSN 235nA is the typical value of the CSA input offset current. VOFS-CSA is the input offset. Usually, “VOFS-CSA + 235nA x (RCSP − RCSN)” is negligible except at very light load and the equation can be simplified as the equation below : IX = IL × DCR RCSN www.richtek.com 12 Frequency (kHz) Then the output current of CSA will follow the equation below : 1000 800 600 400 200 0 0 40 80 120 160 200 240 280 RRT (k ohm) (kΩ) Figure 6. RRT vs. Phase switching Frequency. DS8855-01 April 2011 RT8855 CORE Section- Differential Output Voltage Sensing The RT8855 uses differential voltage sensing by a high gain low offset ErrorAmp as shown in Figure 7. Connect the negative on-die CPU remote sense pin to FBRTN. Connect the positive on-die remote sense pin to FB with a resistor (R FB ) The ErrorAmp compares EAP ( = VDAC − VADJ) with the VFB to regulate the output voltage. C2 CFB RFB VCCP (Positive remote sense pin of CPU) R1 C1 IOFSN FB + EA COMP IOFSP + (Negative remote sense pin of CPU) VCCN RADJ VDAC +- EAP VOFSP = IOFSP × RFB − 9u × R ADJ R = 0.4 × FB − 9u × R ADJ ROFS CORE Section- Programmable Load-line Output current of CSA is summed and averaged in RT8855. Then 0.5Σ (IX[n]) is sent to ADJ pin. Because Σ IX[n] is a PTC (Positive Temperature Coefficient) current, an NTC (Negative Temperature Coefficient) resistor is needed to connect ADJ pin to GND. If the NTC resistor is properly selected to compensate the temperature coefficient of I X[n], the voltage on ADJ pin will be proportional to IOUT without temperature effect. In RT8855, the positive input of ErrorAmp is “VDAC − VADJ” . VOUT will follow “VDAC − VADJ” , too. Thus, the output voltage decreasing linearly with IOUT is obtained. The loadline is defined as : LL(loadline) = ΔVOUT ΔVADJ 1 R = = × DCR × ADJ ΔIOUT ΔIOUT 2 RCSN - FBRTN ADJ Figure 7. Circuit for VCORE Differential Sensing and No load Offest. CORE Section- No-Load Offset In Figure 7, IOFSP and IOFSN are used to generate no-load offset. Either IOFSP or IOFSN is active during normal operation. Connect a resistor from OFS pin to GND to activate IOFSN. IOFSN flows through RFB from FB pin to VCCP. In this case, negative no-load offset voltage (VOFSN) is generated. Connect a resistor from OFS pin to 5VCC to activate IOFSP. IOFSP flows through RFB from the VCCP to FB pin. In this case, positive no-load offset voltage (VOFSP) is generated. Beside IOFSN and IOFSP, the RT8855 generates another DC current for initial no-load negative offset. A DC current source will continuously inject typical 9uA current into the resistors connected to ADJ pin, Therefore, the effect of this 9uA current source and ADJ resistors should counted into the calculation of no-load offset : Briefly, the resistance of RADJ sets the resistance of loadline. The temperature coefficient of RADJ compensates the temperature effect of loadline. CORE Section- Load Transient Quick Response In steady state, the voltage of VFB is controlled to be very close to VEAP. While a load step transient from light load to heavy load could cause VFB lower than VEAP by several tens of mV. In prior design, owing to limited control bandwidth, controller is hard to prevent VOUT undershoot during quick load transient from light load to heavy load. RT8855 buit in proprietary Burst Transient Response (BTRTM ) technology, that detects load transient by comparing VFB and VEAP. If VFB suddenly drops below “VEAP − VOR” , VQR is a predetermined voltage. The quick response indicator QR rises up. When QR = high, RT8855 turns on all high side MOSFETs and turn off all low side MOSFETs. The sensitivity of quick response can be adjusted by the values of CFB and RFB. Smaller RFB and/ or larger CFB will make QR easier to be trigger. Figure8 is the circuit and typical waveforms. VOFSN = IOFSN × RFB + 9u × R ADJ R = 0.4 × FB + 9u × R ADJ ROFS DS8855-01 April 2011 www.richtek.com 13 RT8855 VOUT CFB C2 RFB R1 C1 IOUT VOUT I1 FB FB COMP I2 - - + + QR FB = VEAP = VEAP - VQR EAP = VDAC - VADJ EAP - VQR IOUT, total Constant ratio QR Figure 8. Load Transient Quick Response I1 CORE Section- Current Balance In Figure9, IX[n] is the current signal which is proportional to the current flowing through channel n. The current error signals IERR[n] ( = IX[n] − AVG(IX[n])) are used to raise or lower the valley of internal sawtooth waveforms (EAMP[1] to RAMP[n]) which are compared with ErrorAmp output (COMP) to generate PWM signal. To raise the vally of sawtooth waveform will decrease the PWM duty of the corresponding channel while to lower the sawtooth waveform valley will increase the PWM duty. Eventually, current flowing through each channel will be balanced. I2 IOUT, total Constant difference Figure 10. Category of Phase Current Imbalance CORE Section-Over Current Protection (OCP) V IN ILX HS L X PWM Controller COMP LS DCR X RX CX OCP Comparator RAMP[n] - PWM[1] - + CMP - BUF PWM[n] 1.6V + - If phase current is not balanced due to asymmetric PCB layout of power stage, external resistors can be adjusted to correct current imbalance. Figure10 shows two types of current imbalance, constant ratio type and constant difference type. If the initial current distribution is constant ratio type, according to Equation (3), reducing RCSN[1] can reduce IL[1] and improve current balance. If the initial current distribution is the constant difference type, according to Equation (2), increasing RCSP[1] can reduce IL[1] and improve current balance. 8 + GM - R CSNX IIMAX IX RT8855 CORE section R IMAX Figure 9. Circuit Channel Current Balance CORE Section- Phase Current Adjustment 4 V IMAX IERR [n] x R CB www.richtek.com 14 1/8IX 1/4IIMAX IERR [1] x R CB + + Interleaved + BUF - RAMP[1] + CMP - Figure 11. Over Current Protection for CORE section. CORE section uses an external resistor RIMAX connected to IMAX pin to generate a reference current IMAX for over current protection as depicted in Figure 11. IIMAX = VIMAX RIMAX where VIMAX is typical 1.6V. RT8855 senses each phase current IX and OCP comparator compares sensed average current with the reference current. Equivalently, the maximum phase average current ILX(MAX) is calculated as below : DS8855-01 April 2011 RT8855 1 ×I 1 IMAX = × IX(MAX) 4 8 V IX(MAX) = 2 × IIMAX = 2 × IMAX RIMAX R R V ILX(MAX) = IX(MAX) × CSNX = 2 × IMAX × CSNX DCR X RIMAX DCR X Once IX is larger than 2 x IIMAX, OCP of CORE section is triggered and latched. Then, RT8855 will turn off both high side MOSFET and low side MOSFET of all channels. A 100us delay is used in OCP detection circuit to prevent false trigger. Except the normal OCP function described above, there is another short-circuit-OCP function especially designed for short circuit protection. Since short circuit may cause catastrophic damage over a very short period, this shortcircuit-OCP should have a very short delay for triggering OCP latch. Also to prevent false trigger, the trigger level of short-circuit-OCP is designed 1.5 times of normal OCP level. Hence, the equation of short-circuit-OCP is : R V ILX(MAX), short = 1.5 x ILX(MAX) = 3 × IMAX × CSNX , RIMAX DCR X and the delay of short-curcuit-OCP is 20us. when shortcircuit-OCP is triggered, the RT8855 will turn off both high side MOSFET and low side MOSFET of all channels. CORE Section- Over Voltage Protection (OVP) The over voltage protection monitors the output voltage via the FB pin. Once VFB exceeds 1.8V, OVP is triggered and latched for VCORE section. RT8855 will try to turn on each low side MOSFET and turn off each high side MOSFET to protect CPU. NB Section- Output Current Sensing The RT8855 provides low input offset current-sense amplifier (CSA) to monitor the continuous output current of NB scetion. Output current of CSA (IX_NB) is used for over current detection as shown in Figure 12. In this inductor current sensing topology, RS_NB and CS_NB must be set according to the equation below : LNB = RS_NB × CS_NB DCRNB Then the output current of CSA will follow the equation below : IL_NB × DCRNB IX_NB = RCSN_NB DS8855-01 April 2011 L NB R S_NB DCR NB C S_NB CSA: Current Sense Amplifier IX_NB + R CSN_NB - Figure 12. Current Sensing Circuit for NB Section NB Section- Over Current Protection (OCP) NB section uses an external resistor RIMAX_NB connected to IMAX_NB pin to generate a reference current IMAX_NB for over current protection as depicted in Figure 13. IIMAX_NB = VIMAX_NB RIMAX_NB where VIMAX_NB is typical 1.6V. OCP comparator compares the sensed phase current IX_NB with the reference current. Equivalently, the maximum phase NB current ILX_NB(MAX) is calculated as below : 1 ×I 1 IMAX_NB = × IX_NB 4 8 IX_NB = 2 × IIMAX_NB = 2 × VIMAX_NB RIMAX_NB RCSN_NB DCRNB VIMAX_NB RCSN_NB = 2× × RIMAX_NB DCRNB ILX_NB(MAX) = IX_NB × Once IX_NB is larger than 2 x IIMAX_NB, OCP of NB section is triggered and latched. Then, RT8855 will turn off both high side MOSFET and low side MOSFET of NB section. A 100us delay is used in OCP detection circuit to prevent false trigger. Except the normal OCP function described above, there is another short-circuit-OCP function especially designed for short circuit protection. Since short circuit may cause catastrophic damage over a very short period, this shortcircuit-OCP should have a very short delay for triggering OCP latch. Also to prevent false trigger, the trigger level of short-circuit-OCP is designed 1.5 times of normal OCP level of NB section. Hence, the equation of NB section short-circuit-OCP is : ILX_NB(MAX), short = 1.5 x ILX_NB(MAX) = 3× VIMAX_NB RCSN_NB × , RIMAX_NB DCRNB www.richtek.com 15 RT8855 and the delay of short-curcuit-OCP of NB section is 20us. When short-circuit-OCP is triggered at NB section, the RT8855 will turn off both high side MOSFET and low side MOSFET of NB section. 5VCC PSOC2P ILX L X_NB DCR NB PWM Controller - PSI (Active Low) + - + PS Control R X_NB C X_NB Figure 14. Power-Saving-Mode Circuit. 1/8IX_NB 1/4IIMAX_NB 1.6V PSIA PSI (From I2C) LS OCP Comparator VDDIO EN V IN HS (1) 5VCC for (4 phase to 2 phase) (2) 3.3V for (4 phase to 1 phase) Latch 4 + GM - 8 IIMAX_NB Table 5. PSI Strategy R CSN_NB IX_NB V IMAX_NB PS pin Pull-Up to 3.3V RT8855 NB section R IMAX_NB Pull-Up to 5V PSI Strategy Phase number is set to 1 while PSI is asserted. Phase number is set to 2 while PSI is asserted. Figure 13. Over Current Protection for NB section. PCB Layout Guideline NB Section- Over Voltage Protection (OVP) The over voltage protection monitors the output voltage via the FB_NB pin. Once VFB_NB exceeds 1.8V, OVP is triggered and latched for NB section. RT8855 will try to turn on low side MOSFET and turn off high side MOSFET to protect NB. Power Saving Indicator (PSI) This is an active-low flag that can be set by the CPU to allow the regulator to enter Power-Saving mode to maximize the system efficiency when in light-load conditions. The status of the flag is communicated to the controller through either the SVI bus or PS pin. RT8855 monitors the PS pin to define the PSI strategy that is the action performed by the controller when PSI is asserted. According Figure 14, by programming different voltage on PS pin, it configures the controller to operate in one or two phases condition when PSI is asserted. Pulling-up PS pin to 3.3V through a resistor, the controller operates in only 1 phase configuration. If the 3.3V is changed to 5V, RT8855 operates in 2 phase configuration. When PSI is de-asserted, the controller will return to the original configuration. The PSI strategy is summarized as shown in Table 5. www.richtek.com 16 Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The high-power switching power stage requires particular attention. Follow these guidelines for optimum PCB layout. Place the power components first, that includes power MOSFETs, input and output capacitors, and inductors. It is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. Symmetrical layout allows heat to be dissipated equally across all power trains. Great attention should be paid for routing the UGATE, LGATE, and PHASE traces since they drive the power train MOSFETs using short, high current pulses. It is important to size them as large and as short as possible to reduce their overall impedance and inductance. Extra care should be given to the LGATE traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibility of shoot-through. When placing the MOSFETs try to keep the source of the upper MOSFETs and the drain of the lower MOSFETs and as close as possible. Input Bulk capacitors should be placed close to the drain of the upper MOSFETs and and the source of the lower MOSFETs and . DS8855-01 April 2011 RT8855 Locate the output inductors and output capacitors between the MOSFETs and the load. Route high-speed switching nodes away from sensitive analog areas (ISP, ISN, FB, FBRTN, COMP, ADJ, OFS, IMAX.....) Keep the routing of the bootstrap capacitor short between BOOT and PHASE. Place the snubber R&C as close as possible to the lower MOSFETs of each phase. DS8855-01 April 2011 www.richtek.com 17 RT8855 Outline Dimension 2 1 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 6.950 7.050 0.274 0.278 D2 5.050 5.250 0.199 0.207 E 6.950 7.050 0.274 0.278 E2 5.050 5.250 0.199 0.207 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 48L QFN 7x7 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 18 DS8855-01 April 2011