Ordering number : ENA0755A STK672-600 Thick-Film Hybrid IC 2-phase Stepping Motor Driver Overview The STK672-600 is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control. Applications • Office photocopiers, printers, etc. Features • The motor speed can be controlled by the frequency of an external clock signal. • 2-phase excitation or 1-2 phase excitation is selected according to switching the state of the MODE1 pin (low or high). • The excitation mode is set at the rising edge of the clock signal when the MODE2 pin is high, or at the rising edge or falling edge when the MODE2 pin is low. • The phase is maintained even if the excitation mode is switched in the middle of operation. • The direction of rotation can be changed by applying a high or low signal to the CWB pin used to select the direction of rotation. • Supports schmitt input for 2.5V high level input. • Incorporating a current detection resistor (0.141Ω: resistor tolerance ±2%), motor current can be set using two external resistors. • Equipped with an ENABLE pin that, during clock input, allows motor output to be cut-off and resumed later while maintaining the same excitation timing. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 62911HKPC 018-08-0102/71608HKIM No. A0755-1/19 STK672-600 Specifications Absolute Maximum Ratings at Tc = 25°C Parameter Symbol Conditions Ratings unit Maximum supply voltage 1 VCC max No signal 52 V Maximum supply voltage 2 VDD max No signal -0.3 to +7.0 V Input voltage VIN max Logic input pins -0.3 to +7.0 V Output current IOH max VDD=5V, CLOCK≥200Hz 2.65 A 7.8 W Allowable power dissipation 1 PdMF max With an arbitrarily large heat sink. Per MOSFET Allowable power dissipation 2 PdPK max No heat sink 3.1 W Operating substrate temperature Tc max 105 °C Junction temperature Tj max 150 °C Storage temperature Tstg -40 to +125 °C Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Ratings unit Operating supply voltage 1 VCC With signals applied Operating supply voltage 2 VDD With signals applied Input high voltage VIH Pins 10, 12, 13, 14, 15, 17 Input low voltage VIL Pins 10, 12, 13, 14, 15, 17 0 to 0.6 V Output current 1 IOH1 Tc=105°C, CLOCK≥200Hz, 2.0 A 2.2 A 10 to 42 V 5±5% V 2.5 to VDD V Continuous operation, duty=100% Output current 2 IOH2 Tc=80°C, CLOCK≥200Hz, Continuous operation, duty=100%, See the motor current (IOH) derating curve CLOCK frequency Phase driver withstand voltage Recommended operating fCL VDSS Tc Minimum pulse width: at least 10μs 0 to 50 kHz ID=1mA (Tc=25°C) 100min V 0 to 105 °C 0.14 to 1.38 V No condensation substrate temperature Recommended Vref range Vref Tc=105°C Refer to the graph for each conduction-period tolerance range for the output current and brake current. Electrical Characteristics at Tc = 25°C, VCC = 24V, VDD = 5.0V Parameter Symbol Conditions VDD supply current ICCO Pin 9 current CLOCK=GND Output average current Ioave R/L=1Ω/0.62mH in each phase FET diode forward voltage Vdf If=1A (RL=23Ω) Output saturation voltage Vsat RL=23Ω Input leak current IIL min typ 0.362 max 9 0.402 0.442 IIB PWM frequency fc 35 A 1.0 1.6 V 0.61 V ±10 μA Pins 10, 12, 13, 14, 15, 17 Pin 19 =1.0V mA 0.42 =GND and 5V Vref input bias current unit 5.0 204 216 μA 45 56 kHz *Ioave values are for when the lead frame of the product is soldered to the mounting substrate. Notes: A fixed-voltage power supply must be used. No. A0755-2/19 STK672-600 Package Dimensions unit:mm (typ) 29.2 25.6 (20.47) 4.5 (3.5) 19 14.5 14.5 1 11.0 (R1.7) 7.2 14.4 (5.0) (5.0) (12.9) 2.0 1.0 (5.6) 4.2 0.52 0.4 8.2 18 1.0=18.0 (20.4) Derating curve of motor current, IOH, vs. STK672-600 Operating substrate temperature, Tc IOH - Tc 3.0 200Hz 2 phase excitation Motor current, IOH - A 2.5 Hold mode 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 70 80 90 Operating Substrate Temperature, Tc- °C 100 110 ITF02548 Notes • The current range given above represents conditions when output voltage is not in the avalanche state. • If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-6** series hybrid ICs given in a separate document. • The operating substrate temperature, Tc, given above is measured while the motor is operating. Because Tc varies depending on the ambient temperature, Ta, the value of IOH, and the continuous or intermittent operation of IOH, always verify this value using an actual set. No. A0755-3/19 STK672-600 Block Diagram VDD=5V N.C N.C A AB B BB 8 7 4 5 3 1 9 VDD MODE1 10 N.C 11 MODE2 17 CLOCK 12 CWB 13 RESETB 14 ENABLE 15 F1 F2 F3 Excitation mode selection Phase excitation signal generator FAB FBO FBB Phase advance counter R1 R2 AI VSS 16 S.G 18 Vref 19 F4 FAO Chopper circuit P.G2 2 BI P.G1 CI 6 R3 3.9kΩ/1% VSS S.G R4 1.0kΩ/1% Sample Application Circuit STK672-600 5.0V VDD (5V) 9 C03 CLOCK MODE1 MODE2 10 C06 CWB C07 ENABLE R04 5.0V 10kΩ D1 100Ω 2-phase stepping motor driver 12 C04 C05 4 17 13 5 VCC 15 24V 3 RESETB 14 1 B BB C01 At least 100μF R01 C08 R03 Vref P.G2 2 19 16 C02 10μF A AB R02 VSS 18 6 P.G1 P.GND S.G *: C03 through C08 represents a capacitor recommended for use with a recommended value of 1,000pF. No. A0755-4/19 STK672-600 Precautions [Damage to the internal MOSFET] • The RESETB pin must be fixed low when applying 5V power. If the RESETB pin is allowed to go high at the same time as the 5V power, simultaneous ON of the output phase will result, causing damage to the internal MOSFET. [GND wiring] • To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to Pin 18 (S.G) used to set the current and to the point where P.G1 and P.G2 share a connection. • If the driver region VSS pin (Pin 16), S.G pin (Pin 18), P.G1 pin (Pin 2), and P.G2 pin (Pin 6) cannot be connected to a single ground, make sure to connect the VSS pin to the control system S.GND, and the S.G pin to the P.G1 pin and P.G2 pin. [Input pins] • If VDD is not being applied to the hybrid IC, do not apply voltage to input Pins 10, 12, 13, 14, 15, or 17. In addition, if VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to VSS, Pin 16, and do not apply a voltage greater than or equal to VDD voltage. • Do not wire by connecting the circuit pattern on the P.C.B side to Pins 7, 8, or 11 on the N.C. shown in the internal block diagram. • Insert resistor RO3 (47 to 100Ω) so that the discharge energy from capacitor CO4 is not directly applied to the CMOS IC in this hybrid device. If the diode D1 has Vf characteristics with Vf less than or equal to 0.6V (when If = 0.1A), this will be smaller than the CMOS IC input pin diode Vf. If this is the case RO3 may be replaced with a short without problem. • Both TTL and CMOS levels are used for the pin 10, 12, 13, 15 and 17 inputs. • Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 15, and 17 are used as inputs, a 1 to 15kΩ pull-up resistor (to VDD) must be used. At this time, use a device for the open collector driver that has output current specifications that pull the voltage down to less than 0.6V at Low level (less than 0.6V at Low level when IOL=5mA). • If input pins are connected to GND (VSS) using a pull-down resistor, be sure to mount a resistor having a resistance of 120Ω or less. If designs call for a pull-down resistor having a resistance in the range 120Ω to 30kΩ, be absolutely sure to mount a 1,000pF capacitor between the input pins and the VSS Pin. Because sufficient VIL cannot be maintained due to the effect of input leak current, IIL=±10μA max, do not connect a pull-down resistor having a resistance of 30kΩ or higher. • The sample application circuit includes a simple reset circuit using D1, R03, C02, and R04. If 5V power rises while voltage still remains in C02, the reset signal cannot be detected as LOW and the driver may be damaged because ON operations result at the same time that driver output is in A or AB phase or B or BB phase. The voltage of C02 must therefore be less than 0.6V when the 5V power rises. In addition, if a RESETB signal is to be input based on an external signal such as the CLOCK signal, RESETB must always be fixed to a Low level when the 5V power signal rises. • To prevent malfunction due to chopping noise, we recommend that you mount a 1000pF capacitor between Pin 16 and each of the input Pins 10, 12, 13, 14, 15, and 17. Be sure to mount the capacitor as close as possible to the pins of hybrid IC. If input is fixed Low, directly connect to Pin 16. If input is fixed High, directly connect to the 5V power line. [Current setting Vref] • Considering the specifications of the Vref input bias current, IIB, a value of 1kΩ or less is recommended for R02. • If the motor current is temporarily reduced, the circuit given below (STK672-600: IOH>0.2A, STK672-610: IOH>0.3A) is recommended. • Although the driver is equipped with a fixed current control function, it is not equipped with an overcurrent protection function to ensure that the current does not exceed the maximum output current, IOH max. If Vref is mistakenly set to a voltage that exceeds IOH max, the driver will be damaged by overcurrent. No. A0755-5/19 STK672-600 5V 5V R01 R01 Vref Vref R3 R02 R3 R02 • Motor current peak value IOH setting IOH 0 • When R02 is open IOH= [Vref×1k/1k+3.9k)] ÷Rs= (Vref÷4.9) ÷Rs The values 1k and 3.9k represent internal driver resistance values, while Rs represents the internal driver current detection resistance. Vref= (4.9k÷ (4.9k+R01)) ×5V (or 3.3V) =IOH×4.9×Rs The value 4.9k represents the series resistance value of the internal driver values of 1k and 3.9k. • If R02 is connected IOH= [Vref×1k/ (1k+3.9k)] ÷Rs= (Vref÷4.9) ÷Rs The values 1k and 3.9k represent the internal driver resistance values, while Rs represents the internal driver current detection resistance. Vref= (R0x÷ (R01+R0x)) ×5V (or 3.3V) =IOH×4.9×Rs = [(4.9k×R02) ÷ ((4.9k×R02) +R01× (4.9k+R02))] ×5V(or 3.3V) R0x= (4.9k×R02) ÷ (4.9k+R02) Rs represents the current detection resistance inside the HIC, while the value 4.9k in the formula above represents the internal resistance value of the Vref pin. Rs=0.141Ω when using the STK672-600 Rs=0.089Ω when using the STK672-610 Input Pin Functions Pin Name Pin No. Function CLOCK 12 Reference clock for motor phase current switching MODE1 10 Excitation mode selection Input Conditions When Operating Operates on the rising edge of the signal (MODE2=H) Low: 2-phase excitation High: 1-2 phase excitation MODE2 17 High: Rising edge CWB 13 Motor direction switching RESETB 14 System reset and A, AB, B, and BB outputs cutoff. Low: Rising and falling edge Low: CW (forward) High: CCW (reverse) A reset is applied by a low level Applications must apply a reset signal for at least 10μs when ENABLE 15 VDD is first applied. The A, AB, B, and BB outputs are turned off, and after The A, AB, B, and BB outputs are turned off by a low- operation is restored by returning the ENABLE pin to the high level input. level, operation continues with the same excitation timing as before the low-level input. (1) A simple reset function is formed from D1, CO4, RO3, and RO4 in this application circuit. With the CLOCK input held low, when the 5V supply voltage is brought up a reset is applied if the motor output phases A and BB are driven. If the 5V supply voltage rise time is slow (over 50ms), the motor output phases A and BB may not be driven. Increase the value of the capacitor CO2 and check circuit operation again. (2) See the timing chart for the concrete details on circuit operation. No. A0755-6/19 STK672-600 Timing Charts 2-phase excitation MODE1 MODE2 RESETB CWB CLOCK ENABLE FAO FAB FBO FBB 1-2 phase excitation MODE1 MODE2 RESETB CWB CLOCK ENABLE FAO FAB FBO FBB No. A0755-7/19 STK672-600 1-2 phase excitation (CWB) MODE1 MODE2 RESETB CWB CLOCK ENABLE FAO FAB FBO FBB 2-phase excitation→Switch to 1-2 phase excitation MODE1 MODE2 RESETB CWB CLOCK ENABLE FAO FAB FBO FBB No. A0755-8/19 STK672-600 1-2 phase excitation (ENABLE) MODE1 MODE2 RESETB CWB CLOCK ENABLE FAO FAB FBO FBB 1-2 phase excitation (Hold operation results during fixed CLOCK) MODE1 MODE2 RESETB CWB CLOCK ENABLE Hold operation FAO FAB FBO FBB No. A0755-9/19 STK672-600 2-phase excitation (MODE2) MODE1 MODE2 RESETB CWB CLOCK ENABLE FAO FAB FBO FBB 1-2 phase excitation (MODE2) MODE1 MODE2 RESETB CWB CLOCK ENABLE FAO FAB FBO FBB No. A0755-10/19 STK672-600 Usage Notes 1. STK672-600 and STK672-610 input signal functions and timing (All inputs have no internal pull-up resistor and are TTL level Schmitt trigger inputs.) [RESETB and CLOCK (Input signal timing when power is first applied)] As shown in the timing chart, a RESETB signal input is required by the driver to operate with the timing in which the F1 gate is turned on first. The RESETB signal timing must be set up to have a width of at least 10μs, as shown below. The capacitor CO2, and the resistors RO3 and RO4 in the application circuit form simple reset circuit that uses the RC time constant rising time. However, when designing the RESETB input based on VIH levels, the application must have the timing shown in figure. Rise of the 5V supply voltage RESETB signal input At least 10μs CLOCK signal At least 5μs RESETB and CLOCK Signals Input Timing [CLOCK (Phase switching clock)] • Input frequency: DC to 50kHz • Minimum pulse width: 10μs • MODE2=1(High) Signals are read on the rising edge. • MODE2=0(Low) Signals are read on the rising and falling edges. [CWB (Motor direction setting)] The direction of rotation is switched by setting CWB to 1 (high) or 0 (low). See the timing charts for details on the operation of the outputs. Note: The state of the CWB input must not be changed during the 6.25μs period before and after the rising edge of the CLOCK input. [ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and hybrid IC internal operation)] ENABLE=1: Normal operation ENABLE=0: Outputs A, AB, B, and BB forced to the off state. If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 and then is later restored to the 1 state, the IC will resume operation with the excitation timing continued from before the point ENABLE was set to 0. If sudden stop is applied to the CLOCK signal used for motor rotation, the motor axis may advance beyond the theoretical position due to inertia. To stop at the theoretical position, the SLOW DOWN setting for gradually slowing the CLOCK cycle is required. Enable must be initially set high for input as shown in the timing chart. [MODE1 and MODE2 (Excitation mode selection)] MODE1=0: 2-phase excitation MODE2=1: Rising edge of CLOCK MODE1=1: 1-2 phase excitation MODE2=0: Rising and falling edges of CLOCK See the timing charts for details on output operation in these modes. Note: The state of the MODE input must not be changed during the 5μs period before and after the rising edge of the CLOCK input. No. A0755-11/19 STK672-600 2. Calculating STK672-600 HIC Internal Power Loss The average internal power loss in each excitation mode of the STK672-600 can be calculated from the following formulas. Each excitation mode 2-phase excitation mode 2PdAVex= (Vsat+Vdf) ×0.5×CLOCK×IOH×t2+0.5×CLOCK×IOH× (Vsat×t1+Vdf×t3) 1-2 Phase excitation mode 1-2PdAVex= (Vsat+Vdf) ×0.25×CLOCK×IOH×t2+0.25×CLOCK×IOH× (Vsat×t1+Vdf×t3) Motor hold mode HoldPdAVex= (Vsat+Vdf) ×IOH Vsat: Combined voltage represented by the Ron voltage drop+shunt resistor Vdf: Combined voltage represented by the MOSFET body diode+shunt resistor CLOCK: Input CLOCK (CLOCK pin signal frequency) t1, t2, and t3 represent the waveforms shown in the figure below. t1: Time required for the winding current to reach the set current (IOH) t2: Time in the constant current control (PWM) region t3: Time from end of phase input signal until inverse current regeneration is complete IOH 0A t1 t2 t3 Motor COM Current Waveform Model t1= (-L/(R+0.42)) In (1-((R+0.42)/VCC) ×IOH) t3= (-L/R) In ((VCC+0.42)/(IOH×R+VCC+0.42)) VCC: Motor supply voltage (V) L: Motor inductance (H) R: Motor winding resistance (Ω) IOH: Motor set output current crest value (A) Relationship of CLOCK, t1, t2, and t3 in each excitation mode 2-phase excitation mode: t2= (2/CLOCK) - (t1+t3) 1-2 phase excitation mode: t2= (3/CLOCK) -t1 For Vsat and Vdf, be sure to substitute values from the graphs of Vsat vs. IOH and Vdf vs. IOH while the set current value is IOH. Then, determine whether a heat sink is required by comparing with the graph of ΔTc vs. Pd based on the average HIC power loss calculated. When designing a heat sink, refer to the section “Thermal design” found on the next page. The average HIC power loss, PdAV, described above does not have the avalanche’s loss. To include the avalanche’s loss, be sure to add Equation (2), “STK676-6** Allowable Avalanche Energy Value” to PdAV above. When using this IC without a fin always check for temperature increases in the set, because the HIC substrate temperature, Tc, varies due to effects of convection around the HIC. No. A0755-12/19 STK672-600 STK672-600 Output saturation voltage, Vsat - Output current, IOH Vsat - IOH 1.2 5° C 1.0 0.8 10 Output saturation voltage, Vsat - V 1.4 °C 25 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 Output current, IOH - A 3.0 ITF02549 STK672-600 Forward voltage, Vdf -Output current, IOH Vdf- IOH 1.4 Forward voltage, Vdf - V 1.2 C 25° 1.0 °C 105 0.8 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 Output current, IOH - A 3.0 ITF02550 Substrate temperature rise , ΔTc(no heat sink) - Internal average power dissipation, PdAV ΔTc - PdAV Substrate temperature rise, ΔTc - °C 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Hybrid IC internal average power dissipation, PdAV - W 3.5 ITF02551 No. A0755-13/19 STK672-600 3. STK672-600 Allowable Avalanche Energy Value (1) Allowable Range in Avalanche Mode When driving a 2-phase stepping motor with constant current chopping using an STK672-6** Series hybrid IC, the waveforms shown in Figure 1 below result for the output current, ID, and voltage, VDS. VDSS: Voltage during avalanche operations VDS IOH: Motor current peak value IAVL: Current during avalanche operations ID tAVL: Time of avalanche operations ITF02557 Figure 1 Output Current, ID, and Voltage, VDS, Waveforms 1 of the STK672-6** Series when Driving a 2-Phase Stepping Motor with Constant Current Chopping When operations of the MOSFET built into STK672-6** Series ICs is turned off for constant current chopping, the ID signal falls like the waveform shown in the figure above. At this time, the output voltage, VDS, suddenly rises due to electromagnetic induction generated by the motor coil. In the case of voltage that rises suddenly, voltage is restricted by the MOSFET VDSS. Voltage restriction by VDSS results in a MOSFET avalanche. During avalanche operations, ID flows and the instantaneous energy at this time, EAVL1, is represented by Equation (1). EAVL1=VDSS×IAVL×0.5×tAVL ------------------------------------------- (1) VDSS: V units, IAVL: A units, tAVL: sec units The coefficient 0.5 in Equation (1) is a constant required to convert the IAVL triangle wave to a square wave. During STK672-6** Series operations, the waveforms in the figure above repeat due to the constant current chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (2) used to find the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (1). PAVL=VDSS×IAVL×0.5×tAVL×fc ------------------------------------------- (2) fc: Hz units (fc is set to the PWM frequency of 50kHz.) For VDSS, IAVL, and tAVL, be sure to actually operate the STK672-6** Series and substitute values when operations are observed using an oscilloscope. Ex. If VDSS=110V, IAVL=1A, tAVL=0.2μs when using a STK672-600 driver, the result is: PAVL=110×1×0.5×0.2×10-6×50×103=0.55W VDSS=110V is a value actually measured using an oscilloscope. The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3. When examining the avalanche energy, be sure to actually drive a motor and observe the ID, VDSS, and tAVL waveforms during operation, and then check that the result of calculating Equation (2) falls within the allowable range for avalanche operations. No. A0755-14/19 STK672-600 (2) ID and VDSS Operating Waveforms in Non-avalanche Mode Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result during actual operations. Factors causing avalanche are listed below. • Poor coupling of the motor’s phase coils (electromagnetic coupling of A phase and AB phase, B phase and BB phase). • Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor. • Increases in VDSS, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V. If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as shown in Figure 2. Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss range of PAVL shown in Figure 3. VDS IOH: Motor current peak value ID ITF02558 Figure 2 Output Current, ID, and Voltage, VDS, Waveforms 2 of the STK672-6** Series when Driving a 2-Phase Stepping Motor with Constant Current Chopping Average power loss in the avalanche state, PAVL- W Figure 3 Allowable Loss Range, PAVL-IOH During STK672-600 Avalanche Operations PAVL - IOH 5.0 4.5 80°C 4.0 3.5 3.0 105°C 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 Motor phase current, IOH - A 2.0 2.5 ITF02552 Note: The operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. Because it is possible to apply 2.8W or more at IOH=0A, be sure to avoid using the MOSFET body diode that is used to drive the motor as a zener diode. No. A0755-15/19 STK672-600 4. Thermal design [Operating range in which a heat sink is not used] Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the quality of the HIC. The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC. The value of PdAV increases as the output current increases. To calculate PdAV, refer to “Calculating Internal HIC Loss for the STK672-600 and STK672-610” in the specification document. Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations, IO1 Motor phase current (sink side) IO2 0A -IO1 T1 T2 T3 T0 Figure 1 Motor Current Timing T1: Motor rotation operation time T2: Motor hold operation time T3: Motor current off time T2 may be reduced, depending on the application. T0: Single repeated motor operating cycle IO1 and IO2: Motor current peak values Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. The hybrid IC internal average power dissipation PdAV can be calculated from the following formula. PdAV= (T1×P1+T2×P2+T3×0) ÷TO ---------------------------- (I) (Here, P1 is the PDAV for IO1 and P2 is the PDAV for IO2) If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60°C or less, there is no need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used. [Operating range in which a heat sink is used] Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of θc-a in Equation (II) below and the graph depicted in Figure 3. θc-a= (Tc max-Ta) ÷PdAV ---------------------------- (II) Tc max: Maximum operating substrate temperature =105°C Ta: HIC ambient temperature Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and confirm that the substrate temperature, Tc, is 105°C or less. The average HIC power loss, PdAV, described above represents the power loss when there is no avalanche operation. To add the loss during avalanche operations, be sure to add Equation (2), “Allowable STK672-6** Avalanche Energy Value”, to PdAV. No. A0755-16/19 STK672-600 Figure 2 Substrate temperature rise, ΔTc(no heat sink) - Internal average power dissipation, PdAV ΔTc - PdAV Substrate temperature rise, ΔTc - °C 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Hybrid IC internal average power dissipation, PdAV - W 3.5 ITF02553 Figure 3 Heat sink area (Board thickness: 2mm) - θc-a θc-a - S Heat sink thermal resistance, θc-a - °C/W 100 7 5 3 2 Wit 10 7 Wit ha 5 hn o su flat 3 rfac e fi blac k su nish rfac e 2 1.0 10 2 3 5 7 100 2 f i ni 3 sh 5 Heat sink area, S - cm2 7 1000 ITF02554 5. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink. The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta. Power loss of up to 3.1W is allowable at Ta=25°C, and of up to 1.75W at Ta=60°C. Allowable power dissipation, PdPK(no heat sink) - Ambient temperature, Ta PdPK - Ta Allowable power dissipation, PdPK - W 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 80 Ambient temperature,Ta - °C 100 120 ITF02511 No. A0755-17/19 STK672-600 6. Example of Stepping Motor Driver Output Current Path (1-2 phase excitation) 2-phase stepping motor driver IOA VDD MODE1 MODE2 CLOCK CWB Excitation mode selection Phase advance counter IOAB A AB B BB F1 F2 F3 F4 FAO VCC 24V FAB Phase excitation signal generator FBO FBB R1 RESETB R2 + P.G2 C02 at least 100μF AI ENABLE Chopper circuit BI CI P.G1 P.GND R3 3.9kΩ VSS S.G R4 1.0kΩ CLOCK Phase A output current IOA PWM operations Phase AB output current IOAB When PWM operations of IOA are OFF, for IOAB, negative current flows through the parasitic diode, F2. When PWM operations of IOAB are OFF, for IOA, negative current flows through the parasitic diode, F1. No. A0755-18/19 STK672-600 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2011. Specifications and information herein are subject to change without notice. PS No. A0755-19/19