Ordering number : ENA2138 STK672-410C-E Thick-Film Hybrid IC 2-phase Stepping Motor Driver Overview The STK672-410C-E is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control. Applications • Office photocopiers, printers, etc. Features • Entry of external clock is enough to activate the micro step sinusoidal driver. • The excitation mode of 2, 1-2, W1-2, 2W1-2, or 4W1-2 can be selected with the external pin. • The 4-phase distributor switching timing can be set to occur either on both rising and falling edge detection or on rising edge detection only with an external pin (MODE3). • A phase holding function is provided to prevent phase skip during switching of excitation in the course of operation. • The motor current is set by a voltage divider formed by an external resistor connected to the Vref pin. • The CLK input pin is provided with an internal noise filtering circuit in addition to a Schmidt circuit to increase the margin for extraneous noise. • When set low, the ENABLE pin turns off the motor drive current for all phases and retains the phase excitation state. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. O1712HKPC 018-07-0002 No.A2138-1/19 STK672-410C-E Specifications Absolute Maximum Ratings at Tc = 25°C Parameter Symbol Conditions Ratings unit Maximum supply voltage 1 VCC max No signal 52 V Maximum supply voltage 2 VDD max No signal -0.3 to +7.0 V Input voltage VIN max Logic input pins -0.3 to +5.8 V Output current IOH max VDD=5V, CLOCK≥200Hz 3.2 A Allowable power dissipation Pd max With an arbitrarily large heat sink. Per MOSFET 10 W Operating substrate temperature Tc max 105 °C Junction temperature Tj max 150 °C Storage temperature Tstg -40 to +125 °C Allowable Operating Ranges at Ta=25°C Parameter Symbol Conditions Ratings unit Operating supply voltage 1 VCC With signals applied 10 to 45 V Operating supply voltage 2 VDD With signals applied 5±5% V Input high voltage VIH 0 to 5.8 V Output current IOH Tc=105°C, CLOCK≥200Hz Phase driver withstand voltage VDSS TR1, 2, 3, 4 ID=1mA (Tc=25°C) 3 A 100min V Electrical Characteristics at Tc=25°C, VCC=24V, VDD=5.0V Parameter Symbol Conditions VDD supply current ICCO VDD=5.0V, ENABLE=Low Vref=2V Output average current Ioave R/L=3Ω/3.8mH in each phase FET diode forward voltage Vdf If=1A Output saturation voltage Vsat RL=23Ω Control VIH Except for the Vref pin Input voltage input pin typ max unit 6 10 15 0.51 0.59 0.66 1.2 1.6 V 0.3 0.5 V 2.5 mA A V VIL Except for the Vref pin 0.6 V IIH Except for the Vref pin VIN=5V 10 μA IIL Except for the Vref pin VIN=0V 10 μA Input voltage VI Pin 19 Input current Ios Pin 19, VDD input Input current Vref pin min PWM frequency fc 2 VDD 37.5 50 V μA 12.5 62.5 kHz Current Distribution Ratio 2W1-2 W1-2 2W1-2 W1-2 1-2 2W1-2 2W1-2 W1-2 2W1-2 2W1-2 W1-2 1-2 Vref θ=7/8 100 *1 θ=6/8 93 θ=5/8 84 θ=4/8 71 θ=3/8 55 θ=2/8 40 θ=1/8 2W1-2 2 % 19 100 Notes: A fixed-voltage power supply must be used. The value of Item 1 is the design target and not measured. No.A2138-2/19 STK672-410C-E Package Dimensions unit:mm (typ) 29.2 25.6 (20.47) 4.5 (3.5) 19 14.5 14.5 1 11.0 (R1.7) 7.2 14.4 (5.0) (5.0) (12.9) 2.0 1.0 (5.6) 4.2 0.52 0.4 8.2 18 1.0=18.0 (20.4) Derating Curve of Motor Current, IOH, vs. STK672-410C-E Operating Substrate Temperature, Tc IOH - Tc 3.5 200Hz 2-phase excitation Motor current, IOH - A 3.0 2.5 Hold mode 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 70 80 90 100 110 Operating Substrate Temperature, Tc - °C Notes • The current range given above represents conditions when output voltage is not in the avalanche state. • If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-4** series hybrid ICs given in a separate document. • The operating substrate temperature, Tc, given above is measured while the motor is operating. Because Tc varies depending on the ambient temperature, Ta, the value of IOH, and the continuous or intermittent operation of IOH, always verify this value using an actual set. No.A2138-3/19 STK672-410C-E Block Diagram VDD NC 8 9 MODE1 10 MODE2 11 Excitation mode control CLK 12 Rising edge / falling edge detection MODE3 17 RESET 14 Vref 19 A 4 AB 5 B 3 BB 1 Current distribution ratio switching Phase advance counter CWB 13 NC 7 Voltage division ratio Pseudo sin wave generator Phase excitation drive signal generator Poewr on reset ENABLE 15 + RC oscillator Reference clock generator PWM control + VSS 16 2 P.G2 S.G 18 6 P.G1 SUB Sample Application Circuit VDD=5V 9 RO3 10 D1 0.01μF 11 CLK 17 1 12 3 Simplified power-on reset circuit (this circuit cannot be used to detect drops in the power-supply voltage) VCC1=24V∼ Stepping motor ENABLE 15 CWB STK672-410C-E 5 4 13 1kΩ CO3 14 2 RO1 Vref CO2=10μF RO2 CO1=100μF 6 19 16 18 P.GND S.GND No.A2138-4/19 STK672-410C-E Precautions [Internal MOSFET Destruction] • The internal MOSFFET gate voltage is supplied from the 5V power supply. If the 5V power supply voltage is below its allowable operating voltage range, the resultant insufficient gate drive state may destroy the MOSFET. [GND wiring] • To reduce noise in the 24V system, locate the ground side of CO1 in the circuit above as close as possible to pins 2 and 6 on the hybrid IC. Also, to assure that the current is set accurately, the Vref ground side must be connected to a ground point that is a shared connection between the ground pin (pin 18, S.G) used for the current setting and P.G1 and P.G2. • If the VSS pin (pin 16) near the driver, the S.G pin (pin 18), the P.G1 pin (pin 2), and the P.G2 pin (pin 6) cannot be connected to a single-point ground, connect the VSS pin to the control system S.GND, and the S.G pin to the P.G1 pin and the P.G2 pin. [Input pins] • The voltage range for the input pins is -0.3 to +5.8V. Design applications so that voltages lower than -0.3V and higher than 5.8V are never applied to the input pin. • Do not connect any of the NC pins (pins 7, and 8) shown in the internal equivalent circuit block diagram to the circuit pattern on the printed circuit board. • Connect a resistor (1kΩ) so that discharge energy of capacitor CO2 does not enter the hybrid IC. • Inputs to pins 10, 11, 12, 13, 14, 15, and 17 are signal whose high level is 2.5V. Both TTL and CMOS inputs are supported. • Internal pull-up resistors are not provided for the input pins. If this hybrid IC's inputs are controlled by open-collector type circuits, external pull-up resistors must be provided. • If resistors are connected in series with the inputs, insert capacitors between the inputs and ground to prevent malfunctions due to the hybrid IC's switching noise. • In the application circuit example, a simple reset circuit is formed by D1, RO3, CO2, and a 1kΩ resistor. This circuit will not create a reset signal if the 5V supply voltage drops briefly. This circuit structure requires the 5V supply voltage to fall below 0.6V to operate. Connect the hybrid IC directly to VDD to use the hybrid IC's power on reset function. • A power on reset operation must be applied when the 5V power supply level is first applied. [Vref Current Setting] • To reduce the influence of input impedance 200kΩ input current of the terminal Vref, RO1 recommends about 1kΩ. • We recommend using the following circuit to temporarily reduce the motor current. • Although the driver provides a constant current control function, it does not have an overcurrent protection function to assure that the maximum output current, IOH max, is not exceeded. If Vref is set by mistake to a voltage that such that IOH max is exceeded, the driver will draw excessive current and the device will be destroyed. • If the Vref pin (pin 19) is left open, the Vref voltage will be set to about 2.5V. With the STK672-400, the motor current will then be about 1.8A. With the STK672-410, the motor current will be about 3.2A. These current settings are close to IOH max. 5V 5V RO1 RO1 Vref R3 RO2 R3 Vref RO2 No.A2138-5/19 STK672-410C-E [Setting the motor current] The motor current is set by the hybrid IC's pin 19V, Vref. The formula shows below gives the relationship between IOH and Vref. Vref = VDD-(IOH × Rs × K) ···························································································································· (1) K: 6.55 (voltage divider ratio) Rs: 0.122Ω (hybrid IC internal current detection resistance: precision = ±3%) IOH IOL Ioave 0A Model of the Motor Phase Current Flowing into the Hybrid IC Function Table M2 M1 M3 1 0 0 0 1 1 0 1 0 1 edge timing 2 phase 1-2 phase W1-2 phase 2W1-2 phase excitation excitation excitation excitation 1-2 phase W1-2 phase 2W1-2 phase 4W1-2 phase excitation excitation excitation excitation CWB pin CWB Phase switching clock CLK rising edge Both CLK edges ENABLE and RESET pins Forward Reverse ENABLE Motor current cut: Low 0 1 RESET Active Low No.A2138-6/19 STK672-410C-E Timing Charts 2 Phase Excitation Timing Chart (M3=1) 1 M1 0 M1 0 M2 0 M2 0 1 M3 0 M3 0 RESET CWB 1 RESET CWB CLK A A B B CLK A MOSFET Gate Signal MOSFET Gate Signal 1-2 Phase Excitation Timing Chart (M3=1) 100% Vref A 100% 72% Comparator Reference Voltage Comparator Reference Voltage 100% 72% Vref B W1-2 Phase Excitation Timing Chart (M3=1) A B B 72% Vref A 100% 72% Vref B 2W1-2 Phase Excitation Timing Chart (M3=1) 1 M1 0 M1 0 1 1 M2 0 M2 0 1 1 M3 0 M3 0 CLK Comparator Reference Voltage A A B B 100% 93% 72% 41% Vref A 100% 93% 72% 41% Vref B MOSFET Gate Signal CLK A B B Comparator Reference Voltage RESET CWB MOSFET Gate Signal RESET CWB 100% 93% 84% 72% 55% 41% 21% Vref A 100% 93% 84% 72% 55% 41% 21% Vref B A No.A2138-7/19 STK672-410C-E 1-2 Phase Excitation Timing Chart (M3=0) 1 M1 0 M1 0 M2 0 M2 0 M3 0 M3 0 RESET CWB RESET CWB CLK A A B B CLK A MOSFET Gate Signal MOSFET Gate Signal W1-2 Phase Excitation Timing Chart (M3=0) 72% Vref A 100% 72% Vref B Comparator Reference Voltage Comparator Reference Voltage 100% 2W1-2 Phase Excitation Timing Chart (M3=0) A B B 100% 93% 72% 41% Vref A 100% 93% 72% 41% Vref B 4W1-2 Phase Excitation Timing Chart (M3=0) 1 M1 0 M1 0 M2 0 1 M2 10 M3 0 M3 0 CLK CLK 100% 93% 84% 72% 55% 41% 21% Vref A 100% 93% 84% 72% 55% 41% 21% Vref B Comparator Reference Voltage Comparator Reference Voltage A A B B MOSFET Gate Signal RESET CWB MOSFET Gate Signal RESET CWB A A B B 100% 97% 93% 88% 84% 78% 72% 64% 55% 48% 41% 31% 21% 12% Vref A 100% 97% 93% 88% 84% 78% 72% 64% 55% 48% 41% 31% 21% 12% Vref B No.A2138-8/19 STK672-410C-E Usage Notes 1. Input pins and functional overview [Input pins] Hybrid IC pin No. Symbol Function Pin type 19 Vref Current setting Input impedance: 200kΩ (typical) 10, 11, 17 MODE1, MODE2, MODE3 Excitation mode setting TTL level Schmitt input 12 CLK Phase switching clock Same as the above (speed command) 13 CWB Motor direction setting Same as the above 14 RESET System reset Same as the above 15 ENABLE Motor current off Same as the above 2. Input signal functions [CLK (Phase switching clock)] (1) Input frequency: DC to 50kHz (2) Minimum pulse width: 10μs (3) Pulse width duty: 40 to 60% (4) Pin circuit type: TTL level Schmitt trigger input (5) A multi-stage noise exclusion circuit is included. (6) Function • M3:1 When M3 is 1:The excitation phase is advanced one step on each CLK signal rising edge. • M3:0 When M3 is 0:The excitation phase is advanced one step alternately on each CLK signal rising or falling edge. • Timing chart CLK input System clock Phase excitation counter clock Excitation counter up/down Control output timing Control output switching timing [CWB (Motor direction setting)] (1) Pin circuit type: TTL level Schmitt trigger input (2) Function • When CWB = 0: The motor turns in the clockwise direction • When CWB = 1: The motor turns in the counterclockwise direction (3) Note: The value of the CWB input must not be changed in the period from 7μs before a CLK input rising or falling edge until 7μs after that edge. [ENABLE (Forces the excitation drive outputs A, AB, B, and BB to the off state and selects the hybrid IC's internal state to be operating or hold)] (1) Pin circuit type: TTL level Schmitt trigger input (2) Function a) When ENABLE is 1: Normal operating state b) When ENABLE is 0: The motor current is turned off and the excitation drive output is turned off forcibly. At this time, the hybrid IC's system clock is stopped and the hybrid IC is not influenced by changes to any input pins other than the reset input. No.A2138-9/19 STK672-410C-E [MODE1, MODE2, and MODE3 (Excitation mode and timing mode selection)] (1) Pin circuit type: TTL level Schmitt trigger input (2) Excitation mode selection (See the application circuit example page for details on excitation mode selection.) (3) Valid mode setting timing: Do not change the mode within the ±7μs period around any rising or falling edge on the CLK input signal. CLK input System clock Mode setting Mode switching timing Mode switching clock IC internal setting state Phase excitation clock Phase excitation counter up/down Mode Setting Acquisition Timing [RESET (Whole system reset)] (1) Pin circuit type: TTL level Schmitt trigger input (2) Function: The reset signal to this hybrid IC's internal sequencer can be selected to be either the hybrid IC internal power-on reset function or an external signal. To operate the hybrid IC internal sequencer from the hybrid IC internal power-on reset signal, connect the hybrid IC's pin 14 to VDD. The hybrid IC internal reset signal is generated with a timing such that it is output to internal circuits when VDD is in the range 2.9 to 3.9V. Alternatively, if an external signal is used as the reset signal, it must have the timing relative to the rise of the VDD voltage shown in the figure below. Note that the reset pulse must have a pulse width of at least 1ms. • External reset and power supply application sequence VDD: 5V power supply (hybrid IC pin 9) 4.5V At least 1ms RESET: Hybrid IC pin 14 No.A2138-10/19 STK672-410C-E [Vref (Sets the current that is used as the reference for setting the output current)] (1) Pin circuit type: Analog input (differential amplifier). Input resistance: 200kΩ (2) Function: The input voltage must be in the voltage range from the control system power supply VDD to 2V. Note that there is a resistance component (200kΩ, typical) in this hybrid IC's input and that therefore an input current occurs. If the Vref voltage structure is formed as a resistor voltage divider, that circuit must be designed to take that input current into account. The input current is 12.5μA (typical). Note that this is the current when Vref is 5V. The input current falls according to the formula shown below when the Vref voltage is below that level. Ios=Vref/(200k+200k) --------- (1) • Input circuit structure STK672-410C-E 200kΩ Vref Ios=12.5μA 200kΩ : ±1% 200kΩ Hybrid IC pin 19 to DAC 2.5V No.A2138-11/19 STK672-410C-E 3. Calculating STK672-410C-E HIC Internal Power Loss HIC internal loss calculation of STK672-410C-E The internal average power loss in the excitation modes of STK672-400 is calculated as follows: [Excitation modes] 2 phase excitation mode 2PdAV = (Vsat+Vdf)×0.5×CLOCK×IOH×t2+0.5×CLOCK×IOH× (Vsat×t1+Vdf×t3) --------------------------- (3-1) 1-2 phase excitation mode 1-2PdAV = (Vsat+Vdf)×0.25×CLOCK×IOH×t2+0.25×CLOCK×IOH× (Vsat×t1+Vdf×t3) ---------------------- (3-2) W1-2 phase excitation mode W1-2PdAV =0.64[(Vsat+Vdf)×0.25×CLOCK×IOH×t2+0.25×CLOCK×IOH× (Vsat×t1+Vdf×t3)] ------------- (3-3) 2W1-2 phase excitation mode 2W1-2PdAV =0.64[(Vsat+Vdf)×0.0625×CLOCK×IOH×t2+0.0625×CLOCK×IOH× (Vsat×t1+Vdf×t3)] ------ (3-4) 4W1-2 phase excitation mode 4W1-2PdAV =0.64[(Vsat+Vdf)×0.0625×CLOCK×IOH×t2+0.0625×CLOCK×IOH× (Vsat×t1+Vdf×t3)] ------ (3-5) At motor hold Hold PdAV = (Vsat+Vdf)×IOH---------------------------------------------------------------------------------------------- (3-6) Note: 2-phase 100% conductance is assumed in Equation (3-6). Vsat: Synthetic voltage of Ron voltage drop + Synthetic voltage of current detection resistance Vdf: Synthetic voltage of FET body diode Vdf + Synthetic voltage of current detection resistance CLOCK: Input clock CLK (reference frequency before splitting into four phases) t1, t2, and t3 are waveforms shown in the following figure: t1: Time till the winding current reaches the set value (IOH). t2: Time for the constant-current control (PWM) region t3: Time from the phase signal OFF up to regenerative consumption of the counter electromotive force IOH 0A t1 t2 t3 Motor COM Current Waveform Model t1= (-L/(R+0.3)) ln (1-((R+0.3)/VCC1) ×IOH)) ---------------------------------------------------------------- (3-7) t3= (-L/R) ln ((VCC1+0.3)/(IOH×R+VCC1+0.3)) ---------------------------------------------------------------- (3-8) VCC1: Motor supply voltage (V) L: Motor inductance (H) R: Motor winding resistance (Ω) IOH: Motor set output current crest value (A) No.A2138-12/19 STK672-410C-E Phase signal ON time T and constant-current control time t2 in excitation modes (1) 2 phase excitation mode t2 = (2÷CLOCK) - (t1 + t3)·······························(3-9) (2) 1-2 phase excitation mode t2 = (3÷CLOCK) - t1·········································(3-10) (3) W1-2 mode t2 = (7÷CLOCK) - t1·········································(3-11) (4) 2W1-2 phase excitation (4W1-2 phase excitation) t2 = (15÷CLOCK) - t1·······································(3-12) Enter the value of Vsat and Vdf from Vsat vs IOH and Vdf vs IOH graphs for the set current value of IOH. Compare the HIC average power loss thus determined with the ΔTc vs Pd graph to determine whether the heat sink is necessary. See the section on STK672-400C-E thermal design section later in this document for details on heat sink design. The value HIC for the average power loss PdAV is the loss when the device is not in the avalanche state. To add the avalanche state loss, add the STK672-400D-E avalanche energy allowable value from equation (2) to the PdAV value above. When the fin is not used, the HIC substrate temperature Tc changes because of the effect of air convection, etc. Be sure to check temperature rise with the set. [Calculating PAVL, the average power loss in the avalanche state] The average power loss in the avalanche state, PAVL, is given by formula (4-2), which is the expression for the loss, PAVL, in the avalanche state during constant-current chopping operation multiplied by the chopping frequency. PAVL=VDSS×IAVL×0.5×tAVL×fc······································································································(4-2) fc: Hz (Use the maximum PWM frequency for the STK672-400 series.) The values for VDSS, IAVL, and tAVL must be observed with an oscilloscope in an actual operating circuit based on the STK672-400 series device, and those values must then be substituted into these equations. The PAVL added differs for the different excitation modes: for modes other than 2 phase excitation, multiply PAVL by the following constant and then add to the hybrid IC internal average power loss. For 1-2 phase excitation and higher modes: PAVL(1)=0.7×PAVL··················································· (3-13) For 2 phase excitation mode and motor hold mode: PAVL(1)=1×PAVL·········································· (3-14) No.A2138-13/19 STK672-410C-E STK672-410C-E Output saturation voltage, Vsat - Output current, IOH Vsat - IOH 5° C 1.0 Tc =1 0 Output saturation voltage, Vsat - V 1.2 0.8 °C 25 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Output current, IOH - A STK672-410C-E Forward voltage, Vdf -Output current, IOH Vdf- IOH 1.6 Forward voltage, Vdf - V 1.4 C 25° Tc= °C 105 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Output current, IOH - A Substrate temperature rise, ΔTc (no heat sink) - Internal average power dissipation, PdAV ΔTc - PdAV Substrate temperature rise, ΔTc - °C 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Hybrid IC internal average power dissipation, PdAV - W 3.5 ITF02551 No.A2138-14/19 STK672-410C-E 4. STK672-410C-E Allowable Avalanche Energy Value (1) Allowable Range in Avalanche Mode When driving a 2-phase stepping motor with constant current chopping using an STK672-410C-E hybrid IC, the waveforms shown in Figure 1 below result for the output current, ID, and voltage, VDS. VDSS: Voltage during avalanche operations VDS IOH: Motor current peak value IAVL: Current during avalanche operations ID tAVL: Time of avalanche operations ITF02557 Figure 1 Output Current, ID, and Voltage, VDS, Waveforms 1 of the STK672-400 Series when Driving a 2-Phase Stepping Motor with Constant Current Chopping When operations of the MOSFET built into STK672-400 Series ICs is turned off for constant current chopping, the ID signal falls like the waveform shown in the figure above. At this time, the output voltage, VDS, suddenly rises due to electromagnetic induction generated by the motor coil. In the case of voltage that rises suddenly, voltage is restricted by the MOSFET VDSS. Voltage restriction by VDSS results in a MOSFET avalanche. During avalanche operations, ID flows and the instantaneous energy at this time, EAVL1, is represented by Equation (4-1). EAVL1=VDSS×IAVL×0.5×tAVL ------------------------------------------- (4-1) VDSS: V units, IAVL: A units, tAVL: sec units The coefficient 0.5 in Equation (4-1) is a constant required to convert the IAVL triangle wave to a square wave. During STK672-400 Series operations, the waveforms in the figure above repeat due to the constant current chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (4-2) used to find the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (4-1). PAVL=VDSS×IAVL×0.5×tAVL×fc ------------------------------------------- (4-2) fc: Hz units (fc is set to the PWM frequency of 62.5kHz.) For VDSS, IAVL, and tAVL, be sure to actually operate the STK672-400 Series and substitute values when operations are observed using an oscilloscope. Ex. If VDSS=110V, IAVL=0.8A, tAVL=0.2μs when using a STK672-410C-E driver, the result is: PAVL=110×0.8×0.5×0.2×10-6×62.5×103=0.55W VDSS=110V is a value actually measured using an oscilloscope. The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3. When examining the avalanche energy, be sure to actually drive a motor and observe the ID, VDSS, and tAVL waveforms during operation, and then check that the result of calculating Equation (4-2) falls within the allowable range for avalanche operations. No.A2138-15/19 STK672-410C-E (2) ID and VDSS Operating Waveforms in Non-avalanche Mode Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result during actual operations. Factors causing avalanche are listed below. • Poor coupling of the motor’s phase coils (electromagnetic coupling of A phase and AB phase, B phase and BB phase). • Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor. • Increases in VDSS, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V. If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as shown in Figure 2. Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss range of PAVL shown in Figure 3. VDS IOH: Motor current peak value ID ITF02558 Figure 2 Output Current, ID, and Voltage, VDS, Waveforms 2 of the STK672-410C-E when Driving a 2-Phase Stepping Motor with Constant Current Chopping Average power loss in the avalanche state, PAVL - W Figure 3 Allowable Loss Range, PAVL-IOH During STK672-410C-E Avalanche Operations PAVL - IOH 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Motor phase current, IOH - A Note: The operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. Because it is possible to apply 3W or more at IOH=0A, be sure to avoid using the MOSFET body diode that is used to drive the motor as a zener diode. Consider using these devices in the usage ranges for an operating substrate temperature Tc of 105°C. No.A2138-16/19 STK672-410C-E 5. STK672-410C-E Thermal design [Operating range in which a heat sink is not used] Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the quality of the HIC. The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC. The value of PdAV increases as the output current increases. To calculate PdAV, refer to “Calculating Internal HIC Loss for the STK672-410C-E” in the specification document. Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations. IO1 Motor phase current (sink side) IO2 0A -IO1 T1 T2 T3 T0 Figure 1 Motor Current Timing T1: Motor rotation operation time T2: Motor hold operation time T3: Motor current off time T2 may be reduced, depending on the application. T0: Single repeated motor operating cycle IO1 and IO2: Motor current peak values Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. The hybrid IC internal average power dissipation PdAV can be calculated from the following formula. PdAV= (T1×P1+T2×P2+T3×0) ÷TO ---------------------------- (I) (Here, P1 is the PdAV for IO1 and P2 is the PdAV for IO2) If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60°C or less, there is no need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used. [Operating range in which a heat sink is used] Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of θc-a in Equation (II) below and the graph depicted in Figure 3. θc-a= (Tc max-Ta) ÷PdAV ---------------------------- (II) Tc max: Maximum operating substrate temperature =105°C Ta: HIC ambient temperature Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and confirm that the substrate temperature, Tc, is 105°C or less. The average HIC power loss, PdAV, described above represents the power loss when there is no avalanche operation. To add the loss during avalanche operations, be sure to add Equation (4-2), “Allowable STK672-400 Avalanche Energy Value”, to PdAV. No.A2138-17/19 STK672-410C-E Figure 2 Substrate temperature rise, ΔTc - Internal average power dissipation, PdAV ΔTc - PdAV Substrate temperature rise, ΔTc - °C 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Hybrid IC internal average power dissipation, PdAV - W 3.5 ITF02553 Figure 3 Heat sink area (thickness: 2mm) - θc-a θc-a - S Heat sink thermal resistance, θc-a - °C/W 100 7 5 3 2 Wi t 10 Wit 7 5 ha hn flat 3 o su rfac e fi blac k su nish rfac e 2 1.0 10 2 3 5 7 100 2 Heat sink area, S - cm2 f i ni 3 sh 5 7 1000 ITF02554 No.A2138-18/19 STK672-410C-E 6. STK672-410C-E Ambient Temperature Ta Package Power Loss PdPK Derating Curve The package power loss PdPK is the internal average power loss PdAV that is allowed without a heat sink. The figure below shows the power loss PdPK that is allowable as the ambient temperature Ta changes. At Ta=25°C a power loss of 3.1W is allowable, and at Ta=60°C, 1.75W is allowable. STK672-410C-E package power loss PdPK (no heat sink) - Ambient temperature Ta PdPK - Ta Allowable power dissipation, PdPK - W 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 80 Ambient temperature,Ta - °C 100 120 ITF02511 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. Regarding monolithic semiconductors, if you should intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a confirmation. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2012. Specifications and information herein are subject to change without notice. PS No.A2138-19/19