STMICROELECTRONICS L6360

L6360
IO-Link communication master transceiver IC
Datasheet − production data
Features
■
Supply voltage from 18 to 32.5 V
■
Programmable output stages: high-side,
low-side or push-pull (< 2 Ω)
■
Up to 500 mA L+ protected high-side driver
■
Supports COM1, COM2 and COM3 mode
■
Additional IEC61131-2 type-1 input
■
Short-circuit and overcurrent output protection
through current limitation and programmable
cutoff current
■
3.3 V / 5 V, 50 mA linear regulator
■
5 mA IO-Link digital input
■
Fast mode I2C for IC control, configuration and
diagnostic
■
Diagnostic dual LED sequence generator and
driver
■
5 V and 3.3 V compatible I/Os
■
Overvoltage protection (> 36 V)
■
Overtemperature protection
■
ESD protection
■
Miniaturized: VFQFPN-26L
3.5 x 5 x 1 mm package
Industrial sensors
■
Factory automation
■
Process control
C/QO and L+ output stages are able to drive
resistive, inductive and capacitive loads. Inductive
loads up to 10 mJ can be driven.
To enable full IC control, configuration and
monitoring (i.e. fault conditions stored in the
status register), the communication between the
system microcontroller and the L6360 is based on
a Fast mode 2-wire I2C.
The L6360 has nine registers to manage the
programmable parameters and the status of the
IC.
The L6360 is a monolithic IO-Link master port
compliant with PHY2 (3 wires) supporting COM1
(4.8 kbaud), COM2 (38.4 kbaud) and COM3
(230.4 kbaud) modes.
The C/QO output stage is programmable: highside, low-side or push-pull; also cutoff current,
This is information on a product in full production.
Cutoff current and cutoff current delay time,
combined with thermal shutdown and automatic
restart protect the device against overload and
short-circuit.
The L6360 transfers, through the PHY2(C/QO
pin), data received from a host microcontroller
through the USART (IN C/QO pin), or to the
USART (OUT C/QI pin) data received from PHY2
(C/QI pin).
Description
March 2012
cutoff current delay time, and restart delay are
programmable.
Supply voltage is monitored and low voltage
conditions are detected.
Applications
■
VFQFPN-26L 3.5 x 5 x 1 mm
Monitored fault conditions are: L+ line,
overtemperature, C/Q overload, linear regulator
undervoltage, and parity check.
Internal LED driver circuitries, in open drain
configuration, provide two programmable
sequences to drive two LEDs.
Doc ID 022817 Rev 2
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65
Contents
L6360
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
2/65
6.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.4
SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.5
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1.6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.7
Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.8
I2C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.9
Internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.10
Startup default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3
Demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4
7
I²C single master bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
Fast demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.2
Slow demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I2C protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.1
Protocol configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Physical layer communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.1
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.2
IEC 61131-2 type 1 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Doc ID 022817 Rev 2
L6360
Contents
8
Diagnostic LED sequence generator and driver . . . . . . . . . . . . . . . . . 55
9
Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10
Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11
EMC protection considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2
I/O lines protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Doc ID 022817 Rev 2
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Contents
L6360
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
4/65
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical characteristics - linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical characteristics - logic inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical characteristics - LED driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical characteristics - I2C (Fast mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Main parameters typical variation vs. +/- 1% variation of Rbias value . . . . . . . . . . . . . . . . . 17
Register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ENCGQ: C/Q pull-down enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ICOQ: C/QO HS and LS cutoff current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
tdcoq: C/QO HS and LS cutoff current delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
trcoq: C/QO restart delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
tdbq: C/QI de-bounce time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ENCGI: I/Q pull-down enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CQPDG: C/Q pull-down generator switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L+COD: L+ cutoff disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
tdcol: L+ HS cutoff current delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
trcol: L+ restart delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
tdbi: I/Q de-bounce time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
C/Q output stage configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Parameters default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Registers default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Current Write mode direction bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Sequential Write mode direction bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Read mode: register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Linear regulator selection pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Supply voltage protection component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Refined supply voltage protection component description . . . . . . . . . . . . . . . . . . . . . . . . . 59
VH protection component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical protection in IO-Link applications component description . . . . . . . . . . . . . . . . . . . 61
IO-Link and SIO applications extended protection component description . . . . . . . . . . . . 62
Mechanical data for VFQFPN - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch . . . . . . . . . . . . . . . . . 63
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Doc ID 022817 Rev 2
L6360
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Rise/fall time test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Normalized rise and fall time vs. output capacitor value (typ. values in push-pull
configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
A master transmitter addressing a slave receiver with a 7-bit address
(the transfer is not changed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
A master reads data from the slave immediately after the first byte . . . . . . . . . . . . . . . . . . 19
Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I2C communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-on bit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Overtemperature (OVT) bit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cutoff behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LED1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LED2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Parity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power stage. Q2 is not present on L+ output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fast demagnetization principle schematic. Load connected to L- . . . . . . . . . . . . . . . . . . . 38
Fast demagnetization waveform. Load connected to L- . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Slow demagnetization schematic block. Load connected to L- . . . . . . . . . . . . . . . . . . . . . 39
Slow demagnetization waveform. Load connected to GND . . . . . . . . . . . . . . . . . . . . . . . . 39
Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current Write mode flow chart procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Current Write mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Sequential Write mode flow chart procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Sequential Write mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Microcontroller parity check calculus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Register sequence in sequential Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current Read mode flow chart procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current Read mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Current read communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Sequential/random Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Sequential/random read communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Block diagram communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
System communication mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
C/Q or L+ channel cutoff protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
C/Q or L+ channel current limitation and cutoff protection with latched restart . . . . . . . . . 54
LED drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Linear regulator principle schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Supply voltage protection with uni-directional Transil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Refined supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
VH protection vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Doc ID 022817 Rev 2
5/65
List of figures
Figure 47.
Figure 48.
Figure 49.
6/65
L6360
Typical protection in IO-Link applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
IO-Link and SIO applications extended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Package outline for VFQFPN - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch . . . . . . . . . . . . . . . . . . 63
Doc ID 022817 Rev 2
L6360
Block diagram
1
Block diagram
Figure 1.
Block diagram
6 $$
6(
3%,
,).%!22%'5,!4/2
%. ,
2BIAS
6##
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Table 1.
Device summary
Order code
Package
Packaging
L6360
VFQFPN 3.5 x 5 x 1 - 26 leads
Tray
L6360TR
VFQFPN 3.5 x 5 x 1 - 26 leads
Tape and reel
Doc ID 022817 Rev 2
7/65
Pin connections
2
L6360
Pin connections
Figure 2.
Pin connections (top view)
#1/ #1)
)1
,
6##
6##
,
,
,%$
6(
,%$
6$$
3!
3!
234
3!
3$!
2BIAS
3#,
3%,
)21
%.#1 ).#1 /54#1)/54)1 %.,
!-
Table 2.
8/65
Pin description
Pin
Name
1
VCC
2
Description
Type
IC power supply
Supply
L-
L- line (IC ground)
Supply
3
VH
Linear regulator supply voltage
Supply
4
VDD
Linear regulator output voltage
Output
5
SA1
Serial address 1
Input
6
SA2
Serial address 2
Input
7
Rbias
External resistor for internal reference generation
Input
8
SEL
Linear regulator 3.3 V/5 V voltage selection. Output is 5 V
when SEL pin is pulled to GND.
Input
9
ENC/Q
C/Q output enable
Input
10
INC/Q
C/Q channel logic input
Input
11
OUTC/Q
C/Q channel logic output
Output
12
OUTI/Q
I/Q channel logic output
Output
Doc ID 022817 Rev 2
L6360
Pin connections
Table 2.
Pin description (continued)
Pin
Name
Description
13
ENL+
L+ switch enable. When ENL+ is high the switch is closed
14
IRQ
Interrupt request signal (open drain)
15
SCL
Serial clock line
Input
16
SDA
Serial data line
Input/output
17
RST
Reset - active low
Input
18
SA0
Serial address 0
Input
19
LED1
Status/diagnostic LED (open drain)
Output
20
LED2
Status/diagnostic LED (open drain)
Output
21
L-
L- line (IC ground)
Supply
22
VCC
IC power supply
Supply
23
L+
L+ line
Supply
24
I/Q
I/Q channel line
Input
25
C/QI
Transceiver (C/Q channel) line
Input
26
C/QO
Transceiver (C/Q channel) line
Output
Doc ID 022817 Rev 2
Type
Input
Output
9/65
Absolute maximum ratings
L6360
3
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
Supply voltage
VCLAMP
V
VSEL
Linear regulator selection pin voltage
-0.3 to 4
V
VDD
Linear regulator output voltage
5.5
V
VH
Linear regulator input voltage
VCC
V
-0.3 to VDD + 0.3
V
voltage
-0.3 to VDD + 0.3
V
VLED1, 2
LED1, 2 voltage
-0.3 to VDD + 0.3
V
VC/QI, VI/Q
C/QI, I/Q voltage
-0.3 to VCC + 0.3
V
VRST
Reset voltage
-0.3 to VDD + 0.3
V
VIRQ
IRQ voltage
-0.3 to VDD + 0.3
V
-0.3 to 4
V
2000
V
2
A
VINC/Q, ENC/Q, ENL+ INC/Q, ENC/Q, ENL+ voltage
VSDA, SCL, SA0, 1, 2
I2 C
VRbias
External precision resistance voltage
VESD
Electrostatic discharge (human body model)
ICLAMP
Current through VCLAMP in surge test (1 kV, 500 Ω) condition
IC/QO, IL+
C/QO, L+ current (continuous)
Internally limited
A
IOUTC//Q, IOUTI/Q
OUTC/Q, OUTI/Q output current
±5
mA
ISDA
I2C transmission data current (open drain pin)
10
mA
IIRQ
Interrupt request signal current
10
mA
LED1, 2 current
10
mA
Eload
L+ demagnetization energy
10
mJ
PTOT
Power dissipation at TC = 25 °C
Internally limited
W
PLR
Linear regulator power dissipation
200
mW
Internally limited
°C
-55 to 150
°C
ILED1, 2
TJ
TSTG
10/65
Junction operating temperature
Storage temperature
Doc ID 022817 Rev 2
L6360
4
Recommended operating conditions
Recommended operating conditions
Table 4.
Symbol
Recommended operating conditions
Parameter
Test condition
Min.
Typ.
Max.
Unit
VCC
Supply voltage
18
32.5
V
VH
Linear regulator input voltage
7
VCC
V
400
kHz
0.1%
kΩ
125
°C
-
fSCL
SCL clock frequency
Rbias
Precision resistance
-0.1%
TJ
Junction temperature
-25
Table 5.
Symbol
124
Thermal data
Parameter
Typ.
Unit
Rth j-case
Thermal resistance, junction-to-case
6
°C/W
Rth j-amb
Thermal resistance, junction-to-ambient(1)
50
°C/W
1. Mounted on FR4 PCB with 2 signal Cu layers and 2 power Cu layers interconnected through vias.
Doc ID 022817 Rev 2
11/65
Electrical characteristics
5
L6360
Electrical characteristics
(18 V < VCC < 30 V; -25 °C < TJ < 125 °C; VDD = 5 V; unless otherwise specified.)
Table 6.
Symbol
VCLAMP
xxx
Electrical characteristics - power section
Parameter
Voltage clamp
Test condition
Min.
I = 5 mA
36
Typ.
Max. Unit
V
VUV
Undervoltage ON-threshold
16
17
VUVH
Undervoltage hysteresis
0.3
1
18
V
V
VREGLN5H
Linear regulator undervoltage high
threshold
SEL = L
4.3
4.7
V
VREGLN5L
Linear regulator undervoltage low
threshold
SEL = L
3.6
4.2
V
VREG5HYS
Linear regulator undervoltage
hysteresis
SEL = L
0.1
VREGLN33H
Linear regulator undervoltage high
threshold
SEL = H
2.8
3.1
V
VREGLN33L
Linear regulator undervoltage low
threshold
SEL = H
2.5
2.7
V
VREG33HYS
Linear regulator undervoltage
hysteresis
SEL = H
0.1
V
V
VQTHH
C/QI and I/Q upper voltage threshold
10.5
12.9
V
VQTHL
C/QI and I/Q lower voltage threshold
8
11.4
V
VQHY
C/Q and I/Q hysteresis voltage
1
L+ demagnetization voltage
I = 5 mA
VfHS
C/Q high-side freewheeling diode
forward voltage
I = 10 mA
0.5
V
VfLS
C/Q low-side freewheeling diode
forward voltage
I = 10 mA
0.5
V
VLTHOFF
L+ line diagnostic lower threshold
Vdemag
VLTHY
VLTHON
IS
IOFFCQ
ICOQ
12/65
-8.5
V
-6.5
9
10
L+ line diagnostic hysteresis
0.1
1
L+ line diagnostic upper threshold
10
11
-4.8
11
V
V
V
12
V
OFF-state
100
µA
ON-state VCC at 32.5 V
4
mA
Supply current
OFF-state C/QO current
ENC/Q = 0, VC/Q = 0 V
C/QO low- and high-side cutoff current
Programmable
(see Control register 1)
Doc ID 022817 Rev 2
1
µA
70
115
190
mA
150
220
300
mA
290
350
440
mA
430
580
720
mA
L6360
Table 6.
Electrical characteristics
Electrical characteristics - power section (continued)
Symbol
Parameter
Test condition
Min.
ILIMQ
C/QO low- and high-side limitation
current
IOFFL
L+ OFF-state current
ICOL
L+ cutoff current
480
ILIML
L+ limitation current
IINC/Qi
C/QI pull-down current
IINI/Q
I/Q pull-down current
RONL
L+ high-side ON-state resistance
Typ.
500
1600
mA
0
200
µA
730
mA
500
1600
mA
Programmable (see section
Control register 2)
5
6.5
mA
2
3.3
mA
(see Control register 2)
2
3
mA
ENL+ = 0,
VL+ = 0 V
IOUT = 0.2 A at TJ = 25 °C
580
C/QO high-side ON-state resistance
RONCQL
C/QO low-side ON-state resistance
tdINC/Q
INC/Q to C/QO propagation delay time
tENC/Q
ENC/Q to C/QO propagation delay time
Ω
1
IOUT = 0.2 A at TJ = 125 °C
RONCQH
Max. Unit
2
IOUT = 0.2 A at TJ = 25 °C
Ω
1
IOUT = 0.2 A at TJ = 125 °C
2
IOUT = 0.2 A at TJ = 25 °C
Ω
Ω
0.6
IOUT = 0.2 A at TJ = 125 °C
Ω
1.2
Ω
Push-pull (CQO rising edge)
140
ns
Push-pull (CQO falling edge)
160
ns
Push-pull (CQO rising edge)
110
ns
Push-pull (CQO falling edge)
225
ns
trPP
C/Q rise time in push-pull
configuration
10% to 90%. See Figure 3
250
860
ns
tfPP
C/Q fall time in push-pull configuration
10% to 90%. See Figure 3
290
860
ns
trHS
C/Q rise time in high-side
configuration
410
ns
tfHS
C/Q fall time in high-side configuration
700
ns
trLS
C/Q rise time in low-side configuration
750
ns
tfLS
C/Q fall time in low-side configuration
530
ns
tENL
ENL to L+ propagation delay time
1
µs
trL+
L+ rise time
3
µs
tfL+
L+ fall time
25
µs
C/QI to OUTC/Q (falling) propagation
delay time
40
ns
C/QI to OUTC/Q (rising) propagation
delay time
100
ns
I/Q to OUTI/Q (falling) propagation
delay time
40
ns
I/Q to OUTI/Q (rising) propagation
delay time
100
ns
tdC/Qi
tdI/Q
Doc ID 022817 Rev 2
13/65
Electrical characteristics
Table 6.
Symbol
tdcoq
trcoq
tdbq
tdbl
L6360
Electrical characteristics - power section (continued)
Parameter
Test condition
C/QO low- and high-side cutoff current
delay time
Programmable
(see Control register 1)
Programmable
(see Control register 1)
C/QO restart delay time
Max. Unit
100
µs
150
µs
200
µs
250
µs
255 × tdcoq
Latched(1)
µs
5
µs
20
µs
100
µs
0
µs
5
µs
20
µs
100
µs
Programmable
(see Control register 2)
500
µs
0
µs
Programmable
(see Control register 2)
64
ms
Programmable
(see Control register 2)
I/Q de-bounce time
Typ.
0
Programmable
(see Control register 1)
C/QI de-bounce time
Min.
tdcol
L+ cutoff current delay time
trcol
L+ restart delay time
TJSD
Junction temperature shutdown
150
°C
TJHYST
Junction temperature thermal
hysteresis
20
°C
TJRST
Junction temperature restart threshold
130
°C
1. Unlatch through I2C communication.
14/65
Doc ID 022817 Rev 2
Latched(1)
L6360
Table 7.
Electrical characteristics
Electrical characteristics - linear regulator
Symbol
Parameter
VDD
Linear regulator output voltage
ILIMLR
Linear regulator output current
limitation
Table 8.
Min.
Typ.
Max.
Unit
SEL = L
4.84
5
5.13
V
SEL = H
3.22
3.3
3.37
V
65
Parameter
VIL
Input low-level voltage
VIH
Input high-level voltage
VIHIS
Input hysteresis voltage
Input current
Test condition
Max.
Unit
0.8
V
V
V
VIN = 5 V
1
µA
0.5
V
IOUT = -2 mA
VOH
Output high-level voltage
IOUT = 2 mA
Open drain output low-level
voltage
IOUT = 2 mA
VDD - 0.5 V
V
0.5
V
Max.
Unit
0.5
V
Electrical characteristics - LED driving
Symbol
Parameter
VLED1, 2
Open drain output low-level
voltage
ILED
LED1, 2 leakage current
Table 10.
Typ.
0.2
Output low-level voltage
Table 9.
Min.
2.2
VOL
VLIRQ
mA
Electrical characteristics - logic inputs and outputs
Symbol
IIN
Test condition
Test condition
ILED = 2 mA
Min.
Typ.
-
VLED1 = VLED2 = 5 V
3
nA
Electrical characteristics - I2C (Fast mode)(1)
Symbol
Parameter
VIL(SDA)
SDA low-level input voltage
VIH(SDA)
SDA high-level input voltage
VIL(SCL)
SCL low-level input voltage
VIH(SCL)
SCL high-level input voltage
IIN
I2C
SDA, SCL input current
tr(SDA)
I2C
tr(SCL)
I2C
tf(SDA)
tf(SCL)
Test condition
Min.
Max.
Unit
0.3
V
0.7 x VDD
V
0.3
0.7 x VDD
(0.1 x VDD) <VIN < (0.9 x VDD)
V
V
-10
10
µA
SDA rise time
20 + 0.1 Cb
300
ns
SCL rise time
20 + 0.1 Cb
300
ns
I2C SDA fall time
20 + 0.1 Cb
300
ns
I2C
20 + 0.1 Cb
300
ns
SCL fall time
tsu(SDA)
SDA setup time
th(SDA)
SDA hold time
100
ns
0.9
Doc ID 022817 Rev 2
µs
15/65
Electrical characteristics
Table 10.
L6360
Electrical characteristics - I2C (Fast mode)(1) (continued)
Symbol
Parameter
Test condition
Min.
Max.
Unit
tsu(STA)
Repeated START condition
setup
0.6
µs
tsu(STO)
STOP condition setup time
0.6
µs
STOP to START condition time
(bus free)
1.3
µs
tw(SCLL)
SCL clock low time
1.3
µs
tw(SCLH)
SCL clock high time
0.6
µs
tw(START/STOP)
Cb
Capacitance for each bus line
400
pF
CI
Capacitance for each I/O pin
10
pF
1. Values based on standard I2C protocol requirement.
Figure 3.
Rise/fall time test setup
#1/
N&
N&
,
!-
Figure 4.
Normalized rise and fall time vs. output capacitor value (typ. values in push-pull
configuration)
T200
T&00
#N&
!-
16/65
Doc ID 022817 Rev 2
L6360
Table 11.
Electrical characteristics
Main parameters typical variation vs. +/- 1% variation of Rbias value
Typ. variation vs. Rbias
Symbol
Parameter
Rbias [kΩ]
122.74
124
125.24
Supply current
0.76%
0
-0.50%
IINC/Qi
Input current C/QI pin (5.5 mA)
0.93%
0
-0.93%
IINC/Qi
Input current C/QI pin (2.5 mA)
0.75%
0
-1.13%
IINI/Q
Input current I/Q pin (2.5 mA)
0.85%
0
-0.85%
tdcoq
C/QO low- and high-side cutoff current delay time
-2.44%
0
2.00%
ICOQ
C/QO low- and high-side cutoff current (115 mA)
1.19%
0
-1.28%
tdcol
L+ cutoff current delay time (500 µs)
-0.95%
0
0.47%
ICOL
L+ cutoff current
1.36%
0
-0.91%
trcol
L+ restart delay time
-0.93%
0
0.97%
VUV
Undervoltage ON-threshold
0.00%
0
0.00%
VDD
Linear regulator output voltage (3.3 V)
-0.03%
0
0.03%
VDD
Linear regulator output voltage (5 V)
-0.02%
0
0.02%
ILIMQ
C/QO high-side limitation current
0.64%
0
-0.71%
ILIMQ
C/QO low-side limitation current
0.28%
0
-1.47%
ILIML
L+ limitation current
0.47%
0
-2.09%
VQTHH
C/QI and I/Q upper voltage threshold
0.00%
0
0.00%
VQTHL
C/QI and I/Q lower voltage threshold
0.00%
0
0.00%
VQHY
C/Q and I/Q hysteresis voltage
0.00%
0
0.00%
trPP
C/Q rise time in push-pull configuration
-1.59%
0
1.18%
tfPP
C/Q fall time in push-pull configuration
-2.14%
0
0.94%
tdINC/Q
INC/Q to C/QO propagation delay time
-1.44%
0
0.75%
tdINC/Q
INC/Q to C/QO propagation delay time
-2.36%
0
0.18%
tdC/Qi
C/QI to OUTC/Q propagation delay time
0.49%
0
1.13%
tdC/Qi
C/QI to OUTC/Q propagation delay time
1.82%
0
0.03%
tdbq
C/QI de-bounce time (100 µs)
-1.76%
0
1.50%
tdcoq
C/QO low- and high-side cutoff current delay time (200 µs)
-1.27%
0
2.00%
ICOQ
C/QO low-side cutoff current (220 mA)
0.39%
0
-1.56%
ICOQ
C/QO low-side cutoff current (350 mA)
0.36%
0
-1.43%
ICOQ
C/QO low-side cutoff current (580 mA)
0.65%
0
-1.72%
trcoq
C/QO restart delay time
-0.90%
0
0.97%
ICOQ
C/QO high-side cutoff current (220 mA)
0.84%
0
-0.84%
ICOQ
C/QO high-side cutoff current (350 mA)
1.38%
0
-0.69%
ICOQ
C/QO high-side cutoff current (580 mA)
1.08%
0
-1.08%
Is
Doc ID 022817 Rev 2
17/65
Device configuration
6
L6360
Device configuration
SDA and SCL configure the L6360 device through I2C.
6.1
I²C single master bus interface
6.1.1
Introduction
The I2C bus interface serves as an interface between the microcontroller and the serial I2C
bus.
It provides single master functions, and controls all I2C bus-specific sequencing, protocol
and timing.
It supports fast I2C mode (400 kHz).
6.1.2
6.1.3
Main features
●
Parallel bus / I2C protocol converter
●
Interrupt generation
●
Fast I2C mode
●
7-bit addressing.
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa.
The interface is connected to the I2C bus by a data pin (SDA) and a clock pin (SCL).
6.1.4
SDA/SCL line control
SDA is a bi-directional line, SCL is the clock input. SDA should be connected to a positive
supply voltage via a current-source or pull-up resistor. When the bus is free, both lines are
HIGH.
The output stages of devices connected to the bus must have an open drain or open
collector output to perform the wired AND function. Data on the I2C bus can be transferred
at rates up to 400 Kbit/s in fast mode.
The number of interfaces connected to the bus is limited by the bus capacitance.
For a single master application, the master's SCL output can be a push-pull driver provided
that there are no devices on the bus which would stretch the clock.
Transmitter mode: the microcontroller interface holds the clock line low before transmission.
Receiver mode: the microcontroller interface holds the clock line low after reception.
When the I2C microcontroller cell is enabled, the SDA and SCL ports must be configured as
floating inputs.
In this case, the value of the external pull-up resistors used depends on the application.
18/65
Doc ID 022817 Rev 2
L6360
Device configuration
When the I2C microcontroller cell is disabled, the SDA and SCL ports revert to being
standard I/O port pins.
On the L6360, the SDA output is an open drain pin.
6.1.5
Mode selection
Possible data transfer formats are:
●
The master transmitter transmits to the slave receiver. The transfer direction is not
changed (see Figure 5).
●
The slave receiver acknowledges each byte.
●
The master reads data from the slave immediately after the first byte (see Figure 6). At
the moment of the first acknowledge, the master transmitter becomes a master receiver
and the slave receiver becomes a slave transmitter.
This first acknowledge is still generated by the slave.
Subsequent acknowledges are generated by the master. The STOP condition is generated
by the master which sends a not-acknowledge (A) just prior to the STOP condition.
Figure 5.
A master transmitter addressing a slave receiver with a 7-bit address
(the transfer is not changed)
3
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Figure 6.
A master reads data from the slave immediately after the first byte
3
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Doc ID 022817 Rev 2
19/65
Device configuration
L6360
On the microcontroller, the interface can operate in the two following modes:
●
Master transmitter/receiver
●
Idle mode (default state)
The microcontroller interface automatically switches from idle to master receiver after it
detects a START condition and from master receiver to idle after it detects a STOP
condition.
On the L6360 the interface can operate in the two following modes:
●
Slave transmitter/receiver
●
Idle mode (default state)
The interface automatically switches from idle to slave transmitter after it detects a START
condition and from slave transmitter to idle after it detects a STOP condition.
6.1.6
Functional description
By default, the I2C microcontroller interface operates in idle; to switch from default Idle mode
to Master mode a START condition generation is needed.
The transfer sequencing is shown in Figure 7.
Figure 7.
Transfer sequencing
B ITM ASTER TRANSMITTER MICROCONTROLLERSLAVERECEIVER,
3
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!.!
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0
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BIT MASTER RECEIVER MICROCONTROLLER SLAVE TRANSMITTER ,
3
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27
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x
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FROMMASTERTOSLAVE
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!-
20/65
Doc ID 022817 Rev 2
L6360
6.1.7
Device configuration
Communication flow
The communication is managed by the microcontroller that generates the clock signal.
A serial data transfer always begins with a START condition and ends with a STOP
condition.
Data is transferred as 8-bit bytes, MSB first.
The first byte following the START condition contains the address (7 bits). A 9th clock pulse
follows the 8th clock cycle of a byte transfer, during which the receiver must send an
acknowledge bit to the transmitter.
Figure 8.
I2C communication
Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in the
sequence. A START condition immediately followed by a STOP condition (void message) is
a prohibited format.
6.1.8
I2C address
Each I2C connected to the bus is addressable by a unique address.
The I2C address is 7 bits long, and there is a simple master/slave relationship.
The LSB of the L6360 address can be programmed by means of dedicated IC pins (SA0,
SA1 and SA2, which can be hard wired to VDD or GND, or handled by µC outputs): the
microcontroller can interface up to 8 L6360 ICs.
The I2C inside the device has 5 pins:
●
SDA: data
●
SCL: clock
●
SA0: LSB of L6360 address
●
SA1: bit 1 of L6360 address
●
SA2: bit 2 of L6360 address
Doc ID 022817 Rev 2
21/65
Device configuration
L6360
The I2C L6360 IC address is:
●
Fixed part (4 MSBits): set to “1100”
●
Programmable part (3 LSBits) by hardware: from “000 to 111" connecting SAx pins to
GND or VDD.
In L6360 the SDA is an open drain pin.
6.1.9
Internal registers
The L6360 has some internal registers to perform control, configuration, and diagnostic
operations.
These registers are listed below:
●
Status register
●
Configuration register
●
Control register 1
●
Control register 2
●
LED1 register MSB
●
LED1 register LSB
●
LED2 register MSB
●
LED2 register LSB
●
Parity register.
Each register is addressable:
Table 12.
22/65
Register addresses
Address
Register name
0000
Status register
0001
Configuration register
0010
Control register 1
0011
Control register 2
0100
LED1 MSB
0101
LED1 LSB
0110
LED2 MSB
0111
LED2 LSB
1000
Parity register
Doc ID 022817 Rev 2
L6360
Device configuration
Status register
Read only
Reset Value: [00000000]
Figure 9.
0/
Status register
/64
#1/,
,/,
2%'
,.
0%
!-
The status register stores diagnostic information. It can be read to check the status of the
run-time of the device (faults, warning, transmission corrupted, etc.).
When a fault condition occurs, a bit (corresponding to the fault condition) in the status
register is set and an interrupt (via the IRQ pin) is generated.
If there is no persistent fault condition, the status register is cleared after a successful
current read.
Bit 7 = PO:
Power-on (L+ line).
This bit indicates the status of L+ line voltage.
If the voltage goes under the lower threshold (VLTHOFF) and ENL+ is
high, the PO bit is set. It is reset after a successful current read if the L+
voltage has returned above the upper threshold VLTHON and the read
operation has begun after the bit has been set.
When the PO bit is high, IRQ is generated.
During ENL+ transition (from low-level to high-level) and during L+ line
voltage transition, a fault condition is reported setting the PO bit and
activating the IRQ pin. To reset the fault a successful current read is
necessary.
Doc ID 022817 Rev 2
23/65
Device configuration
L6360
Figure 10. Power-on bit behavior
#URRENTREAD
6 ,
6,(934
6 4(/.
6 4(/&&
0/
!-
Bit 6 = not used: always at zero
Bit 5 = OVT:
Overtemperature fault
This bit indicates the status of the IC internal temperature.
If the temperature goes above the thermal shutdown threshold (T > TJSD)
the OVT bit is set. It is reset after a successful current read if the
temperature has returned below the thermal restart threshold (TJDS TJHIST) and the read operation has begun after the bit has been set.
When OVT bit is high, the power outputs are disabled and IRQ is
generated.
Figure 11. Overtemperature (OVT) bit behavior
#URRENTREAD
4*
4*3$
4*(934
4*234
/64
!-
24/65
Doc ID 022817 Rev 2
L6360
Device configuration
Bit 4 = CQOL: C/Q overload
This bit is set if a cutoff occurs on the C/Q channel.
It is reset after a successful current read if the restart delay time (trcoq)
has elapsed or the protection is latched (bit trcoq = 1 in Control register 1).
The read operation should begin after the CQOL bit has been set. See also
the Control register 1 and Transceiver sections.
When CQOL bit is high, IRQ is generated.
When CQOL bit is high and the protection is latched (bit trcoq = 1 in
Control register 1), the C/Q power output is disabled. See Figure 12.
Figure 12. Cutoff behavior
#URRENTREAD
#1DRIVERDISABLED
#ONTROL
REGISTER
)#/ 1
T DCOQ 88
T RCOQ
T
T DCOQ
T RCOQ
#1/,
T
#URRENTREAD
#1DRIVERDISABLED
)#/1
#ONTROL
REGISTER
T DCOQ
T
T DCOQ 88
T RCOQ
T RCOQ
#1/,
T
!-
Doc ID 022817 Rev 2
25/65
Device configuration
L6360
Bit 3 = LOL:
L+ overload
This bit is set if a cutoff occurs on the L+ driver.
It is reset after a successful current read if the restart delay time (trcol)
has elapsed or the protection is latched (bit trcol = 1 in Control register 2).
The read operation should begin after the LOL bit has been set. See also
the Control register 2 and Transceiver sections.
When LOL bit is high, IRQ is generated.
When LOL bit is high and the protection is latched (bit trcol = 1 in
Control register 2), the L+ power output is disabled.
The behavior is the same as the C/Q driver (see Figure 12).
Bit 2 = not used: always at zero
Bit 1 = REG LN: Linear regulator undervoltage fault
This bit is set in case of undervoltage of the linear regulator output
(VREGLNL). It is reset after a successful current read if the linear
regulator output has returned to normal operation and the read operation
has begun after the bit has been set.
When REG LN bit is high, IRQ is generated.
Bit 0 = PE:
Parity check error
This flag is set if parity error occurs.
Control register 1
Read/write
Reset value: [00100001]
Figure 13. Control register 1
The control register holds the parameters to control the L6360. See also the Transceiver
section.
Bit 7 = ENCGQ:
Table 13.
ENCGQ: C/Q pull-down enable
ENCGQ
Pull-down generator status
0
Always OFF
1
26/65
C/QI pull-down enable
If ENC/Q = 0
ON
If ENC/Q = 1
OFF
Doc ID 022817 Rev 2
L6360
Device configuration
Bit 6:5 = ICOQ [1:0]: C/QO HS and LS cutoff current
This bit is used to configure the cutoff current value on the C/Q
channel, as shown in Table 14.
Table 14.
ICOQ: C/QO HS and LS cutoff current
Icoq [1]
Icoq[0]
Typ.
0
0
115 mA
0
1
220 mA
1
0
350 mA
1
1
580 mA
Bit 4:3 = tdcoq [1:0]: C/QO HS and LS cutoff current delay time
The channel output driver is turned off after a delay (tdcoq)
programmable by means of these two bits:
Table 15.
tdcoq: C/QO HS and LS cutoff current delay time
tdcoq [1]
tdcoq[0]
Typ.
0
0
100 µs
0
1
150 µs
1
0
200 µs
1
1
250 µs(1)
1. According to power dissipation at 2 kHz switching, C < 1 µF, power dissipation 0.7 W.
Bit 2
= trcoq:
C/QO restart delay time
After a cutoff event, the channel driver automatically restarts after
a delay (trcoq) programmable by means of this bit:
Table 16.
trcoq: C/QO restart delay time
trcoq
Typ.
0
255 x tdcoq
1
Latched(1)
1. Unlatch through I2C communication (reading or writing any internal registers).
Doc ID 022817 Rev 2
27/65
Device configuration
L6360
Bit 1:0 = tdbq [1:0]: C/QI de-bounce time
De-bounce time is the minimum time that data must be in a given state
after a transition.
It is a programmable time, and can be configured as shown in
Table 17.
Table 17.
tdbq: C/QI de-bounce time
tdbq [1]
tdbq [0]
Typ.
0
0
0 µs
0
1
5 µs
1
0
20 µs
1
1
100 µs
Control register 2
Read/write
Reset value: [0x100001]
Figure 14. Control register 2
%. #')
#1 0$'
, #/$
T DCOL
T RCOL
T DBI
T DBI !-
The control register holds the parameters to control the L6360. See also the Transceiver
section.
Bit 7
= ENCGI:
.
Table 18.
I/Q pull-down enable
ENCGI: I/Q pull-down enable
Bit 5 = CQPDG:
ENCGI
Pull-down generator status
0
Always OFF
1
Always ON
C/Q, channel pull-down generators
In order to reduce consumption, it is possible to switch from default to
low-power configuration by resetting the CQPDG bit.
.
Table 19.
28/65
CQPDG: C/Q pull-down generator switching
CQPDG
Pull-down generator status
0
IINI/Qi (input current C/QI pin) = 2.5 mA
1
IINC/Qi (input current C/QI pin) = 5.5 mA
Doc ID 022817 Rev 2
L6360
Device configuration
Bit 4 = L+COD:
L+ cutoff disable
The cutoff function on the L+ switch can be enabled or disabled
according to the L+COD bit.
Table 20.
L+COD: L+ cutoff disable
L+COD
L+ cutoff current status
0
Enabled
1
Disabled
As the cutoff function is intended to protect the integrated switches against overload and
short-circuit, disabling the cutoff is not recommended.
Bit 3
= tdcol:
L+ cutoff current delay time
The channel output driver is turned off after a delay (tdcol)
programmable by means of this bit:
Table 21.
tdcol: L+ HS cutoff current delay time
Bit 2 = trcol:
tdcol
Typ.
0
500 µs
1
0 µs
L+ restart delay time
After a cutoff event, the channel driver automatically restarts again
after a delay (trcol) programmable by means of this bit:
Table 22.
trcol: L+ restart delay
trcol
Typ.
0
64 ms
1
Latched(1)
1. Unlatch through I2C communication (reading or writing any internal registers).
Bit 1:0 = tdbi [1:0]:
I/Q de-bounce time
De-bounce time is the minimum time that data must be in a given
state after a transition. It is a programmable time, and it can be
configured as shown in Table 23.
Table 23.
tdbi: I/Q de-bounce time
tdbi [1]
tdbi [0]
Typ.
0
0
0 µs
0
1
5 µs
1
0
20 µs
1
1
100 µs
Doc ID 022817 Rev 2
29/65
Device configuration
L6360
Configuration register
Read/write
Reset value: [100xxxxx]
Figure 15. Configuration register
#1
#1
#1
!-
The configuration register holds data to configure the L6360 IC.
Bit 7:5 = C/Q[2:0]:
Table 24.
C/Q output stage configuration
C/Q output stage configuration
C/Q[2] C/Q[1] C/Q[0] Configuration
0
0
0
0
0
1
OFF
Low-side
Notes
HS and LS are OFF regardless of the state of ENC/Q and INC/Q.
The receiver is OFF regardless of the state of ENC/Q.
HS is always disabled.
LS is ON when INC/Q is high and ENC/Q is high, OFF in all other cases.
Slow asynchronous decay when the LS is turned off by ENC/Q or in case
of cutoff.
The receiver is OFF when ENC/Q is high: OUTC/Q is high.
The receiver is ON when ENC/Q is low:
if C/QI is high, OUTC/Q is low.
if C/QI is low, OUTC/Q is high.
0
1
0
High-side
LS is always disabled.
HS is ON when INC/Q is low and ENC/Q is high, OFF in all other cases.
Slow asynchronous decay if the HS is turned off by ENC/Q or in case of
cutoff.
The internal pull-down current generator on C/QI should be disabled
through Control register 1, unless C/QI is connected to C/QO through
a 100 Ω (or more) resistor.
The receiver is OFF when ENC/Q is high: OUTC/Q is high.
The receiver is ON when ENC/Q is low:
if C/QI is high, OUTC/Q is low.
if C/QI is low, OUTC/Q is high.
30/65
Doc ID 022817 Rev 2
L6360
Device configuration
Table 24.
C/Q output stage configuration (continued)
C/Q[2] C/Q[1] C/Q[0] Configuration
0
1
1
Push-pull
Notes
INC/Q low and ENC/Q high: HS ON and LS OFF.
INC/Q high and ENC/Q high: LS ON and HS OFF.
If ENC/Q is low, both HS and LS are OFF.
Slow asynchronous decay in case of cutoff or turn-off of both switches.
An internal deadtime is generated between each LS turn-off and the
following HS turn-on and between each HS turn-off and the following LS
turn-on.
The receiver is OFF when ENC/Q is high: OUTC/Q is high.
The receiver is ON when ENC/Q is low:
if C/QI is high, OUTC/Q is low.
if C/QI is low, OUTC/Q is high.
HS and LS are OFF regardless of the state of ENC/Q and INC/Q.
The receiver is OFF when ENC/Q is high: OUTC/Q is high.
1
0
0
TRISTATE
The receiver is ON when ENC/Q is low:
if C/QI is high, OUTC/Q is low.
if C/QI is low, OUTC/Q is high.
1
0
1
Low-side ON
LS is ON regardless of the state of ENC/Q and INC/Q.
Slow asynchronous decay in case of cutoff.
The receiver is OFF when ENC/Q is high: OUTC/Q is high
The receiver is ON when ENC/Q is low:
if C/QI is high, OUTC/Q is low.
if C/QI is low, OUTC/Q is high.
1
1
0
High-side ON
HS is ON regardless of the state of ENC/Q and INC/Q.
Slow asynchronous decay in case of cutoff.
The receiver is OFF when ENC/Q is high: OUTC/Q is high.
The receiver is ON when ENC/Q is low:
if C/QI is high, OUTC/Q is low.
if C/QI is low, OUTC/Q is high.
1
1
1
INC/Q low and ENC/Q high: HS ON and LS OFF.
INC/Q high and ENC/Q high: LS ON and HS OFF.
If ENC/Q is low, both HS and LS are OFF.
Slow asynchronous decay in case of cutoff or turn-off of both switches.
An internal deadtime is generated between each LS turn-off and the
Push-pull
following HS turn-on and between each HS turn-off and the following LS
inductive load
turn-on.
The receiver is OFF when ENC/Q is high: OUTC/Q is high.
The receiver is ON when ENC/Q is low:
if C/QI is high, OUTC/Q is low.
if C/QI is low, OUTC/Q is high.
Note:
See also the Demagnetization section.
Doc ID 022817 Rev 2
31/65
Device configuration
L6360
In order to reduce the risk of damage to the output stage (e.g. switching from push-pull
inductive load to any transceiver configuration while an inductive load has some residual
energy), the user must not switch between any two “active” (low-side, high-side, push-pull,
low-side ON, high-side ON, push-pull inductive load) configurations of the bridge.
For example, if the microcontroller needs to switch from push-pull to high-side configuration,
it needs to modify the configuration register twice:
First-step: switch from push-pull to OFF (or TRISTATE)
Second-step: switch from OFF (or TRISTATE) to high-side
If the microcontroller asks for a forbidden jump between configurations, the IC remains in
the previous configuration and reports a parity error to the microcontroller.
In case of sequential write, no parity error is generated if the microcontroller rewrites the
configuration register with the previous value; if the operation, instead, requires a forbidden
jump, all data are rejected also for other registers (and a parity error is raised).
The L+ switch is a high-side switch. HS is ON when ENL+ is high, otherwise it is OFF. Fast
decay with active clamp (-Vdemag) is operated when the HS is turned off or in the case of
cutoff.
Receiver I/Q is always ON.
Bit 4:2 = not used
Bit 1:0 = not used
LED registers
See also the Diagnostic LED sequence generator and driver section.
These registers are used to configure the two LED drivers integrated in the IC. Each LED
driver has two associated registers and turns on or off the external LED according to the
information stored in the registers, which are scanned with a rate of 63 ms per bit. LED
drivers can be used for status or diagnostic information, or for other purposes, and should
be configured by the host microcontroller.
LED1 registers
Reset value: [00000000]
Figure 16. LED1 registers
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2 ,2
,2
,2
,2
,2
!-
32/65
Doc ID 022817 Rev 2
L6360
Device configuration
LED2 registers
Reset value: [00000000]
Figure 17. LED2 registers
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
,2
!-
Parity register
Read only
Reset value: [00000000]
Figure 18. Parity register
This register stores the parity of each register, calculated after the L6360 receives data
registers.
Bit 7 = SR:
Status register parity
This bit is the parity of the status register.
Bit 6 = CR:
Configuration register parity
This bit is the parity of the configuration register.
Bit 5 = CT1:
Control register 1 parity
This bit is the parity of control register 1.
Bit 4 = CT2:
Control register 2 parity
This bit is the parity of control register 2.
Bit 3 = L1H:
LED1 high register parity
This bit is the parity of the LED1 MSB register (15 down to 8).
Bit 2 = L1L:
LED1 low register parity
This bit is the parity of the LED1 LSB register (7 down to 0).
Bit 1 = L2H:
LED2 high register parity
This bit is the parity of the LED2 MSB register (15 down to 8).
Bit 0 = L2L:
LED2 low register parity
This bit is the parity of the LED2 LSB register (7 down to 0).
Doc ID 022817 Rev 2
33/65
Device configuration
6.1.10
L6360
Startup default configuration
Table 25 and Table 26 show the device registers default configuration.
Table 25.
Table 26.
Parameters default configuration
Parameter
Default value
Icoq
220 mA
tdcoq
100 µs
trcoq
25 ms
tdbq
5 µs
tdcol
0 µs
trcol
64 ms
tbdq
5 µs
Output stage
TRISTATE
Registers default configuration
Registers
Bit position
Bit name
Reset value
Bit 7
PO
0
Bit 6
Not used
x
Bit 5
OVT
0
Bit 4
CQOL
0
Bit 3
IQOL
0
Bit 2
Not used
x
Bit 1
REG LN
0
Bit 0
PE
0
Bit 7
C/Q2
1
Bit 6
C/Q1
0
Bit 5
C/Q0
0
Bit 4
Not used
x
Bit 3
Not used
x
Bit 2
Not used
x
Bit 1
Not used
x
Bit 0
Not used
x
Status register
Configuration register
34/65
Doc ID 022817 Rev 2
L6360
Device configuration
Table 26.
Registers default configuration (continued)
Registers
Bit position
Bit name
Reset value
Bit 7
ENCGQ
0
Bit 6
Icoq1
0
Bit 5
Icoq0
1
Bit 4
tdcoq1
0
Bit 3
tdcoq0
0
Bit 2
trcoq
0
Bit 1
tdbq1
0
Bit 0
tdbq0
1
Bit 7
ENCGI
0
Bit 6
Not used
x
Bit 5
CQPDG
1
Bit 4
L+COD
0
Bit 3
tdcoi0
0
Bit 2
trcoi
0
Bit 1
tdbi1
0
Bit 0
tdbi0
1
Bit 7
L1R15
0
Bit 6
L1R14
0
Bit 5
L1R13
0
Bit 4
L1R12
0
Bit 3
L1R11
0
Bit 2
L1R10
0
Bit 1
L1R9
0
Bit 0
L1R8
0
Bit 7
L1R7
0
Bit 6
L1R6
0
Bit 5
L1R5
0
Bit 4
L1R4
0
Bit 3
L1R3
0
Bit 2
L1R2
0
Bit 1
L1R1
0
Bit 0
L1R0
0
Control register 1
Control register 2
LED1 register MSB
LED1 register LSB
Doc ID 022817 Rev 2
35/65
Device configuration
Table 26.
L6360
Registers default configuration (continued)
Registers
Bit position
Bit name
Reset value
Bit 7
L2R15
0
Bit 6
L2R14
0
Bit 5
L2R13
0
Bit 4
L2R12
0
Bit 3
L2R11
0
Bit 2
L2R10
0
Bit 1
L2R9
0
Bit 0
L2R8
0
Bit 7
L2R7
0
Bit 6
L2R6
0
Bit 5
L2R5
0
Bit 4
L2R4
0
Bit 3
L2R3
0
Bit 2
L2R2
0
Bit 1
L2R1
0
Bit 0
L2R0
0
Bit 7
SR
0
Bit 6
CR
0
Bit 5
CT1
0
Bit 4
CT2
0
Bit 3
L1H
0
Bit 2
L1L
0
Bit 1
L2H
0
Bit 0
L2L
0
LED2 register MSB
LED2 register LSB
Parity register
6.2
Interrupt
The IRQ pin (interrupt pin) should normally be held to a high logic level by an external pullup resistor or microcontroller pin configuration. The internal structure is an open drain
transistor.
It should be connected directly to the microcontroller so, in the case of a fault event (C/Q
overload, power-on L+ line, overtemperature condition, etc.), it is pulled down to a low logic
level, reporting the fault condition to the microcontroller. See also the Status register section.
36/65
Doc ID 022817 Rev 2
L6360
6.3
Device configuration
Demagnetization
The power stage can be represented as in Figure 19.
Figure 19. Power stage. Q2 is not present on L+ output
When a power stage output (C/Q or L+) is connected to an inductance, the energy stored in
the load is:
Equation 1
1 2
E = --- LI
2
This energy must be properly dissipated at the switch-off. Without an appropriate circuitry
the output voltage would be pulled to very negative values, therefore recovering the stored
energy through the power transistor's breakdown.
To avoid this, the output voltage must be clamped so that the voltage across the power
switch does not exceed its breakdown voltage.
In the case of load connected between the C/QO pin and VCC, at switch-off (of the low-side
switch) the output is pushed to a voltage higher than VCC.
Doc ID 022817 Rev 2
37/65
Device configuration
6.3.1
L6360
Fast demagnetization
Applies to L+ channel only.
Figure 20. Fast demagnetization principle schematic. Load connected to L-
When a high-side driver turns off an inductance, a reversed polarity voltage appears across
the load.
The output pin (L+) of the power switch becomes more negative than the ground until it
reaches the demagnetization voltage, Vdemag. The conduction state of the power switch Q1
is linearly modulated by an internal circuitry in order to keep the voltage at C/Q or the I/Q pin
at about Vdemag until the energy in the load has been dissipated. The energy is dissipated in
both IC internal switch and load resistance.
Figure 21. Fast demagnetization waveform. Load connected to L-
38/65
Doc ID 022817 Rev 2
L6360
6.3.2
Device configuration
Slow demagnetization
Applies to C/Q channel.
Figure 22. Slow demagnetization schematic block. Load connected to L-
When a high-side driver turns off an inductance a reversed polarity voltage appears across
the load.
In slow demagnetization configuration the low-side switch Q2 is ON and the C/Q pin is
pulled at a voltage slightly (depending on Q2 drop) below the ground (L-). The energy is
dissipated in both the IC internal switch and the load resistance.
In the case of load connected between the C/Q pin and VCC, at switch-off (of the low-side
switch Q2), the switch Q1 is ON and the output is pushed to a voltage slightly higher than
VCC.
Figure 23. Slow demagnetization waveform. Load connected to GND
Doc ID 022817 Rev 2
39/65
Device configuration
L6360
6.4
I2C protocol
6.4.1
Protocol configuration
Figure 24. Device initialization
-ICROCONTROLLER
INITIALIZATION
7RITEMODE
%XIT
0ARITY
CHECK
.
2ESEND
FAILED
REGISTERS
9
2EAD
MODE
7521
!-
Microcontroller initialization: Microcontroller initialization phase.
Write mode: The L6360 is configured by the microcontroller through I2C.
To configure the device, it is necessary to write its internal registers (see Write modes
section).
Parity check: L6360 calculates the parity of each received register and stores it in the parity
register. After which, it compares it with the parity transmitted together with the data.
If the parity check of one or more registers failed, the “parity error bit” in the status register is
set and an interrupt is generated by the L6360.
The microcontroller can now read the status register and the parity register (current read).
So the microcontroller can understand the interrupt cause and which register failed the
transmission. If the parity check is ok, the flow goes on (Read modes).
Write register failed: The microcontroller can again write the register(s) that failed the
check.
Read mode: Read status register to monitor if the configuration was good (Read modes).
40/65
Doc ID 022817 Rev 2
L6360
6.4.2
Device configuration
Operating modes
Write modes
The L6360 is configured by the microcontroller through I2C. To configure the device, it is
necessary to write its internal registers.
There are two writing modes:
●
Current: single register
●
Sequential: all registers in sequence
Current Write mode
The microcontroller I2C is configured as master transmitter.
The L6360 I2C is configured as the slave receiver.
Figure 25. Current Write mode flow chart procedure
7RITE
MODE
#522%.4
#URRENT 2EADMODE
3TARTCONDITION
-ICROCONTROLLER SENDS
SLAVEADDRESS
$ATAREGISTER
TRANSMISSION
!DDRESS REGISTER
PARITY TRANSMISSION
3TOPCONDITION
0ARITYCHECK
)NTERRUPT
.
0ARITY
CHECK
9
%XIT
!-
Doc ID 022817 Rev 2
41/65
Device configuration
L6360
1.
Microcontroller I2C establishes the communication: START condition
2.
Microcontroller I2C sends the slave address on the I2C bus to check if the slave is
online (1st frame)
3.
After the address is matched, the microcontroller starts the data transmission:
the 2nd frame is the data to be written into the selected register (see 3rd frame)
4.
The 3rd frame is composed of the address of the register to be written and of the parity
of the 2nd frame.
5.
Microcontroller I2C finishes the communication: STOP condition
6.
The L6360 calculates the parity of the data received
7.
The L6360 compares its parity calculation with the parity bits in the 3rd frame (sent by
the microcontroller)
8.
If the parities match, the protocol flow goes on (exit), otherwise the PE bit inside the
L6360 status register is set and the flow goes to the next state.
9.
The L6360 generates an interrupt to report the parity check error.
10. The microcontroller sends a read request to the device. The L6360 then sends the
status and parity registers. The microcontroller can resend the corrupted data register.
11. Back to step 1.
The I2C frame (configuration, control, diagnostic phases) must provide:
●
Slave address (7 bits)
●
Transmission direction (read/write)
●
Data (8 bits: data register)
●
Parity bits (P2, P1, P0)
●
Registers address (4 bits: 16 registers addressable)
The three frames are shown in Figure 26 and below:
Figure 26. Current Write mode frames
3
!
!
!
!
!
!
!
7
ST
FRAME
ND
FRAME
!DDRESS
$IRECTION
$
$
$
$
$
$
$
$
$ATA
0
0
0
2
0ARITY
2
2
2
0
3
3TART CONDITION
0
3TOP CONDITION
RD
FRAME
2EGISTER
5NUSED
!-
42/65
Doc ID 022817 Rev 2
L6360
Device configuration
1st frame
Bit 7÷1:
L6360 address
Bit 0:
Direction
Table 27.
Current Write mode direction bit
W bit
Master
Slave
0
Write mode
Read mode
1
Read mode
Write mode
2nd frame
Bit 7÷0:
3rd
Data register
frame
Bit 7÷5:
Parity bits
Bit 4:
Unused
Bit 3÷0:
Register address
The parity check bits are calculated as shown in Equation 2:
Equation 2
P0 = D7 ⊕ D6 ⊕ D5 ⊕ D4 ⊕ D3 ⊕ D2 ⊕ D1 ⊕ D0
P1 = D7 ⊕ D5 ⊕ D3 ⊕ D1 (odd parity)
P2 = D6 ⊕ D4 ⊕ D2 ⊕ D0 (even parity)
If parity error occurs, the register are not overwritten.
Doc ID 022817 Rev 2
43/65
Device configuration
L6360
Sequential Write mode
Figure 27. Sequential Write mode flow chart procedure
7RITE MODE
3%15%.4)!,
#URRENT 2EADMODE
3TARTCONDITION
3TARTCONDITION
-ICROCONTROLLERSENDS
SLAVEADDRESS
-ICROCONTROLLERSENDS
SLAVEADDRESS
3EQUENTIAL
TRANSMISSION
.EW
TRANSMISSION
0ARITYFROM
MICROCONTROLLER
3TOPCONDITION
)NTERRUPT
.
0ARITY
CHECK
9
%XIT
!-
2
1.
The microcontroller I C establishes the communication: START condition.
2.
The microcontroller I2C sends the slave address on the I2C bus to check if the slave is
online (1st frame).
3.
After the address is matched, the microcontroller starts the sequential transmission
(2nd ÷ 8th frame).
4.
The microcontroller sends its parity register (last frame: 9th frame).
5.
Microcontroller I2C finishes the communication: STOP condition.
6.
The L6360 calculates the parity of the registers received, and stores the results in the
parity register.
7.
The L6360 compares its parity register with the parity register sent by the
microcontroller (9th frame).
8.
If the parities match, the protocol flow goes on (EXIT), otherwise the PE bit inside the
L6360 status register is set, and the flow goes to the next state.
9.
The L6360 generates an interrupt to report the parity check error.
10. The microcontroller sends a read request to the device. In this phase the L6360 sends
the status register and the parity register allowing the microcontroller to verify which
register failed the configuration.
44/65
Doc ID 022817 Rev 2
L6360
Device configuration
11. Now the microcontroller can perform a new write sequential procedure.
12. Microcontroller I2C establishes the communication: START condition.
13. Microcontroller I2C sends the slave address on the I2C bus to check if the slave is
online.
14. The microcontroller resends the data registers.
15. Back to step 5.
The I2C frame (configuration, control, diagnostic phases) must provide:
●
Slave address (7 bits)
●
Transmission direction (read/write)
●
Data (8 bits: data registers)
The 9 frames are shown below:
Figure 28. Sequential Write mode frames
STFRAME
3
!
!
!
!
!
!
!
7
!DDRESS
NDFRAME
$
$
$
$
$IRECTION
$
$
$
$
$
$
$
$
$
$
$
$
$ATA
THFRAME
$
$
$
$
$ATA
THFRAME
$
$
$
$
0
$ATA
3
3TARTCONDITION
0
3TOPCONDITION
!-
1st frame
Bit 7÷1:
L6360 address
Bit 0:
Direction (write/read)
Doc ID 022817 Rev 2
45/65
Device configuration
Table 28.
L6360
Sequential Write mode direction bit
W
Master
Slave
0
Write mode
Read mode
1
Read mode
Write mode
2nd ÷ 8th frame
Bit 7÷0:
Data register
9th frame
Bit 7÷0:
Microcontroller parity register
The microcontroller parity check (for each register) calculus performed is shown below:
Figure 29. Microcontroller parity check calculus
0
0
0
0
0
0
0
!-
Bit 6 = P6:
Microcontroller configuration register parity
This bit is the parity of the configuration register.
Bit 5 = P5:
Microcontroller control register 1 parity
This bit is the parity of control register 1.
Bit 4 = P4:
Microcontroller control register 2 parity
This bit is the parity of control register 2.
Bit 3 = P3:
Microcontroller LED1 register high parity
This bit is the parity of the LED1 MSB register (15 down to 8).
Bit 2 = P2:
Microcontroller LED1 register low parity
This bit is the parity of the LED1 LSB register (7 down to 0).
Bit 1 = P1:
Microcontroller LED2 register high parity
This bit is the parity of the LED2 MSB register high (15 down to 8).
Bit 0 = P0:
Microcontroller LED2 register low parity
This bit is the parity of the LED2 LSB register high (7 down to 0).
For each register, a parity check is calculated as shown in Equation 3, in general formulas:
Equation 3
PX = D7 ⊕ D6 ⊕ D5 ⊕ D4 ⊕ D3 ⊕ D2 ⊕ D1⊕ D0 (X = 0 to 6)
D7 ÷ D0 indicates bits inside each register.
If parity error occurs, the registers are not overwritten.
In this writing mode, all writable registers and the microcontroller parity register are sent.
46/65
Doc ID 022817 Rev 2
L6360
Device configuration
Figure 30. Register sequence in sequential Write mode
Read modes
The status register and parity check register are read only.
The other registers are readable/writable (by microcontroller).
There are three reading modes:
●
Current: status register only
●
Sequential: all registers in sequence
●
Random: to read registers in sequence starting from a register address fixed by the
microcontroller.
All registers are addressed as shown in Table 30:
Table 29.
Read mode: register address
Address
Register name
0000
Status register
0001
Configuration register
0010
Control register 1
0011
Control register 2
0100
LED1 register MSB
0101
LED1 register LSB
0110
LED2 register MSB
0111
LED2 register LSB
1000
Parity register
Doc ID 022817 Rev 2
47/65
Device configuration
L6360
Current Read mode
Figure 31. Current Read mode flow chart procedure
2EAD
MODE
#522%.4
3TARTCONDITION
-ICROCONTROLLERSENDS
SLAVEADDRESS
3TATUS
DATA REGISTER
REGISTER
0ARITY
3TOPCONDITION
%XIT
!-
2
1.
Microcontroller I C establishes the communication: START condition
2.
Microcontroller I2C sends slave address on the I2C bus to check if the slave is online
(1st frame)
3.
After the address is matched, the L6360 sends its status register (2nd frame)
4.
The L6360 sends its parity register (3rd frame)
5.
Microcontroller I2C finishes the communication: STOP condition.
The I2C frame (configuration, control, diagnostic phases) must provide:
48/65
●
Slave address (7 bits)
●
Transmission direction (read/write)
●
Data (8-bit data registers): status and parity registers.
Doc ID 022817 Rev 2
L6360
Device configuration
The three frames are shown in Figure 32.
Figure 32. Current Read mode frames
3
!
!
!
!
!
!
!
2
STFRAME
!DDRESS
$IRECTION MASTERWRITESLAVEREAD
MASTERREADSLAVEWRITE
$IRECTION
$
$
$
$
$
$
$
$
NDFRAME
3TATUSREGISTER
$
$
$
$
$
$
$
$
0
3
3TARTCONDITION
0
3TOPCONDITION
RDFRAME
0ARITYREGISTER
!-
When a “read request” comes from the microcontroller (it is configured as master receiver),
the IC (slave transmitter) sends the contents of the status and parity registers.
Figure 33. Current read communication flow
-ASTERRECEIVER
3LAVETRANSMITTER
3TART
3LAVEADDRESS
.!
!
STO0
$ATA
3ENDBYTHEMASTER
3ENDBYTHESLAVE
!-
Doc ID 022817 Rev 2
49/65
Device configuration
L6360
Sequential/random Read modes
Figure 34. Sequential/random Read mode
2ANDOMSEQUENTIALINITIALIZATION
2EAD
MODE
2!.$/-
3%15%.4)!,
3TARTCONDITION
3TARTCONDITION
-ICROCONTROLLER
SENDSSLAVEADDRESS
7RITEMODE
-ICROCONTROLLER
SENDSSLAVEADDRESS
2EADMODE
-ICROCONTROLLERSENDS
ADDRESSREGISTER
STARTPOINT
3EQUENTIALREADING
3TOPCONDITION
3TOPCONDITION
%XIT
!-
1.
Random/sequential Read mode initialization: Microcontroller I2C establishes the
communication: START condition.
2.
Microcontroller I2C sends the slave address, in Write mode, on the I2C bus to check if
the slave is online (1st frame).
3.
Microcontroller I2C sends the register address start point, which sets the first register to
read in sequence (2nd frame).
4.
Microcontroller I2C finishes the communication: STOP condition.
5.
Microcontroller I2C sends the slave address, in Read mode, on the I2C bus to check if
the slave is online (3rd frame).
6.
After the address is matched, the L6360 sends its registers in sequential mode, starting
from the register set in the 2nd frame.
7.
Microcontroller I2C finishes the communication: STOP condition.
The I2C frame (configuration, control, diagnostic phases) must provide:
50/65
●
Slave address (7 bits)
●
Transmission direction (read/write)
●
Data (8-bit data register)
Doc ID 022817 Rev 2
L6360
Device configuration
The frames structure is shown in Figure 35:
Figure 35. Sequential/random read communication flow
3
!
!
!
!
!
!
!
7
ST
$IRECTIONMASTERWRITESLAVEREAD
MASTERREADSLAVEWRITE
FRAME
!DDRESS
$IRECTION
$
$
$
$
$
$
$
$
0
!
!
!
!
ND
FRAME
$ATA
3
!
!
!
2
RD
FRAME
$IRECTIONMASTERWRITESLAVEREAD
MASTERREADSLAVEWRITE
!DDRESS
$IRECTION
$
$
$
$
$
$
$
$
TH
FRAME
$ATAREGISTER
FROMREGISTER STARTPOINT
$
$
$
$
$
$
$
$
N
TH
FRAME
$ATAREGISTER PENULTIMATEREGISTER
$
$
$
$
$
$
$
$
TH
FRAME
0ARITYREGISTER
3
3TARTCONDITION
0
3TOPCONDITION
!-
st
1 frame
Bit 7 ÷ 1:
L6360 address
Bit 0:
Direction (write)
2nd frame
Bit 7 ÷ 0:
Address register starting point
Doc ID 022817 Rev 2
51/65
Device configuration
Table 30.
L6360
Address register
Address
Register name
0000
Status register
0001
Configuration register
0010
Control register 1
0011
Control register 2
0100
LED1 register MSB
0101
LED1 register LSB
0110
LED2 register MSB
0111
LED2 register LSB
1000
Parity register
3rd frame
Bit 7 ÷ 1:
L6360 address
Bit 0:
Direction (read)
th
4 ÷n
th
frame
Bit 7÷0:
Data register (from address register starting point to penultimate address
register)
9th frame
Bit 7÷0:
52/65
Parity register (the last register)
Doc ID 022817 Rev 2
L6360
7
Physical layer communication
Physical layer communication
The IC transfers the data received (on the INC/Q digital input pin) at the C/QO output. The
ENC/Q pin allows the C/QO line to be put into TRISTATE.
Data received from the line (C/QI and I/Q pins) is transferred to the digital output pins
OUTC/Q and OUTI/Q.
Figure 36. Block diagram communication mode
!-
Figure 37. System communication mode
/UTPUT STAGE ON #1
ISENABLED
/UTPUTSTAGEON #1
IS DISABLED
/UTPUT STAGE ON #1
ISENABLED
%. #1
)/,INKFRAME
/54#1
). #1
88888888888
)/,INKFRAME
). #1 DISABLED
)/,INKFRAME
)# TRANSMITS ON THE
LINE THE DATA RECEIVED
ON).
#1
)# RECEIVES DATA FROM THE
LINE#1ANDPROVIDESIT
ON/54 #1
)# TRANSMITS ON THE
LINE THE DATA RECEIVED
ON). #1
!-
Doc ID 022817 Rev 2
53/65
Physical layer communication
7.1
L6360
Transceiver
Output drivers (C/QO and L+) are protected against short-circuit or overcurrent by means of
two different functions.
One is the current limiting function: output current is linearly limited to ILIMQ/L.
The cutoff protection, on the other side, is intended to turn off the drivers when the output
current exceeds a (programmable for the C/QO driver) threshold (ICOL/I). When the current
reaches the (programmed) cutoff value the channel output driver is turned off after
a programmable delay (tdcoq/l). The channel output driver automatically restarts again after
a programmable delay time (trcoq/l). See Figure 38.
Figure 38. C/Q or L+ channel cutoff protection
#URRENTREAD
#1 OOR ,DRIVERDISABLED
) #/1,
T DCOQL T RCOQL T
T DCOQL
T RCOQL
#1/,,/,
T
!-
Figure 39. C/Q or L+ channel current limitation and cutoff protection with latched
restart
#URRENTREAD
#1O OR ,DRIVERDISABLED ) ,)-1, ) #/1, TDCOQL
TRCOQL
T
T DCOQL
T RCOQL
#1/,,/,
T
!-
For CQOL/LOL bit reset see the related Status register section.
54/65
Doc ID 022817 Rev 2
L6360
7.2
Diagnostic LED sequence generator and driver
IEC 61131-2 type 1 digital inputs
Two IEC61131-2 type 1 inputs are provided: one is available on C/QI (as per IO-Link
specification to support SIO mode) and one on the I/Q pin.
Both are provided with a programmable de-bounce filter (tdbq and tdbi, see Table 17 and
Table 23) to prevent false triggering.
8
Diagnostic LED sequence generator and driver
Each LED indication block can drive, through open drain output, one external LED.
LED drivers can be used for status or diagnostic information, or for other purposes, and
should be configured by the host microcontroller.
Two sequences of 16 bits can be programmed (through I2C) to generate user specific
sequences; each LED driver has two associated registers and turns the external LED on or
off according to the information stored in the registers, which are scanned at a rate of
63 ms per bit; total sequence time of each LED is approximately 1 s.
See also the LED registers section.
Figure 40 shows how to wire up the two LEDs:
Figure 40. LED drivers
6$$
$, 2 $, 2
6$$
-ICROCONTROLLER
,%$
,
,%$
'.$
!-
Doc ID 022817 Rev 2
55/65
Linear regulator
9
L6360
Linear regulator
The L6360 embeds a linear regulator with output voltage selectable (by the SEL pin)
at 3.3 V or 5 V.
The input voltage is VH (seeTable 3) and the maximum power dissipation is 200 mW.
The linear regulator minimum limitation current value is ILIMLR (see Table 7).
Figure 41. Linear regulator
6(
6$$
N&
3%,
6OR6 SELECTION
!-
Table 31.
Linear regulator selection pin
SEL
VDD
0
5 V ± 2.5%
1
3.3 V ± 2%
The linear regulator cannot be turned off as it is necessary to supply (through VDD pin)
internal circuitries.
It can also be used to supply external circuitry (e.g. the microcontroller).
Figure 42. Linear regulator principle schematic
6(
,
6"'
,IMITATION
CIRCUIT
%. ,
6$$
2
2
!-
56/65
Doc ID 022817 Rev 2
L6360
10
Application example
Application example
The IO-Link master system typically consists of a microcontroller and physical layer and it
communicates with an IO-Link device. The principle connection can be seen in Figure 43.
Figure 43. Application example
Doc ID 022817 Rev 2
57/65
EMC protection considerations
11
L6360
EMC protection considerations
Depending on final product use and environmental conditions, the master application may
require additional protection.
11.1
Supply voltage protection
In order to avoid overvoltages on a system supply, a voltage suppressor such as Transil™
can be added. A simple protection diagram example is shown in Figure 44.
Figure 44. Supply voltage protection with uni-directional Transil
6##
072
$?3
3-4!
'.$
'.$
'.$
!-
Performance of the above mentioned example is limited and does not include reverse
polarity protection. It is just a cost-effective solution.
Table 32.
Part
Supply voltage protection component description
Function
Description
D_S
Works as a primary overvoltage clamp to limit supply line
distortions - like surge pulses, oscillations caused by line
Supply overvoltage protection parasitic parameters (inductance) during plug-in phase, etc.
1500 W is recommended to provide reliable protection, unidirectional type helps to avoid negative stress of the L6360.
C_F
Filtering bulk capacitor
An energy buffer for application supply, filters the application
supply to avoid high ripple during power driver switching, etc.
A more sophisticated solution can be seen in Figure 45.
58/65
Doc ID 022817 Rev 2
L6360
EMC protection considerations
Figure 45. Refined supply voltage protection
6##
$0/,
072
3403(
$?072
3-4#!
'.$
'.$
$?3
3-4!
'.$
'.$
!-
The above reference diagram provides an extended level of protection in both polarities as
well as the reverse polarity protection.
Table 33.
Part
Refined supply voltage protection component description
Function
Description
Works as a primary overvoltage clamp to limit supply line
distortions - like surge pulses, oscillations caused by line
parasitic parameters (inductance) during plug-in phase, etc.
1500 W is recommended to provide reliable protection, unidirectional type is chosen to cover reverse polarity protection.
D_PWR
Primary overvoltage
protection
D_POL
Avoids reverse direction current flow and negative voltage
stress of the L6360. Its current rating (3 A) is chosen in
accordance with the maximum driving capabilities of the
Reverse polarity protection
L6360 power stages. Schottky type is recommended to limit
power dissipation (low VF). Voltage rating (100 V) comes from
negative surge to the supply condition.
D_S
D_PWR support and IO
overvoltage protection
a) Shares a positive surge current with the primary protection
and limits the overvoltage amplitude.
b) clamps surges applied to the L6360 C/Q and L+ lines.
C_F
Filtering bulk capacitor
An energy buffer for application supply, filters the application
supply to avoid high ripple during power driver switching, etc.
If the VH pin of the L6360 is supplied from a separate power supply or if it is decoupled from
the main power supply and blocked by bulk capacitors, an additional circuit may be required
to ensure the VH voltage is always lower than (or equal to) the main supply voltage (VCC).
A possible solution with diode is shown in Figure 46.
Doc ID 022817 Rev 2
59/65
EMC protection considerations
L6360
Figure 46. VH protection vs. VCC
6##
5
%.?,
%.?#1
).?#1/
/54?#1)
6##
6##
/54?)1
,
#1/
#1)
)1
'.$,
'.$,
3$!
3#,
3!
3!
3!
6(
)21
234
6$$
3%,
,%$
,%$
2BIAS
,
$?6(
6(
'.$
!-
Table 34.
Part
D_VH
60/65
VH protection component description
Function
Description
VH overvoltage protection
VH voltage must be always lower than (or equal to) VCC. Even
during the powering-up and down of an application. This fact
must be taken into consideration if VH is supplied from another
source (VCC and VH not connected together), charged
capacitors, etc. In some cases a diode placed between VCC
and VH may help to avoid this violation.
Doc ID 022817 Rev 2
L6360
EMC protection considerations
11.2
I/O lines protection
Figure 47 shows external components (capacitors) suitable for IO-Link communication protection level in accordance with specification.
Figure 47. Typical protection in IO-Link applications
6##
5
#
%.?,
%.?#1
6##
6##
).?#1/
/54?#1)
/54?)1
,
#1/
3$!
#1)
3#,
3!
)1
'.$,
3!
'.$,
3!
6(
)21
6$$
234
3%,
,%$
,%$
,
2BIAS
N&
#.
,
#1
)1
,
#?)1
P&
#?#1
P&
#?,
N&
'.$
'.$
'.$
'.$
'.$
'.$
!-
Table 35.
Part
C_1
Typical protection in IO-Link applications component description
Function
Power supply blocking
C_I/Q, C_C/Q, C_L+ Filtration capacitors
Description
Energy buffer for the L6360 supply, makes chip supply voltage
stable, limits EMI noise.
Work as a basic protection against fast transient signals like burst or
radio-frequency domain applied to the lines. Limit voltage spikes
frequency spectrum and amplitude.
Doc ID 022817 Rev 2
61/65
EMC protection considerations
L6360
If an extended protection level is required, the solution seen in Figure 48 is recommended. It
provides robust protection according to IEC61131-2. It is suitable for IO-Link communication
and is backward compatible with SIO (standard I/O). It protects the L6360 application
against high energy surge pulses according to the IEC61000-4-5 standard. All the lines are
protected against ±2.5 kV surge pulse amplitude in common mode and ±1 kV in differential
mode considering 42 Ω/0.5 μF generator coupling.
Figure 48. IO-Link and SIO applications extended protection
,
,
N&
#?,
,
#1 /
#1
#?#1
P&
,
#1 )
)1
)1
$?#1
3403,2?)1
#?)1
P&
6
+
,3
6
!
(3
$?)1
3403,,
5304 $%%
!-
Table 36.
IO-Link and SIO applications extended protection component description
Part
Function
Description
C_I/Q, C_C/Q, C_L+
Filtration capacitors
Work as a basic protection against fast transient signals like burst
or radio-frequency domain applied to the lines. Limit voltage spike
frequency spectrum and amplitude.
D_I/Q, D_C/Q
Negative voltage spike
suppression
Schottky diodes with low VF clamp the disturbance applied to the
lines in a reverse polarity direction. Capable of conducting high
surge current pulses to avoid high peak current flow through
L6360 pins.
R_I/Q
Reduces the current flow in the L6360 - the I/Q pin in both
Surge current limitation polarities when e.g. surge noise is applied to the line. If this
resistor is omitted, the I/Q line surge immunity is lower.
U2 (SPT01-335DEE) Overvoltage protection
62/65
Primary surge protection to avoid overvoltage on the L6360
interface. Protects L+ switch against negative voltage pulses.
Shares current flow of negative surge pulses with the additional
Schottky diodes on C/Q and I/Q lines. Clamps positive surge
pulse amplitude applied to I/Q line.
Doc ID 022817 Rev 2
L6360
12
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK®2 packages, depending on their level of environmental compliance. ECOPACK2
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK2 is an ST trademark.
Figure 49. Package outline for VFQFPN - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch
$
!
%
%
$
E
,
!
B
!
6&1&0.,
Mechanical data for VFQFPN - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch(1) (2) (3)
Table 37.
Dimensions
Symbol
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0
0.02
0.05
A2
b
0.20
0.18
D
D2
1.90
2.00
2.10
5.00
3.40
e
L
0.30
3.50
E
E2
0.25
3.50
3.60
0.50
0.30
0.40
0.50
1. VFQFPN stands for thermally enhanced “very thin fine pitch quad flat package no lead”.
2. Very thin profile: 0.80 < A ≤ 1.00 mm.
3. All dimensions are in millimeters.
Doc ID 022817 Rev 2
63/65
Revision history
13
L6360
Revision history
Table 38.
64/65
Document revision history
Date
Revision
Changes
12-Mar-2012
1
Initial release.
15-Mar-2012
2
Updated Eload definition in Table 3: Absolute maximum ratings.
Updated Figure 36: Block diagram communication mode.
Doc ID 022817 Rev 2
L6360
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