FUJITSU SEMICONDUCTOR DATA SHEET DS07-16302-2E 32-bit RISC Microcontroller CMOS FR Family MB91106 MB91106 ■ DESCRIPTION The MB91106 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To carry out hi-speed performance of CPU instructions, instruction/data ROM of 64 Kbytes and RAM of 2 Kbytes are embedded in the MB91106. The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers. *: FR Family stands for FUJITSU RISC controller. ■ FEATURES FR CPU • • • • • • 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) General purpose registers: 32 bits × 16 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages • Register interlock functions, efficient assembly language coding • Branch instructions with delay slots: Reduced overhead time in branch executions (Continued) ■ PACKAGE 100-pin Plastic LQFP 100-pin Plastic QFP (FPT-100P-M05) (FPT-100P-M06) MB91106 Series (Continued) • Internal multiplier/supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles • Interrupt (push PC and PS): 6 cycles, 16 priority levels External bus interface • • • • • • Clock doublure: Maximum internal bus 50 MHz, maximum external bus 25 MHz operation 25-bit address bus (32 Mbytes memory space) 8/16-bit data bus Basic external bus cycle: 2 clock cycles Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6 Interface supported for various memory technologies DRAM interface (area 4 and 5) • Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area • Unused data/address pins can be configured us input/output ports • Little endian mode supported (Select 1 area from area 1 to 5) DRAM interface • • • • • 2 banks independent control (area 4 and 5) Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode • Supports 8/9/10/12-bit column address width • 2CAS/1WE, 2WE/1CAS selective DMA controller (DMAC) • • • • • 8 channels Transfer incident/external pins/internal resource interrupt requests Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer Transfer data length: 8 bits/16 bits/32 bits selective NMI/interrupt request enables temporary stop operation UART • • • • • • • • 2 3 independent channels Full-duplex double buffer Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity) Asynchronous (start-stop system), CLK-synchronized communication selective Multi-processor mode Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate Use external clock can be used as a transfer clock Error detection: Parity, frame, overrun MB91106 Series (Continued) 10-bit A/D converter (successive approximation conversion type) • • • • • 10-bit resolution, 4 channels Successive approximation type: Conversion time of 5.6 µs at 25 MHz Internal sample and hold circuit Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective Start: Software/external trigger/internal timer selective 16-bit reload timer • 3 channels • Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective Other interval timers • 16-bit timer: 3 channels (U-TIMER) • PWM timer: 4 channels • Watchdog timer: 1 channel Bit search module First bit transition “1” or “0” from MSB can be detected in 1 cycle Interrupt controller • External interrupt input: Non-maskable interrupt (NMI), normal interrupt × 4 (INT0 to INT3) • Internal interrupt incident: UART, DMA controller (DMAC), 10-bit A/D converter, 16-bit reload-timer, PWM timer, U-TIMER and delayed interrupt module • Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps) Others • Reset cause: Power-on reset/software reset/external reset • Low-power consumption mode: Sleep mode/stop mode • Clock control Gear function: Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) (However, operating frequency for peripherals is less than 25 MHz.) • Packages: LQFP-100 and QFP-100 • CMOS technology (0.35 µm) • Power supply voltage: 3.3 V ± 0.3 V ■ PRODUCT LINEUP Part number MB91106 MB91V106 Mass production products (mask ROM products) Piggyback/evaluation product (for evaluation and development) IROM size 63 Kbytes — IRAM size — 64 Kbytes CROM size 64 Kbytes — CRAM size — 64 Kbytes 2 Kbytes 5 Kbytes Parameter Classification RAM size I$ Other — Under trial manufacture Under development 3 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24/P30 D25/P31 D26/P32 D27/P33 D28/P34 D29/P35 D30/P36 VSS D31/P37 A00/P40 VCC A01/P41 A02/P42 A03/P43 A04/P44 A05/P45 A06/P46 A07/P47 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CS1L/PB5/DREQ2 CS1H/PB6/DACK2 DW1/PB7 VCC CLK/PA6 CS5/PA5 CS4/PA4 CS3/PA3/EOP1 CS2/PA2 CS1/PA1 CS0/PA0 NMI VCC RST VSS MD0 MD1 MD2 RDY/P80 BGRNT/P81 BRQ/P82 RD/P83 WR0/P84 WR1/P85 D16/P20 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RAS1/PB4/EOP2 DW0/PB3 CS0H/PB2 CS0L/PB1 RAS0/PB0 INT0/PE0 INT1/PE1 VCC X0 X1 VSS INT2/SC1/PE2 INT3/SC2/PE3 DREQ0/PE4 DREQ1/PE5 DACK0/PE6 DACK1/PE7 OCPA0/PF7/ATG SO2/OCPA2/PF6 SI2/OCPA1/PF5 SO1/TRG3/PF4 SI1/TRG2/PF3 SC0/OCPA3/PF2 SO0/TRG1/PF1 SI0/TRG0/PF0 MB91106 Series ■ PIN ASSIGNMENT (Top view) (FPT-100P-M05) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/EOP0/P70 A23/P67 A22/P66 VSS A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 A16/P60 A15/P57 A14/P56 A13/P55 A12/P54 A11/P53 A10/P52 A09/P51 A08/P50 MB91106 Series 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CS0L/PB1 RAS0/PB0 INT0/PE0 INT1/PE1 VCC X0 X1 VSS INT2/SC1/PE2 INT3/SC2/PE3 DREQ0/PE4 DREQ1/PE5 DACK0/PE6 DACK1/PE7 OCPA0/PF7/ATG SO2/OCPA2/PF6 SI2/OCPA1/PF5 SO1/TRG3/PF4 SI1/TRG2/PF3 SC0/OCPA3/PF2 (Top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SO0/TRG1/PF1 SI0/TRG0/PF0 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/EOP0/P70 A23/P67 A22/P66 VSS A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 A16/P60 A15/P57 A14/P56 A13/P55 A12/P54 A11/P53 A10/P52 A09/P51 A08/P50 A07/P47 A06/P46 A05/P45 31 32 33 34 35 36 37 38 39 34 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24/P30 D25/P31 D26/P32 D27/P33 D28/P34 D29/P35 D30/P36 VSS D31/P37 A00/P40 VCC A01/P41 A02/P42 A03/P43 A04/P44 CS0H/PB2 DW0/PB3 RAS1/PB4/EOP2 CS1L/PB5/DREQ2 CS1H/PB6/DACK2 DW1/PB7 VCC CLK/PA6 CS5/PA5 CS4/PA4 CS3/PA3/EOP1 CS2/PA2 CS1/PA1 CS0/PA0 NMI VCC RST VSS MD0 MD1 MD2 RDY/P80 BGRNT/P81 BRQ/P82 RD/P83 WR0/P84 WR1/P85 D16/P20 D17/P21 D18/P22 (FPT-100P-M06) 5 MB91106 Series ■ PIN DESCRIPTION Pin no. LQFP*1 25 to 32 QFP*2 Pin name 28 to 35 D16 to D23 Circuit type C P20 to P27 33 to 39, 41 36 to 42, D24 to D30, 44 D31 45, A00, 47 to 53, A01 to A07, 54 to 61 A08 to A15 C 62 to 67, A16 to A21, 69, A22, 70 A23 E 19 71 22 A24 E 23 E 24 Can be configured as DMAC EOP output (ch. 0) when DMAC EOP output is enabled. P70 Can be configured as general purpose I/O port when A24 and EOP0 are not used. RDY C BGRNT BRQ 25 RD P83 *1: FPT-100P-M05 *2: FPT-100P-M06 6 External ready input Inputs “0” when bus cycle is being executed and not completed. Can be configured as general purpose I/O port when RDY is not used. E External bus release acknowledge output Outputs “L” level when external bus is released. Can be configured as general purpose I/O port when BGRNT is not used. C P82 22 Bit 24 of external address bus EOP0 P81 21 Bit 16 to bit 23 of external address bus Can be configured as general purpose I/O ports when not used as address bus. P80 20 Bit 00 to bit 15 of external address bus Can be configured as general purpose I/O ports when not used as address bus. P60 to P67, P69, P70 68 Bit 24 to bit 31 of external data bus Can be configured as general purpose I/O ports when not used as address bus. P40, P41 to P47, P50 to P57 59 to 64, 66, 67 Bit 16 to bit 23 of external data bus Can be configured as general purpose I/O port when external data bus width is set to 8-bit or in single chip mode. P30 to P36, P37 42, 44 to 50, 51 to 58 Function External bus release request input Inputs “1” when release of external bus is required. Can be configured as general purpose I/O port when BRQ is not used. E Read strobe output pin for external bus Can be configured as general purpose I/O port when RD is not used. (Continued) MB91106 Series Pin no. 1 LQFP* QFP* 23 26 2 Pin name P84 Circuit type E WR0 24 27 WR1 Function Can be configured as general purpose I/O port when WR0 is not used. Write strobe output pin for external bus Relation between control signals and effective byte locations is as follows: 16-bit bus width 8-bit bus width Single chip mode D31 to D24 WR0 WR0 (I/O port enabled) D23 to D16 WR1 (I/O port enabled) (I/O port enabled) E Note: WR1 is Hi-Z during resetting. Attach an external pull-up resister when using at 16-bit bus width. P85 11 14 CS0 Can be configured as general purpose I/O port when WR1 is not used. E PA0 10 13 CS1 Can be configured as general purpose I/O port when CS0 is not used. E PA1 9 12 CS2 7 11 10 CS3 E 9 E 8 Can be configured as a port when CS3 and EOP1 are not used. EOP1 EOP output pin for DMAC (ch. 1) This function is available when EOP output for DMAC is enabled. CS4 CS5 CLK PA6 *1: FPT-100P-M05 *2: FPT-100P-M06 Chip select 3 output (“L” active) PA3 E Chip select 4 output (“L” active) Can be configured as general purpose I/O port when CS4 is not used. E PA5 5 Chip select 2 output (“L” active) Can be configured as a port when CS2 is not used. PA4 6 Chip select 1 output (“L” active) Can be configured as general purpose I/O port when CS1 is not used. PA2 8 Chip select 0 output (“L” active) Chip select 5 output (“L” active) Can be configured as general purpose I/O port when CS5 is not used. E System clock output Outputs clock signal of external bus operating frequency. Can be configured as general purpose I/O port when CLK is not used. (Continued) 7 MB91106 Series Pin no. 1 LQFP* QFP* 96 99 2 Pin name RAS0 Circuit type E PB0 97 100 CS0L 1 CS0H E 2 DW0 E 1 2 3 3 4 5 6 RAS1 E E RAS output for DRAM bank 1 PB4 Can be configured as general purpose I/O port when RAS1 and EOP2 are not used. EOP2 DMAC EOP output (ch. 2) This function is available when DMAC EOP output is enabled. CS1L E CASL output for DRAM bank 1 PB5 Can be configured as general purpose I/O port when CS1L and DREQ are not used. DREQ2 External transfer request input pin for DMA This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. CS1H E CASH output for DRAM bank 1 PB6 Can be configured as general purpose I/O port when CS1H and DACK2 are not used. DACK2 External transfer request accept output pin for DMAC (ch. 2) This function is available when transfer request output for DMAC is enabled. DW1 19 to 21 MD0 to MD2 E WE output for DRAM bank 1 (“L” active) Can be configured as general purpose I/O port when DW1 is not used. F Mode pins 0 to 2 MCU basic operation mode is set by these pins. Directly connect these pins with VCC or VSS for use. 92 95 X0 A Clock (oscillator) input 91 94 X1 A Clock (oscillator) output 14 17 RST B External reset input 12 15 NMI G NMI (non-maskable interrupt pin) input (“L” active) *1: FPT-100P-M05 *2: FPT-100P-M06 8 WE output for DRAM bank 0 (“L” active) Can be configured as general purpose I/O port when DW0 is not used. PB7 16 to 18 CASH output for DRAM bank 0 Can be configured as general purpose I/O port when CS0H is not used. PB3 100 CASL output for DRAM bank 0 Can be configured as general purpose I/O port when CS0L is not used. PB2 99 RAS output for DRAM bank 0 Can be configured as general purpose I/O port when RAS0 is not used. PB1 98 Function (Continued) MB91106 Series Pin no. 1 LQFP* QFP* 95, 94 98, 97 2 Pin name INT0, INT1 Circuit type E PE0, PE1 89 88 87, 86 92 91 90, 89 INT2 88 E External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. SC1 Clock I/O pin for UART1 Clock output is available when clock output of UART1 is enabled. PE2 Can be configured as general purpose I/O port when INT2 and SC1 are not used. This function is available when UART1 clock output is disabled. INT3 E External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. SC2 UART2 clock I/O pin Clock output is available when UART2 clock output is enabled. PE3 Can be configured as general purpose I/O port when INT3 and SC2 are not used. This function is available when UART2 clock output is disabled. DREQ0, DREQ1 DACK0 PE6 *1: FPT-100P-M05 *2: FPT-100P-M06 External interrupt request input pins These pins are used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. Can be configured as general purpose I/O ports when INT0 and INT1 are not used. E PE4, PE5 85 Function External transfer request input pins for DMA These pins are used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. Can be configured as general purpose I/O ports when DREQ0 and DREQ1 are not used. E External transfer request acknowledge output pin for DMAC (ch. 0) This function is available when transfer request output for DMAC is enabled. Can be configured as general purpose I/O port when DACK0 is not used. This function is available when transfer request acknowledge output for DMAC or DACK0 output is disabled. (Continued) 9 MB91106 Series Pin no. 1 LQFP* QFP* 84 87 2 Pin name DACK1 Circuit type E PE7 76 77 78 79 79 80 81 82 *1: FPT-100P-M05 *2: FPT-100P-M06 10 SI0 Function External transfer request acknowledge output pin for DMAC (ch. 1) This function is available when transfer request output for DMAC is enabled. Can be configured as general purpose I/O port when DACK1 is not used. This function is available when transfer request output for DMAC or DACK1 output is disabled. E UART0 data input pin This pin is used for input during UART0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. TRG0 PWM timer external trigger input pin (ch.0) This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PF0 Can be configured as general purpose I/O port when SI0 and TRG0 are not used. SO0 E UART0 data output pin This function is available when UART0 data output is enabled. TRG1 PWM timer external trigger input pin This function is available when serial data output of PF1, UART0 are disabled. PF1 Can be configured as general purpose I/O port when SO0 and TRG1 are not used. This function is available when serial data output of UART0 is disabled. SC0 E UART0 clock I/O pin Clock output is available when UART0 clock output is enabled. OCPA3 PWM timer output pin This function is available when PWM timer output is enabled. PF2 Can be configured as general purpose I/O port when SC0 and OCPA3 are not used. This function is available when UART0 clock output is disabled. SI1 E UART1 data input pin This pin is used for input during UART1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. TRG2 PWM timer external trigger input pin This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PF3 Can be configured as general purpose I/O port when SI1 and TRG2 are not used. (Continued) MB91106 Series Pin no. LQFP*1 QFP*2 80 83 81 82 83 72 to 75 84 85 86 Pin name SO1 Circuit type E Function UART1 data output pin This function is available when UART1 data output is enabled. TRG3 PWM timer external trigger input pin This function is available when PF4, UART1 data outputs are disabled. PF4 Can be configured as general purpose I/O port when SO1 and TRG3 are not used. This function is available when UART1 data output is disabled. SI2 E UART2 data input pin This pin is used for input during UART2 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. OCPA1 PWM timer output pin This function is available when PWM timer output is enabled. PF5 Can be configured as general purpose I/O port when SI2 and OCPA2 are not used. SO2 E UART2 data output pin This function is available when UART2 data output is enabled. OCPA2 PWM timer output pin This function is available when PWM timer output is enabled. PF6 Can be configured as general purpose I/O port when SO2 and OCPA2 are not used. This function is available when UART2 data output is disabled. OCPA0 E PWM timer output pin This function is available when PWM timer output is enabled. PF7 Can be configured as a port when OCPA0 and ATG are not used. This function is available when PWM timer output is disabled. ATG External trigger input pin for A/D converter This pin is used for input when external trigger is selected to cause A/D converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. 75 to 78 AN0 to AN3 D Analog input pins of A/D converter This function is available when AIC register is set to specify analog input mode. 69 72 AVCC — Power supply pin (VCC) for A/D converter 70 73 AVRH — Reference voltage input (high) for A/D converter Make sure to turn on and off this pin with potential of AVRH or more applied to VCC. 71 74 AVSS, AVRL — Power supply pin (VSS) for A/D converter and reference voltage input pin (low) *1: FPT-100P-M05 *2: FPT-100P-M06 (Continued) 11 MB91106 Series (Continued) Pin no. 1 2 Pin name Circuit type Function LQFP* QFP* 4, 13, 43, 93 7, 16, 46, 96 VCC — Power supply pin (VCC) for digital circuit Always power supply pin (VCC) must be connected to the power supply 15, 40, 65, 90 18, 43, 68, 93 VSS — Earth level (VSS) for digital circuit *1: FPT-100P-M05 *2: FPT-100P-M06 Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. xxx/Pxxx. In case of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O. 12 MB91106 Series ■ DRAM CONTROL PIN Pin name Data bus 16-bit mode 2CAS/1WR mode 1CAS/2WR mode Data bus 8-bit mode RAS0 Area 4 RAS Area 4 RAS Area 4 RAS RAS1 Area 5 RAS Area 5 RAS Area 5 RAS CS0L Area 4 CASL Area 4 CAS Area 4 CAS CS0H Area 4 CASH Area 4 WEL Area 4 CAS CS1L Area 5 CASL Area 5 CAS Area 5 CAS CS1H Area 5 CASH Area 5 WEL Area 5 CAS DW0 Area 4 WE Area 4 WEH Area 4 WE DW1 Area 5 WE Area 5 WEH Area 5 WE Remarks Correspondence of “L” “H” to lower address 1 bit (A0) in data bus 16bit mode “L”: “0” “H”: “1” CASL: CAS which A0 corresponds to “0” area CASH: CAS which A0 corresponds to “1” area WEL: WE which A0 corresponds to “0” area WEH: WE which A0 corresponds to “1” area 13 MB91106 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks A X1 Clock input • Oscillation feedback resistance 1 MΩ approx. With standby control X0 Standby control signal B VCC P-channel type transister P-ch • CMOS level hysteresis input Without standby control With pull-up resistance N-channel type transister Diffused resistor VSS Digital input C • CMOS level I/O With standby control R P-ch Digital output N-ch Digital output Digital input Standby control signal D • Analog input R P-ch Digital output N-ch Digital output Analog input (Continued) 14 MB91106 Series (Continued) Type Circuit Remarks E P-ch R N-ch Digital output • CMOS level output • CMOS level hysteresis input With standby control Digital output Digital input Standby control signal F • CMOS level input Without standby control P-ch R N-ch Digital input G • CMOS level hysteresis input Without standby control P-ch R N-ch Digital input 15 MB91106 Series ■ HANDLING DEVICES 1. Preventing Latchup In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over rating across VCC and VSS may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating. Take care that the analog power supply (AVCC AVR) and the analog input do not exceed the digital power supply (VCC) when the analog power supply turned on or off. 2. Treatment of Unused Pins Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors. 3. External Reset Input It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly. 4. Remarks for External Clock Operation When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at “H” output in stop mode). And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than. • Using an external clock X0 X1 MB91106 Using an external clock (normal) Note: Can not be used stop mode (oscillation stop mode). X0 Open X1 MB91106 Using an external clock (can be used at 12.5 MHz and less than.) (5 V power supply only) 16 MB91106 Series 5. Power Supply Pins When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND. It is preferred to connect VCC and VSS of MB91106 to power supply with minimal impedance possible. It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC and VSS at a position as close as possible to MB91106. 6. Crystal Oscillator Circuit Noises around X0 and X1 pins may cause malfunctions of MB91106. In designing the PC board, layout X0, X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for stable operation. 7. Turning-on Sequence of A/D Converter Power Supply and Analog Input Make sure to turn on the digital power supply (VCC) before turning on the A/D converter (AVCC, AVRH) and applying voltage to analog input (AN0 to AN3). Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies may be turned on simultaneously.) Make sure that AVRH never exceeds AVCC when turning on/off power supplies. 8. Treatment of N.C. Pins Make sure to leave N.C. pins open. 9. Fluctuation of Power Supply Voltage Warranty range for normal operation against fluctuation of power supply voltage VCC is as given in rating. However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended that by controlling power supply as a reference of stabilizing, VCC ripple fluctuation (P-P value) at the commercial frequency (50 Hz to 60 Hz) should be less than 10% of the standard VCC value and the transient regulation should be less than 0.1 V/ms at instantaneous deviation like turning off the power supply. 10. Mode Setting Pins (MD0 to MD2) Connect mode setting pins (MD0 to MD2) directly to VCC or VSS. Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. 11. Turning on the Power Supply When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to “H” level. 17 MB91106 Series 12. Pin Condition at Turning on the Power Supply The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation of the internal regulator becomes stable. So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz. Take care that the pin condition may be output condition at initial unstable condition. 13. Source Oscillation Input at Turning on the Power Supply At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. 14. Initialization Some internal resistors initialized only via power on reset are embedded in the device. To initialize these resistors, run power on reset by returning on the power supply or to set RST pin to “H” level. 18 MB91106 Series ■ BLOCK DIAGRAM I-bus (16 bits) FR CPU Bit search module DREQ0 to DREQ2 DACK0 to DACK2 EOP0 to EOP2 3 3 3 D-bus (32 bits) RAM (2 Kbytes) Instruction ROM 63 Kbytes, 32bits Bus converter (Harvard↔Princeton) DMA controller (DMAC) (8 ch.) 16 25 Bus converter (32 bits↔16bits) 2 X0 X1 RST 6 4 Interrupt control unit C-bus (32 bits) AN0 to AN3 AVCC AVSS AVRH AVRL ATG Clock control unit (Watchdog timer) 4 10-bit A/D converter (4 ch.) 16-bit reload timer (3 ch.) R-bus (16 bits) INT0 to INT3 NMI Bus controller RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1 DRAM interface Instruction ROM and data ROM 64 Kbytes 8 8 PE0 to PE7 PF0 to PF7 D16 to D31 A00 to A24 RD WR0, WR1 RDY CLK CS0 to CS5 BRQ BGRNT 8 8 Port E, Port F Port 2 to port B 8 8 8 6 7 8 UART (3 ch.) (Baud rate timer) 3 3 3 PWM timer (4 ch.) 4 4 Other pins P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 PA80 to P85 PA0 to PA6 PB0 to PB7 SI0 to SI2 SO0 to SO2 SC0 to SC2 MD0 to MD2, VCC, VSS OCPA0 to OCPA3 TRG0 to TRG3 Note: Pins are display for functions (Actually some pins are multiplexer). When using REALOS, time control should be done by using external interrupt or inner timer. 19 MB91106 Series ■ CPU CORE 1. Memory Space The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory space. • Memory space • Memory Space Single chip mode Address Internal ROM/ external bus mode External ROM/ external bus mode 0000 0000H I/0 Area I/0 Area I/0 Area Direct addressing area* See “■I/O MAP” 0000 0400H I/0 Area I/0 Area I/0 Area Access inhibited Access inhibited Access inhibited Embedded RAM (2 Kbytes) Embedded RAM (2 Kbytes) Embedded RAM (2 Kbytes) Access inhibited Access inhibited Access inhibited Access inhibited External area Instruction ROM (63 Kbytes) Instruction ROM (63 Kbytes) Access inhibited Access inhibited Instruction ROM/data ROM (64 Kbytes) Instruction ROM/data ROM (64 Kbytes) Access inhibited External area 0000 0800H 0000 1000H 0000 1800H 0001 0000H 0008 0000H 0008 FC00H External area 000F 0000H 0010 0000H FFFF FFFFH * : Direct addressing area The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an address can be specified in a direct operand of a code. Direct areas consists of the following areas dependent on accessible data sizes. Byte data access: 000H to 0FFH Half word data access: 000H to 1FFH Word data access: 000H to 3FFH Notes: • Access to the external area can be execute in the single chip mode. To access to the external area, select internal ROM external bus mode via mode resistor. Never execute data access to the instruction ROM area. • In the instruction/data ROM, images in block of 64 Kbytes can be seen. Make an instruction/data in the area 000F0000H to 000FFFFFH. 20 MB91106 Series 2. Registers The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose registers on memory. • Dedicated registers Program counter (PC): Program status (PS): Table base register (TBR): 32-bit length, indicates the location of the instruction to be executed. 32-bit length, register for storing register pointer or condition codes Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap) processing. Return pointer (RP): Holds address to resume operation after returning from a subroutine. System stack pointer (SSP): Indicates system stack space. User's stack pointer (USP): Indicates user’s stack space. Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division 32 bits PC Program counter PS Program status Initial value XXXX XXXXH Indeterminate Table base register 000F Return pointer XXXX XXXXH SSP System stack pointer 0000 USP User’s stack pointer XXXX XXXXH Indeterminate XXXX XXXXH Indeterminate XXXX XXXXH Indeterminate TBR RP MDH Multiplication/division result register MDL FC00H Indeterminate 0000H • Program status (PS) The PS register is for holding program status and consists of a condition code register (CCR), a system condition code register (SCR) and a interrupt level mask register (ILM). 31 PS — 20 19 18 17 16 ILM4 ILM3 ILM2 ILM1 ILM0 ILM — 10 9 8 7 6 5 4 3 2 1 0 D1 D0 T — — S I N Z V C SCR CCR 21 MB91106 Series • Condition code register (CCR) S-flag: I-flag: N-flag: Z-flag: V-flag: Specifies a stack pointer used as R15. Controls user interrupt request enable/disable. Indicates sign bit when division result is assumed to be in the 2’s complement format. Indicates whether or not the result of division was “0”. Assumes the operand used in calculation in the 2’s complement format and indicates whether or not overflow has occurred. Indicates if a carry or borrow from the MSB has occurred. C-flag: • System condition code register (SCR) T-flag: Specifies whether or not to enable step trace trap. • Interrupt level mask register (ILM) ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 ILM3 ILM2 ILM1 ILM0 Interrupt level High-low 0 0 0 0 0 0 High : : 0 1 0 : : 0 0 : : 1 22 1 1 15 : : 1 1 31 Low MB91106 Series ■ GENERAL-PURPOSE REGISTERS R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer (field for indicating address). • Register bank structure 32 bits Initial value R0 R13 AC (accumulator) R14 FP (frame pointer) XXXX XXXXH : : : : : : : : : : : XXXX XXXXH R15 SP (stack pointer) 0 0 0 0 0 0 0 0H R1 : : R12 Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13: Virtual accumulator (AC) R14: Frame pointer (FP) R15: Stack pointer (SP) Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value). 23 MB91106 Series ■ SETTING MODE 1. Pin • Mode setting pins and modes Mode setting pins Mode name Reset vector access area External data bus width MD2 MD1 MD0 Bus mode 0 0 0 External vector mode 0 External 8 bits 0 0 1 External vector mode 1 External 16 bits 0 1 0 — — — 0 1 1 Internal vector mode Internal (Mode register) 1 — — — — — External ROM/external bus mode Inhibited Single-chip mode* Not use * : MB91106 support single-chip mode. 2. Registers • Mode setting registers (MODR) and modes Address 0000 07FFH M1 M0 * * * * * * Initial value Access XXXX XXXXB W Bus mode setting bit W : Write only X : Indeterminate * : Always write “0” except for M1 and M0. • Bus mode setting bits and functions 24 M1 M0 Functions 0 0 Single-chip mode 0 1 Internal ROM/external bus mode 1 0 External ROM/external bus mode 1 1 — Note Inhibited MB91106 Series ■ I/O MAP Address Register name (abbreviated) Register name Read/write Resources name Initial value 000000H PDR3 Port 3 data register R/W Port 3 XXXXXXXXB 000001H PDR2 Port 2 data register R/W Port 2 XXXXXXXXB 000002H (Vacancy) 000003H 000004H PDR7 Port 7 data register R/W Port 7 –––––––XB 000005H PDR6 Port 6 data register R/W Port 6 XXXXXXXXB 000006H PDR5 Port 5 data register R/W Port 5 XXXXXXXXB 000007H PDR4 Port 4 data register R/W Port 4 XXXXXXXXB 000008H PDRB Port B data register R/W Port B XXXXXXXXB 000009H PDRA Port A data register R/W Port A – XXXXXXXB R/W Port 8 – – XXXXXXB 00000AH 00000BH PDR8 (Vacancy) Port 8 data register 00000CH to 000011H (Vacancy) 000012H PDRE Port E data register R/W Port E XXXXXXXXB 000013H PDRF Port F data register R/W Port F XXXXXXXXB 000014H to 00001BH (Vacancy) 00001CH SSR0 Serial status register 0 R/W 00001DH SIDR0/SODR0 Serial input data register 0/serial output data register 0 R/W 00001EH SCR0 Serial control register 0 R/W 00000100B 00001FH SMR0 Serial mode register 0 R/W 00––0–00B 000020H SSR1 Serial status register 1 R/W 00001–00B 000021H SIDR1/SODR1 Serial input data register 1/serial output data register 1 R/W 000022H SCR1 Serial control register 1 R/W 00000100B 000023H SMR1 Serial mode register 1 R/W 00––0–00B 000024H SSR2 Serial status register 2 R/W 00001–00B 000025H SIDR2/SODR2 Serial input data register 2/serial output data register 2 R/W 000026H SCR2 Serial control register 2 R/W 00000100B 000027H SMR2 Serial mode register 2 R/W 00––0–00B 00001–00B UART0 UART1 UART2 XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 25 MB91106 Series Address 000028H 000029H 00002AH 00002BH Register name (abbreviated) TMRLR0 Register name 16-bit reload register 0 TMR0 000030H 000031H 000032H 000033H TMCSR0 16-bit reload timer control status register 0 TMRLR1 16-bit reload register 1 W TMR1 16-bit timer register 1 R 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH TMCSR1 16-bit reload timer control status register 1 ADCR A/D converter data register ADCS A/D converter control status register TMRLR2 16-bit reload register 2 000044H to 000077H R/W 16-bit reload timer 0 ––––0000B 00000000B XXXXXXXXB 16-bit reload timer 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W 16-bit reload timer 1 TMR2 R/W 00000000B XXXXXXXXB 00000000B 00000000B XXXXXXXXB W 16-bit timer register 2 ––––0000B 0 0 0 0 0 0XXB R 16-bit reload timer 2 R XXXXXXXXB XXXXXXXXB XXXXXXXXB (Vacancy) 000041H 000043H XXXXXXXXB 10-bit A/D converter 000040H 000042H XXXXXXXXB (Vacancy) 000035H 000037H R XXXXXXXXB (Vacancy) 000034H 000036H Initial value XXXXXXXXB W 16-bit timer register 0 00002DH 00002FH Resources name 16-bit reload timer 0 00002CH 00002EH Read/write TMCSR2 16-bit reload timer control status register 2 R/W 16-bit reload timer 2 ––––0000B 00000000B (Vacancy) (Continued) 26 MB91106 Series Address 000078H 000079H Register name (abbreviated) UTIM0/UTIMR0 Register name U-TIMER register ch. 0 /U-TIMER reload register ch. 0 00007AH Read/write Resources name R/W U-TIMER 0 00000000B 00000000B (Vacancy) 00007BH UTIMC0 U-TIMER control register ch. 0 R/W U-TIMER 0 00007CH U-TIMER register ch. 1/reload register ch. 1 R/W U-TIMER 1 00007DH Initial value UTIM1/UTIMR1 00007EH 0––00001B 00000000B 00000000B (Vacancy) 00007FH UTIMC1 U-TIMER control register ch. 1 R/W U-TIMER 1 000080H U-TIMER register ch. 2/U-TIMER reload register ch. 2 R/W U-TIMER 2 R/W U-TIMER 2 0––00001B External interrupt/ NMI 00000000B 000081H UTIM2/UTIMR2 000082H 0––00001B 00000000B 00000000B (Vacancy) 000083H UTIMC2 U-TIMER control register ch. 2 000084H to 000093H (Vacancy) 000094H EIRR External interrupt cause register R/W 000095H ENIR Interrupt enable register R/W 000096H to 000098H 00000000B (Vacancy) 000099H ELVR External interrupt request level setting register 00009AH to 0000D1H R/W External interrupt/ NMI 00000000B (Vacancy) 0000D2H DDRE Port E data direction register W Port E 00000000B 0000D3H DDRF Port F data direction register W Port F 00000000B R/W PWM timer 1 00110010B R/W PWM timer 2 0000D4H to 0000DBH 0000DCH 0000DDH (Vacancy) GCN1 General control register 1 0000DEH 0000DFH GCN2 00010000B (Vacancy) General control register 2 00000000B (Continued) 27 MB91106 Series Address 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H Register name (abbreviated) Register name Read/write PTMR0 PWM timer register 0 R PCSR0 PWM cycle setting register 0 W Resources name 11111111B 11111111B XXXXXXXXB PWM timer 0 PDUT0 PWM duty setting register 0 Initial value W XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000E6H PCNH0 Control status register H 0 R/W 0000000–B 0000E7H PCNL0 Control status register L 0 R/W 00000000B 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH PTMR1 PWM timer register 1 R PCSR1 PWM cycle setting register 1 W 11111111B 11111111B XXXXXXXXB PWM timer 1 PDUT1 PWM duty setting register 1 W XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000EEH PCNH1 Control status register H 1 R/W 0000000–B 0000EFH PCNL1 Control status register L 1 R/W 00000000B 0000F0H 0000F1H 0000F2H 0000F3H 0000F4H 0000F5H PTMR2 PWM timer register 2 R PCSR2 PWM cycle setting register 2 W 11111111B 11111111B XXXXXXXXB PWM timer 2 PDUT2 PWM duty setting register 2 W XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000F6H PCNH2 Control status register H 2 R/W 0000000–B 0000F7H PCNL2 Control status register L 2 R/W 00000000B 0000F8H 0000F9H 0000FAH 0000FBH 0000FCH 0000FDH PTMR3 PWM timer register 3 R PCSR3 PWM cycle setting register 3 W 11111111B 11111111B XXXXXXXXB PWM timer 3 PDUT3 PWM duty setting register 3 W XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000FEH PCNH3 Control status register H 3 R/W 0000000–B 0000FFH PCNL3 Control status register L 3 R/W 00000000B (Continued) 28 MB91106 Series Address Register name (abbreviated) Register name 000100H to 0001FFH Read/write Resources name (Vacancy) 000200H 000201H 000202H XXXXXXXXB DPDP DMAC parameter descriptor pointer XXXXXXXXB R/W XXXXXXXXB 000203H X0000000B 000204H 000205H 000206H Initial value 00000000B DACSR DMAC control status register R/W DMA controller (DMAC) 00000000B 00000000B 000207H 00000000B 000208H XXXXXXXXB 000209H 00020AH DATCR DMAC pin control register XX0 0 0 0 0 0 B R/W XX0 0 0 0 0 0 B 00020BH XX0 0 0 0 0 0 B 00020CH to 0003EFH (Vacancy) XXXXXXXXB 0003F0H 0003F1H 0003F2H BSD0 Bit search module 0-detection data register XXXXXXXXB W XXXXXXXXB 0003F3H XXXXXXXXB 0003F4H XXXXXXXXB 0003F5H 0003F6H BSD1 Bit search module 1-detection data register 0003F7H 0003FAH XXXXXXXXB Bit search module 0003F8H 0003F9H XXXXXXXXB R/W BSDC Bit search module transitiondetection data register W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0003FBH XXXXXXXXB 0003FCH XXXXXXXXB 0003FDH 0003FEH 0003FFH BSRR Bit search module detection result register R XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 29 MB91106 Series Address Register name (abbreviated) Register name Read/write Resources name Initial value 000400H ICR00 Interrupt control register 0 R/W –––11111B 000401H ICR01 Interrupt control register 1 R/W –––11111B 000402H ICR02 Interrupt control register 2 R/W –––11111B 000403H ICR03 Interrupt control register 3 R/W –––11111B 000404H ICR04 Interrupt control register 4 R/W –––11111B 000405H ICR05 Interrupt control register 5 R/W –––11111B 000406H ICR06 Interrupt control register 6 R/W –––11111B 000407H ICR07 Interrupt control register 7 R/W –––11111B 000408H ICR08 Interrupt control register 8 R/W –––11111B 000409H ICR09 Interrupt control register 9 R/W –––11111B 00040AH ICR10 Interrupt control register 10 R/W –––11111B 00040BH ICR11 Interrupt control register 11 R/W –––11111B 00040CH ICR12 Interrupt control register 12 R/W –––11111B 00040DH ICR13 Interrupt control register 13 R/W –––11111B 00040EH ICR14 Interrupt control register 14 R/W –––11111B 00040FH ICR15 Interrupt control register 15 R/W 000410H ICR16 Interrupt control register 16 R/W 000411H ICR17 Interrupt control register 17 R/W –––11111B 000412H ICR18 Interrupt control register 18 R/W –––11111B 000413H ICR19 Interrupt control register 19 R/W –––11111B 000414H ICR20 Interrupt control register 20 R/W –––11111B 000415H ICR21 Interrupt control register 21 R/W –––11111B 000416H ICR22 Interrupt control register 22 R/W –––11111B 000417H ICR23 Interrupt control register 23 R/W –––11111B 000418H ICR24 Interrupt control register 24 R/W –––11111B 000419H ICR25 Interrupt control register 25 R/W –––11111B 00041AH ICR26 Interrupt control register 26 R/W –––11111B 00041BH ICR27 Interrupt control register 27 R/W –––11111B 00041CH ICR28 Interrupt control register 28 R/W –––11111B 00041DH ICR29 Interrupt control register 29 R/W –––11111B 00041EH ICR30 Interrupt control register 30 R/W –––11111B 00041FH ICR31 Interrupt control register 31 R/W –––11111B Interrupt controller –––11111B –––11111B (Continued) 30 MB91106 Series Address Register name (abbreviated) Register name 000420H to 00042EH Read/write Interrupt control register 47 R/W 000430H DICR Delayed interrupt control register R/W 000431H HRCL Hold request cancel request level setting register R/W 000432H to 00047FH –––11111B Interrupt controller –––––––0B –––11111B (Vacancy) 000480H RSRR/WTCR Reset cause register/ watchdog cycle control register R/W 000481H STCR Standby control register R/W 000482H PDRR DMA controller request squelch register R/W 000483H CTBR Timebase timer clear register 000484H GCR Gear control register 000485H WPR Watchdog reset occurrence postpone register 000486H W 1X X X X – 0 0 B 000111––B Clock control ––––0000B XXXXXXXXB R/W 110011–1B W XXXXXXXXB (Vacancy) 000487H 000489H to 0005FFH Initial value (Vacancy) 00042FH ICR47 000488H PCTR Resources name PLL control register R/W PLL control 00––0–––B (Vacancy) 000600H DDR3 Port 3 data direction register W Port 3 00000000B 000601H DDR2 Port 2 data direction register W Port 2 00000000B 000602H to 000603H (Vacancy) 000604H DDR7 Port 7 data direction register W Port 7 –––––––0B 000605H DDR6 Port 6 data direction register W Port 6 00000000B 000606H DDR5 Port 5 data direction register W Port 5 00000000B 000607H DDR4 Port 4 data direction register W Port 4 00000000B 000608H DDRB Port B data direction register W Port B 00000000B 000609H DDRA Port A data direction register W Port A –0000000B W Port 8 ––000000B 00060AH 00060BH DDR8 (Vacancy) Port 8 data direction register (Continued) 31 MB91106 Series Address 00060CH Register name (abbreviated) Register name Read/write Resources name Initial value 00000000B ASR1 Area select register 1 W AMR1 Area mask register 1 W ASR2 Area select register 2 W AMR2 Area mask register 2 W ASR3 Area select register 3 W AMR3 Area mask register 3 W ASR4 Area select register 4 W AMR4 Area mask register 4 W ASR5 Area select register 5 W AMR5 Area mask register 5 W 000620H AMD0 Area mode register 0 R/W –––00111B 000621H AMD1 Area mode register 1 R/W 0––00000B 000622H AMD32 Area mode register 32 R/W 00000000B 000623H AMD4 Area mode register 4 R/W 0––00000B 000624H AMD5 Area mode register 5 R/W 0––00000B 000625H DSCR DRAM signal control register W 00000000B 00060DH 00060EH 00060FH 000610H 000611H 000612H 000613H 000614H 000615H 000616H 000617H 000618H 000619H 00061AH 00061BH 00061CH 00061DH 00061EH 00061FH 000626H 000627H 000628H 000629H 00062AH 00062BH 00062CH 00062DH 00062EH 00062FH RFCR Refresh control register R/W EPCR0 External pin control register 0 W EPCR1 External pin control register 1 W DMCR4 DRAM control register 4 R/W DMCR5 DRAM control register 5 R/W 00000001B 00000000B 00000000B 00000000B 00000010B 00000000B 00000000B 00000000B 00000011B 00000000B 00000000B 00000000B 00000100B 00000000B 00000000B 00000000B External bus 0 0 0 0 0 1 0 1 B interface 00000000B 00000000B – –XXXXXXB 00–––000B ––––1100B –1111111B –––––––1B 11111111B 00000000B 0000000–B 00000000B 0000000–B (Continued) 32 MB91106 Series (Continued) Address Register name (abbreviated) Register name 000630H to 0007FDH Read/write Resources name Initial value (Vacancy) 0007FEH LER Little endian register W 0007FFH MODR Mode register W External bus – – – – – 0 0 0 B interface XXXXXXXXB About Programming R/W: Readable and writable R: Read only W: Write only Explanation of initial values 0: The initial value of this bit is “0”. 1: The initial value of this bit is “1”. X: The initial value of this bit is undefined. –: This bit is not used. The initial value of this bit is undefined. RMW system instructions (RMW: Read Modify Write) AND Rj, @ Ri OR Rj, @ Ri EOR ANDH Rj, @ Ri ORH Rj, @ Ri EORH ANDB Rj, @ Ri ORB Rj, @ Ri EORB BANDL #µ4, @ Ri BORL #µ4, @ Ri BEORL BANDH #µ4, @ Ri BORH #µ4, @ Ri BEORH Rj, @ Ri Rj, @ Ri Rj, @ Ri #µ4, @ Ri #µ4, @ Ri Notes: • Never execute a RMW system instruction to the resistor has a write only bit. • The area “vacancy” on the I/O map is reserved area. Access to this area are deal with to an internal area. No access signals to the external area would be generated. 33 MB91106 Series ■ INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS Interrupt number Interrupt level Decimal Hexadecimal Register Offset TBR default address Reset 0 00 — 3FCH 000FFFFCH Reserved for system 1 01 — 3F8H 000FFFF8H Reserved for system 2 02 — 3F4H 000FFFF4H Reserved for system 3 03 — 3F0H 000FFFF0H Reserved for system 4 04 — 3ECH 000FFFECH Reserved for system 5 05 — 3E8H 000FFFE8H Reserved for system 6 06 — 3E4H 000FFFE4H Reserved for system 7 07 — 3E0H 000FFFE0H Reserved for system 8 08 — 3DCH 000FFFDCH Reserved for system 9 09 — 3D8H 000FFFD8H Reserved for system 10 0A — 3D4H 000FFFD4H Reserved for system 11 0B — 3D0H 000FFFD0H Reserved for system 12 0C — 3CCH 000FFFCCH Reserved for system 13 0D — 3C8H 000FFFC8H Exception for undefined instruction 14 0E — 3C4H 000FFFC4H NMI request 15 0F FH fixed 3C0H 000FFFC0H External interrupt 0 16 10 ICR00 3BCH 000FFFBCH External interrupt 1 17 11 ICR01 3B8H 000FFFB8H External interrupt 2 18 12 ICR02 3B4H 000FFFB4H External interrupt 3 19 13 ICR03 3B0H 000FFFB0H UART0 receive complete 20 14 ICR04 3ACH 000FFFACH UART1 receive complete 21 15 ICR05 3A8H 000FFFA8H UART2 receive complete 22 16 ICR06 3A4H 000FFFA4H UART0 transmit complete 23 17 ICR07 3A0H 000FFFA0H UART1 transmit complete 24 18 ICR08 39CH 000FFF9CH UART2 transmit complete 25 19 ICR09 398H 000FFF98H DMAC0 (complete, error) 26 1A ICR10 394H 000FFF94H DMAC1 (complete, error) 27 1B ICR11 390H 000FFF90H DMAC2 (complete, error) 28 1C ICR12 38CH 000FFF8CH DMAC3 (complete, error) 29 1D ICR13 388H 000FFF88H DMAC4 (complete, error) 30 1E ICR14 384H 000FFF84H DMAC5 (complete, error) 31 1F ICR15 380H 000FFF80H Interrupt causes (Continued) 34 MB91106 Series Interrupt number Interrupt level Decimal Hexadecimal Register Offset TBR default address DMAC6 (complete, error) 32 20 ICR16 37CH 000FFF7CH DMAC7 (complete, error) 33 21 ICR17 378H 000FFF78H A/D converter (successive approximation conversion type) 34 22 ICR18 374H 000FFF74H 16-bit reload timer 0 35 23 ICR19 370H 000FFF70H 16-bit reload timer 1 36 24 ICR20 36CH 000FFF6CH 16-bit reload timer 2 37 25 ICR21 368H 000FFF68H PWM 0 38 26 ICR22 364H 000FFF64H PWM 1 39 27 ICR23 360H 000FFF60H PWM 2 40 28 ICR24 35CH 000FFF5CH PWM 3 41 29 ICR25 358H 000FFF58H U-TIMER 0 42 2A ICR26 354H 000FFF54H U-TIMER 1 43 2B ICR27 350H 000FFF50H U-TIMER 2 44 2C ICR28 34CH 000FFF4CH Reserved for system 45 2D ICR29 348H 000FFF48H Reserved for system 46 2E ICR30 344H 000FFF44H Reserved for system 47 2F ICR31 340H 000FFF40H Reserved for system 48 30 — 33CH 000FFF3CH Reserved for system 49 31 — 338H 000FFF38H Reserved for system 50 32 — 334H 000FFF34H Reserved for system 51 33 — 330H 000FFF30H Reserved for system 52 34 — 32CH 000FFF2CH Reserved for system 53 35 — 328H 000FFF28H Reserved for system 54 36 — 324H 000FFF24H Reserved for system 55 37 — 320H 000FFF20H Reserved for system 56 38 — 31CH 000FFF1CH Reserved for system 57 39 — 318H 000FFF18H Reserved for system 58 3A — 314H 000FFF14H Reserved for system 59 3B — 310H 000FFF10H Reserved for system 60 3C — 30CH 000FFF0CH Reserved for system 61 3D — 308H 000FFF08H Reserved for system 62 3E — 304H 000FFF04H Delayed interrupt cause bit 63 3F ICR47 300H 000FFF00H Interrupt causes (Continued) 35 MB91106 Series (Continued) Interrupt number Hexadecimal Register Offset TBR default address Reserved for system (used in REALOS*) 64 40 — 2FCH 000FFEFCH Reserved for system (used in REALOS*) 65 41 — 2F8H 000FFEF8H Used in INT instructions 66 to 255 42 to FF — 2F4H to 000H 000FFEF4H to 000FFD00H * : When using in REALOS/FR, interrupt 0x40, 0x41 for system code. 36 Interrupt level Decimal Interrupt causes MB91106 Series ■ PERIPHERAL RESOURCES 1. I/O Ports There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register (DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/ output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. Bit “0” specifies input and “1” specifies output. • For input (DDR = “0”) setting; PDR reading operation: reads level of corresponding external pin. PDR writing operation: writes set value to PDR. • For output (DDR = “1”) setting; PDR reading operation: reads PDR value. PDR writing operation: outputs PDR value to corresponding external pin. (1) Register configuration • Port data register Address bit 7 bit 0 Initial value 000001H PDR2 XXXXXXXX B (R/W) 000000H PDR3 XXXXXXXX B (R/W) 000007H PDR4 XXXXXXXX B (R/W) 000006H PDR5 XXXXXXXX B (R/W) 000005H PDR6 XXXXXXXX B (R/W) 000004H PDR7 - - - - - - -X B (R/W) 00000BH PDR8 - - XXXXXX B (R/W) 000009H PDRA - XXXXXXX B (R/W) 000008H PDRB XXXXXXXX B (R/W) 000012H PDRE XXXXXXXX B (R/W) 000013H PDRF XXXXXXXX B (R/W) ( ) : Access R/W : Readable and writable X : Indeterminate 37 MB91106 Series • Data direction register Address bit 7 bit 0 Initial value 000601H DDR2 00000000 B (W) 000600H DDR3 00000000 B (W) 000607H DDR4 00000000 B (W) 000606H DDR5 00000000 B (W) 000605H DDR6 00000000 B (W) 000604H DDR7 - - - - - - - 0 B (W) 00060BH DDR8 - - 000000 B (W) 000609H DDRA - 0000000 B (W) 000608H DDRB 00000000 B (W) 0000D2H DDRE 00000000 B (W) 0000D3H DDRF 00000000 B (W) ( ) : Access W : Write only – : Unused (2) Block diagram Resource input 0 1 Data bus PDR read 0 PDR (Port data register) Resource output 1 Resource output enable DDR (Data direction register) 38 Pin MB91106 Series 2. DMA Controller (DMAC) The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. • • • • • • • 8 channels Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer Transfer all through the area Max. 65536 of transfer cycles Interrupt function right after the transfer Selectable for address transfer increase/decrease by the software External transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each (1) Registers configuration • DMAC internal registers • DMAC parameter descriptor pointer Address 00000200H bit 31 bit 0 DPDP • DMAC control status register Address 00000204H bit 31 bit 0 DACSR • DMAC pin control register Address bit 31 00000208H bit 0 DATCR Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B X0000000 B Initial value 00000000 B 00000000 B 00000000 B 00000000 B Initial value XXXXXXXX XX0 0 0 0 0 0 XX0 0 0 0 0 0 XX0 0 0 0 0 0 (R/W) (R/W) B B (R/W) B B ( ) : Access R/W : Readable and writable X : Indeterminate 39 MB91106 Series • DMAC descriptor • The first word of descriptor bit 31 bit 16 (R/W) DMACT bit 15 – bit 11 bit 8 bit 7 bit 0 (R/W) BLK • The second word of descriptor bit 0 bit 31 (R/W) SADR • The third word of descriptor bit 0 bit 31 DADR R/W: Readable and writable 40 (R/W) MB91106 Series (2) Block diagram 3 Edge/level detection circuit 3 3 Sequencer Inner resource Transfer request DACK0 to DACK2 3 EOP0 to EOP2 8 Interrupt request 5 Data buffer Switcher DMAC parameter descriptor pointer (DPDP) DMAC control status registger (DACSR) DMAC pin control registger (DATCR) Data bus DREQ0 to DREQ2 Mode BLK DEC BLK The first word of descriptor (DMACT) INC / DEC The second word of descriptor (SADR) The third word of descriptor (DADR) 41 MB91106 Series 3. UART The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features. The MB91106 consists of 3 channels of UART. • • • • Full double double buffer Both a synchronous (start-stop system) communication and CLK synchronous communication are available. Supporting multi-processor mode Perfect programmable baud rate Any baud rate can be set by internal timer (refer to section “4. U-TIMER”). • Any baud rate can be set by external clock. • Error checking function (parity, framing and overrun) • Transfer signal: NRZ code • Enable DMA transfer/start by interrupt. (1) Register configuration • Serial control register 0 to 2 Address SCR0 : 00001EH SCR1 : 000022H SCR2 : 000026H bit 15 bit 8 bit 7 SCR0 to SCR2 bit 0 SMR Initial value 00000100 B (R/W) B (R/W) B (R/W) • Serial model register 0 to 2 Address SMR0 : 00001FH SMR1 : 000023H SMR2 : 000027H bit 15 bit 8 bit 7 (SCR) bit 0 SMR0 to SMR2 Initial value 00- - 0- 00 • Serial status register 0 to 2 Address SSR0 : 00001CH SSR1 : 000020H SSR2 : 000024H bit 15 bit 8 bit 7 SSR0 to SSR2 bit 0 SID Initial value 00001- 00 • Serial input data register 0 to 2 Address SIDR0 : 00001DH SIDR1 : 000021H SIDR2 : 000025H bit 15 bit 8 bit 7 (SSR) bit 0 SIDR0 to SIDR2 Initial value X X X X X X X X B (R) • Serial output data register 0 to 2 Address SODR0 : 00001DH SODR1 : 000021H SODR2 : 000025H () R/W – X 42 : : : : bit 15 Access Readable and writable Unused Indeterminate bit 8 bit 7 (SSR) SODR0 to SODR2 bit 0 Initial value X X X X X X X X B (W) MB91106 Series (2) Block diagram Control signals Receive interrupt (to CPU) SC (clock) Transmit interrupt (to CPU) Transmit clock From U-TIMER Clock select circuit Receive clock From external clock SC SI (receive data) Receive control circuit Transmit control circuit Start bit detect circuit Transmit start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter SO (transmit data) Receive status judge circuit Receive shifter Receive error generate signal for DMA (to DMAC) Transmit shifter Transmit start Receive complete Serial input data register SIDR Serial output data register SIDR R-bus MD1 MD0 Serial register (SMR) CS0 SCKE SOE Serial control register (SCR) PEN P SBL CL A/D REC RXE TXE Serial status register (SSR) PE ORE FRE RDRF TDRE RIE TIE Control signals 43 MB91106 Series 4. U-TIMER (16-bit Timer for UART Baud Rate Generation) The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91106 has 3 channel U-TIMER embedded on the chip. When used as an interval timer, two cupple of U-TIMER (ch0, ch1) can be cascaded and an interva of up to 232 × φ can be counted. (1) Register configuration • U-TIMER register ch.0 to ch.2 Address UTIM0 : 00000078H UTIM1 : 0000007CH UTIM2 : 00000080H bit 15 bit 0 UTIM0 to UTIM2 Initial value 00000000 00000000 B Initial value 00000000 00000000 B (R) B • U-TIMER reload register ch.0 to ch.2 Address UTIMR0 : 00000078H UTIMR1 : 0000007CH UTIMR2 : 00000080H bit 15 bit 0 UTIMR0 to UTIMR2 (W) B • U-TIMER control register ch.0 to ch.2 Address UTIMC0 : 0000007BH UTIMC1 : 0000007FH UTIMC2 : 00000083H bit 8 bit 7 bit 15 (Vacancy) Initial value bit 0 0- - 00001 UTIMC0 to UTIMC2 B (R/W) ( ) : Access R/W : Readable and writable – : Unused (2) Block diagram bit 15 bit 0 Reload register (U-TIMER) Load bit 15 bit 0 U-TIMER register (UTIM) Underflow φ (Peripheral clock) MUX Clock U-TIMER control register (UTIMC) (ch.0 only) Underflow U-TIMER 44 f.f. To UART MB91106 Series 5. PWM Timer The PWM timer can output high accurate PWM waves efficiently. MB91106 has inner 4-channel PWM timers, and has the following features. • Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16bit compare resister with a buffer for duty setting, and a pin controller. • The count clock of a 16-bit down counter can be selected from the following four inner clocks. Inner clock φ, φ/4, φ/16, φ/64 • The counter value can be initialized “FFFFH” by the resetting or the counter borrow. • PWM output (each channel) 45 MB91106 Series (1) Register configuration • Control status register H0 to 3 Address PCNH0 : 0000E6H PCNH1 : 0000EEH PCNH2 : 0000F6H PCNH3 : 0000FEH bit 15 bit 8 bit 7 bit 0 PCNH0 to PCNH3 (PCNL) Initial value 0000000- B (R/W) B (R/W) • Control status register L0 to 3 Address PCNL0 : 0000E7H PCNL1 : 0000EFH PCNL2 : 0000F7H PCNL3 : 0000FFH bit 15 bit 0 (PCNH) PCNL0 to PCNL3 Initial value 00000000 • PWM cycle setting register 0 to 3 Address PCSR0 : 0000E2H PCSR1 : 0000EAH PCSR2 : 0000F2H PCSR3 : 0000FAH bit 15 bit 0 PCSR0 to PCSR3 Initial value X X X X X X X X B (W) • PWM duty setting register 0 to 3 Address PDUT0 : 0000E4H PDUT1 : 0000ECH PDUT2 : 0000F4H PDUT3 : 0000FCH bit 15 bit 0 Initial value XXXXXXXXB (W) XXXXXXXXB bit 0 Initial value 11111111 11111111 B Initial value 00110010 00010000 B PDUT0 to PDUT3 • PWM timer register 0 to 3 Address PTMR0 : 0000E0H PTMR1 : 0000E8H PTMR2 : 0000F0H PTMR3 : 0000F8H bit 15 PTMR0 to PTMR3 (R) B • General control register 1, 2 Address GCN1 : 0000DCH Address GCN1 : 0000DFH () R/W R W – X 46 : : : : : : bit 15 bit 0 GCN1 bit 15 Access Readable and writable Read only Write only Unused Indeterminate bit 8 bit 7 (Vacancy) bit 0 GCN2 (R/W) B Initial value 00000000 B (R/W) MB91106 Series (2) Block diagram • Block diagram (general construction) 16-bit reload timer ch.0 TRG input PWM timer ch.0 PWM0 TRG input PWM timer ch.1 PWM1 4 TRG input PWM timer ch.2 PWM2 4 TRG input PWM timer ch.3 PWM3 16-bit reload timer ch.1 General control register 1 (cause selection) General control register 2 External TRG0 to TRG3 • Block diagram (for one channel) PWM duty setting register (PDUT) PWM cycle setting register (PCSR) Prescaler 1/1 1/4 1 / 16 1 / 64 ck cmp Load 16-bit down counter Start Borrow PPG mask S Q PWM output Peripheral clock R Enable TRG input Edge detect Interrupt selection Reverse bit IRQ Soft trigger 47 MB91106 Series 6. 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock). The DMA transfer can be started by the interruption. The MB91106 consists of 3 channels of the 16-bit reload timer. (1) Register configuration • 16-bit reload timer control status register 0 to 2 Address TMCSR0 : 00002EH TMCSR1 : 000036H TMCSR2 : 000042H bit 15 bit 0 TMCSR0 to TMCSR2 Initial value - - - - 0000 00000000 B (R/W) B • 16-bit timer register 0 to 2 Address TMR0 : 00002AH TMR1 : 000032H TMR2 : 00003EH bit 15 bit 0 Initial value XXXXXXXXB (R) XXXXXXXXB bit 0 Initial value XXXXXXXXB (W) XXXXXXXXB TMR0 to TMR2 • 16-bit reload register 0 to 2 Address TMRLR0 : 000028H TMRLR1 : 000030H TMRLR2 : 00003CH () R/W R W – X 48 : : : : : : bit 15 Access Readable and writable Read Only Write Only Unused Indeterminate TMRLR0 to TMRLR2 MB91106 Series (2) Block diagram 16 16-bit reload register (TMRLR) 8 Reload RELD 16 OUTE 16-bit down counter UF OUTL 2 INTE OUT CTL. GATE R-bus 2 IRQ UF CSL1 Clock selector CNTE CSL0 TRG 2 Retrigger IN CTL. EXCK φ φ 21 23 φ 25 3 Prescaler clear PWM (ch.0, ch.1) A/D (ch.2) MOD2 MOD1 Internal clock MOD0 3 49 MB91106 Series 7. Bit Search Module The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. (1) Register configuration • Bit search module 0, 1-detection data register Address BSD0 : 000003F0H BSD1 : 000003F4H bit 31 bit 0 BSD0, BSD1 Initial value XXXXXXXXB X X X X X X X X B (R/W) XXXXXXXXB XXXXXXXXB • Bit search module transition-detection data register Address 000003F8H bit 31 bit 0 BSDC Initial value XXXXXXXXB X X X X X X X X B (W) XXXXXXXXB XXXXXXXXB • Bit search module detection result register Address bit 31 000003FCH () R/W R W X : : : : : bit 0 BSRR Initial value XXXXXXXXB X X X X X X X X B (R) XXXXXXXXB XXXXXXXXB Access Readable and writable Read only Write only Indeterminate (2) Block diagram Input latch D-bus Address decoder Detection mode Single-detection data recovery Bit search circuit Search result register (BSRR) 50 MB91106 Series 8. 10-bit A/D Converter (Successive Approximation Conversion Type) The A/D converter is the module which converts an analog input voltage to a digital value, and it has following features. Minimum converting time: 5.6 µs/ch. (system clock: 25 MHz) Inner sample and hold circuit Resolution: 10 bits Analog input can be selected from 4 channels by program. Single convert mode: 1 channel is selected and converted. Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable. Continuous convert mode: Converting the specified channel repeatedly. Stop convert mode: After converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. • DMA transfer operation is available by interruption. • Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer (rising edge). • • • • (1) Register configuration • A/D converter control status register Address bit 15 0000003AH bit 0 ADCS Initial value 00000000 00000000 B (R/W) B • A/D converter data register Address bit 15 00000038H () R/W R – X : : : : : bit 0 ADCR Initial value 0 0 0 0 0 0 XXB (R) XXXXXXXXB Access Readable and writable Read only Unused Indeterminate 51 MB91106 Series (2) Block diagram AVCC AVR AVSS Internal voltage generator MPX AN1 AN2 Input circuit AN0 Successive approximation register Comparator AN3 Decoder R-bus Sample & hold circuit A/D Converter Data register (ADCR) A/D Converter control status register (ADCS) Trigger start ATG TIM0 (internal connection) (16-bit reload timer 2) φ (Peripheral clock) 52 Timer start Operating clock Prescaler MB91106 Series 9. Interrupt Controller The interrupt controller processes interrupt acknowledgments and arbitration between interrupts. • Hardware Configuration Interrupt controller is configured by ICR resistor, interrupt priority decision circuit, interrupt level, vector generation and HLDREQ cancel request, and has the following functions. • Main Functions NMI request/Interrupt request detection Priority (judgement) decision (via level and vector) Transfer of judged interrupt level to CPU Transfer of judged interrupt vector to CPU Return instruction from the stop mode via NMI/interrupt Generation of HOLD request cancel request to the bus timer 53 MB91106 Series (1) Register configuration • Interrupt control register 0 to 31, 47 Address bit 7 bit 0 Initial value Address bit 7 bit 0 Initial value 00000400H ICR00 - - - 11111 B (R/W) 00000411H ICR17 - - - 11111 B (R/W) 00000401H ICR01 - - - 11111 B (R/W) 00000412H ICR18 - - - 11111 B (R/W) 00000402H ICR02 - - - 11111 B (R/W) 00000413H ICR19 - - - 11111 B (R/W) 00000403H ICR03 - - - 11111 B (R/W) 00000414H ICR20 - - - 11111 B (R/W) 00000404H ICR04 - - - 11111 B (R/W) 00000415H ICR21 - - - 11111 B (R/W) 00000405H ICR05 - - - 11111 B (R/W) 00000416H ICR22 - - - 11111 B (R/W) 00000406H ICR06 - - - 11111 B (R/W) 00000417H ICR23 - - - 11111 B (R/W) 00000407H ICR07 - - - 11111 B (R/W) 00000418H ICR24 - - - 11111 B (R/W) 00000408H ICR08 - - - 11111 B (R/W) 00000419H ICR25 - - - 11111 B (R/W) 00000409H ICR09 - - - 11111 B (R/W) 0000041AH ICR26 - - - 11111 B (R/W) 0000040AH ICR10 - - - 11111 B (R/W) 0000041BH ICR27 - - - 11111 B (R/W) 0000040BH ICR11 - - - 11111 B (R/W) 0000041CH ICR28 - - - 11111 B (R/W) 0000040CH ICR12 - - - 11111 B (R/W) 0000041DH ICR29 - - - 11111 B (R/W) 0000040DH ICR13 - - - 11111 B (R/W) 0000041EH ICR30 - - - 11111 B (R/W) 0000040EH ICR14 - - - 11111 B (R/W) 0000041FH ICR31 - - - 11111 B (R/W) 0000040FH ICR15 - - - 11111 B (R/W) 0000042FH ICR47 - - - 11111 B (R/W) 00000410H ICR16 - - - 11111 B (R/W) • Hold request cancel request level setting register Address 00000431H ( ) : Access R/W : Redable and writable – : Unused 54 bit 7 bit 0 HRCL Initial value - - - 11111 B (R/W) MB91106 Series (2) Block diagram INT0*2 Priority judgment OR 5 NMI 5 NMI processing 4 Level judgment ICR00 RI00 • • • 6 • • • • • Vector judgment 6 HLDCAN*3 VCT5 to VCT0*5 ICR47 RI47 (DLYIRQ) Level, vector generation HLDREQ cancel request LEVEL4 to LEVEL0*4 DLYI*1 R-bus *1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11. Delayed Interrupt Module” for detail). *2: INT0 is a wake-up signal to clock control block in the sleep or stop status. *3: HLDCAN is a bus release request signal for bus masters other than CPU. *4: LEVEL5 to LEVEL0 are interrupt level outputs. *5: VCT5 to VCT0 are interrupt vector outputs. 55 MB91106 Series 10. External Interrupt/NMI Control Block The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to INT3 pins. Detecting levels can be selected from “H”, “L”, rising edge and falling edge (not for NMI pin). (1) Register configuration • Interrupt enable register Address bit 15 bit 0 bit 7 00000095H (EIRR) Initial value 00000000 ENIR B (R/W) B (R/W) B (R/W) • External interrupt cause register Address bit 8 bit 15 00000094H EIRR bit 0 (ENIR) Initial value 00000000 • External interrupt request level setting register Address bit 15 bit 0 00000099H ELVR Initial value 00000000 ( ) : Access R/W : Redable and writable (2) Block diagram 8 Interrupt enable register (ENIR) 9 R-bus Interrupt request 8 8 56 Gate Cause F/F Edge detection circuit External interrupt cause register (EIRR) External interrupt request level setting register (ELVR) 5 INT0 to INT3 NMI MB91106 Series 11. Delayed Interrupt Module Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed interrupt module, an interrupt request to CPU can be generated/cancelled by the software. Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram. • Register configuration • Delayed interrupt control register Address bit 7 00000430H bit 0 DICR Initial value - - - - - - - 0 B (R/W) ( ) : Access R/W : Redable and writable – : Unused 57 MB91106 Series 12. Clock Generation (Low-power consumption mechanism) The clock control block is a module which undertakes the following functions. • • • • • • CPU clock generation (including gear function) Peripheral clock generation (including gear function) Reset generation and cause hold Standby function DMA request prohibit PLL (multiplier circuit) embedded (1) Register configuration • Reset cause register/watchdog cycle control register Address bit 10 bit 9 bit 8 bit 15 00000480H RSRR WTCR bit 0 Initial value 1 XXXX- 0 0 (STCR) B (R/W) B (R/W) B (R/W) • Standby control register Address bit 7 bit 15 00000481H bit 0 (STCR) (RSRR/WTCR) Initial value 000111- - • DMA controller request squelch register Address bit 8 bit 15 00000482H bit 0 (CTBR) PDRR Initial value - - - - 0000 • Timebase timer clear register Address bit 7 bit 15 00000483H (PDRR) bit 0 CTBR Initial value X X X X X X X X B (W) • Gear control register Address bit 8 bit 15 00000484H GCR bit 0 (WPR) Initial value 110011- 1 B (R/W) • Watchdog reset occurrence postpone register Address bit 7 bit 15 00000485H (GCR) bit 0 WPR Initial value X X X X X X X X B (W) • PLL control register Address () R/W R W – X 58 : : : : : : bit 8 bit 15 00000488H Access Readable and writable Read Only Write Only Unused Indeterminate PCTR bit 0 (Vacancy) Initial value 00- - 0- - - B (R/W) MB91106 Series (2) Block diagram [Gear control block] Gear control register (GCR) X0 X1 Oscillator circuit PLL control register (PCTR) PLL 1/2 Peripheral gear Selection circuit R-bus CPU gear CPU clock Internal bus clock Internal clock generation circuit External bus clock Peripheral DMA clock Internal peripheral clock [Stop/sleep control block] Internal interrupt request Internal reset Standby control register (STCR) STOP state Status transition control circuit CPU hold enable SLEEP state CPU hold request Reset generation F/F Internal reset [DMA prohibit circuit] DMA request DMA request prohibit register (PDRR) [Reset cause circuit] Power on sel RST pin Reset cause register (RSRR) [Watchdog control block] Watchdog reset generation postpone register (WPR) Watchdog reset postpone register F/F Timebase timer clear register (CTBR) Timebase time Count clock 59 MB91106 Series 13. External Bus Interface The external bus interface controls the interface between the device and the external memory and also the external I/O, and has the following features. • 25-bit (32 Mbytes) address output • 6 independent banks owing to the chip select function. Can be set to anywhere on the logical address space for minimum unit 64 Kbytes. Total 32 Mbytes × 6 area setting is available by the address pin and the chip select pin. • 8/16-bit bus width setting are available for every chip select area. • Programmable automatic memory wait (max. for 7 cycles) can be inserted. • DRAM interface support Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F) Single CAS DRAM Hyper DRAM 2 banks independent control (RAS, CAS, etc. control signals) DRAM select is available from 2CAS/1WE and 1CAS/2WE. Hi-speed page mode supported CBR/self refresh supported Programmable wave form • Unused address/data pin can be used for I/O port. • Little endian mode supported • Clock doublure: Internal bus 50 MHz, external bus 25 MHz (at source oscillation 12.5 MHz) 60 MB91106 Series (1) Register configuration • Area select register 1 to 5 Address 0000060CH bit 15 bit 0 ASR1 00000610H ASR2 00000614H ASR3 00000618H ASR4 0000061CH ASR5 Initial value 00000000 00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 4 0 5 B B B B B B B B B B • Area mask register 1 to 5 Address bit 15 AMR1 : 0000060EH AMR2 : 00000612H AMR3 : 00000616H AMR4 : 0000061AH AMR5 : 0000061EH bit 0 AMR1 to AMR5 • Area mode register 0, 1, 32, 4, 5 Initial value 00000000 00000000 B B (W) B AMD0 AMD1 Initial value - - - 00111 0- - 00000 AMD32 : 00000622H AMD4 : 00000623H AMD32 AMD4 00000000 0- - 00000 B AMD5 : 00000624H AMD5 (DSCR) 0- - 00000 B (R/W) Initial value 00000000 B (W) Address AMD0 : 00000620H AMD1 : 00000621H bit 15 bit 8 bit 7 bit 0 (R/W) B B (R/W) • DRAM signle control register Address bit 15 00000625H bit 8 bit 7 (AMD5) bit 0 DSCR • Refresh control register Address bit 15 00000626H bit 0 Initial value - - XXXXXXB (R/W) 00- - - 000B bit 0 RFCR • External pin control register 0, 1 EPCR0 : 00000628H EPCR0 Initial value - - - - 1100 - 1111111 EPCR1 : 0000062AH EPCR1 - - - - - - - 1 11111111 Address bit 15 B (W) B B (W) B • DRAM control register 4, 5 Address DMCR4 : 0000062CH DMCR5 : 0000062EH bit 15 bit 0 DMCR4, DMCR5 Initial value 00000000 0000000- B (R/W) B • Litter endian register Address bit 15 000007FEH bit 8 bit 7 LER bit 0 (MODR) Initial value - - - - - 000 B (W) • Mode register Address bit 15 000007FFH () R/W W – X : : : : : bit 8 bit 7 (LER) bit 0 MODR Initial value X X X X X X X X B (W) Access Redable and writable Write only Unused Indeterminate 61 MB91106 Series (2) Block diagram Address bus 32 A-OUT Data bus 32 External data bus MUX Write buffer Switch Read buffer Switch DATA BLOCK ADDRESS BLOCK +1 or +2 External address bus Inpage Address buffer Shifter 6 Area select register(ASR) Area mask register(AMR) CS0 to CS5 Comparator 8 DRAM control RAS0, RAS1 CS0L, CS1L CS0H, CS1H DW0, DW1 Underflow DRAM control register (DMCR) Refresh counter register (RFCR) To TBT External pin control block 3 RD WR0, WR1 All blocks control Registers and control 62 4 BRQ BGRNT CLK RDY MB91106 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Symbol Value Min. Max. Unit Remarks Power supply voltage VCC VSS – 0.3 VSS + 4.0 V *1 Analog supply voltage AVCC VSS – 0.3 VSS + 4.0 V *2 Analog reference voltage AVRH VSS – 0.3 VSS + 4.0 V *2 Analog pin input voltage VIA VSS – 0.3 AVCC + 0.3 V Input voltage VI VSS – 0.3 VCC + 0.3 V Output voltage VO VSS – 0.3 VCC + 0.3 V “L” level maximum output current IOL — 10 mA *3 “L” level average output current IOLAV — 8 mA *4 “L” level maximum total output current ΣIOL — 100 mA “L” level average total output current ΣIOLAV — 50 mA *5 “H” level maximum output current IOH — –10 mA *3 “H” level average output current IOHAV — –4 mA *4 “H” level maximum total output current ΣIOH — –50 mA “H” level average total output current ΣIOHAV — –20 mA Power consumption PD — 500 mW Operating temperature TA 0 +70 °C Storage temperature Tstg –55 +150 °C *1: *2: *3: *4: *5: *5 VCC must not be less than VSS – 0.3 V. Make sure that the voltage does not exceed VCC + 0.3 V, such as when turning on the device. Maximum output current is a peak current value measured at a corresponding pin. Average output current is an average current for a 100 ms period at a corresponding pin. Average total output current is an average current for a 100 ms period for all corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 63 MB91106 Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Unit Remarks Min. Max. VCC 3.0 3.6 V Normal operation VCC 3.0 3.6 V Retaining the RAM state in stop mode Analog supply voltage AVCC VSS – 0.3 VSS + 3.6 V Analog reference voltage AVRH AVSS AVCC V Operating temperature TA 0 +70 °C Power supply voltage 64 Symbol Value MB91106 Series • Normal operation warranty rage Supply voltage VCC (V) Normal operation warranty range (TA = 0°C to +70°C) Net masked area are fCPP. 3.6 3.0 0 25 0.625 fCP/fCPP (MHz) 50 Internal clock • External/Internal clock setting rage Max. internal clock frequency setting fCP/fCPP (MHz) fCP CPU 50 PLL system (12.5MHz(Fixed) 4 multiplication) fCPP Peripheral 25 12.5 Divide-by-2 system 5 0 0 10 12.5 25 Fc (MHz) External clock Self-oscillation Notes: • When using PLL, the external clock must be used need 12.5 MHz. • PLL oscillation stabilizing period > 100 µs • The setting of internal clock must be within above ranges. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 65 MB91106 Series 3. DC Characteristics (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Symbol Pin name Condition VIH Input pin except for hysteresis input Unit Min. Typ. Max. — 0.7 × VCC — VCC + 0.3 V VIHS NMI, RST, P40 to P47, P50 to P57, P60 to P67, P70, P81, P83 to P85, PA0 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7 — 0.8 × VCC — VCC + 0.3 V VIL Input other than following symbols — VSS – 0.3 — 0.25 × VCC V VILS NMI, RST, P40 to P47, P50 to P57, P60 to P67, P70, P81, P83 to P85, PA0 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7 — VSS – 0.3 — 0.2 × VCC V VCC – 0.5 — — V “H” level input voltage “L” level input voltage Remarks Hysteresis input Hysteresis input “H” level output VOH voltage P2 to PF VCC = 3.0 V IOH = –4.0 mA “L” level output voltage P8 to PF VCC = 3.0 V IOL = 8.0 mA — — 0.4 V Input leakage current ILI (Hi-Z output leakage current) P2 to PF VCC = 3.6 V 0.45 V < VI < VCC –5 — +5 µA Pull-up resistance RPULL RST VCC = 3.6 V VI = 0.45 V 25 50 100 kΩ ICC VCC FC = 12.5 MHz VCC = 3.3 V — 70 150 mA Operation at 50 MHz ICCS VCC FC = 12.5 MHz VCC = 3.3 V — 37 70 mA Sleep mode ICCH VCC TA = +25°C VCC = 3.3 V — 1.4 150 µA Stop mode CIN Except for VCC, AVCC, AVSS, VSS — 10 — Power supply current Input capacitance 66 Value VOL — (4 multiplication) pF MB91106 Series 4. AC Characteristics (1) Measurement Conditions (VCC = 3.0 V to 3.6 V) Parameter Symbol Value Min. Typ. Max. Unit “H” level input voltage VIH — 1/2* × VCC — V “L” level input voltage VIL — 1/2* × VCC — V “H” level output voltage VOH — 1/2* × VCC — V “L” level output voltage VOL — 1/2* × VCC — V Remarks * : Input rise/fall time is 10 ns. and less. VCC 0.0 V ·Output Input VIH VOH VIL VOL 67 MB91106 Series (2) Clock Timing Rating (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Symbol Parameter Pin name Frequency shift ratio (when locked) Value Unit Min. Max. 12.5 12.5 MHz Remarks FC X0, X1 Self-oscillation at 12.5 MHz Internal operation at 50 MHz (Via PLL,quadruplex) FC X0, X1 Self-oscillation (divide-by-2 input) 10 25 MHz FC X0, X1 External clock (divide-by-2 input) 10 25 MHz tC X0, X1 Self-oscillation at 12.5 MHz Internal operation at 50 MHz (Via PLL,quadruplex) — 80 ns tC X0, X1 40 100 ns Self-oscillation at 12.5 MHz Internal operation at 50 MHz (Via PLL,quadruplex) — 5 % *1 Clock frequency Clock cycle time Condition ∆f — — PWH, PWL X0, X1 12.5 MHz to 25.0 MHz 20 — ns Input clock pulse to X0 and X1 PWH X0 12.5 MHz and less 25 — ns Input clock pulse to X0 only tCR, tCF X0, X1 — — 8 ns (tCR + tCF) Internal operating clock frequency fCP — CPU system 0.625*2 50 MHz fCPP — Peripheral system 2 0.625* 25 MHz Internal operating clock cycle time tCP — CPU system 20 1600*2 ns tCPP — Peripheral system 40 1600*2 ns Input clock pulse width Input clock rising/falling time *1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system. ∆f = α ×100 (%) f0 + +α Center frequency f0 –α – *2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and a 1/8 gear. 68 MB91106 Series • Load conditions Output pin C = 50 pF • Clock timing rating measurement conditions tC 0.8 VCC 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC X0 PWL PWH tCF tCR 69 MB91106 Series (3) Clock Output Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Symbol Pin name Parameter tCYC CLK tCYC CLK CLK ↑ → CLK ↓ tCHCL CLK CLK ↓ → CLK ↑ tCLCH CLK Cycle time Value Condition — Remarks Max. tCP*1 — ns 2 × tCP*1 — ns 1/2 × tCYC – 5 1/2 × tCYC + 5 ns *3 1/2 × tCYC – 5 1/2 × tCYC + 5 ns *4 — Using the doublure Unit Min. *2 *1: For information on tCP (internal operating clock cycle time), see “(2) Clock Timing Rating.” *2: tCYC is a frequency for 1 clock cycle including a gear cycle. Use the doublure when CPU frequency is above 25 MHz. *3: Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8, respectively. Min. : (1 – n/2) × tCYC – 10 Max. : (1 – n/2) × tCYC + 10 Select a gear cycle of × 1 when using the doublure. *4: Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8, respectively. Min. : n/2 × tCYC – 10 Max. : n/2 × tCYC + 10 Select a gear cycle of × 1 when using the doublure. tCYC tCHCL CLK tCLCH VOH VOH VOL 70 MB91106 Series The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows: However, in this chart source oscillation input means X0 input clock. Source oscillation input (when using the doublure) (1) PLL system (CHC bit of GCR set to “0”) (a) Gear × 1 CLK pin CCK1/0: “00” tCYC Source oscillation input (2) 2 dividing system (CHC bit of GCR set to “1”) (a) Gear × 1 CLK pin CCK1/0: “00” (b) Gear × 1/2 CLK pin CCK1/0: “01” (c) Gear × 1/4 CLK pin CCK1/0: “10” (d) Gear × 1/8 CLK pin CCK1/0: “11” tCYC tCYC tCYC tCYC 71 MB91106 Series • Ceramic oscillator applications Recommended circuit (2 contacts) Recommended circuit (3 contacts) X1 X0 X1 X0 * * C1 C1 C2 C2 C1, C2 internally connected. * : Murata Mfg. Co., Ltd. • Discreet type Oscillation frequency [MHz] 5.00 to 6.30 6.31 to 10.0 10.1 to 13.0 13.01 to 15.00 Model 30 CSA MG CST MGW CSA MG093 CST MGW093 CSA MTZ 30 CST MTW (30) CSA MTZ093 30 CST MTW093 (30) CSA MTZ 30 CST MTW (30) CSA MTZ093 30 CST MTW093 (30) (30) 30 (30) CSA MXZ040 15 CST MXW0C3 (15) ( ): C1 and C2 internally connected 3 contacts type. 72 Load capacitance C1 = C2 [pF] Power supply voltage VCC [V] 2.9 to 5.5 2.7 to 5.5 2.9 to 5.5 2.7 to 5.5 3.0 to 5.5 2.9 to 5.5 3.2 to 5.5 MB91106 Series (4) Reset Input Ratings (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Reset input time Symbol Pin name Condition tRSTL RST — Value Min. Max. tCP* × 5 — Unit Remarks ns * : For information on tCP (internal operating clock cycle time), see “(2) Clock Timing Rating.” tRSTL RST 0.2 VCC 0.2 VCC 73 MB91106 Series (5) Power on Supply Specifications (Power-on Reset) (AVCC = VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Symbol Pin name Power supply rising time tR VCC Power supply shut off time tOFF VCC Oscillation stabilizing time tOSC Value Condition Min. — Unit Remarks — 18 ms VCC < 0.2 V before the power supply rising 1 — ms Repeated operations 2 × tC* × 220 + 100 µs — ns VCC = 3.3 V — Max. * : For information on tC (clock cycle time), see “(2) Clock Timing Rating.” tR 0.9 VCC VCC 0.2 V 0.2 V 0.2 V tOFF Note: Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage. VCC A voltage rising rate of 50 mV/ms or less is recommended. VSS 336 ms approx. (@12.5 MHz) VCC tOSC (Oscillation stabilizing time) 0.8 VCC RST tRSTL + (tC × 219) tRSTL: Reset input time Notes: • Set RST pin to “L” level when turning on the device, at least the described above duration after the supply voltage reaches Vcc is necessary before turning the RST to “H” level. • Some internal resistors which are initialized only via power on reset are embedded in the device. To initialize these resistors, run power on reset by returning on the power supply. 74 MB91106 Series (6) Normal Bus Access Read/write Operation (AVCC = VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Symbol Pin name Condition Value Min. Max. Unit Remarks tCHCSL CLK, CS0 to CS5 — 15 ns tCHCSH CLK, CS0 to CS5 — 15 ns Address delay time tCHAV CLK, A24 to A00 — 15 ns Data delay time tCHDV CLK, D31 to D16 — 15 ns tCLRL CLK, RD — 6 ns tCLRH CLK, RD — 6 ns tCLWL CLK, WR0, WR1 — 6 ns tCLWH CLK, WR0, WR1 — 6 ns tAVDV A24 to A00, D31 to D16 — 3/2 × tCYC*1 – 25 ns *2 *3 RD ↓→ valid data input time tRLDV RD, D31 to D16 — tCYC*1 – 10 ns *2 Data set up → RD ↑ time tDSRH RD, D31 to D16 10 — ns RD ↑→ data hold time tRHDX RD, D31 to D16 10 — ns CS0 to CS5 delay time RD delay time WR0, WR1 delay time Valid address → valid data input time — *1: For information on tCYC (a cycle time of peripheral system clock), see “(3) Clock Output Timing.” *2: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC × extended cycle number for delay) to this rating. *3: Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (2 – n/2) × tCYC – 25 75 MB91106 Series BA2 BA1 tCYC CLK 2.4 V 2.4 V 0.8 V 2.4 V 0.8 V tCHCSL CS0 to CS5 tCHCSH 2.4 V 0.8 V tCHAV A24 to A00 2.4 V 0.8 V 2.4 V 0.8 V tCLRH tCLRL RD 2.4 V 0.8 V tRLDV tRHDX tAVDV 2.4 V 0.8 V D31 to D16 Read 2.4 V 0.8 V tDSRH tCLWL WR0, WR1 2.4 V 0.8 V tCLWH tCHDV D31 to D16 76 2.4 V 0.8 V Write 2.4 V 0.8 V MB91106 Series (7) Ready Input Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Symbol Pin name RDY set up time → CLK ↓ tRDYS RDY, CLK CLK ↓→ RDY hold time CLK, RDY tRDYH Value Condition — Unit Min. Max. 15 — ns 0 — ns Remarks tCYC CLK 2.4 V tRDYS RDY When wait(s) is inserted. RDY When no wait is inserted. 2.4 V 0.8 V 0.8 V tRDYH tRDYS 2.4 V 0.8 V 2.4 V tRDYH 2.4 V 0.8 V 2.4 V 0.8 V 0.8 V 77 MB91106 Series (8) Hold Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Symbol Pin name Condition Parameter Value Unit Min. Max. — 6 ns — 6 ns tCHBGL CLK, BGRNT tCHBGH CLK, BGRNT Pin floating → BGRNT ↓ time tXHAL BGRNT tCYC* – 10 tCYC* + 10 ns BGRNT ↑→ pin valid time tHAHV BGRNT tCYC* – 10 tCYC* + 10 ns BGRNT delay time — * : For information on tCYC (a cycle time of peripheral system clock), see “(3) Clock Output Timing.” Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change. tCYC CLK 2.4 V 2.4 V 2.4 V 2.4 V BRQ tCHBGL tCHBGH BGRNT 2.4 V 0.8 V tXHAL tHAHV Each pin High impedance 78 Remarks MB91106 Series (9) Normal DRAM Mode Read/Write Cycle (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Symbol Pin name Condition Value Min. Max. Unit tCLRAH CLK, RAS — 6 ns tCHRAL CLK, RAS — 6 ns tCLCASL CLK, CS0H, CS1H, CS0L, CS1L — 6 ns tCLCASH CLK, CS0H, CS1H, CS0L, CS1L — 6 ns ROW address delay time tCHRAV CLK, A24 to A00 — 15 ns COLUMN address delay time tCHCAV CLK, A24 to A00 — 15 ns — 15 ns RAS delay time CAS delay time — Remarks tCHDWL CLK, DW*2 tCHDWH CLK, DW*2 — 15 ns Output data delay time tCHDV1 CLK, D31 to D16 — 15 ns RAS ↓→ valid data input time tRLDV RAS, D31 to D16 — 5/2 × tCYC*1 – 16 ns *3 *4 CAS ↓→ valid data input time tCLDV CS0H, CS1H, CS0L, CS1L, D31 to D16 — tCYC*1 – 17 ns *3 CAS ↑→ data hold time tCADH CS0H, CS1H, CS0L, CS1L, D31 to D16 10 — ns DW delay time *1: For information on tCYC (a cycle time of peripheral system clock), see “(3) Clock Output Timing.” *2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE. *3: When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating. *4: Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (3 – n/2) × tCYC – 16 79 MB91106 Series Q1 Q2 Q3 Q4 Q5 tCYC CLK 2.4 V 0.8 V 2.4 V 2.4 V 2.4 V RAS 2.4 V 0.8 V 0.8 V 2.4 V 0.8 V tCHRAL tCLRAH tCLCASL CS0H, CS1H, CS0L, CS1L, 0.8 V 2.4 V 0.8 V 2.4 V tCHCAV tCHRAV A24 to A00 tCLCASH ROW address 2.4 V 0.8 V 2.4 V 0.8 V COLUMN address 2.4 V 0.8 V tRLDV tCADH tCLDV 2.4 V 0.8 V D31 to D16 Read 2.4 V DW 0.8 V tCHDWL D31 to D16 2.4 V 0.8 V tCHDV1 80 2.4 V 0.8 V Write tCHDWH 2.4 V 0.8 V MB91106 Series (10) Normal DRAM Mode Fast Page Read/Write Cycle (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter RAS delay time Symbol Pin name Condition Value Min. Max. Unit tCLRAH CLK, RAS — 6 ns tCLCASL CLK, CS0H, CS1H, CS0L, CS1L — 6 ns tCLCASH CLK, CS0H, CS1H, CS0L, CS1L — 6 ns COLUMN address delay time tCHCAV CLK, A24 to A00 — 15 ns DW delay time tCHDWH CLK, DW*2 — 15 ns Output data delay time tCHDV1 CLK, D31 to D16 — 15 ns CAS ↓→ valid data input time tCLDV CS0H, CS1H, CS0L, CS1L, D31 to D16 — tCYC*1 – 17 ns CAS ↑→ data hold time tCADH CS0H, CS1H, CS0L, CS1L, D31 to D16 10 — ns CAS delay time — Remarks *3 *1: For information on tCYC (a cycle time of peripheral system clock), see “(3) Clock Output Timing.” *2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE. *3: When Q4 cycle is extended for 1 cycle, add tCYC time to this rating. 81 MB91106 Series Q5 Q4 2.4 V CLK Q5 0.8 V Q4 Q5 2.4 V 0.8 V 0.8 V tCLRAH 2.4 V RAS tCLCASL tCLCASH CS0H, CS1H, CS0L, CS1L, A24 to A00 2.4 V 0.8 V tCHCAV COLUMN address 2.4 V 0.8 V 2.4 V 0.8 V COLUMN address 2.4 V 0.8 V Read 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V tCADH tCLDV D31 to D16 COLUMN address Read 2.4 V 0.8 V 2.4 V 0.8 V Read 2.4 V 0.8 V tCHDWH 2.4 V DW tCHDV1 D31 to D16 82 2.4 V 0.8 V Write 2.4 V 0.8 V 2.4 V 0.8 V Write 2.4 V 0.8 V MB91106 Series (11) Single DRAM Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Symbol Pin name Condition Value Unit Min. Max. — 6 ns 6 ns tCLRAH2 CLK, RAS tCHRAL2 CLK, RAS tCHCASL2 CLK, CS0H, CS1H, CS0L, CS1L — n/2 × tCYC*1 ns tCHCASH2 CLK, CS0H, CS1H, CS0L, CS1L — 6 ns ROW address delay time tCHRAV2 CLK, A24 to A00 — 15 ns COLUMN address delay time tCHCAV2 CLK, A24 to A00 — 15 ns tCHDWL2 CLK, DW*2 — 15 ns tCHDWH2 CLK, DW*2 — 15 ns Output data delay time tCHDV2 CLK, D31 to D16 — 15 ns CAS ↓→ Valid data input time tCLDV2 CS0H, CS1H, CS0L, CS1L, D31 to D16 — (1 – n/2) × tCYC*1 – 17 ns CAS ↑→ data hold time tCADH2 CS0H, CS1H, CS0L, CS1L, D31 to D16 10 — ns RAS delay time CAS delay time DW delay time — Remarks *1: For information on tCYC (a cycle time of peripheral system clock), see “(3) Clock Output Timing.” *2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE. 83 MB91106 Series tCYC Q1 CLK 2.4 V Q2 0.8 V 2.4 V 2.4 V 2.4 V RAS *1 Q4S Q3 Q4S Q4S 2.4 V 2.4 V 2.4 V 0.8 V tCHRAL2 tCLRAH2 tCHCASL2 CS0H, CS1H, CS0L, CS1L, tCHCASH2 0.8 V 2.4 V 0.8 V A24 to A00 ROW address 2.4 V 0.8 V 2.4 V 2.4 V COLUMN-0 0.8 V tCHRAV2 2.4 V 0.8 V COLUMN-2 COLUMN-1 tCHCAV2 tCADH2 tCLDV2 Read-0 D31 to D16 (Read) DW (Read) 2.4 V 0.8 V Read-1 2.4 V 0.8 V Read-2 2.4 V 0.8 V tCHDWH2 tCHDWL2 *2 D31 to D16 (Write) 2.4 V 0.8 V tCHDV2 Write-0 2.4 V 0.8 V tCHDV2 2.4 V 0.8 V 2.4 V 2.4 V 0.8 V 0.8 V Write-1 *1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. *2: indicates the timing when the bus cycle begins from the high spead page mode. 84 Write-2 MB91106 Series (12) Hyper DRAM Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Symbol Pin name Condition Value Min. Max. Unit tCLRAH3 CLK, RAS — 6 ns tCHRAL3 CLK, RAS — 6 ns tCHCASL3 CLK, CS0H, CS1H, CS0L, CS1L — n/2 × tCYC*1 ns tCHCASH3 CLK, CS0H, CS1H, CS0L, CS1L — 6 ns ROW address delay time tCHRAV3 CLK, A24 to A00 — 15 ns COLUMN address delay time tCHCAV3 CLK, A24 to A00 — 15 ns tCHRL3 CLK, RD — 15 ns tCHRH3 CLK, RD — 15 ns tCLRL3 CLK, RD — 15 ns tCHDWL3 CLK, DW*2 — 15 ns tCHDWH3 CLK, DW*2 — 15 ns Output data delay time tCHDV3 CLK, D31 to D16 — 15 ns CAS ↓→ valid data input time tCLDV3 CS0H, CS1H, CS0L, CS1L, D31 to D16 — tCYC – 17 ns CAS ↓→ data hold time tCADH3 CS0H, CS1H, CS0L, CS1L, D31 to D16 10 — ns RAS delay time CAS delay time RD delay time DW delay time — Remarks *1: For information on tCYC (a cycle time of peripheral system clock), see “(3) Clock Output Timing.” *2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE. 85 MB91106 Series tCYC *1 Q1 CLK 2.4 V Q2 0.8 V Q3 2.4 V 2.4 V 2.4 V RAS 2.4 V Q4H Q4H Q4H 2.4 V 2.4 V 0.8 V 0.8 V tCHRAL3 tCLRAH3 tCHCASL3 tCHCASH3 CS0H, CS1H, CS0L, CS1L, 2.4 V 2.4 V 0.8 V A24 to A00 ROW address tCHRAV3 DW (Read) 0.8 V 0.8 V 2.4 V 0.8 V 2.4 V COLUMN-0 0.8 V COLUMN-1 2.4 V COLUMN-2 tCHCAV3 *2 0.8 V 0.8 V tCHRL3 2.4 V tCHRH3 tCLRL3 tCLDV3 2.4 V 0.8 V D31 to D16 (Read) DW (Read) tCADH3 Read-0 Read-1 2.4 V 0.8 V 2.4 V 0.8 V tCHDWH3 tCHDWL3 *2 D31 to D16 (Write) 2.4 V 0.8 V tCHDV3 Write-0 2.4 V 0.8 V tCHDV3 2.4 V 0.8 V Write-2 Write-1 *1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. *2: indicates the timing when the bus cycle begins from the high spead page mode. 86 MB91106 Series (13) CBR Refresh (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter RAS delay time Symbol Pin name Unit — 6 ns tCHRAL CLK, RAS — 6 ns tCLCASL CLK, CS0H, CS1H, CS0L, CS1L — 6 ns tCLCASH CLK, CS0H, CS1H, CS0L, CS1L — 6 ns 2.4 V — R2 2.4 V 0.8 V R3 2.4 V 0.8 V 2.4 V Remarks R4 0.8 V 0.8 V tCHRAL tCLRAH CS0H, CS1H, CS0L, CS1L, Max. CLK, RAS tCYC R1 RAS Min. tCLRAH CAS delay time CLK Value Condition 0.8 V tCLCASL 2.4 V tCLCASH DW 87 MB91106 Series (14) Self Refresh (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Symbol Parameter RAS delay time CLK 2.4 V Condition Max. Unit — 6 ns tCHRAL CLK, RAS — 6 ns tCLCASL CLK, CS0H, CS1H, CS0L, CS1L — 6 ns tCLCASH CLK, CS0H, CS1H, CS0L, CS1L — 6 ns SR2 2.4 V — SR3 2.4 V 0.8 V RAS 0.8 V Remarks SR3 0.8 V 0.8 V tCLCASL 88 Min. CLK, RAS tCHRAL CS0H, CS1H, CS0L, CS1L, Value tCLRAH CAS delay time tCYC SR1 Pin name tCLRAH 2.4 V 2.4 V tCLCASH MB91106 Series (15) UART Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Serial clock cycle time Symbol Pin name Condition Value Unit Min. Max. 8 × tCYCP* — ns –80 80 ns 100 — ns tSCYC — SCLK ↓→ SOUT delay time tSLOV — Valid SIN → SCLK ↑ tIVSH — SCLK ↑→ valid SIN hold time tSHIX — 60 — ns Serial clock “H” pulse width tSHSL — 4 × tCYCP* — ns Serial clock “L” pulse width tSLSH — 4 × tCYCP* — ns — 150 ns 60 — ns 60 — ns SCLK ↓→ SOUT delay time tSLOV — Valid SIN → SCLK ↑ tIVSH — SCLK ↑→ valid SIN hold time tSHIX — Internal shift clock mode External shift clock mode Remarks * : For information on tCYCP (a cycle time of peripheral system clock), see “(2) Clock Timing Rating.” Notes: This rating is for AC characteristics in CLK synchronous mode. • Internal shift clock mode tSCYC SCLK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V 0.8 V SOUT tIVSH tSHIX 0.8 VCC 0.2 VCC SIN 0.8 VCC 0.2 VCC • External shift clock mode tSHSL tSLSH 0.8 VCC(2.6V) 0.8 VCC(2.6V) SCLK 0.2 VCC(0.7V) 0.2 VCC(0.7V) tSLOV SOUT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 89 MB91106 Series (16) Trigger System Input Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter A/D start trigger input time Symbol tATGX Pin name ATG Condition — Value Min. Max. 5 × tCYCP* — Unit ns * : For information on tCYCP (a cycle time of peripheral system clock), see “(2) Clock Timing Rating.” tATGX ATG 0.2 VCC 90 0.2 VCC Remarks MB91106 Series (17) DMA Controller Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C) Parameter Symbol Pin name Condition Value Unit Min. Max. DREQ0 to DREQ2 2 × tCYC* — ns tCLDL CLK, DACK0 to DACK2 — 6 ns tCLDH CLK, DACK0 to DACK2 — 6 ns EOP delay time (Normal bus) (Normal DRAM) tCLEL CLK, EOP0 to EOP2 — 6 ns tCLEH CLK, EOP0 to EOP2 — 6 ns DACK delay time (Single DRAM) (Hyper DRAM) tCHDL CLK, DACK0 to DACK2 — n/2 × tCYC* ns tCHDH CLK, DACK0 to DACK2 — 6 ns tCHEL CLK, EOP0 to EOP2 — n/2 × tCYC* ns tCHEH CLK, EOP0 to EOP2 — 6 ns DREQ input pulse width tDRWH DACK delay time (Normal bus) (Normal DRAM) EOP delay time (Single DRAM) (Hyper DRAM) — Remarks * : For information on tCYC (a cycle time of peripheral system clock), see “(3) Clock Output Timing.” tCYC CLK 2.4 V 2.4 V 0.8 V 0.8 V tCLDH tCLEH tCLDL tCLEL DACK0 to DACK2 EOP0 to EOP2 (Normal bus) (Normal DRAM) 2.4 V 0.8 V DACK0 to DACK2 EOP0 to EOP2 (Single DRAM) (Hyper DRAM) 2.4 V 0.8 V tCHDL tCHEL tCHDH tDRWH DREQ0 to DREQ2 2.4 V 2.4 V 91 MB91106 Series 5. A/D Converter Block Electrical Characteristics (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, AVRH = 3.0 V to 3.6 V, TA = 0°C to +70°C) Symbol Pin name Resolution — Total error Parameter Value Typ. Max. — — 10 10 bit — — — — ±3.0 LSB Linearity error — — — — ±2.5 LSB Differentiation linearity error — — — — ±1.9 LSB Zero transition voltage VOT AN0 to AN3 –1.5LSB +0.5LSB +2.5LSB mV Full-scale transition voltage VFST AN0 to AN3 AVRH – 4.5LSB AVRH – 1.5LSB AVRH + 0.5LSB mV — 5.6 *1 — — µs Conversion time — Analog port input current IAIN AN0 to AN3 — 0.1 10 µA Analog input voltage VAIN AN0 to AN3 AVSS — AVRH V AVRH AVSS — AVCC V IA AVCC — 4 — mA IAH AVCC — — 5 *2 µA IR AVRH — 110 — µA IRH AVRH — — 5 *2 µA AN0 to AN3 — — 4 LSB Reference voltage Power supply current Reference voltage supply current Conversion variance between channels — — *1: VCC = AVCC = 3.0 V to 3.6 V, machine clock 25 MHz *2: Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.6 V) 92 Unit Min. MB91106 Series 6. A/D Converter Glossary • Resolution The smallest change in analog voltage detected by A/D converter. • Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000 0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”). • Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage. • Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error. Total error 3FF 1.5 LSB’ 3FE Actual conversion characteristic Digital output 3FD {1 LSB’ × (N – 1) + 0.5 LSB’} 004 VNT (measured value) 003 Actual conversion characteristic 002 Ideal characteristic 001 0.5 LSB’ AVRL AVRH Analog input Total error of digital output N = VOT’ VFST’ VNT – {1 LSB’ × (N – 1) + 0.5 LSB’} 1 LSB' [LSB] (ideal value) = AVRL + 0.5 LSB’ [V] (ideal value) = AVRL – 1.5 LSB’ [V] VNT: A voltage for causing transition of digital output from (N – 1) to N (Continued) 93 MB91106 Series (Continued) Linearity error 3FF Differential Iinearity error Ideal characteristic Actual conversion characteristic 3FE N+1 {1 LSB × (N – 1) + VOT} Actual characteristic VFST (measured value) VNT (measured value) 004 Actual conversion characteristic 003 Digital output Digital output 3FD N N–1 V(N + 1)T VNT (measured value) (measured value) 002 Ideal characteristic N–2 001 VOT (measured value) AVRL Actual conversion characteristic AVRH AVRL Analog input Linearity error of = digital output N 1 LSB = VFST – VOT 1022 1 LSB’ (ideal value) = VNT – {1 LSB’ × (N – 1) + VOT} 1 LSB [LSB] Differential Iinearity error of digital output N = [V] AVRH – AVRL [V] 1022 VOT: A voltage for causing transition of digital output from (000)H to (001)H VFST: A voltage for causing transition of digital output from (3FE)H to (3FF)H VNT: A voltage for causing transition of digital output from (N – 1)H to N 94 AVRH Analog input V(N + 1)T – VNT 1 LSB –1 [LSB] MB91106 Series 7. Notes on Using A/D Converter Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 7 kΩ. If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling (sampling time is 5.6 µs for a machine clock of 25 MHz). • Analog input Equivalent Circuit Sample hold circuit Analog input pin C0 Comparator RON1 RON2 ON2 RON3 RON4 C1 RON1: 5 kΩ RON2: 620 kΩ RON3: 620 kΩ C0: 2 pF RON4: 620 kΩ C1: 2 pF • Error As the absolute value of AVRH decreases, relative error increases. 95 MB91106 Series ■ EXAMPLE CHARACTERISTICS (1) “H” Level Output Voltage VOH (V) 4.0 (2) “L” Level Output Voltage VOL (V) 0.25 VOH-IOH VCC = 3.6 V VCC = 3.3 V VCC = 3.0 V VCC = 2.7 V 3.5 3.0 2.5 VOL-IOL VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V 0.20 0.15 2.0 0.10 1.5 1.0 0.05 0.5 0.0 TA = +25°C TA = +25°C 0.00 -1 -2 -3 -4 -5 -6 -7 -8 IOH (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) 2.2 96 TA = +25°C 2.0 1.8 VIL 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 3.0 3.3 4 5 6 7 8 IOL (mA) VIN-VCC TA = +25°C 2.2 VIH 2.7 3 VIN (V) 2.4 2.0 0.4 2.4 2 (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN-VCC VIN (V) 2.4 1 3.6 VCC (V) VIH VIL 0.4 2.4 2.7 3.0 3.3 VIH: Threshold when input voltage is set to "H" Level. VIH: Threshold when input voltage in hysteresis characteristics is set to "H" Level. VIL: Threshold when input voltage is set to "L" Level. VIL: Threshold when input voltage in hysteresis characteristics is set to "L" Level. 3.6 VCC (V) MB91106 Series (5) Power Supply Current (fcp = Internal clock frequency) ICC (mA) ICC-VCC 100 TA = +25°C 90 fCP = 50 MHz ICCS (mA) ICCS-VCC 50 TA = +25°C 45 70 fCP = 40 MHz 30 50 25 40 fCP = 20 MHz fCP = 40 MHz 35 60 20 fCP = 20 MHz 15 30 20 fCP = 10 MHz 10 fCP = 10 MHz 5 10 0 2.7 fCP = 50 MHz 40 80 3.0 3.3 3.6 3.9 0 2.7 3.0 3.3 3.6 VCC (V) ICCH(µA) 2.0 TA = +25°C 1.8 3.9 VCC (V) IA (mA) IA-AVCC 2.5 TA = +25°C ICCH-VCC 2.0 1.6 1.4 1.5 1.2 1.0 1.0 0.8 0.6 0.5 0.4 0.2 0.0 2.7 3.0 3.3 3.6 0.0 2.7 3.0 3.3 3.6 AVCC (V) VCC (V) IR(µA) 130 125 3.9 IR-AVCC (6) Pull-up Resistance TA = +25°C R-VCC R (kΩ) 100 120 TA = +25°C 115 110 105 100 95 90 85 80 2.7 3.0 3.3 3.6 3.9 AVCC (V) 10 2.7 3.0 3.3 3.6 3.9 VCC (V) 97 MB91106 Series ■ INSTRUCTIONS (165 INSTRUCTIONS) 1. How to Read Instruction Set Summary Mnemonic ADD * ADD ↓ (1) Rj, Ri #s5, Ri , , ↓ (2) Type OP CYC NZVC Operation A C , , A6 A4 , , 1 1 , , CCCC CCCC , , Ri + Rj → Ri Ri + s5 → Ri , , ↓ (3) ↓ (4) ↓ (5) ↓ (6) ↓ (7) Remarks (1) Names of instructions Instructions marked with * are not included in CPU specifications. These are extended instruction codes added/extended at assembly language levels. (2) Addressing modes specified as operands are listed in symbols. Refer to “2. Addressing mode symbols” for further information. (3) Instruction types (4) Hexa-decimal expressions of instructions (5) The number of machine cycles needed for execution a: Memory access cycle and it has possibility of delay by Ready function. b: Memory access cycle and it has possibility of delay by Ready function. If an object register in a LD operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or if the instruction belongs to instruction format A group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. For a, b, c and d, minimum execution cycle is 1. (6) Change in flag sign • Flag change C : Change – : No change 0 : Clear 1 : Set • Flag meanings N : Negative flag Z : Zero flag V : Over flag C : Carry flag (7) Operation carried out by instruction 98 MB91106 Series 2. Addressing Mode Symbols Ri Rj R13 Ps Rs CRi CRj #i8 : Register direct (R0 to R15, AC, FP, SP) : Register direct (R0 to R15, AC, FP, SP) : Register direct (R13, AC) : Register direct (Program status register) : Register direct (TBR, RP, SSP, USP, MDH, MDL) : Register direct (CR0 to CR15) : Register direct (CR0 to CR15) : Unsigned 8-bit immediate (–128 to 255) Note: –128 to –1 are interpreted as 128 to 255 #i20 : Unsigned 20-bit immediate (–0X80000 to 0XFFFFF) Note: –0X7FFFF to –1 are interpreted as 0X7FFFF to 0XFFFFF #i32 : Unsigned 32-bit immediate (–0X80000000 to 0XFFFFFFFF) Note: –0X80000000 to –1 are interpreted as 0X80000000 to 0XFFFFFFFF #s5 : Signed 5-bit immediate (–16 to 15) #s10 : Signed 10-bit immediate (–512 to 508, multiple of 4 only) #u4 : Unsigned 4-bit immediate (0 to 15) #u5 : Unsigned 5-bit immediate (0 to 31) #u8 : Unsigned 8-bit immediate (0 to 255) #u10 : Unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : Unsigned 8-bit direct address (0 to 0XFF) @dir9 : Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only) @dir10 : Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only) label9 : Signed 9-bit branch address (–0X100 to 0XFC, multiple of 2 only) label12 : Signed 12-bit branch address (–0X800 to 0X7FC, multiple of 2 only) label20 : Signed 20-bit branch address (–0X80000 to 0X7FFFF) label32 : Signed 32-bit branch address (–0X80000000 to 0X7FFFFFFF) @Ri : Register indirect (R0 to R15, AC, FP, SP) @Rj : Register indirect (R0 to R15, AC, FP, SP) @(R13, Rj) : Register relative indirect (Rj: R0 to R15, AC, FP, SP) @(R14, disp10) : Register relative indirect (disp10: –0X200 to 0X1FC, multiple of 4 only) @(R14, disp9) : Register relative indirect (disp9: –0X100 to 0XFE, multiple of 2 only) @(R14, disp8) : Register relative indirect (disp8: –0X80 to 0X7F) @(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only) @Ri+ : Register indirect with post-increment (R0 to R15, AC, FP, SP) @R13+ : Register indirect with post-increment (R13, AC) @SP+ : Stack pop @–SP : Stack push (reglist) : Register list 99 MB91106 Series 3. Instruction Types MSB Type A Type B LSB 16 bits OP Rj Ri 8 4 4 OP i8/o8 Ri 4 8 4 Type C OP u4/m4 Ri 8 4 4 ADD, ADDN, CMP, LSL, LSR and ASR instructions only Type *C’ Type D Type E Type F 100 OP s5/u5 Ri 7 5 4 OP u8/rel8/dir/reglist 8 8 OP SUB-OP Ri 8 4 4 OP rel11 5 11 MB91106 Series 4. Detailed Description of Instructions • Add/subtract operation instructions (10 instructions) Mnemonic Type OP Cycle N Z V C Operation ADD * ADD Rj, Ri #s5, Ri A C’ A6 A4 1 1 C C C C Ri + Rj → Ri C C C C Ri + s5 → Ri ADD ADD2 #i4, Ri #i4, Ri C C A4 A5 1 1 C C C C Ri + extu (i4) → Ri C C C C Ri + extu (i4) → Ri ADDC Rj, Ri A A7 1 C C C C Ri + Rj + c → Ri ADDN * ADDN Rj, Ri #s5, Ri A C’ A2 A0 1 1 – – – – Ri + Rj → Ri – – – – Ri + s5 → Ri ADDN ADDN2 #i4, Ri #i4, Ri C C A0 A1 1 1 – – – – Ri + extu (i4) → Ri – – – – Ri + extu (i4) → Ri SUB Rj, Ri A AC 1 C C C C Ri – Rj → Ri SUBC Rj, Ri A AD 1 C C C C Ri – Rj – c → Ri SUBN Rj, Ri A AE 1 – – – – Ri – Rj → Ri Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension Add operation with sign MSB is interpreted as a sign in assembly language Zero-extension Sign-extension Subtract operation with carry • Compare operation instructions (3 instructions) Mnemonic Type OP Cycle N Z V C Operation CMP * CMP Rj, Ri #s5, Ri A C’ AA A8 1 1 C C C C Ri – Rj C C C C Ri – s5 CMP CMP2 #i4, Ri #i4, Ri C C A8 A9 1 1 C C C C Ri + extu (i4) C C C C Ri + extu (i4) Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension • Logical operation instructions (12 instructions) Mnemonic Type OP Cycle N Z V C AND AND ANDH ANDB Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri A A A A 82 84 85 86 1 1 + 2a 1 + 2a 1 + 2a CC CC CC CC – – – – – – – – Ri & (Ri) & (Ri) & (Ri) & = Rj = Rj = Rj = Rj Word Word Half word Byte OR OR ORH ORB Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri A A A A 92 94 95 96 1 1 + 2a 1 + 2a 1 + 2a CC CC CC CC – – – – – – – – Ri (Ri) (Ri) (Ri) | | | | = Rj = Rj = Rj = Rj Word Word Half word Byte EOR EOR EORH EORB Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri A A A A 9A 9C 9D 9E 1 1 + 2a 1 + 2a 1 + 2a CC CC CC CC – – – – – – – – Ri ^ (Ri) ^ (Ri) ^ (Ri) ^ = Rj = Rj = Rj = Rj Word Word Half word Byte Operation Remarks 101 MB91106 Series • Bit manipulation arithmetic instructions (8 instructions) Mnemonic Type OP Cycle N Z V C Operation Remarks BANDL BANDH * BAND #u4, @Ri(u4: 0 to 0FH) #u4, @Ri(u4: 0 to 0FH) #u8, @Ri *1 C C 80 81 1 + 2a – – – – (Ri) & = (F0H + u4) Manipulate lower 4 bits 1 + 2a – – – – (Ri) & = ((u4<<4) + 0FH) Manipulate upper 4 – – – – – (Ri) & = u8 bits BORL BORH * BOR #u4, @Ri(u4: 0 to 0FH) #u4, @Ri(u4: 0 to 0FH) #u8, @Ri *2 C C 90 91 1 + 2a – – – – (Ri) | = u4 1 + 2a – – – – (Ri) | = (u4<<4) – – – – – (Ri) | = u8 Manipulate lower 4 bits Manipulate upper 4 bits BEORL BEORH * BEOR #u4, @Ri(u4: 0 to 0FH) #u4, @Ri(u4: 0 to 0FH) #u8, @Ri *3 C C 98 99 1 + 2a – – – – (Ri) ^ = u4 1 + 2a – – – – (Ri) ^ = (u4<<4) – – – – – (Ri) ^ = u8 Manipulate lower 4 bits Manipulate upper 4 bits BTSTL BTSTH #u4, @Ri(u4: 0 to 0FH) #u4, @Ri(u4: 0 to 0FH) C C 88 89 2+a 2+a Test lower 4 bits Test upper 4 bits 0 C – – (Ri) & u4 C C – – (Ri) & (u4<<4) *1: Assembler generates BANDL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates BANDH if “u8&0xF0” leaves an active bit. Depending on the value in the “u8” format, both BANDL and BANDH may be generated. *2: Assembler generates BORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates BORH if “u8&0xF0” leaves an active bit. *3: Assembler generates BEORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates BEORH if “u8&0xF0” leaves an active bit. • Add/subtract operation instructions (10 instructions) Mnemonic Type OP Cycle N Z V C MUL MULU MULH MULUH Rj, Ri Rj, Ri Rj, Ri Rj, Ri A A A A AF AB BF BB 5 5 3 3 CCC CCC CC– CC– DIVOS DIVOU DIV1 DIV2 DIV3 DIV4S * DIV Ri Ri Ri Ri E E E E E E 97 – 4 97 – 5 97 – 6 97 – 7 9F – 6 9F – 7 Ri *1 1 1 d 1 1 1 – – – – – – – – * DIVU Ri *2 – – – C C – – C – – – – – – – – – – – Operation Rj × Ri → MDH, MDL Rj × Ri → MDH, MDL Rj × Ri → MDL Rj × Ri → MDL – – C C – – C MDL/Ri → MDL, MDL%Ri → MDH – C – C MDL/Ri → MDL, MDL%Ri → MDH Remarks 32-bit × 32-bit = 64-bit Unsigned 16-bit × 16-bit = 32-bit Unsigned Step calculation 32-bit/32-bit = 32-bit Unsigned *1: DIVOS, DIV1 × 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes. *2: DIVOU and DIV1 × 32 are generated. A total instruction code length of 66 bytes. 102 MB91106 Series • Shift arithmetic instructions (9 instructions) Mnemonic Type OP Cycle N Z V C Operation Remarks LSL * LSL LSL LSL2 Rj, Ri #u5, Ri #u4, Ri #u4, Ri A C’ C C B6 B4 B4 B5 1 1 1 1 CC CC CC CC – – – – C C C C Ri<<Rj → Ri Ri<<u5 → Ri Ri<<u4 → Ri Ri<<(u4 + 16) → Ri Logical shift LSR * LSR LSR LSR2 Rj, Ri #u5, Ri #u4, Ri #u4, Ri A C’ C C B2 B0 B0 B1 1 1 1 1 CC CC CC CC – – – – C C C C Ri>>Rj → Ri Ri>>u5 → Ri Ri>>u4 → Ri Ri>>(u4 + 16) → Ri Logical shift ASR * ASR ASR ASR2 Rj, Ri #u5, Ri #u4, Ri #u4, Ri A C’ C C BA B8 B8 B9 1 1 1 1 CC CC CC CC – – – – C C C C Ri>>Rj → Ri Ri>>u5 → Ri Ri>>u4 → Ri Ri>>(u4 + 16) → Ri Logical shift • Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) Mnemonic Type OP Cycle N Z V C Operation LDI: 32 LDI: 20 #i32, Ri #i20, Ri E C 9F – 8 9B 3 2 – – – – i32 → Ri – – – – i20 → Ri LDI: 8 * LDI #i8, Ri # {i8 | i20 | i32}, Ri *1 B C0 1 – – – – – i8 → Ri – – – – {i8 | i20 | i32} → Ri Remarks Upper 12 bits are zeroextended Upper 24 bits are zeroextended *1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. If an immediate value contains relative value or external reference, assembler selects i32. • Memory load instructions (13 instructions) Mnemonic Type OP Cycle N Z V C Operation (Rj) → Ri (R13 + Rj) → Ri (R14 + disp10) → Ri (R15 + udisp6) → Ri (R15) → Ri, R15 + = 4 (R15) → Rs, R15 + = 4 Remarks LD LD LD LD LD LD @Rj, Ri @(R13, Rj), Ri @(R14, disp10), Ri @(R15, udisp6), Ri @R15 +, Ri @R15 +, Rs A A B C E E 04 00 20 03 07 – 0 07 – 8 b b b b b b LD @R15 +, PS E 07 – 9 1+a+b LDUH LDUH LDUH @Rj, Ri @(R13, Rj), Ri @(R14, disp9), Ri A A B 05 01 40 b b b – – – – (Rj) → Ri – – – – (R13 + Rj) → Ri – – – – (R14 + disp9) → Ri Zero-extension Zero-extension Zero-extension LDUB LDUB LDUB @Rj, Ri @(R13, Rj), Ri @(R14, disp8), Ri A A B 06 02 60 b b b – – – – (Rj) → Ri – – – – (R13 + Rj) → Ri – – – – (R14 + disp8) → Ri Zero-extension Zero-extension Zero-extension – – – – – – – – – – – – – – – – – – – – – – – – C C C C (R15) → PS, R15 + = 4 Rs: Special-purpose register Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 → o8 = disp8 disp9 → o8 = disp9>>1 Each disp is a code extension. disp10 → o8 = disp10>>2 udisp6 → u4 = udisp6>>2 udisp4 is a 0 extension. 103 MB91106 Series • Memory store instructions (13 instructions) Mnemonic Type OP Cycle N Z V C – – – – – – – – – – – – – – – – – – Operation Ri → (Rj) Ri → (R13 + Rj) Ri → (R14 + disp10) Ri → (R15 + usidp6) R15 – = 4, Ri → (R15) R15 – = 4, Rs → (R15) Remarks ST ST ST ST ST ST Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp10) Ri, @(R15, udisp6) Ri, @–R15 Rs, @–R15 A A B C E E 14 10 30 13 17 – 0 17 – 8 a a a a a a – – – – – – Word Word Word ST PS, @–R15 E 17 – 9 a – – – – R15 – = 4, PS → (R15) STH STH STH Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp9) A A B 15 11 50 a a a – – – – Ri → (Rj) – – – – Ri → (R13 + Rj) – – – – Ri → (R14 + disp9) Half word Half word Half word STB STB STB Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp8) A A B 16 12 70 a a a – – – – Ri → (Rj) – – – – Ri → (R13 + Rj) – – – – Ri → (R14 + disp8) Byte Byte Byte Rs: Special-purpose register Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 → o8 = disp8 disp9 → o8 = disp9>>1 Each disp is a code extension. disp10 → o8 = disp10>>2 udisp6 → u4 = udisp6>>2 udisp4 is a 0 extension. • Transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) Mnemonic 104 Type OP Cycle N Z V C Operation MOV Rj, Ri A 8B 1 – – – – Rj → Ri MOV Rs, Ri A B7 1 – – – – Rs → Ri MOV Ri, Rs A B3 1 – – – – Ri → Rs MOV MOV PS, Ri Ri, PS E E 17 – 1 07 – 1 1 c – – – – PS → Ri C C C C Ri → PS Remarks Transfer between general-purpose registers Rs: Special-purpose register Rs: Special-purpose register MB91106 Series • Non-delay normal branch instructions (23 instructions) Mnemonic Type OP Cycle N Z V C Operation JMP @Ri E 97 – 0 2 – – – – Ri → PC CALL label12 F D0 2 CALL @Ri E 97 – 1 2 – – – – PC + 2 → RP, PC + 2 + rel11 × 2 → PC – – – – PC + 2 → RP, Ri → PC E 97 – 2 2 – – – – RP → PC D 1F 3+3a RET INT #u8 Remarks Return – – – – SSP – = 4, PS → (SSP), SSP – = 4, PC + 2 → (SSP), 0 → I flag, 0 → S flag, (TBR + 3FC – u8 × 4) → PC INTE E 9F – 3 3 + 3a – – – – SSP – = 4, PS → (SSP), For emulator SSP – = 4, PC + 2 → (SSP), 0 → S flag, (TBR + 3D8 – u8 × 4) → PC RETI E 97 – 3 2 + 2a C C C C (R15) → PC, R15 – = 4, (R15) → PS, R15 – = 4 BNO BRA BEQ BNE BC BNC BN BP BV BNV BLT BGE BLE BGT BLS BHI label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 D D D D D D D D D D D D D D D D E1 E0 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF 1 2 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Non-branch PC + 2 + rel8 × 2 → PC PCif Z = = 1 PCif Z = = 0 PCif C = = 1 PCif C = = 0 PCif N = = 1 PCif N = = 0 PCif V = = 1 PCif V = = 0 PCif V xor N = = 1 PCif V xor N = = 0 PCif (V xor N) or Z = = 1 PCif (V xor N) or Z = = 0 PCif C or Z = = 1 PCif C or Z = = 0 Notes: • “2/1” in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. • The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 → rel8 = (label9 – PC – 2)/2 label12 → rel11 = (label12 – PC – 2)/2 • RETI must be operated while S flag = 0. 105 MB91106 Series • Branch instructions with delays (20 instructions) Mnemonic Type OP Cycle N Z V C Operation JMP:D @Ri E 9F – 0 1 – – – – Ri → PC CALL:D label12 F D8 1 CALL:D @Ri E 9F – 1 1 – – – – PC + 4 → RP, PC + 2 + rel11 × 2 → PC – – – – PC + 4 → RP, Ri → PC E 9F – 2 1 – – – – RP → PC D D D D D D D D D D D D D D D D F1 F0 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 – – – – – – – – – – – – – – – – RET:D BNO:D BRA:D BEQ:D BNE:D BC:D BNC:D BN:D BP:D BV:D BNV:D BLT:D BGE:D BLE:D BGT:D BLS:D BHI:D label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Remarks Return Non-branch PC + 2 + rel8 × 2 → PC PCif Z = = 1 PCif Z = = 0 PCif C = = 1 PCif C = = 0 PCif N = = 1 PCif N = = 0 PCif V = = 1 PCif V = = 0 PCif V xor N = = 1 PCif V xor N = = 0 PCif (V xor N) or Z = = 1 PCif (V xor N) or Z = = 0 PCif C or Z = = 1 PCif C or Z = = 0 Notes: • The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 → rel8 = (label9 – PC – 2)/2 label12 → rel11 = (label12 – PC – 2)/2 • Delayed branch operation always executes next instruction (delay slot) before making a branch. • Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other instruction is stored, this device may operate other operation than defined. The instruction described “1” in the other cycle column than branch instruction. The instruction described “a”, “b”, “c” or “d” in the cycle column. 106 MB91106 Series • Direct addressing instructions Mnemonic Type OP Cycle N Z V C Operation DMOV DMOV DMOV DMOV DMOV DMOV @dir10, R13, @dir10, @R13+, @dir10, @R15+, R13 @dir10 @R13+ @dir10 @–R15 @dir10 D D D D D D 08 18 0C 1C 0B 1B b a 2a 2a 2a 2a – – – – – – – – – – – – – – – – – – – – – – – – (dir10) → R13 R13 → (dir10) DMOVH DMOVH DMOVH DMOVH @dir9, R13, @dir9, @R13+, R13 @dir9 @R13+ @dir9 D D D D 09 19 0D 1D b a 2a 2a – – – – – – – – – – – – – – – – (dir9) → R13 R13 → (dir9) Half word Half word (dir9) → (R13), R13 + = 2 Half word (R13) → (dir9), R13 + = 2 Half word DMOVB DMOVB DMOVB DMOVB @dir8, R13, @dir8, @R13+, R13 @dir8 @R13+ @dir8 D D D D 0A 1A 0E 1E b a 2a 2a – – – – – – – – – – – – – – – – (dir8) → R13 R13 → (dir8) (dir8) → (R13), R13 + + (R13) → (dir8), R13 + + (dir10) → (R13), R13 + = 4 (R13) → (dir10), R13 + = 4 R15 – = 4, (dir10) → (R15) (R15) → (dir10), R15 – = 4 Remarks Word Word Word Word Word Word Byte Byte Byte Byte Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from disp8 to disp10 are as follows: disp8 → dir + disp8 disp9 → dir = disp9>>1 Each disp is a code extension disp10 → dir = disp10>>2 • Resource instructions (2 instructions) Mnemonic Type OP Cycle N Z V C Operation Remarks LDRES @Ri+, #u4 C BC a – – – – (Ri) → u4 resource Ri + = 4 u4: Channel number STRES #u4, @Ri+ C BD a – – – – u4 resource → (Ri) Ri + = 4 u4: Channel number • Co-processor instructions (4 instructions) Mnemonic COPOP COPLD COPST COPSV #u4, #CC, CRj, CRi #u4, #CC, Rj, CRi #u4, #CC, CRj, Ri #u4, #CC, CRj, Ri Type OP E E E E 9F – C 9F – D 9F – E 9F – F Cycle N Z V C 2+a 1 + 2a 1 + 2a 1 + 2a – – – – – – – – – – – – – – – – Operation Calculation Rj → CRi CRj → Ri CRj → Ri Remarks No error traps 107 MB91106 Series • Other instructions (16 instructions) Mnemonic Type OP NOP E 9F – A 1 – – – – No changes ANDCCR #u8 ORCCR #u8 D D 83 93 c c C C C C CCR and u8 → CCR C C C C CCR or u8 → CCR STILM #u8 D 87 1 – – – – i8 → ILM Set ILM immediate value ADDSP #s10 D A3 1 – – – – R15 + = s10 ADD SP instruction EXTSB EXTUB EXTSH EXTUH Ri Ri Ri Ri E E E E 97 – 8 97 – 9 97 – A 97 – B 1 1 1 1 – – – – LDM0 (reglist) D 8C *4 Load-multi R0 to R7 LDM1 (reglist) D 8D *4 * LDM (reglist) – – – – (R15) → reglist, R15 increment – – – – (R15) → reglist, R15 increment – – – – (R15 + +) → reglist, STM0 (reglist) D 8E *6 Store-multi R0 to R7 STM1 (reglist) D 8F *6 * STM2 (reglist) *5 – – – – R15 decrement, reglist → (R15) – – – – R15 decrement, reglist → (R15) – – – – reglist → (R15 + +) ENTER #u10 *2 LEAVE XCHB @Rj, Ri *1 *3 Cycle N Z V C – – – – – – – – – – – – – – Operation Remarks Sign extension 8 → 32 bits Zero extension 8 → 32 bits Sign extension 16 → 32 bits Zero extension 16 → 32 bits Load-multi R8 to R15 Load-multi R0 to R15 Store-multi R8 to R15 Store-multi R0 to R15 D 0F 1+a – – – – R14 → (R15 – 4), R15 – 4 → R14, R15 – u10 → R15 Entrance processing of function E 9F – 9 b – – – – R14 + 4 → R15, (R15 – 4) → R14 Exit processing of function A 8A 2a – – – – Ri → TEMP, (Rj) → Ri, TEMP → (Rj) For SEMAFO management Byte data *1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler description s10 is as follows. s10 → s8 = s10>>2 *2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler description u10 is as follows. u10 → u8 = u10>>2 *3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified, assembler generates LDM1. Both LDM0 and LDM1 may be generated. *4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following calculation; a × (n – 1) + b + 1 when “n” is number of registers specified. *5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified, assembler generates STM1. Both STM0 and STM1 may be generated. *6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following calculation; a × n + 1 when “n” is number of registers specified. 108 MB91106 Series • 20-bit normal branch macro instructions Mnemonic Operation Remarks * CALL20 label20, Ri Next instruction address → RP, label20 → PC Ri: Temporary register *1 * BRA20 * BEQ20 * BNE20 * BC20 * BNC20 * BN20 * BP20 * BV20 * BNV20 * BLT20 * BGE20 * BLE20 * BGT20 * BLS20 * BHI20 label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20 → PC if (Z = = 1) then label20 → PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *1: CALL20 (1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL @Ri *2: BRA20 (1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP @Ri *3: Bcc20 (BEQ20 to BHI20) (1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP @Ri false: 109 MB91106 Series • 20-bit delayed branch macro instructions Mnemonic Operation Remarks * CALL20:D label20, Ri Next instruction address + 2 → RP, label20 → PC Ri: Temporary register *1 * BRA20:D * BEQ20:D * BNE20:D * BC20:D * BNC20:D * BN20:D * BP20:D * BV20:D * BNV20:D * BLT20:D * BGE20:D * BLE20:D * BGT20:D * BLS20:D * BHI20:D label20 → PC if (Z = = 1) then label20 → PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri *1: CALL20:D (1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL:D @Ri *2: BRA20:D (1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP:D @Ri *3: Bcc20:D (BEQ20:D to BHI20:D) (1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP:D @Ri false: 110 MB91106 Series • 32-bit normal macro branch instructions Mnemonic Operation Remarks * CALL32 label32, Ri Next instruction address → RP, label32 → PC Ri: Temporary register *1 * BRA32 * BEQ32 * BNE32 * BC32 * BNC32 * BN32 * BP32 * BV32 * BNV32 * BLT32 * BGE32 * BLE32 * BGT32 * BLS32 * BHI32 label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32 → PC if (Z = = 1) then label32 → PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *1: CALL32 (1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL @Ri *2: BRA32 (1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP @Ri *3: Bcc32 (BEQ32 to BHI32) (1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP @Ri false: 111 MB91106 Series • 32-bit delayed macro branch instructions Mnemonic Operation Remarks * CALL32:D label32, Ri Next instruction address + 2 → RP, label32 → PC Ri: Temporary register *1 * BRA32:D * BEQ32:D * BNE32:D * BC32:D * BNC32:D * BN32:D * BP32:D * BV32:D * BNV32:D * BLT32:D * BGE32:D * BLE32:D * BGT32:D * BLS32:D * BHI32:D label32 → PC if (Z = = 1) then label32 → PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri *1: CALL32:D (1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL:D @Ri *2: BRA32:D (1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP:D @Ri *3: Bcc32:D (BEQ32:D to BHI32:D) (1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP:D @Ri false: 112 MB91106 Series ■ ORDERING INFORMATION Part number Package MB91106PFV-XXX 100-pin Plastic LQFP (FPT-100P-M05) MB91106PF-XXX 100-pin Plastic QFP (FPT-100P-M06) Remarks 113 MB91106 Series ■ PACKAGE DIMENSIONS 100-pin Plastic LQFP (FPT-100P-M05) +0.20 16.00±0.20(.630±.008)SQ 75 1.50 –0.10 +.008 76 (Mouting height) .059 –.004 51 14.00±0.10(.551±.004)SQ 50 12.00 (.472) REF 15.00 (.591) NOM Details of "A" part 0.15(.006) INDEX 100 0.15(.006) 26 0.15(.006)MAX AD No. 1 "B" 25 0.40(.016)MAX "A" 0.50(.0197)TYP +0.08 0.18 –0.03 .007 +.003 –.001 +0.05 0.08(.003) M 0.127 –0.02 +.002 Details of "B" part .005 –.001 0.10±0.10 (STAND OFF) (.004±.004) 0.10(.004) 114 0.50±0.20(.020±.008) 0~10° MB91106 Series 100-pin Plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 20.00±0.20(.787±.008) 80 51 81 50 14.00±0.20 (.551±.008) 12.35(.486) REF 17.90±0.40 (.705±.016) 16.30±0.40 (.642±.016) INDEX 31 100 "A" LEAD No. 1 30 0.65(.0256)TYP 0.30±0.10 (.012±.004) 0.13(.005) 0.15±0.05(.006±.002) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 18.85(.742)REF 22.30±0.40(.878±.016) C 1994 FUJITSU LIMITED F100008-3C-2 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX 0 10° 0.80±0.20 (.031±.008) Dimensions in mm (inches) Note: The design may be modified changed without notice, contact to Fujitsu sales division when using the device. 115 MB91106 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 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