STMICROELECTRONICS STLUX385ATR

STLUX385A
Digital controller for lighting and power conversion applications with
6 programmable PWM generators, 96 MHz PLL, DALI
Datasheet - production data
TSSOP38
Features
• 6 programmable PWM generators (SMEDs)
(state machine event driven)
– 10 ns event detection and reaction
– Max.1.3 ns PWM resolution
– Single, coupled and two-coupled
operational modes
– Up to 3 internal/external events per SMED
• DALI (digital addressable lighting interface)
– Interrupt driven hardware encoder
– Bus frequency: 1.2, 2.4 or 4.8 kHz
– IEC 60929 and IEC 62386 compliant plus
24-bit frame extension
– Configurable noise rejection filter
– Reverse polarity on Tx/Rx lines
• 4 analog comparators
– 4 internal 4-bit references
– 1 external reference
– Less than 50 ns propagation time
– Continuous comparison cycle
• 8 analog-to-digital converters (ADC)
– 10-bit precision, with operational amplifier
to extend resolution to 12-bit equivalent
– Sequencer functionality
– Input impedance: 1 MΩ
– Configurable gain value: x1 or x 4
• Integrated microcontroller
– Advanced STM8 core with Harvard
architecture and 3-stage pipeline
– Max. fCPU: 16 MHz
June 2013
This is information on a product in full production.
• Memories
– Flash and E2PROM with read while write
(RWW) and error correction code (ECC)
– Program memory: 32 Kbytes Flash; data
retention 15 years at 85 °C after 10 kcycles
at 25 °C
– Data memory: 1 Kbyte true data E2PROM;
data retention:15 years at 85 °C after 100
kcycles at 85 °C
– RAM: 2 Kbytes
– ROM: 2 Kbytes
• Clock management
– Internal 96 MHz PLL
– Low-power oscillator circuit for external
crystal resonator or direct clock input
– Internal, user-trimmable 16 MHz RC and
low-power 153.6 kHz RC oscillators
– Clock security system with clock monitor
• Basic peripherals
– System and auxiliary timers
– IWDG/WWDG watchdog, AWU, ITC
• Reset and supply management
– Multiple low-power modes (wait, slow, autowakeup, Halt) with user definable clock
gating
– Low consumption power-on and powerdown reset
• I/O
– 12 multi-function bidirectional GPIO with
highly robust design, immune against
current injection
– 6 fast digital input DIGIN, with configurable
pull-up
• Communication interfaces
– UART asynchronous with SW flow-control
– I2C master/slave fast-slow speed rate
• Operating temperature
– -40 °C up to 105 °C
DocID024387 Rev 2
1/98
www.st.com
98
Contents
STLUX385A
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Introducing SMED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
3.4
3.5
SMED (state machine event driven): configurable PWM generator . . . . . . 9
3.1.1
SMED coupling schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2
Connection matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Internal controller (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1
Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.4
Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.5
Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Basic peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1
Vectored interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.2
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash program and data E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2
Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.3
Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.4
Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.1
Internal 16 MHz RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.2
Internal 153.6 kHz RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.3
Internal 96 MHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.4
External clock input/crystal oscillator (HSE) . . . . . . . . . . . . . . . . . . . . . 18
3.6
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7.1
2/98
Digital addressable lighting interface (DALI) . . . . . . . . . . . . . . . . . . . . . 19
DocID024387 Rev 2
STLUX385A
4
5
Contents
3.7.2
Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . 20
3.7.3
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8
Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9
Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3
Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I/O multifunction signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
Multifunction configuration policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2
Port P0 I/O multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 26
5.3
5.4
5.2.1
Alternate function P0 configuration signals . . . . . . . . . . . . . . . . . . . . . . 27
5.2.2
Port P0 diagnostic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.3
Port P0 I/O functional multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.4
P0 programmable pull-up and speed feature . . . . . . . . . . . . . . . . . . . . 28
Port P1 I/O multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 28
5.3.1
Port P1 I/O multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.2
P1 programmable pull-up feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Port P2 I/O multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 30
5.4.1
5.5
6
P2 programmable pull-up feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Multifunction Port configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1
Memory map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.1
General purpose I/O GPIO0 register map . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.2
General purpose I/O GPIO1 register map . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.3
Miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2.4
Flash and E2PROM non-volatile memories . . . . . . . . . . . . . . . . . . . . . . 37
6.2.5
Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2.6
Clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2.7
WWDG timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.2.8
IWDG timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.2.9
AWU timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID024387 Rev 2
3/98
Contents
STLUX385A
6.2.10
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.11
Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . 42
6.2.12
System timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2.13
Digital addressable lighting interface (DALI) . . . . . . . . . . . . . . . . . . . . . 43
6.2.14
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2.15
State machine event driven (SMEDs) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2.16
CPU register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2.17
Global configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2.18
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2.19
SWIM control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7
Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9
10
8.1
Option byte register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.2
Option byte register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.1
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2
Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1
4/98
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.4
Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.5
Loading capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.1.6
Pin output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.1
VOUT external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3.2
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3.3
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 77
10.3.4
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 80
10.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3.6
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DocID024387 Rev 2
STLUX385A
Contents
10.3.7
Typical output curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.3.8
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.3.9
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.3.10 10-bit Sar ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3.11
Analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.3.12 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.4
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.4.1
Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.4.2
Static latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13
STLUX385A development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
DocID024387 Rev 2
5/98
List of tables
STLUX385A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
6/98
Connection matrix interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Multifunction configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
P0 internal multiplexing signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Port P1 I/O multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Port P2 I/O multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Internal memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General purpose I/O GPIO0 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
General purpose I/O GPIO0 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Miscellaneous direct register address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Miscellaneous indirect register address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Non-volatile memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RST_SR register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clock and clock controller register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
WWDG timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IWDG timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AWU timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
UART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
System timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DALI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ADC register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SMED register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CFG_GCR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupt software priority register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SWIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupt vector exception table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option byte register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Unique ID register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Dev ID register overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Supply base current consumption at VDD/VDDA = 3.3/5 V . . . . . . . . . . . . . . . . . . . . . . . . . 70
Supply low power consumption at VDD/VDDA = 3.3/5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Peripheral supply current consumption at VDD/VDDA = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . 72
Peripheral supply current consumption at VDD/VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 73
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
HSE crystal/ceramic resonator oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
HSI RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LSI RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PLL internal source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Flash program memory/data E2PROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Voltage DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Current DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DocID024387 Rev 2
STLUX385A
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
List of tables
Operating frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC accuracy characteristics at VDD/VDDA 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ADC accuracy characteristics at VDD/VDDA 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TSSOP38 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DocID024387 Rev 2
7/98
List of figures
STLUX385A
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
8/98
STLUX385A internal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Coupled SMED overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SMED subsystem overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash and E2PROM internal memory organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TSSOP38 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Port P0 I/O functional multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Port P1 I/O multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
External capacitor CVOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PWM current consumption with fSMED=PLL fPWM=0.5 MHz at VDD/VDDA=3.3V . . . . . . . . 75
PWM current consumption with fSMED=PLL fPWM=0.5 MHz at VDD/VDDA=5V . . . . . . . . . . 75
PWM current consumption with fSMED=HSI fPWM=0.5 MHz at VDD/VDDA=3.3V. . . . . . . . . 76
PWM current consumption with fSMED=HSI fPWM=0.5 MHz at VDD/VDDA=5V . . . . . . . . . . 76
HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
TSSOP8 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DocID024387 Rev 2
STLUX385A
1
Description
Description
The STLUX385A is part of the MASTERLUX™ family of ST Microelectronics digital devices
tailored for lighting and power conversion. The STLUX385A has been successfully
integrated in a wide range of architectures and applications, starting from simple buck
converters for LED driving, boost for power factor correction, half-bridge resonant
converters for dimmable LED strings, up to full-bridge control in HID lamp ballasts, wireless
power chargers and TV power supplies.
1.1
Introducing SMED
The heart of the STLUX385A is the SMED (state machine event driven) technology which
allows the device to operate six independently configurable PWM clocks with a maximum
resolution of 1.3 ns. A SMED is a powerful autonomous state machine, which is
programmed to react to both external and internal events and may evolve without any
software intervention. The SMED reaction time can be as low as 10.4 ns, giving the
STLUX385A the ability of operating in time-critical applications. The SMED offers superior
performance when compared to traditional, timer based, PWM generators.
Each SMED is configured via the STLUX385A internal microcontroller. The integrated
controller extends the STLUX385A reliability and guarantees more than 15 years of both
operating lifetime and memory data retention for program and data memory after cycling.
A set of dedicated peripherals complete the STLUX385A:
•
1.2
4 analog comparators with configurable references and 50 ns max. propagation delay.
It is ideal to implement zero current detection algorithms or detect current peaks.
•
10-bit ADC with configurable op-amp and 8 channel sequencer.
•
DALI: hardware interface that provides full IEC 60929 and IEC 62386 slave interface.
•
96 MHz PLL for high output signal resolution.
Documentation
The following datasheet contains the description of features, pinout, pin assignment,
electrical characteristics, mechanical data and ordering information.
•
•
•
For information on programming, erasing and protection of the internal Flash memory,
please refer to the STM8 Flash programming manual (PM0047).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
DocID024387 Rev 2
9/98
System architecture
2
STLUX385A
System architecture
The STLUX385A generates and controls PWM signals by means of a state machine, called
SMED (state machine event driven). The following picture gives an overview of the internal
architecture.
Figure 1. STLUX385A internal design
The core of the device is the SMED unit: a hardware state machine driven by system
events. The SMED includes 4 states (S0, S1, S2 and S3) available during running
operations. A special HOLD state is provided as well. The SMED allows the user to
configure, for every state, which system events trigger a transaction to a new state. During a
transaction from one state to the other, the PWM output signal level can be updated.
Once a SMED is configured and running, it becomes an autonomous unit, so no interaction
is required since the SNMED automatically reacts to system events.
Thanks to the SMED's 96 MHz operating frequency and their automatic dithering function,
the PWM maximum resolution is 1.3 ns.
The STLUX385A has 6 SMEDs available. Multiple SMEDs can operate independently from
each other or they can be grouped together to form a more powerful state machine.
The STLUX385A also integrates a low-power STM8 microcontroller which is used to
configure and monitor the SMED activity and to supply external communication such as
DALI. The STM8 controller has full access to all the STLUX385A sub-systems, including the
SMEDs. The STLUX385A also features a sequential ADC, which can be configured to
continuously sample up to 8 channels.
The following section illustrates the overall system block and shows how SMEDs have been
implemented in the STLUX385A architecture.
10/98
DocID024387 Rev 2
STLUX385A
2.1
System architecture
Block diagram
Figure 2. Internal block diagram
LSI int. Oscillator
Clock Controller
HSI int. Oscillator
PLL 96MHz
ResetController
POR
HSE ext. Oscillator
Clock controller
PowerManagement
MVR
MLVD
LVD
LVR
DLVD
D
Reset control unit
32KB FLASH
Program area
DALI
1KB E²PROM
Data area
UART
2KB RAM
GPIO0
2KB ROM
BootRom
IC
I
O
2
MSC
(Misc. registers)
Address and Data Bus
Internal controller
P
0
I
n
t.
6 Digital input lines
B
u
s
P
2
I
O
4 Analog Comparators
Connection Box
SWIM & DM
(debug module)
SMED0 (PWM0)
SMED1 (PWM1)
ITC
(Interrupt Ctrl)
SMED2 (PWM2)
AWU
(Auto-wakeup)
SMED3 (PWM3)
SMED4 (PWM4)
WWDG
(Win. Watchdog)
SMED5 (PWM5)
IWDG
(Ind. Watchdog)
GPIO1
P
1
I
O
ADC –
8 channel
System Timer
DocID024387 Rev 2
11/98
Product overview
3
STLUX385A
Product overview
This following section describes the features implemented in the product device.
3.1
SMED (state machine event driven): configurable PWM
generator
The SMED is an advanced programmable PWM generator signal. The SMED (state
machine event driven) is a state machine device controllable by both external events
(primary I/O signals) and internal events (counter timers), which generate an output signal
(PWM) depending on the evolution of the internal state machine.
The PWM signal generated by the SMED is therefore shaped by external events and not by
a single timer. This mechanism allows controlled high frequency PWM signals to be
generated.
The SMED is also autonomous: once it has been configured by the STLUX385A internal
controller, the SMED can operate without any software interaction.
STLUX385A provides 6 SMED units. Multiple SMEDs can operate independently from each
other or they can be grouped together to form a more powerful state machine.
The main features of a SMED are here below described:
•
Configurable state machine generating a PWM signal
•
More than 10.4 ns PWM native resolution
•
Up to 1.3 ns PWM resolution when using SMED dithering
•
6 states available in each SMED: IDLE, S0, S1, S2, S3 plus a special HOLD state
•
3.1.1
Transactions triggered by synchronous and asynchronous external events or internal
timer
•
Each transaction can generate an interrupt
•
Fifteen registers available to configure the state machine behavior
•
Four 16-bit configurable time registers, one for each running state (T0, T1, T2, T3)
•
Internal resources accessible through processor interface
•
Eight interrupt request lines
SMED coupling schemes
The SMED coupling extends the capability of the single SMED, preserving the
independence of each FSM programmed state evolution. The coupling scheme allows the
SMED pulse signals to be interleaved on their own PWM or on a merged single PWM
output. The STLUX385A supports the following coupled configuration schemes:
12/98
•
Single SMED configuration
•
Synchronous coupled SMED
•
Asynchronous coupled SMED
•
Synchronous two coupled SMED
•
Asynchronous two coupled SMED
•
External controlled SMED
DocID024387 Rev 2
STLUX385A
Product overview
The SMED units may be configured in different coupled schemes through the
SMDx_GLBCONF and SMDx_DRVOUT bit fields of MSC_SMEDCFGxy registers.
An outline of SMED subsystem is shown in Figure 3.
Figure 3. Coupled SMED overview
PAIR1
SMED0
SMED1
PWM0
PWM1
PAIR2
SMED2
SMED3
PWM2
PWM3
PAIR3
SMED4
SMED5
PWM4
PWM5
GIPC08051437FSR
3.1.2
Connection matrix
The connection matrix extends the input connectivity of each SMED unit so that a SMED
can receive events from a wide range of sources. Through the matrix, it's possible to
connect the SMED inputs to various signal families such as digital inputs, comparator output
signals, SW events, and three PWM internal feedback signals as shown in Figure 4.
The list of the available event sources is the following:
•
DIGIN(5:0) digital input lines
•
CMP(3:0) analog comparator outputs
•
PWM(5:0) output signals of SMEDs (only PWM 0, 1 and 5 are accessible)
•
SW(5:0) software events
DocID024387 Rev 2
13/98
Product overview
STLUX385A
The following image shows the connection matrix and signal interconnections as they are
implemented in the STLUX385A device.
Figure 4. SMED subsystem overview
InSig00
InSig01
DAC0
CPP[0]
DAC1
CPP[1]
DAC2
CPP[2]
+
+
+
CP0
CP1
CP2
DAC3
CMP3
CPP[3]
+
CP3
C
o
n
n
e
c
t
i
o
n
m
a
t
r
i
x
PWM0
PWM1
PWM5
DIGIN[5:0]
PWM0
InSig02
InSig10
InSig11
SMED1
PWM1
InSig12
IInSig20
InSig21
SMED2
PWM2
PInSig22
InSig30
InSig31
SW[5:0]
SMED0
SMED3
PWM3
InSig32
InSig40
InSig41
SMED4
PWM4
InSig42
InSig50
Digital Comparators
InSig51
SMED5
PWM5
InSig52
GIPC080520131443FSR
Connection matrix interconnection
Every SMED unit has three input selection lines, one for each In_Sig input, configurable via
the MSC_CBOXS(5:0) register. The selection lines choose the interconnection between one
of possible four connection matrix signals for each SMED input event In_Sig(Y).
The next table shows the layout of the connection matrix interconnection signals as
implemented on the STLUX385A.
14/98
DocID024387 Rev 2
STLUX385A
Product overview
Table 1. Connection matrix interconnection
Conb_s(x)_(y)(z)
SMED number
(x)
0
1
2
3
4
5
SMED
SMED input signal selection (z)
input
(y)
00
01
10
11
0
CP0
DIG0
DIG2
DIG5
1
CP1
DIG0
DIG3
CP3
2
CP2
DIG1
DIG4
SW0
0
CP1
DIG1
DIG3
DIG0
1
CP2
DIG1
DIG4
CP3
2
CP0
DIG2
DIG5
SW1
0
CP2
DIG2
DIG4
DIG1
1
CP0
DIG2
DIG5
PWM0
2
CP1
DIG3
DIG0
SW2
0
CP0
DIG3
DIG5
DIG2
1
CP1
DIG3
DIG0
PWM1
2
CP2
DIG4
DIG1
SW3
0
CP1
DIG4
DIG0
DIG3
1
CP2
DIG4
DIG1
PWM5
2
CP0
DIG5
DIG2
SW4
0
CP2
DIG5
DIG1
DIG4
1
CP0
DIG5
DIG2
CP3
2
CP1
DIG0
DIG3
SW5
Connection matrix legend:
•
X represents the SMED[5:0] number
•
Y represents the SMED input signal number (In_Sig[2:0])
•
Z represents the In_Sig(Y) selection signal
Note:
Each SMED input has independent connection matrix selection signals.
3.2
Internal controller (CPU)
The STLUX385A device integrates a programmable STM8 controller acting as a device
supervisor. The STM8 is a modern CISC core and has been designed for code efficiency
and performance. It contains 21 internal registers (six of them directly addressable in each
execution context), 20 addressing modes including indexed indirect and relative addressing
and 80 instructions.
DocID024387 Rev 2
15/98
Product overview
3.2.1
Architecture and registers
•
Harvard architecture with 3-stage pipeline
•
32-bit wide program memory bus with single cycle fetching for most instructions
•
8-bit accumulator
•
24-bit program counter with 16 Mbyte linear memory space
•
16-bit stack pointer with access to a 64 Kbyte stack
3.2.4
8-bit condition code register with seven condition flags updated with the results of last
executed instruction
Addressing
•
20 addressing modes
•
Indexed indirect addressing mode for lookup tables located in the entire address space
•
3.2.3
X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
•
•
3.2.2
STLUX385A
Stack pointer relative addressing mode for efficient implementation of local variables
and parameter passing
Instruction set
•
80 instructions with 2-byte average instruction size
•
Standard data movement and logic/arithmetic functions
•
8-bit by 8-bit multiplication
•
16-bit by 8-bit and 16-bit by 16-bit division
•
Bit manipulation
•
Data transfer between stack and accumulator (push/pop) with direct stack access
•
Data transfer using the X and Y registers or direct memory-to-memory transfers
Single wire interface module (SWIM)
The single wire interface module (SWIM), together with the integrated debug module (DM),
permits non-intrusive, real-time in-circuit debugging and fast memory programming. The
interface can be activated in all device operation modes and can be connected to a running
device (hot plugging).The maximum data transmission speed is 145 byte/ms.
3.2.5
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.
•
R/W of RAM and peripheral registers in real-time
•
R/W for all resources when the application is stopped
•
•
16/98
Breakpoints on all program-memory instructions (software breakpoints), except for the
interrupt vector table
Two advanced breakpoints and 23 predefined breakpoint configurations
DocID024387 Rev 2
STLUX385A
3.3
Product overview
Basic peripherals
The following sections describe the basic peripherals accessed by the internal CPU
controller.
3.3.1
3.3.2
Vectored interrupt controller
•
Nested interrupts with three software priority levels
•
21 interrupt vectors with hardware priority
•
Two vectors for 12 external maskable or un-maskable interrupt request lines
•
Trap and reset interrupts
Timers
The STLUX385A device provides several timers which are used by software and do not
interact directly with the SMED and the PWM generation.
System timers
The system timer consists of a 16-bit auto-reload counter driven by a programmable
prescaled clock and operating in one shoot or free running operating mode. The timer is
used to provide the IC time base system clock, with interrupt generation on timer overflow
events.
Auxiliary timer
The auxiliary timer is a light timer with elementary functionality. The time base frequency is
provided by the CCO clock logic (configurable with different source clock and prescale
division factors), while the interrupt functionality is supplied by an interrupt edge detection
logic similarly to the solution adopted for Port P0/P2.
The timer has the following main features:
•
Free running mode
•
Up counter
•
Timer prescaler 8-bit
•
Interrupt timer capability:
•
–
Vectored interrupt
–
Interrupt IRQ/NMI or Polling mode
Timer pulse configurable as a clock output signal via CCO primary pin
Thanks to the great configurability of the CCO frequency, the timer can cover a wide range
of interval time to fit better the target application requirements.
Auto-wakeup timer
The AWU timer is used to cyclically wake up the IC device from the active-halt state. The
AWU frequency time base fAWU can be selected between the following clock sources: LSI
(153.6 kHz) and the external clock HSE scaled down to 128 kHz clock.
DocID024387 Rev 2
17/98
Product overview
STLUX385A
By default the fAWU clock is provided by the LSI internal source clock.
Watchdog timers
The watchdog system is based on two independent timers providing a high level of
robustness to the applications. The watchdog timer activity is controlled by the application
program or by suitable option bytes. Once the watchdog is activated, it cannot be disabled
by the user program without going through reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which causes the
application program to break the normal operating sequence.
The window function can be used to adjust the watchdog intervention period in order to
match the application timing perfectly. The application software must refresh the counter
before time-out and during a limited time window. If the counter is refreshed outside this
time window, a reset is issued.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve malfunctions due to hardware
or software failures.
It is clocked by the 153.6 kHz LSI internal RC clock source. If the hardware watchdog
feature is enabled through the device option bits, the watchdog is automatically enabled at
power-on, and generates a reset unless the key register is written by software before the
counter reaches the end of count.
3.4
Flash program and data E2PROM
Embedded Flash and E2PROM with memory ECC code correction and protection
mechanism preventing embedded program hacking.
•
32 Kbyte of single voltage program Flash memory
•
1 Kbyte true (not emulated) data E2PROM
•
•
18/98
Read while write: writing in the data memory is possible while executing code program
memory
The device setup is stored in a user option area in the non-volatile memory
DocID024387 Rev 2
STLUX385A
3.4.1
Product overview
Architecture
Figure 5. Flash and E2PROM internal memory organizations
UBC area
Remains write protected during IAP
Flash program
memory
Data EEPROM
memory
Programmable area
maximum 32 Kbytes
Program memory area
Write access possible for IAP
Data memory area (1Kbytes)
Option bytes
GIPC080520131510FSR
•
The memory is organized in blocks of 128 bytes each
•
Read granularity: 1 word = 4 bytes
•
Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel
•
3.4.2
Writing, erasing, word and block management is handled automatically by the memory
interface
Write protection (WP)
Write protection in application mode is intended to avoid unintentional overwriting of the
memory. The write protection can be removed temporarily by executing a specific sequence
in the user software.
3.4.3
Protection of user boot code (UBC)
In the STLUX385A a memory area of 32 Kbyte can be protected from overwriting at user
option level. In addition to the standard write protection, the UBC protection can exclusively
be modified via the debug interface, the user software cannot modify the UBC protection
status.
The UBC memory area contains the reset and interrupt vectors and its size can be adjusted
in increments of 512 bytes by programming the UBC and NUBC option bytes.
Note:
If users choose to update the boot code in the application programming (IAP), this has to be
protected so to prevent unwanted modification.
3.4.4
Read-out protection (ROP)
The STLUX385A provides a read-out protection of the code and data memory which can be
activated by an option byte setting.
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Product overview
STLUX385A
The read-out protection prevents reading and writing program memory, data memory and
option bytes via the debug module and SWIM interface. This protection is active in all device
operation modes. Any attempt to remove the protection by overwriting the ROP option byte
triggers a global erase of the program and data memory.
The ROP circuit may provide a temporary access for debugging or failure analysis. The
temporary read access is protected by a user defined, 8-byte keyword stored in the option
byte area. This keyword must be entered via the SWIM interface to temporarily unlock the
device.
If desired, the temporary unlock mechanism can be permanently disabled by the user.
3.5
Clock controller
The clock controller distributes the system clock provided by different oscillators to the core
and the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness.
The main clock controller features are:
•
Clock sources
•
Internal 16 MHz and 153.6 kHz RC oscillators
•
External source clock:
•
•
•
•
•
•
•
3.5.1
–
Crystal/resonator oscillator
–
External clock input
Internal PLL @ 96 MHz (not used as fMASTER source clock)
Reset: after the reset the microcontroller restarts by default with an internal 2 MHz
clock (16 MHz/8). The clock source and speed can be changed by the application
program as soon as the code execution starts.
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core or individual peripherals.
Wakeup: In case the device wakes up from low-power modes, the internal RC oscillator
(16 MHz/8) is used for quick startup. After a stabilization time, the device switches to
the clock source that was selected before Halt mode was entered.
Clock security system (CSS): the CSS permits monitoring of external clock sources
and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.
Configurable main clock output (CCO): this feature outputs the clock signal.
Internal 16 MHz RC oscillator (HSI)
The high speed internal (HSI) clock is the default master clock line, generated by an internal
RC oscillator and with nominal frequency of 16 MHz. It has the following major features:
20/98
•
RC architecture
•
Glitch free oscillation
•
3-bit user calibration circuit
DocID024387 Rev 2
STLUX385A
3.5.2
Product overview
Internal 153.6 kHz RC oscillator (LSI)
The low speed internal (LSI) clock is a low speed clock line provided by an internal RC
circuit. It drives both the independent watchdog (IWDG) circuit and the auto-wakeup unit
(AWU). It can also be used as a low power clock line for the master clock fMASTER.
3.5.3
Internal 96 MHz PLL
The PLL provides a high frequency 96 MHz clock used to generate high frequency and
accurate PWM waveforms. The input reference clock must be 16 MHz and may be sourced
either by the internal HSI signal or by the external HSE auxiliary input crystal oscillator line.
The internal PLL prescaled clock cannot be selected as fMASTER.
Note:
Should the end application require a PWM signal with a high degree of stability over long
periods, an external clock source connected to the HSE auxiliary clock line as PLL input
reference clock, should be used. In this case, the external clock source determines the
PWM output stability.
3.5.4
External clock input/crystal oscillator (HSE)
The high speed external clock (HSE) allows the connection of an external clock generated,
for example, by a highly accurate crystal oscillator. The HSE is interconnected with the
fMASTER clock line and to several peripherals. It allows users to provide a custom clock
characterized by a high level of precision and stability to meet the application requirements.
HSE supports two possible external clock sources with a maximum of 24 MHz:
•
crystal/ceramic resonator interconnected with the HseOscin/HseOscout signals
•
direct drive clock interconnected with the HseOscin signal
The HseOscin and HseOscout signals are multifunction pins configurable through the I/O
multiplex mechanism; for further information refer to Section 5.
Note:
When HSE is configured as fMASTER source clock, the HSE input frequency cannot be
higher than 16 MHz.
When the HSE is the PLL input reference clock, then the HSE input frequency must be
equal to 16 MHz.
If HSE is the reference for the SMED or the ADC logic, the input frequency can be
configured up to 24 MHz.
3.6
Power management
For efficient power management, the application can be put in one of four different lowpower modes. Users can configure each mode to obtain the best compromise between the
lowest power consumption, the fastest startup time and available wakeup sources.
•
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
•
Active-halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the autowakeup unit (AWU). The main voltage regulator is kept powered on, so current
consumption is higher than in active-halt mode with regulator off, but the wakeup time
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Product overview
STLUX385A
is faster. The wakeup is triggered by the internal AWU interrupt, external interrupt or
reset.
•
Active-halt mode with regulator off: this mode is the same as active-halt with
regulator on, except that the main voltage regulator is powered off, so the wakeup time
is slower.
•
Halt mode: in this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, while main voltage regulator is switched in power-off.
Wakeup is triggered by external event or reset.
In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules. The RAM content is preserved and the brown-out reset
circuit remains enabled.
3.7
Communication interfaces
3.7.1
Digital addressable lighting interface (DALI)
DALI (digital addressable lighting interface), standardized as IEC 929, is the new interface
for lighting control solutions defined by the lighting industry.
The DALI protocol is generally implemented in a DALI communication module (DCM): a
serial communication circuit designed for controllable electronic ballasts. “Ballast” is a
device or circuit used to provide the required starting voltage and operating current for LED,
fluorescent, mercury or other electronic-discharge lamps.
The STLUX385A DALI driver has the following characteristics.
•
Improved DALI noise rejection filter (see section: DALI noise rejection filter)
•
Speed line:1.2, 2.4 and 4.8 kHz transmission rate ±10%
•
Forward payload: 16, 17, 18 and 24-bit message length
•
Backward payload: 8-bit message length.
•
Bi-directional communications
•
Monitor receiver line timeout 500 ms ±10%
•
Polarity insensitive on DALI_rx, DALI_tx signal line
•
Interoperability with different message length
•
Configurable noise rejection filter on DALI_rx input line
•
Maskable interrupt request line
•
DALI peripheral clock has slowed down to 153.6 kHz in low speed operating mode
DALI noise rejection filter
The STLUX385A DALI interface includes a noise rejection filter interconnected on the RX
channel capable to remove any bounce, glitch or spurious pulse from the RX line. The filter
can be configured via three registers:
22/98
•
MSC_DALICKSEL: selects the source clock of filter timing
•
MSC_DALICKDIV: configures the clock prescaler value
•
MSC_DALICONF: configures the filter count and operating mode
DocID024387 Rev 2
STLUX385A
3.7.2
Product overview
Universal asynchronous receiver/transmitter (UART)
UART is the asynchronous receiver/transmitter communication interface.
•
SW flow control operating mode
•
Full duplex, asynchronous communications
•
High precision baud rate generator system
•
Programmable data word length (8 or 9-bit)
•
Configurable stop bit - support for 1 or 2 stop bit
•
Configurable parity control
•
Separate enable bits for transmitter and receiver
•
Interrupt sources:
–
•
Common programmable transmit and receive baud rates up to fMASTER/16
–
Transmit events
–
Receive events
–
Error detection flags
2 interrupt vectors:
–
Transmitter interrupt
–
Receiver interrupt
•
Reduced power consumption mode
•
Wakeup from mute mode (by idle line detection or address mark detection)
•
2 receiver wakeup modes:
–
Address bit (MSB)
–
Idle line
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Product overview
3.7.3
STLUX385A
Inter-integrated circuit interface (I2C)
I2C (inter-integrated circuit) bus interface serves as an interface between the microcontroller
and the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific
sequencing, protocol, arbitration and timing. It supports standard and fast speed modes.
•
Parallel-bus/I2C protocol converter
•
Multi-master capability: the same interface can act as master or slave
•
I2C master features:
•
–
Clock generation
–
Start and stop generation
I2
–
Programmable I2C address detection
–
Stop bit detection
•
Generation and detection of 7-bit/10-bit addressing and general call
•
Supports different communication speeds:
•
•
•
•
–
Standard speed (up to 100 kHz)
–
Fast speed (up to 400 kHz)
Status flags:
–
Transmitter/receiver mode flag
–
End-of-byte transmission flag
–
I2C busy flag
Error flags:
–
Arbitration lost condition for master mode
–
Acknowledgment failure after address/ data transmission
–
Detection of misplaced start or stop condition
–
Overrun/underrun if clock stretching is disabled
Interrupt sources:
–
Communication interrupt
–
Error condition interrupt
–
Wakeup from Halt interrupt
Wakeup capability:
–
3.8
C slave features:
MCU wakes up from low power mode on address detection in slave mode
Analog to digital converter (ADC)
The STLUX385A includes a 10-bit successive approximation ADC with 8 multiplexed input
channels. The analog input signal can be amplified before conversion by a selectable gain
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STLUX385A
Product overview
of 1 or 4 times. The analog-to-digital converter can operate either in single or in
continuous/circular modes. The ADC unit has the following main features:
•
8 ADC input channel
•
10-bit resolution
•
Single and continuous conversion mode
•
•
3.9
Independent channel gain value x1 or x4 to extend dynamic range and resolution to 12bit equivalent
Interrupt events:
–
EoC interrupt asserted on end of conversion cycle
–
EoS interrupt asserted on end of conversion sequences
–
SEQ_FULL_EN interrupt assert on sequencer buffer full
•
ADC input voltage range dependent on selected gain value
•
Selectable conversion data alignment
•
Individual registers for up to 8 successive conversions
Analog comparators
The STLUX385A includes four independent fast analog comparator units (COMP3-0). Each
comparator has an internal reference voltage. COMP3 can be also configured to use an
external reference voltage connected to CPM3 input pin.
Each comparator reference voltage is generated by a dedicated internal-only 4-bit DAC unit.
The main characteristics of the analog comparator unit (ACU) are the following:
•
•
Each comparator has an internally configurable reference
Internal reference voltages configurable in 16 steps with 83 mV voltage grain from 0 V
(GND) to 1.24 V (voltage reference)
•
Two stage comparator architecture is used to reach a high gain
•
Comparator output stage value accessible from processor interface
•
Continuous fast cycle comparison time
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Pinout and pin description
STLUX385A
4
Pinout and pin description
4.1
Pinout
Figure 6. TSSOP38 pinout
26/98
GPIO1[0]/PWM[0]
1
38
ADCIN[0]
DIGIN[0]/CCO_Clk
2
37
ADCIN[1]
DIGIN1
3
36
ADCIN[2]
GPIO1[1]/PWM[1]
4
35
ADCIN[3]
GPIO1[2]/PWM[2]
5
34
ADCIN[4]
DIGIN[2]
6
33
ADCIN[5]
DIGIN[3]
7
32
ADCIN[6]
GPIO1[5]/PWM[5]
8
31
ADCIN[7]
SWIM
9
30
VSSA
NRST
10
29
VDDA
VDD
11
28
CPP[0]
VSS
12
27
CPP[1]
VOUT
13
26
CPM3
GPIO0[4]/Dali_TX/I2C_sda/Uart_TX
14
25
CPP[2]
GPIO0[5]/Dali_RX/I2C_scl/Uart_RX
15
24
CPP[3]
GPIO1[4]/PWM[4]
16
23
GPIO0[1]/Uart_RX/I2C_scl
DIGIN[4]/I2C_sda
17
22
GPIO0[0]/Uart_TX/I2C_sda
DIGIN[5]/I2C_scl
18
21
GPIO0[3]/I2C_scl/HseOscin/Uart_RX
GPIO1[3]/PWM[3]
19
20
GPIO0[2]/I2C_sda/HseOscout/Uart_TX
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STLUX385A
4.2
Pinout and pin description
Pin description
Table 2. Pin description
Pin
Type
Pin name
Main function
Alternate
function 1
Alternate
function 2
Alternate
function 3
1
I/O
GPIO1[0]/PWM[0]
SMED PWM
channel 0
General purpose
I/O 10
-
-
2
I/O
DIGIN[0]/CCO_clk
Digital input 0
Configurable
clock output
signal (CCO)
-
-
3
I
DIGIN[1]
Digital input 1
-
-
-
4
I/O
GPIO1[1]/PWM[1]
SMED PWM
channel 1
General purpose
I/O 11
-
-
5
I/O
GPIO1[2]/PWM[2]
SMED PWM
channel 2
General purpose
I/O 12
-
-
6
I
DIGIN[2]
Digital input 2
-
-
-
7
I
DIGIN[3]
Digital input 3
-
-
-
8
I/O
GPIO1[5]/PWM[5]
SMED PWM
channel 5
General purpose
I/O 15
-
-
9
I/O
SWIM
SWIM data
interface
-
-
-
10
I/O
NRST
Reset
-
-
-
11
PS
VDD
Digital and I/O
power supply
-
-
-
12
PS
VSS
Digital and I/O
ground
-
-
-
13
PS
VOUT
1.8 V regulator
capacitor
-
-
-
14
I/O
GPIO0[4]/DALI_tx
General purpose
I/O 04
DALI data
transmit
-
-
15
I/O
GPIO0[5]/DALI_rx
General purpose
I/O 05
DALI data
receive
-
-
16
I/O
GPIO1[4]/PWM[4]
SMED PWM
channel 4
General purpose
I/O 14
-
-
17
I
DIGIN[4]
Digital input 4
-
-
-
18
I
DIGIN[5]
Digital input 5
-
-
-
19
I/O
GPIO1[3]/PWM[3]
SMED PWM
channel 3
General purpose
I/O 13
-
-
20
I/O
GPIO0[2]/I2C_sda/
HseOscout/UART_tx
General purpose
I/O 02
I2C data
Output crystal
oscillator
signal
UART data
transmit
number
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Pinout and pin description
STLUX385A
Table 2. Pin description (continued)
Pin
number
Type
Pin name
Main function
Alternate
function 1
Alternate
function 2
Alternate
function 3
UART data
receive
21
I/O
GPIO0[3]/I C_scl/
HseOscin/UART_rx
General purpose
I/O 03
I2C clock
Input crystal
oscillator
signal / input
frequency
signal
22
I/O
GPIO0[0]/UART_tx/I
2
C_scl
General purpose
I/O 00
UART data
transmit
-
-
23
I/O
GPIO0[1]/UART_rx/I
2
C_scl
General purpose
I/O 01
UART data
receive
-
-
24
I
CPP[3]
Positive analog
comparator input 3
-
-
-
25
I
CPP[2]
Positive analog
comparator input 2
-
-
-
26
I
CPM3
Negative analog
comparator input 3
-
-
-
27
I
CPP[1]
Positive analog
comparator input 1
-
-
-
28
I
CPP[0]
Positive analog
comparator input 0
-
-
-
29
PS
VDDA
Analog power
supply
-
-
-
30
PS
VSSA
Analog ground
-
-
-
31
I
ADCIN[7]
Analog input 7
-
-
-
32
I
ADCIN[6]
Analog input 6
-
-
-
33
I
ADCIN[5]
Analog input 5
-
-
-
34
I
ADCIN[4]
Analog input 4
-
-
-
35
I
ADCIN[3]
Analog input 3
-
-
-
36
I
ADCIN[2]
Analog input 2
-
-
-
37
I
ADCIN[1]
Analog input 1
-
-
-
38
I
ADCIN[0]
Analog input 0
-
-
-
2
4.3
Input/output specifications
The STLUX385A device includes two different I/O types:
•
Normal I/Os configurable either at 2 or 10 MHz (high sink)
•
Fast I/O operating at 12 MHz
The STLUX385A I/Os are designed to withstand current injection. For a negative injection
current of 4 mA, the resulting leakage current in the adjacent input does not exceed 1 μA;
further details are available in Section 10.
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STLUX385A
5
I/O multifunction signal configuration
I/O multifunction signal configuration
Several I/Os have multiple functionalities selectable through the configuration mechanism
described in the following sections. The STLUX385A I/Os are grouped into three different
configurable ports: P0, P1 and P2.
5.1
Multifunction configuration policy
The STLUX385A supports either a cold or warm multifunction signal configuration policy
according to the content of the EN_COLD_CFG bit field, part of the GENCFG option byte
register.
When EN_COLD_CFG bit is set, the cold configuration is selected and the multifunction
signals are configured according to the values stored in the option bytes; otherwise when
the EN_COLD_CFG bit is cleared (default case), the warm configuration mode is chosen
and the multifunction pin functionality is configured through the miscellaneous registers.
The configuration options and the proper configuration registers are detailed in the following
table:
Table 3. Multifunction configuration registers
EN_COLD_CFG
Configuration
policy
Multifunction configuration registers
1
Cold
AFR_IOMXP0, AFR_IOMXP1 and AFR_IOMXP2
0 (default)
Warm
MISC_IOMXP0, MISC_IOMXP1 and MISC_IOMXP2
The warm configuration is volatile, thus not maintained after a device reset.
5.2
Port P0 I/O multifunction configuration signal
Port P0 multiplexes several input/output functionalities, increasing the device flexibility. The
P0 port pins can be independently assigned to general purpose I/Os or to internal
peripherals. All communication peripherals and the external oscillator are hosted by port P0
pins.
In order to avoid electrical conflicts on the user application board, the P0 signals are
configured at reset as GPIO0[5:0] inputs without pull-up resistors. Once reset is released,
the firmware application must initialize the inputs with the proper configuration according to
the application needs.
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I/O multifunction signal configuration
5.2.1
STLUX385A
Alternate function P0 configuration signals
The multifunction pins can be configured via one of the following two registers, depending
on the overall configuration policy (warm/cold):
•
Cold configuration: AFR_IOMXP0 option byte registers (refer to Section 8). After reset
the P0 signals are configured in line with AFR_IOMXP0 contents.
•
Warm configuration: MISC_IOMXP0 miscellaneous register (refer to Section 5.5). After
reset, the P0 signals are configured as GPIO input lines with pull-up disabled.
The next table summarizes the port P0 configuration scheme. Both registers MSC_IOMXP0
and AFR_IOMXP0 use the same register fields Sel_p054, Sel_p032 and Sel_p010 which
respectively control the bits [5,4], [3,2] and [1,0] of port P0.
Table 4. P0 internal multiplexing signals
Port P0 multifunction configuration signal
Port pins
Multifunction
signal
GPIO0[1]
GPIO0[0]
UART_rx
UART_tx
Mux sel
Selection fields
P0[1,0]
00
01
Sel_p010
I2C_scl
I2C_sda
10
RFU Reserved encoding
11
GPIO0[3]
GPIO0[2]
00
I2C_scl
I2C_sda
P0[3,2]
01
Sel_p032
HseOscin
HseOscout
10
UART_rx
UART_tx
11
GPIO0[5]
GPIO0[4]
00
DALI_rx
DALI_tx
P0[5,4]
Note:
Value (binary)
01
Sel_p054
I2C_scl
I2C_sda
10
UART_rx
UART_tx
11
Sel_p054, Sel_p032, Sel_p010 are register fields for both registers MSC_IOMXP0 and
AFR_IOMXP0.
The peripheral conflict (same resources selected on different pins at the same time) has to
be prevented by SW configuration.
When the I2C interface is selected either on GPIO0[5:4] or on GPIO0[3:2] signals the related
I/O port speed has to be configured at 10 MHz by programming the GPIO0 internal
peripheral.
5.2.2
Port P0 diagnostic signals
The primary I/Os can be used to trace the SMED's state evolution. This feature allows the
debug of the complex SMED configurations. The trace selection can be enabled or disabled
via register MSC_IOMXSMD. The diagnostic signal selection through MSC_IOMXSMD
register overrides the functional configuration of MSC_IOMXP0 register.
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I/O multifunction signal configuration
The port P0[5:3] or P0[2:0] can be configured to output one or two different SMEDs’ current
state.
5.2.3
Port P0 I/O functional multiplexing signal
Figure 7 shows an outline view of port P0 multi-function multiplexing scheme.
Figure 7. Port P0 I/O functional multiplexing scheme
A/F IN
A/F(s) in
P0_IDR[5:0]
INPUT
P0_ODR[5:0]
OUTPUT
P0[5:0]
A/F OUT
A/F(s) out
-MSC_IOMXP0
-AFR_IOMXP0
GIPC080520131629FSR
Note:
Where “A/F(s) in” and “A/F(s) out” signals are defined in Section 4.2.
5.2.4
P0 programmable pull-up and speed feature
The I/O speed and pad pull-up resistance (47 kΩ) of Port P0 may be configured through the
GPIO0 internal registers.
5.3
Port P1 I/O multifunction configuration signal
The Port1 I/O multifunction pins, similarly to Port0, can be individually configured through
the following set of registers based on the selected device configuration policy:
•
Cold configuration: AFR_IOMXP1 option byte register (refer to Section 8). After reset
the P1 signals are configured in line with AFR_IOMXP1 contents.
•
Warm configuration: MISC_IOMXP1 miscellaneous register (refer to Section 5.5). After
reset the P1 signals are configured as PWM output lines.
Every Port1 I/O can be configured to operate as a PWM output pin or a GPIO. Differently
from port P0s, the pins are configured as PWM output signals by default after reset.
The next table summarizes the port P1 configurations as selected by the register fields
Sel_p15…Sel_p10 which respectively control the bits [5]…[0] of port P1.
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I/O multifunction signal configuration
STLUX385A
Table 5. Port P1 I/O multiplexing signal
Port P1 multifunction configuration signal
Output
signal
Mux selection
Multi-function
signal
Selection bits
Value (binary)
PWM[0]
1
P1[0]
Sel_p10
GPIO1[0]
0
PWM[1]
1
P1[1]
Sel_p11
GPIO1[1]
0
PWM[2]
1
P1[2]
Sel_p12
GPIO1[2]
0
PWM[3]
1
P1[3]
Sel_p13
GPIO1[3]
0
PWM[4]
1
P1[4]
Sel_p14
GPIO1[4]
0
PWM[5]
1
P1[5]
Sel_p15
GPIO1[5]
Note:
0
Sel_p15…Sel_p10 are common register fields of both registers MISC_IOMXP1 and
AFR_IOMXP1.
The PWM default polarity level is configured by the register option byte GENCFG.
5.3.1
Port P1 I/O multiplexing signal
The next figure shows an outline view of port P1 signal multiplex scheme.
Figure 8. Port P1 I/O multiplexing scheme
P1_IDR[5:0]
INPUT
P1_ODR[5:0]
OUTPUT
P1[5:0]
PWM[5..0]
PWM out
-MSC_IOMXP1
-AFR_IOMXP1
GIPC080520131642FSR
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STLUX385A
Note:
I/O multifunction signal configuration
The P1[5:0] output signals may be read back from the P1_IDR register only when the pins
are configured as GPIO out or PWM signals.
The PWM internal signal is read-back also by the its own SMED through the
SMD<n>_FSM_STS register
5.3.2
P1 programmable pull-up feature
The pad pull-up resistances (47 kΩ) of Port1 may be configured through the GPIO1 internal
register.
5.4
Port P2 I/O multifunction configuration signal
The Port2 I/O multifunction pins, similarly to Port0 and Port2, can be individually configured
through the following set of registers based on the selected device configuration policy:
•
Cold configuration: AFR_IOMXP2 option byte registers (refer to Section 8). After reset
the P2 signals are configured in line with AFR_IOMXP2 contents.
•
Warm configuration: MISC_IOMXP2 miscellaneous register (refer to Section 5.5). After
reset the P2 signals are configured as DIGINs input lines with pull-up enabled.
The following table summarizes the port P2 configurations selected by the register fields
Sel_p25…Sel_p20 which respectively control the bits [5]…[0] of port P2.
Table 6. Port P2 I/O multiplexing signal
Port P2 multifunction configuration signal
Output
signal
Multi-function
signal
Mux Sel
Selection bits
DIGIN[0]
P2[0]
0
CCOEN
CCO
1
DIGIN[4]
P2[4]
1
Sel_p254
I2
C_sda
0
DIGIN[5]
P2[5]
1
Sel_p254
I2
C_scl
Note:
Value (binary)
0
Sel_p254 is a common register field of both registers MSC_IOMXP2 and AFR_IOMXP2.
The peripheral conflict (same resources selected on different pins at the same time) has to
be prevented by SW configuration.
The option byte AFR_IOMXP2 before user configuration by default selects the I2C
alternative functionality.
The signal ports P2[3:1] are exclusively interconnected with DIGIN[3:1] primary pins.
When the I2C i/f is selected on DIGIN[5:4] signals the I/O speed is auto-configured at 10
MHz and the internal pull-up functionality is controlled by the MSC_INPP2AUX1 register.
The P2[0] signal for backward product compatibility is only controlled by field CCOEN of
CKC_CCOR register as shown in the previous table.
DocID024387 Rev 2
33/98
I/O multifunction signal configuration
5.4.1
STLUX385A
P2 programmable pull-up feature
The pad pull-up resistances (47 kΩ) of Port2 signals are individually controllable by
MSC_INPP2AUX1 register.
5.5
Multifunction Port configuration registers
MSC_IOMXP0 (Port P1 I/O mux control register)
Offset: 0x2A
Default value: 0x00
7
6
5
4
3
2
1
0
RFU
Sel_p054[1:0]
Sel_p032[1:0]
Sel_p010[1:0]
r
r/w
r/w
r/w
Port0 I/O multifunction signal configurations register (for functionality description refers to
Section 5.2).
Bit 1-0:
Sel_p010[1:0] Port0[1:0] I/O multiplexing scheme:
00: Port0[1:0] are interconnected to GPIO0[1:0] signals
01: Port0[1:0] are interconnected to UART_rx and UART_tx signals
10: Port0[1:0] are interconnected to I2C_scl and I2C_sda signals
11: RFU
Bit 3-2:
Sel_p032[1:0] Port0[3:2] I/O multiplexing scheme:
00: Port0[3:2] are interconnected to GPIO0[3:2] signals
01: Port0[3:2] are interconnected to I2C_scl and I2C_sda signals
10: Port0[3:2] are interconnected to HseOscin and HseOscout analog signals
11: Port0[3:2] are interconnected to UART_rx and UART_tx signals
Bit 5-4:
Sel_p054[1:0] Port0[5:4] I/O multiplexing scheme:
00: Port0[5:4] are interconnected to GPIO0[5:4] signals
01: Port0[5:4] are interconnected to DALI_rx and DALI_tx signals
10: Port0[5:4] are interconnected to I2C_scl and I2C_sda signals
11: Port0[5:4] are interconnected to UART_rx and UART_tx signals
Bit 7-6:
RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0
during register write operations
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DocID024387 Rev 2
STLUX385A
I/O multifunction signal configuration
MSC_IOMXP1 (Port P1 I/O mux control register)
Offset: 0x2B
Default value: 0x3F
7
6
RFU
5
4
3
2
1
0
Sel_p15
Sel_p14
Sel_p13
Sel_p12
Sel_p11
Sel_p10
r
r/w
Port1 I/O multifunction signal configuration register (for functionality description refers to
Section 5.3).
Bit 0:
Sel_p10 Port1[0] I/O multiplexing scheme:
0: Port1[0] is interconnected to GPIO1[0] signal
1: Port1[0] is interconnected to PWM[0] signal
Bit 1:
Sel_p11 Port1[1] I/O multiplexing scheme:
0: Port1[1] is interconnected to GPIO1[1] signal
1: Port1[1] is interconnected to PWM[1] signal
Bit 2:
Sel_p12 Port1[2] I/O multiplexing scheme:
0: Port1[2] is interconnected to GPIO1[2] signal
1: Port1[2] is interconnected to PWM[2] signal
Bit 3:
Sel_p13 Port1[3] I/O multiplexing scheme:
0: Port1[3] is interconnected to GPIO1[3] signal
1: Port1[3] is interconnected to PWM[3] signal
Bit 4:
Sel_p14 Port1[4] I/O multiplexing scheme:
0: Port1[4] is interconnected to GPIO1[4] signal
1: Port1[4] is interconnected to PWM[4] signal
Bit 5:
Sel_p15 Port1[5] I/O multiplexing scheme:
0: Port1[5] is interconnected to GPIO1[5] signal
1: Port1[5] is interconnected to PWM[5] signal
Bit 7-6:
RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0
during register write operations
DocID024387 Rev 2
35/98
I/O multifunction signal configuration
STLUX385A
MSC_IOMXP2 (Port P2 I/O mux control register)
Offset: 0x13 (indirect area)
Default value: 0xFF
7
6
5
4
3
2
1
RFU
Sel_p254
RFU
r
r/w
r
0
Port1 I/O multifunction signal configurations register (for functionality description refers to
Section 5.4).
Bit 3-0:
RFU reserved; must be kept 0 during register writing for future compatibility
Bit 4:
Sel_p254 Port2[5:4] I/O multiplexing scheme:
0: Port2[5:4] are interconnected to I2C_scl and I2C_sda signals
1: Port2[5:4] are interconnected to DIGIN[5:4] signals
Bit 7-5:
RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0
during register write operations
MSC_INPP2AUX1 (INPP aux register)
Offset: 0x08
Default value: 0x00
7
6
5
4
3
2
RFU
INPP2_PULCTR [5:0]
r
r/w
1
0
Bit 5-0:
INPP2_PULCTR[5:0] This register configures respectively the INPP2[5:0] pull-up
functionality as follows:
0: Enable pad pull-up features (enabled by default for compatibility with the
STLUX385)
1: Disable pad pull-up
Bit 7-6:
RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0
during register write operations.
Note:
36/98
MSC_IOMXP2 and MSC_INPP2AUX1 are addressable in indirect mode.
DocID024387 Rev 2
STLUX385A
Memory and register map
6
Memory and register map
6.1
Memory map overview
This section describes the register map implemented by the STLUX385A device. The
following picture shows the main memory map organization. All registers and memory
spaces are configured within the first 64 Kbytes of memory, the remaining address spaces
are kept reserved for future use.
Table 7. Internal memory map
Address
Description
00.0000h
2 kB RAM
00.07FFh
Stack
00.0800h
Reserved
00.3FFFh
00.4000h
1 kB data E2PROM
00.43FFh
00.4400h
Reserved
00.47FFh
00.4800h
128 option bytes
00.487Fh
00.4880h
Reserved
00.4FFFh
00.5000h
Peripheral register region
00.57FFh
00.5800h
Reserved
00.5FFFh
00.6000h
2 kB boot ROM
00.67FFh
00.6800h
Reserved
00.7EFFh
00.7F00h
Core register region
00.7FFFh
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Memory and register map
STLUX385A
Table 7. Internal memory map (continued)
Address
Description
00.8000h
32 interrupt vectors
00.8080h
32 kB program Flash
00.FFFFh
01.0000h
Reserved
FF.FFFFh
By default the stack address is initialized at 0x07FF and rolls-over when it reaches the
address value of 0x0400.
6.2
Register map
The following section shows the STLUX385A memory map.
6.2.1
General purpose I/O GPIO0 register map
Table 8. General purpose I/O GPIO0 register map
Address
Register name
Register description
0x00.5000
P0_ODR
Output data
0x00.5001
P0_IDR
Input data
P0_DDR
Data direction
0x00.5003
P0_CR1
Control register 1
0x00.5004
P0_CR2
Control register 2
0x00.5002
6.2.2
Block
GPIO0
General purpose I/O GPIO1 register map
Table 9. General purpose I/O GPIO0 register map
Address
Register name
Register description
0x00.5005
P1_ODR
Output data
0x00.5006
P1_IDR
Input data
P1_DDR
Data direction
0x00.5008
P1_CR1
Control register 1
0x00.5009
P1_CR2
Control register 2
0x00.5007
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Block
GPIO1
DocID024387 Rev 2
STLUX385A
6.2.3
Memory and register map
Miscellaneous registers
Direct register address mode
Table 10. Miscellaneous direct register address mode
Address
Block
Register name
Register description
0x00.5010
MSC_CFGP00
P00 input line control
0x00.5011
MSC_CFGP01
P01 input line control
0x00.5012
MSC_CFGP02
P02 input line control
0x00.5013
MSC_CFGP03
P03 input line control
0x00.5014
MSC_CFGP04
P04 input line control
0x00.5015
MSC_CFGP05
P05 input line control
0x00.5016
MSC_CFGP20
P20 input line control
0x00.5017
MSC_CFGP21
P21 input line control
0x00.5018
MSC_CFGP22
P22 input line control
0x00.5019
MSC_CFGP23
P23 input line control
0x00.501A
MSC_CFGP24
P24 input line control
0x00.501B
MSC_CFGP25
P25 input line control
0x00.501C
MSC_STSP0
Port0 status
MSC_STSP2
Port2 status
0x00.501E
MSC_INPP2
Port2 read
0x00.501F
RFU
0x00.5020
MSC_DACCTR
Comparator4 and DAC4 configuration
0x00.5021
MSC_DACIN0
DAC0 input data
0x00.5022
MSC_DACIN1
DAC1 input data
0x00.5023
MSC_DACIN2
DAC2 input data
0x00.5024
MSC_DACIN3
DAC3 input data
0x00.5025
MSC_SMDCFG01
SMED 0-1 behavior
0x00.5026
MSC_SMDCFG23
SMED 2-3 behavior
0x00.5027
MSC_SMDCFG45
SMED 4-5 behavior
0x00.5028
MSC_SMSWEV
0x00.5029
MSC_SMUNLOCK
0x00.502A
MSC_CBOXS0
0x00.501D
MSC
DocID024387 Rev 2
Reserved for future use
SMED software events
SMED unlock
Connection matrix selection for SMED 0
39/98
Memory and register map
STLUX385A
Indirect register address mode
Table 11. Miscellaneous indirect register address mode
Address (IDX)
Block
Register name
Register description
0x00 – 0x04
RFU
0x05
MSC_DALICKSEL
DALI clock selection
0x06
MSC_DALICKDIV
DALI filter clock division factor
MSC_DALICONF
DALI filter mode configuration
0x08
MSC_INPP2AUX1
INPP2 auxiliary configuration register 1
0x09
MSC_INPP2AUX2
INPP2 auxiliary configuration register 2
0x0A – 0x12
RFU
0x13
MSC_IOMXP2
0x07
Reserved for future use
MSC
6.2.4
Reserved for future use
Port2 alternate function mux register
Flash and E2PROM non-volatile memories
Table 12. Non-volatile memory register map
Address
Register name
Register description
0x00.505A
FLASH_CR1
Control register 1
0x00.505B
FLASH_CR2
Control register 2
0x00.505C
FLASH_nCR2
Control register 2 (protection)
0x00.505D
FLASH_FPR
Memory protection
0x00.505E
FLASH_nFPR
Memory protection (complemented reg.)
FLASH_IAPSR
Flash status
0x00.5062
FLASH_PUKR
Write memory protection removal key reg.
0x00.5063
RFU
0x00.5064
FLASH_DUKR
Write memory protection removal data
0x00.5071
FLASH_WAIT
Time access wait-state reg.
0x00.505F
40/98
Block
MIF
DocID024387 Rev 2
Reserved for future use
STLUX385A
6.2.5
Memory and register map
Reset register
Table 13. RST_SR register map
Address
Block
Register name
0x00.50B3
RSTC
RST_SR
DocID024387 Rev 2
Register description
Reset control status
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Memory and register map
6.2.6
STLUX385A
Clock and clock controller
Table 14. Clock and clock controller register map
Address
Block
Register name
Register description
0x00.50B4
CLK_SMD0
SMED 0 clock configuration
0x00.50B5
CLK_SMD1
SMED 1 clock configuration
0x00.50B6
CLK_SMD2
SMED 2 clock configuration
0x00.50B7
CLK_SMD3
SMED 3 clock configuration
0x00.50B8
CLK_SMD4
SMED 4 clock configuration
0x00.50B9
CLK_SMD5
SMED 5 clock configuration
0x00.50BA
RFU
Reserved for future use
0x00.50BB
RFU
Reserved for future use
0x00.50BC
RFU
Reserved for future use
0x00.50BD
RFU
Reserved for future use
0x00.50BE
CLK_PLLDIV
PLL clock divisor
0x00.50BF
CLK_AWUDIV
AWU clock divisor
0x00.50C0
CLK_ICKR
Internal clock control
CLK_ECKR
External clock control
0x00.50C2
CLK_PLLR
PLL control
0x00.50C3
CLK_CMSR
Clock master
0x00.50C4
CLK_SWR
Clock switch
0x00.50C5
CLK_SWCR
Switch control
0x00.50C6
CLK_CKDIVR
Clock dividers
0x00.50C7
CLK_PCKENR1
0x00.50C8
CLK_CSSR
Clock security system
0x00.50C9
CLK_CCOR
Configurable clock output
0x00.50CA
CLK_PCKENR2
Peripheral clock enable
0x00.50CB
RFU
Reserved for future use
0x00.50CC
CLK_HSITRIMR
HSI calibration trimmer
0x00.50CD
CLK_SWIMCCR
SWIM clock division
0x00.50CE
CLK_CCODIVR
CCO divider
0x00.50CF
CLK_ADCR
0x00.50C1
CKC
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DocID024387 Rev 2
Peripherals clock
ADC clock configuration
STLUX385A
6.2.7
Memory and register map
WWDG timers
Table 15. WWDG timer register map
Address
Block
0x00.50D1
Register name
Register description
WWDG_CR
Watchdog control
WWDG_WR
Watchdog window
WWDG
0x00.50D2
6.2.8
IWDG timers
Table 16. IWDG timer register map
Address
Block
0x00.50E0
0x00.50E1
IWDG
0x00.50E2
6.2.9
Register name
Register description
IWDG_KR
Watchdog key
IWDG_PR
Watchdog time base
IWDG_RLR
Watchdog counter value after reload
AWU timers
Table 17. AWU timer register map
Address
Block
0x00.50F0
0x00.50F1
0x00.50F2
AWU
Register name
Register description
AWU_CSR
AWU control status
AWU_APR
AWU asynchronous prescaler buffer
AWU_TBR
AWU time base selection
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Memory and register map
6.2.10
STLUX385A
Inter-integrated circuit interface (I2C)
Table 18. I2C register map
Address
Block
Register name
Register description
0x00.5210
I2C_CR1
I2C control register 1
0x00.5211
I2C_CR2
I2C control register 2
0x00.5212
I2C_FREQR
I2C frequency register
0x00.5213
I2C_OARL
I2C own add-low reg.
0x00.5214
I2C_OARH
I2C own add-high reg.
0x00.5215
RFU
Reserved for future use
I2C_DR
I2C data register
0x00.5217
I2C_SR1
I2C status register 1
0x00.5218
I2C_SR2
I2C status register 2
0x00.5219
I2C_SR3
I2C status register 3
0x00.521A
I2C_ITR
I2C interrupt and DMA control
0x00.521B
I2C_CCRL
I2C clock control
0x00.521C
I2C_CCRH
I2C clock control
0x00.521D
I2C_TRISER
0x00.5216
I2C
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DocID024387 Rev 2
I2C rising edge
STLUX385A
6.2.11
Memory and register map
Universal asynchronous receiver/transmitter (UART)
Table 19. UART register map
Address
Block
Register name
Register description
0x00.5230
UART_SR
UART status
0x00.5231
UART_DR
UART data
0x00.5232
UART_BRR1
UART baud rate div mantissa [7:0]
0x00.5233
UART_BRR2
UART baud rate div mantissa [11:8]
SCIDIV FRACT[3:0]
0x00.5234
UART_CR1
UART control register 1
0x00.5235
UART_CR2
UART control register 2
0x00.5236
UART_CR3
UART control register 3
0x00.5237
UART_CR4
UART control register 4
0x00.5238
UART_CR5
UART control register 5
0x00.5239
UART_GTR
UART guard time
0x00.523A
UART_PSCR
UART
6.2.12
SCI1 prescaler
System timer registers
Table 20. System timer register map
Address
Block
Register name
Register description
0x00.5340
STMR_CR1
Control register 1
0x00.5341
STMR_IER
Interrupt enable
0x00.5342
STMR_SR1
Status register 1
0x00.5343
STMR_EGR
Event generation
0x00.5344
STMR_CNTH
Counter high
0x00.5345
STMR_CNTL
Counter low
0x00.5346
STMR_PSCL
Prescaler low
0x00.5347
STMR_ARRH
Auto-reload high
0x00.5348
STMR_ARRL
Auto-reload low
STMR
DocID024387 Rev 2
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Memory and register map
6.2.13
STLUX385A
Digital addressable lighting interface (DALI)
Table 21. DALI register map
Address
Block
Register name
Register description
0x00.53C0
DALI_CLK_L
Data rate control
0x00.53C1
DALI_CLK_H
Data rate control
0x00.53C2
DALI_FB0
Forward message
0x00.53C3
DALI_FB1
Forward message
DALI_FB2
Forward message
0x00.53C5
DALI_BD
Backward message
0x00.53C6
DALI_CR
Control
0x00.53C7
DALI_CSR
Control and status register
0x00.53C8
DALI_CSR1
Control and status register 1
0x00.53C9
DALI_REVLN
0x00.53C4
DALI
6.2.14
Analog-to-digital converter (ADC)
The ADC_DATL/H register number <n> is 0-7
46/98
DocID024387 Rev 2
Control reverse signal line
STLUX385A
Memory and register map
Table 22. ADC register map and reset value
Address
Block
Register name
Register description
0x00.5400
ADC_CFG
Configuration
0x00.5401
ADC_SOC
Start of conversion
0x00.5402
ADC_IER
Interrupt enable
0x00.5403
ADC_SEQ
Sequencer
0x00.5404
ADC_DATL_0
Low part data 0 converted
0x00.5405
ADC_DATH_0
High part data 0 converted
0x00.5406
ADC_DATL_1
Low part data 1 converted
0x00.5407
ADC_DATH_1
High part data 1 converted
0x00.5408
ADC_DATL_2
Low part data 2 converted
0x00.5409
ADC_DATH_2
High part data 2 converted
ADC_DATL_3
Low part data 3 converted
0x00.540B
ADC_DATH_3
High part data 3 converted
0x00.540C
ADC_DATL_4
Low part data 4 converted
0x00.540D
ADC_DATH_4
High part data 4 converted
0x00.540E
ADC_DATL_5
Low part data 5 converted
0x00.540F
ADC_DATH_5
High part data 5 converted
0x00.5410
ADC_DATL_6
Low part data 6 converted
0x00.5411
ADC_DATH_6
High part data 6 converted
0x00.5412
ADC_DATL_7
Low part data 7 converted
0x00.5413
ADC_DATH_7
High part data 7 converted
0x00.5414
ADC_SR
0x00.5415
ADC_DLYCNT
0x00.540A
ADC
6.2.15
Status
SOC delay counter
State machine event driven (SMEDs)
The SMED<n> address register is:
ADD_REG = (5500h + (40h)*n) + offset
where <n> is the SMED instance number 0-5
DocID024387 Rev 2
47/98
Memory and register map
STLUX385A
Table 23. SMED register map
Address
(offset)
Register name
Register description
0x00
SMD<n>_CTR
0x01
SMD<n>_CTR_TMR
Control time
0x02
SMD<n>_CTR_INP
Control input
0x03
SMD<n>_CTR_DTR
Dithering
0x04
SMD<n>_TMR_T0L
Time T0 LSB
0x05
SMD<n>_TMR_T0H
Time T0 MSB
0x06
SMD<n>_TMR_T1L
Time T1 LSB
0x07
SMD<n>_TMR_T1H
Time T1 MSB
0x08
SMD<n>_TMR_T2L
Time T2 LSB
0x09
SMD<n>_TMR_T2H
Time T2 MSB
0x0A
SMD<n>_TMR_T3L
Time T3 LSB
0x0B
SMD<n>_TMR_T3H
Time T3 MSB
0x0C
SMD<n>_PRM_ID0
IDLE state parameter0
SMD<n>_PRM_ID1
IDLE state parameter1
0x0E
SMD<n>_PRM_ID2
IDLE state parameter2
0x0F
SMD<n>_PRM_S00
S0 state parameter0
0x10
SMD<n>_PRM_S01
S0 state parameter1
0x11
SMD<n>_PRM_S02
S0 state parameter2
0x12
SMD<n>_PRM_S10
S1 state parameter0
0x13
SMD<n>_PRM_S11
S1 state parameter1
0x14
SMD<n>_PRM_S12
S1 state parameter2
0x15
SMD<n>_PRM_S20
S2 state parameter0
0x16
SMD<n>_PRM_S21
S2 state parameter1
0x17
SMD<n>_PRM_S22
S2 state parameter2
0x18
SMD<n>_PRM_S30
S3 state parameter0
0x19
SMD<n>_PRM_S31
S3 state parameter1
0x1A
SMD<n>_PRM_S32
S3 state parameter2
0x0D
48/98
Block
SMED<n>
DocID024387 Rev 2
Control
STLUX385A
Memory and register map
Table 23. SMED register map (continued)
Address
(offset)
Register name
Register description
0x1B
SMD<n>_CFG
0x1C
SMD<n>_DMP_L
Counter dump LSB
0x1D
SMD<n>_DMP_H
Counter dump MSB
0x1E
SMD<n>_GSTS
0x1F
6.2.16
Block
Timer configuration register
General status
SMD<n>_IRQ
Interrupt request register
0x20
SMD<n>_IER
Interrupt enable register
0x21
SMD<n>_ISEL
External event control
0x22
SMD<n>_DMP
Dump enable
0x23
SMD<n>_FSM_STS
SMED<n>
FSM core status
CPU register
Table 24. CPU register map
Address
Register name
Register description
0x00.7F00
A
0x00.7F01
PCE
Program counter extended
0x00.7F02
PCH
Program counter high
0x00.7F03
PCL
Program counter low
0x00.7F04
XH
X-index high
XL
X-index low
0x00.7F06
YH
Y-index high
0x00.7F07
YL
Y-index low
0x00.7F08
SPH
Stack pointer high
0x00.7F09
SPL
Stack pointer low
0x00.7F0A
CC
Code condition
0x00.7F05
Note:
Block
CPU
Accumulator
Register space accessible in debug mode only.
DocID024387 Rev 2
49/98
Memory and register map
6.2.17
STLUX385A
Global configuration register
Table 25. CFG_GCR register map
6.2.18
Address
Block
Register name
0x00.7F60
GCR
CFG_GCR
Register description
Global configuration
Interrupt controller
Table 26. Interrupt software priority register map
Address
Block
Register name
Register description
0x00.7F70
ITC_SPR0
Interrupt SW priority register 0
0x00.7F71
ITC_SPR1
Interrupt SW priority register 1
0x00.7F72
ITC_SPR2
Interrupt SW priority register 2
ITC_SPR3
Interrupt SW priority register 3
0x00.7F74
ITC_SPR4
Interrupt SW priority register 4
0x00.7F75
ITC_SPR5
Interrupt SW priority register 5
0x00.7F76
ITC_SPR6
Interrupt SW priority register 6
0x00.7F77
ITC_SPR7
Interrupt SW priority register 7
0x00.7F73
ITC
6.2.19
SWIM control register
Table 27. SWIM register map
50/98
Address
Block
Register name
0x00.7F80
SWIM
SWIM_CSR
DocID024387 Rev 2
Register description
SWIM control status
STLUX385A
7
Interrupt table
Interrupt table
The following table shows the STLUX385A internal controller's interrupt.
Table 28. Interrupt vector exception table
Priority
Source
block
RESET
TRAP
Description
Reset
Wakeup
from Halt
Yes
Wakeup from Interrupt vector
active-halt
address
Yes
Software interrupt
8000h
8004h
Yes
(1)
Yes
(1)
8008h
0
NMI
NMI (not maskable interrupt)
1
AWU
Auto-wakeup from Halt
2
CKC
Clock controller
3
PO
4
AUXTIM
5
P2
6
SMED0
SMED-0 control logic
8020h
7
SMED1
SMED-1 control logic
8024h
8
RFU
Reserved for future use
8028h
9
RFU
Reserved for future use
802Ch
10
RFU
Reserved for future use
8030h
11
RFU
Reserved for future use
8034h
12
RFU
Reserved for future use
8038h
13
RFU
Reserved for future use
803Ch
14
RFU
Reserved for future use
8040h
15
SMED2
SMED-2 control logic
8044h
16
SMED3
SMED-3 control logic
8048h
17
UART
Tx complete
804Ch
18
UART
Receive register DATA FULL
Yes
800Ch
8010h
GPIO0[5:0]external interrupts
Yes
Yes
Auxiliary timer
8014h
8018h
DIGIN[5:0] external interrupts
Yes
Indirect (2)
Indirect (2)
8050h
Yes
8054h
19
I C interrupt
20
RFU
Reserved for future use
8058h
21
RFU
Reserved for future use
805Ch
22
ADC
End of conversion
8060h
23
SYS-TMR
Update/overflow
8064h
24
FLASH
EOP/WR_PG_DIS
8068h
25
DALI
DALI interrupt line
26
SMED4
SMED-4 control logic
8070h
27
SMED5
SMED-5 control logic
8074h
Indirect
(2)
801Ch
I2
C
2
Yes
Indirect (1)
DocID024387 Rev 2
Indirect (1)
806Ch
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Interrupt table
STLUX385A
Table 28. Interrupt vector exception table (continued)
Priority
Source
block
28
RFU
Reserved future use
8078h
29
RFU
Reserved future use
807Ch
Description
1. P0[x] may be configured to generate an NMI request.
2. P0[x] may be configured to generate an IRQ request.
52/98
DocID024387 Rev 2
Wakeup
from Halt
Wakeup from Interrupt vector
active-halt
address
STLUX385A
8
Option bytes
Option bytes
The user option byte is a memory E²PROM area allowing users to customize the IC device
major functionalities:
•
ROP: read-out protection control field
•
UBC: user boot code protection
•
PWM: configurable reset output value
•
WDG: internal watchdog HW configuration
•
AFR: alternate multifunction signals configuration
•
CKC: clock controller functionalities (PLL, HSE enable, AWU clock selection…)
•
HSE: clock stabilization counter
•
WAIT: Flash and E²PROM wait state access time has to be configured with value 0x00
•
BOOT: configurable internal boot sources
•
BL: boot-loader control sequences
Except the ROP byte all the other option bytes are stored twice in a regular (OPT) and
complemented format (NOPT) for redundancy. The option byte can be programmed in ICP
mode through the SWIM interface or in IAP mode by the application with the exception of
the ROP byte that can be only configured via SWIM interface.
Refer to the STM8 Flash programming manual (PM0047) for further information about Flash
programming.
Refer to STM8 SWIM communication protocol and debug module user manual (UM0470)
for information on SWIM programming procedures.
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Option byte register overview
Table 29. Option byte register overview
Address
Option bits
Option name
7
6
5
4
3
2
1
0
Default
settings
4800h
ROP
ROP[7:0]
00h
4801h
UCB
UBC[7:0]
00h
4802h
nUCB
nUBC[7:0]
FFh
GENCFG
4803h
Rst_PWM5
Rst_PWM4
Rst_PWM3
Rst_PWM2
Rst_PWM1
Rst_PWM0
COMP1_2
EN_COLD_C
FG
00h
DocID024387 Rev 2
nGENCFG
nRst_PWM5
nRst_PWM4
nRst_PWM3
nRst_PWM2
nRst_PWM1
nRst_PWM0
nCOMP1_2
nEN_COLD_
CFG
FFh
4805h
MISCUOPT
-
-
-
-
LSI_EN
IWDG_HW
WWDG_HW
WWDG_HAL
T
28h
4806h
nMISCUOPT
-
-
-
-
nLSI_EN
nIWDG_HW
nWWDG_H
W
nWWDG_HA
LT
D7h
4807h
CLKCTL
-
-
-
CCKAWUSE
L1
EXTCLK
CCKAWUSE
L0
PRSC[1:0]
09h
4808h
nCLKCTL
-
-
-
nCCKAWUS
EL1
nEXTCLK
nCCKAWUS
EL0
nP RSC[1:0]
F6h
4809h
HSESTAB
HSECNT[7:0]
00h
480Ah
nHSESTAB
nHSECNT[7:0]
FFh
480Bh
480Ch
RESERVED
-
00h
FFh
480Dh
WAITSTATE
-
-
-
-
-
-
WS[1:0]
00h
480Eh
nWAITSTATE
-
-
-
-
-
-
nWS[1:0]
FFh
480Fh
AFR_IOMXP
0
-
-
Sel_p010[1:0]
00h
Sel_p054[1:0]
Sel_p032[1:0]
STLUX385A
4804h
Option bytes
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8.1
Address
Option bits
Option name
7
6
5
4
3
2
1
0
Default
settings
DocID024387 Rev 2
4810h
nAFR_IOMX
P0
-
-
4811h
AFR_IOMXP
1
AUXTIM
-
Sel_p15
Sel_p14
Sel_p13
Sel_p12
Sel_p11
Sel_p10
00h
4812h
nAFR_IOMX
P1
nAUXTIM
-
nSel_p15
nSel_p14
nSel_p13
nSel_p12
nSel_p11
nSel_p10
FFh
4813h
AFR_IOMXP
2
-
-
-
Sel_p254
-
-
-
-
00h
4814h
nAFR_IOMX
P2
-
-
-
nSel_p254
-
-
-
-
FFh
4815h
MSC_OPT0
-
-
UARTLine(1:0)
-
BOTSEL[2:0]
00h
4816h
nMSC_OPT0
-
-
nUARTLine(1:0)
-
nBOTSEL[2:0]
FFh
487Dh
Reserved
-
-
-
-
487Eh
OPTBL
BL(7:0)
00h
487Fh
nOPTBL
nBL(7:0)
FFh
Note:
nSel_p054[1:0]
nSel_p032[1:0]
-
-
nSel_p010[1:0]
-
-
STLUX385A
Table 29. Option byte register overview (continued)
FFh
00h
The default setting values refer to the factory configuration.The factory configuration can be overwritten by the user in accordance
with the target application requirements.
This area of memory may be erased by the global Flash erase instruction generated by an unauthorized attempt to modify the ROP
protection.
Option bytes
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Option bytes
8.2
STLUX385A
Option byte register description
The option byte registers are mapped inside the E²PROM data region.
ROP (memory read-out protection register)
Offset: 0x004800
Default value: 0x00
7
6
5
4
3
2
1
0
ROP [7:0]
r/w
Bit 7-0:
ROP[7:0] memory read-out protection:
0xAA: enable read-out protection. When read-out protection is enabled, reading or
modifying the Flash program memory and DATA area in ICP mode (using the SWIM
interface) is forbidden, whatever the write protection settings are.
UBC (UBC user boot code reg.)
Offset: 0x004801
Default value: 0x00
7
6
5
4
3
2
1
0
UBC [7:0]
r/w
Bit 7-0:
UBC[7:0] user boot code write protection memory size:
0x00: no UBC, no Flash memory write-protection
0x01: pages 0 to 1 defined as UBC; 1 Kbyte memory write-protected (0x00.80000x00.83FF)
0x02: pages 0 to 3 defined as UBC; 2 Kbyte memory write-protected (0x00.80000x00.87FF)
0x03: pages 0 to 4 defined as UBC; 2.5 Kbyte memory write-protected (0x00.80000x00.89FF)
...
0x3E: pages 0 to 63 defined as UBC; 32 Kbyte memory write-protected (0x00.80000x00.FFFF)
Other values: reserved
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STLUX385A
Option bytes
nUBC (UBC user boot code reg. protection)
Offset: 0x004802
Default value: 0xFF
7
6
5
4
3
2
1
0
nUBC [7:0]
r/w
nUBC: not(UBC) EMC byte protection.
GENCFG (general configuration reg.)
Offset: 0x004803
Default value: 0xFF
7
6
5
4
3
2
1
0
Rst_PWM [5:0]
COMP1_2
EN_COLD_C
FG
r/w
r/w
r/w
Bit 0:
EN_COLD_CFG enables IC cold configuration through the option byte register
AFR_IOMXP0,P1:
0: default case, the IC multifunction signal configuration is performed by the
miscellaneous registers MSC_IOMXP0 and MSC_IOMXP1 (warm configuration).
1: enables the multifunction signal configuration through the option byte registers
AFR_IOMXP0 and AFR_IOMXP1 (cold configuration).
Bit 1:
COMP1_2 enables the complete backward compatibility with the previous device
implementations. In detail, below features are inhibited:
Multiplexing of I2C interface on GPIO[5:4], GPIO[1:0], DIGIN[5:4]
Multiplexing of UART interface on GPIO[5:4]
Port0 and Port2 interrupt mask feature (polling)
DIGIN[5:0] pull-up disabling feature
DALI noise rejection filter
Note:
This bit setting ensures the full device compatibility with the previous device model
(STLUX385).
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Option bytes
STLUX385A
Bit 7:2:
Rst_PWM[5:0] configures the PWM[n] reset value after the NRST signal
0: PWM[n] output low level (native default value)
1: PWM[n] output high level
Note:
The PWM signal programmed reset value is configured during the option byte loader phase,
then before the NRST is released it assumes its proper initial values.
nGENCFG (general configuration reg. protect.)
Offset: 0x004804
Default value: 0xFF
7
6
5
4
3
2
1
0
Rst_PWM [5:0]
nCOMP1_2
nEN_COLD_C
FG
r/w
r/w
r/w
nGENCFG: not(GENCFG) EMC byte protection
MISCUOPT (miscellaneous config. reg.)
Offset: 0x004805
Default value: 0x28 (factory configuration)
7
6
5
4
3
2
1
0
RFU
RFU
RFU
LSI_EN
lWdg_hw
WWdg_hw
WWdg_HAL
T
r
r
r
r/w
r/w
r/w
r/w
Bit 0:
WWdg_HALT window watchdog reset on Halt:
0: No reset generated on Halt if WWDG is active
1: Reset generated on Halt if WWDG is active
Bit 1:
WWdg_hw window watchdog hardware enable:
0: Window watchdog activation by SW
1: Window watchdog activation by HW
Bit 2:
IWdg_hw independent watchdog hardware enable:
0: Independent watchdog activation by SW
1: Independent watchdog activation by HW
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STLUX385A
Option bytes
Bit 3:
LSI_EN low speed internal RCOSC clock enable:
0: LSI clock is not available to CPU
1: LSI cock is enabled for CPU
Bit 4:
RFU reserved; must be kept 0 during register writing for future compatibility
Bit 5:
RFU reserved; must be kept 1 during register writing for future compatibility
Bit 7-6:
RFU reserved; must be kept 0 during register writing for future compatibility
nMISCUOPT (miscellaneous config. reg. protect.)
Offset: 0x004806
Default value: 0xD7
7
6
5
4
3
RFU
RFU
RFU
nLSI_EN
r
r
r
r/w
2
1
0
nlWdg_hw nWWdg_hw
r/w
nWWdg_HAL
T
r/w
r/w
nMISCUOPT: not(MISCUOPT) EMC byte protection
CLKCTL (CKC configuration reg.)
Offset: 0x004807
Default value: 0x09 (factory configuration)
7
6
5
4
3
2
1
0
RFU
CKAWUSEL1
EXTCLK
CKAWUSEL0
PRSC [1:0]
r
r/w
r/w
r/w
r/w
Bit 1-0:
PRSC[1:0] prescaler value for HSE to provide AWU unit with the low speed clock:
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
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Option bytes
STLUX385A
Bit 3:
EXTCLK external clock selection:
0: External crystal oscillator clock connected to HseOscin and HseOscout signals
1: External direct drive clock connected to HseOscin
Bit 4,2:
CKAWUSEL[1:0] AWU clock selection:
00: Low speed internal clock used for AWU module
01: HSE high speed external clock with prescaler used for AWU module
10: Reserved encoding value
11: Reserved encoding value
Bit 7-5:
RFU reserved; must be kept 0 during register writing for future compatibility
nCLKCTL (CKC configuration reg.)
Offset: 0x004808
Default value: 0xF6 (factory configuration)
7
6
5
RFU
4
3
2
1
nCKAWUSEL1 nEXTCLK nCKAWUSEL0
r
r/w
r/w
0
nPRSC [1:0]
r/w
r/w
nCLKCTL: not(CLKCTL) EMC byte protection.
HSESTAB (HSE clock stabilization reg.)
Offset: 0x004809
Default value: 0x00
7
6
5
4
3
HSECNT [7:0]
r/w
Bit 7-0:
HSECNT[7:0] HSE crystal oscillator stabilization cycles:
0x00: 2048 clock cycles
0xB4: 128 clock cycles
0xD2: 8 clock cycles
0xE1: 0.5 clock cycles
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DocID024387 Rev 2
2
1
0
STLUX385A
Option bytes
nHSESTAB (HSE clock stabilization reg. protect.)
Offset: 0x00480A
Default value: 0xFF
7
6
5
4
3
2
1
0
2
1
0
nHSECNT [7:0]
r/w
nHSESTAB: not(HSESTAB) EMC byte protection.
WAITSTATE (Flash wait state reg.)
Offset: 0x00480D
Default value: 0x00
7
6
5
4
3
RFU
Waitstat [1:0]
r
r/w
Bit 1-0:
Waitstat[1:0] configures the E²PROM and Flash programmable delay read access time:
00: 0 no delay cycle (default case fMASTER@16 MHz)
01: 1 delay cycles
10: 2 delay cycles
11: 3 delay cycles
Bit 7-2:
RFU reserved; must be kept 0 during register writing for future compatibility
nWAITSTATE (Flash wait state reg.)
Offset: 0x00480E
Default value: 0xFF
7
6
5
4
3
2
1
0
RFU
nWaitstat [1:0]
r
r/w
nWAITSTATE: not(WAITSTATE) EMC byte protection.
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Option bytes
STLUX385A
AFR_IOMXP0 (alternative Port0 config. reg.)
Offset: 0x00480F
Default value: 0x00
7
6
5
4
3
2
1
0
RFU
Sel_p054 [1:0]
Sel_p032 [1:0]
Sel_p010 [1:0]
r
r/w
r/w
r/w
Bit 5-0:
Refer to MSC_IOMXP0 miscellaneous register field description Section 6.2
Bit 7-6:
RFU reserved; must be kept 0 during register writing for future compatibility
nAFR_IOMXP0 (alternative Port0 config. reg. protect.)
Offset: 0x004810
Default value: 0xFF
7
6
5
4
3
2
1
0
RFU
nSel_p054 [1:0]
nSel_p032 [1:0]
nSel_p010 [1:0]
r
r/w
r/w
r/w
nAFR_IOMXP0: not(AFR_IOMXP0) EMC byte protection.
AFR_IOMXP1 (alternative Port1 config. reg.)
Offset: 0x004811
Default value: 0x00
7
6
5
4
3
2
1
0
AUXTIM
RFU
Sel_p15
Sel_p14
Sel_p13
Sel_p12
Sel_p11
Sel_p10
r
r
r/w
r/w
r/w
r/w
r/w
r/w
Bit 5-0:
Refer to MSC_IOMXP1 miscellaneous register field description Section 6.2.3
Bit 6:
RFU reserved; must be kept 0 during register writing for future product compatibility
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STLUX385A
Option bytes
Bit 7:
AUXTIM CCO Aux timer compatibility features
0: CCO Aux timer enabled
1: CCO Aux timer disabled
nAFR_IOMXP1 (alternative Port1 config. reg. protect)
Offset: 0x004812
Default value: 0xFF
7
6
5
4
3
2
1
0
nAUXTIM
RFU
nSel_p15
nSel_p14
nSel_p13
nSel_p12
nSel_p11
nSel_p10
r
r
r/w
r/w
r/w
r/w
r/w
r/w
nAFR_IOMXP1: not(AFR_IOMXP1) EMC byte protection.
AFR_IOMXP2 (alternative Port2 config. reg.)
Offset: 0x004811
Default value: 0x00
7
6
5
4
3
2
1
0
RFU
Sel_p254
RFU
RFU
RFU
RFU
r
r
r
r
r
r
Bit 3-0:
RFU reserved; must be kept 0 during register writing for future product compatibility
Bit 4:
Refer to MSC_IOMXP2 Miscellaneous register field description Section 6.2.3
Bit 7-5:
RFU reserved; must be kept 0 during register writing for future product compatibility
Offset: 0x004812
Default value: 0xFF
7
6
5
4
3
2
1
0
RFU
nSel_p254
RFU
RFU
RFU
RFU
r
r
r
r
r
r
nAFR_IOMXP2: not(AFR_IOMXP2) EMC byte protection.
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Option bytes
STLUX385A
MSC_OPT0 (misc. config. reg0.)
Offset: 0x004815
Default value: 0x00
7
6
5
4
3
2
1
RFU
UARTline [1:0]
RFU
Bootsel [2:0]
r
r/w
r
r/w
0
Bit 2-0:
Bootsel[2:0] boot-rom peripheral enables:
000: Automatic scan boot sources; this selection enables the automatic scan
configuration sequence of all possible initializing peripheral devices: Periph0(UART),
Periph1(RFU), Periph2(RFU).
001: Enable boot source: Periph0
010: Enable boot source: Periph1
011: Enable boot sources: Periph1, Periph0
100: Enable boot source: Periph2
101: Enable boot sources: Periph2, Periph0
110: Enable boot sources: Periph2, Periph1
111: Enable boot sources: Periph2, Periph1, Periph0
Bit 3:
RFU reserved; must be kept 0 during register writing for future compatibility
Bit 5-4:
UARTline[1:0] selects the UART port configuration pins involved during the bootload
sequence in warm configuration mode; in case of cold configuration, this field is
ignored since the UART port is selected by register AFR_IOXP0.
00: Boot sequence with UART i/f configured in all possible UART multiplexed signal
schemes. This sequence is used when UART i/f position is not specified.
01: Boot sequence with UART i/f configured on P0(1,0)
10: Boot sequence with UART i/f configured on P0(3,2)
11: Boot sequence with UART i/f configured on P0(5,4)
Bit 7-6:
RFU reserved; must be kept 0 during register writing for future compatibility
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STLUX385A
Option bytes
nMSC_OPT0 (misc. config. reg0. protect)
Offset: 0x004816
Default value: 0xFF
7
6
5
4
3
2
1
RFU
UARTline [1:0]
RFU
nBootsel [2:0]
r
r/w
r
r/w
0
nMSC_OPT0: not(MSC_OPT0) EMC byte protection.
OPTBL (option byte bootloader)
Offset: 0x00487E
Default value: 0x00
7
6
5
4
3
2
1
0
BL [7:0]
r/w
Bit 7-0:
BL[7:0] bootloader field checked by the internal BootROM code during the STLUX385A
initialization phase. The content of register locations 0x00487E, 0x00487F and
0x008000 determine the bootloader SW flow execution sequence.
OPTBL (option byte boot loader protect.)
Offset: 0x00487F
Default value: 0x00
7
6
5
4
3
2
1
0
nBL [7:0]
r/w
nOPTBL: not(OPTBL) EMC byte protection.
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Device identification
STLUX385A
9
Device identification
9.1
Unique ID
The STLUX385A provides a 56-bits unique identifier code usable as device identification
number which can be used to increase the device security. The unique ID code is a frozen
signature not alterable by user.
The unique device identifier is ideally used by the application software and is suited for:
•
•
•
serial code
security keys in conjunction with cryptographic software to increase the embedded
flash code security
activating the secure boot sequence
Table 30. Unique ID register overview
Address
9.2
Option
name
Unique ID bits
7
6
5
4
3
2
1
48E0h
UID0
LotNum[7:0]
48E1h
UID1
LotNum[15:8]
48E2h
UID2
LotNum[23:16]
48E3h
UID3
WaferNum[4:0]
Xcoord[7:5]
48E4h
UID4
Xcoord[4:0]
Ycoord[7:5]
48E5h
UID5
Ycoord[4:0]
LotNum[42:40]
48E6h
UID6
LotNum[31:24]
48E7h
UID7
LotNum[39:32]
0
Device ID
The STLUX385A device identification model is coded in the following register area and it
cannot be altered by the user.
The register fields have the follow meaning:
Dev_ID [7:0]:
Device identification model
0x00: STLUX385
Others: RFU reserved values
Rev_ID [4:0]:
Revision identification model
00000: STLUX385
00001: STLUX385A
Others: RFU reserved values
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STLUX385A
Device identification
Table 31. Dev ID register overview
Address
Option
name
Dev ID bits
7
6
5
4
3
2
1
0
Default
settings
4896h
DVD0
DEV_ID[7:0]
00h
4897h
nDVD0
nDEV_ID[7:0]
FFh
4898h
DVD1
RFU
Rev_ID[4:0]
01h
4899h
nDVD1
nRFU
nRev_ID[4:0]
FEh
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Electrical characteristics
STLUX385A
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS. VDDA and VDD must be
connected to the same voltage value.
10.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TA max. (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.
10.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD and VDDA = 3.3 V.
They are given only as design guidelines and are not tested. Typical ADC accuracy values
are determined by characterization of a batch of samples from a standard diffusion lot over
the full temperature range.
10.1.3
Typical curves
Unless otherwise specified, all typical curves are given as design guidelines only and are
not tested.
10.1.4
Typical current consumption
For typical current consumption measurements, VDD and VDDA are connected together as
shown in the following picture.
Figure 9. Supply current measurement conditions
5 V or 3.3 V
VDDIO
VDDIA
GNDIO
GNDA
GIPD090520131534FSR
68/98
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STLUX385A
10.1.5
Electrical characteristics
Loading capacitors
The loading conditions used for pin parameter measurement are shown in the following
picture:
Figure 10. Pin loading conditions
50 pF
GIPD090520131536FSR
10.1.6
Pin output voltage
The input voltage measurement on a pin is described in the following picture.
Figure 11. Pin input voltage
VIN
GIPD090520131542FSR
DocID024387 Rev 2
69/98
Electrical characteristics
10.2
STLUX385A
Absolute maximum ratings
Stresses above those listed as 'absolute maximum ratings' may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect the device reliability.
Table 32. Voltage characteristics
Symbol
Ratings
Min.
Max.
-0.3
6.5
VSS -0.3
VDD +0.3
VDDX – VSSX Supply voltage(1)
Unit
V
VIN
Input voltage on any other pin
(2)
VDD - VDDA
Variation between different power pins
50
VSS - VSSA
Variation between all the different ground
pins(3)
50
VESD
mV
Refer to absolute maximum ratings
(electrical sensitivity) on Section 10.4.1
Electrostatic discharge voltage
1. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external
power supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
3. VSS and VSSA signals must be interconnected together with a short wire loop.
Table 33. Current characteristics
Symbol
IVDDX
IVSSX
Max.(1)
Ratings
Total current into VDDX power lines (2)
Total current out of VSSX power lines
(2)
Unit
100
100
Output current sunk by any I/Os and control pin
IIO
Ref.
mA
Output current source by any I/Os and control pin
IINJ(PIN)(3) (4)
IINJ(TOT)(3)(4)(5)
Injected current on any pin
±4
Sum of injected currents
±20
1. Data based on characterization results, not tested in production.
2. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external
power supply.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
4. Negative injection disturbs the analog performance of the device.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on characterization
with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
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STLUX385A
Electrical characteristics
Table 34. Thermal characteristics
Symbol
TSTG
Ratings
Max.
Storage temperature range
Unit
-65 to 150
ºC
TJ
10.3
Maximum junction temperature
150
Operating conditions
The device must be used in operating conditions that respect the parameters in the table
below. In addition, full account must be taken for all physical capacitor characteristics and
tolerances.
Table 35. General operating conditions
Symbol
Parameter
fCPU
Internal CPU clock
frequency
VDD1,
VDDA1
Operating voltages
Conditions
Min.
-40 ≤ TA ≤ 105 °C
VDD, VDDA Nominal operating voltages
Max.
Unit
0
16
MHz
3(1)
5.5(1)
3.3(1)
5(1)
V
470
3300
nF
0.05
0.2
Ω
15
nH
1.8(2)
Core digital power supply
VOUT
CVOUT: capacitance of
external capacitor(3)
ESR of external capacitor(2)
ESL of external
Typ.
at 1 MHz
capacitor(2)
ΘJA (4)
FR4 multilayer PCB
TA
Ambient temperature
80
Pd=100 mW
°C/W
-40
105
°C
1. The external power supply can be within range from 3 V up to 5.5 V although IC performances are
optimized for power supply equal to 3.3 V.
2. Internal core power supply voltage.
3. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature,
DC bias and frequency.
4. To calculate PDmax (TA), use the formula PDmax = (TJmax - TA)/ΘJA.
Table 36. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min.(1)
Typ.
VDD rise time rate
2 μs/V
1 sec/V(2)
VDD fall time rate
2 μs/V
1 sec/V(2)
tVDD
tTEMP
Max.(1)
Reset release delay
VDD rising
DocID024387 Rev 2
3
Unit
ms
71/98
Electrical characteristics
STLUX385A
Table 36. Operating conditions at power-up/power-down (continued)
Symbol
Parameter
Conditions
Min.(1)
Typ.
Max.(1)
VIT+
Power-on reset threshold
2.65
2.8
2.98
VIT-
Brown-out reset threshold
2.58
2.73
2.88
VHYS(BOR)
Brown-out reset hysteresis
Unit
V
70
mV
1. Guaranteed by design, not tested in production.
2. Power supply ramp must be monotone
10.3.1
VOUT external capacitor
The stabilization of the main regulator is achieved by connecting an external capacitor
CVOUT(a) to the VOUT pin. CVOUT is specified in the operating condition section. Care
should be taken to limit the series inductance to less than 15 nH.
Figure 12. External capacitor CVOUT
C
ESR
ESL
RLEAK
GIPD100520131002FSR
10.3.2
Supply current characteristics
The STLUX385A supply current is calculated by summing the supply base current in the
desired operating mode as per Table 37, with the peripheral supply current value reported in
Table 39 and Table 40.
For example, considering an application where:
•
fMASTER = fCPU = 16 MHz provided by HSI internal RC oscillator
•
CPU code execution in Flash
•
All base peripheral actives: I2C, UART, DALI, ITC, GPIO0, SysTimr, WWDG and IWDG
•
ADC conversion frequency fADC = 5.3 MHz
•
ACU (comparator and DAC units) actives
•
6 PWM toggling @ fPWM = 0.5 MHz provided by 6 SMEDs running @ fSMED = 12 MHz
(NPWM = 6)
a. ESR is the equivalent series resistance and ESL is the equivalent inductance.
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STLUX385A
Electrical characteristics
The total current consumption is given by the following formula:
I DD = I DD ( Run2 ) + I DD ( ADC2 ) + IDD ( ACU ) + I DD ( PLL ) + I DD ( PWM )
where IDD(PWM) = IDD(PWM1) *NPWM
More generally, the PWM current consumption has to be individually evaluated for each
fSMED clock grouping, using the formula below:
I DD ( PWM ) =
i
NfSMED
[ I DD ( PWM [ i1 ] ) • N i ]
= 1
where i = fSMED clock group index; Ni = PWM number of the i_th clock group; NfSMED =
fSMED clock group number.
IC supply base current consumption
The following table summarizes the current consumption measured on VDD/VDDA supply
pins in relevant operative conditions.
Table 37. Supply base current consumption at VDD/VDDA = 3.3/5 V
Symbol
Code
Op. mode
Code
area
Clock
Peripheral
Consumption(6)
SRC(2)
fMASTER
fCPU
Periph (1,4)
Typ.(5)
Max.(5)
Clock
MHz
MHz
Enable
mA
mA
Note
Description
IDD(Run1)
Flash
HSI
2
2
All
2.3
2.77
IDD(Run2)
Flash
HSI
16
16
All
9.4
11.3
IDD(Run3)
RAM
HSI
16
16
All
4.2
5.1
10.0
12.1
Flash
HSE(1)
VDD/VDDA = 3.3 V
IDD(Run4)
16
16
All
10.6
12.74
VDD/VDDA = 5 V
4.6
5.53
VDD/VDDA = 3.3 V
5.2
6.63
VDD/VDDA = 5 V
IDD(Run5)
RAM
HSE(5)
16
16
Reset exit condition
All
IDD(SLOW1)
Flash
HSI
16
2
All
3.6
4.33
IDD(SLOW2)
RAM
HSI
16
2
All
2.9
3.5
3.9
4.7
Flash
HSE(5)
VDD/VDDA = 3.3 V
IDD(SLOW3)
16
2
All
4.5
5.5
VDD/VDDA = 5 V
2.7
3.3
3.0
3.7
VDD/VDDA = 3.3 V
3.6
4.4
VDD/VDDA = 5 V
IDD(SLOW4)
Flash
HSI
16
0.125
All
IDD(SLOW5)
Flash
HSE(5)
16
0.125
All
IDD(SLOW6)
Flash
LSI
0,153
0.153
All
1.5
1.9
IDD(WFI1)
Flash
HSI
16
16
All
2.6
3.2
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Electrical characteristics
STLUX385A
Table 37. Supply base current consumption at VDD/VDDA = 3.3/5 V (continued)
Symbol
Code
IDD(WFI2)
Flash
Clock
HSE(5)
16
Peripheral
16
Consumption(6)
Note
3.1
3.8
VDD/VDDA =3.3 V
3.8
5.6
VDD/VDDA =5 V
All
1. “All” means: I2C, UART, Dali, ITC, GPIO0, SysTimr, WWDG and IWDG peripherals active.
2. fMASTER clock source.
3. HSE frequency provided by external quartz.
4. The peripheral current consumption is supplied by the VCORE voltage (1.8 V).
5. Temperature operating: TA= 25 °C.
6. Data based on characterization results not tested in production.
IC low power current consumption
The following table summarizes the current consumption measured on VDD/VDDA supply
pins in power saving conditions.
Table 38. Supply low power consumption at VDD/VDDA = 3.3/5 V
Symbol
Code
Op.
mode(1)(2)
Code
area
Clock
Peripheral
Consumption(11)
fMASTER
fCPU
E2PROM(6)
Clock
MHz
Enable
Enable
mA
mA
SRC(3)
MVRreg.
(5)
Note
Typ.(8.10) Max.(9,10)
Description
IDD(AHLT1)
Flash
HSI
16
Enable
Enable
0.23
0.32
AWU clocked by LSI
IDD(AHLT2)
Flash
HSI
16
Enable
Disable
0.085
0.12
AWU clocked by LSI
0.73
0.90
Flash
HSE(4,7)
VDD/VDDA =3.3 V
IDD(AHLT3)
16
Enable
Enable
1.4
1.7
VDD/VDDA =5 V
0.65
0.95
VDD/VDDA =3.3 V
1.2
1.45
VDD/VDDA =5 V
0.087
0.13
0.075
0.11
VDD/VDDA =3.3 V
0.090
0.15
VDD/VDDA =5 V
IDD(AHLT4)
Flash
HSE(4,7)
16
Enable
Disable
IDD(HLT1)
Flash
HSI
16
Enable
Disable
IDD(HLT2)
Flash
HSE(4,7)
16
Enable
Disable
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STLUX385A
Electrical characteristics
1. Active-halt op. mode: all peripherals except AWU and IWDG are disabled (clock gated).
2. HALT op. mode: all peripherals are disabled (clock gated).
3. fMASTER clock source.
4. HSE frequency provided by external quartz.
5. VCORE Main DC voltage regulator.
6. E2PROM is considered always enabled.
7. AWU clocked by HSE source clock.
8. Temperature operating: TA= 25 °C.
9. Temperature operating: TA= 105 °C.
10. All the analog input signals are connected to GND; the signals of port P0, P1 and P2 are configured as input with pull-up
enabled.
11. Data based on characterization results not tested in production.
Note:
All the input analog signals are connected to GND; signals of port P0, P1 and P2 are
configured as input with pull-up enabled.
IC peripheral current consumption (3.3 V)
The following table summarizes the peripheral current consumption measured on VDD/VDDA
supply pins.
Table 39. Peripheral supply current consumption at VDD/VDDA = 3.3 V
Symbol
Clock
Peripherals
Consumption(9)
fSMED(1)
fPWM(2)
fADC(3)
ADC(7)
PWM(4),(5)
ACU(6)
Typ(8)
Max(8)
Enb/Dis
MHz
MHz
MHz
Enb/Dis
Num
Enb/Di
s
mA
mA
IDD(PLL)
Enab
0
0
0
Disab
0
Disab
2.26
2.7
IDD(ACU)
Disab
0
0
0
Disab
0
Enab
1.89
2.27
1.75
2.1
Enab
96
0.5
0
Disab
10.12
12.2
1.12
1.33
6.54
7.85
0.71
0.86
4.39
5.27
0.54
0.65
3.33
4
0.44
0.53
2.81
3.4
Op.mode
IDD(PWM1PLL96)
1
IDD(PWM6PLL96)
Disab
6
IDD(PWM1PLL48)
1
Enab
48
0.5
0
Disab
IDD(PWM6PLL48)
Disab
6
IDD(PWM1PLL24)
1
Enab
24
0.5
0
Disab
IDD(PWM6PLL24)
Disab
6
IDD(PWM1PLL12)
1
Enab
12
0.5
0
Disab
IDD(PWM6PLL12)
Disab
6
IDD(PWM1PLL6)
1
Enab
6
0.5
0
Disab
IDD(PWM6PLL6)
Disab
6
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Electrical characteristics
STLUX385A
Table 39. Peripheral supply current consumption at VDD/VDDA = 3.3 V (continued)
Symbol
Clock
Peripherals
IDD(PWM1HSI16)
Consumption(9)
1
Enab
16
0.5
0
Disab
IDD(PWM6HSI16)
6
IDD(PWM1HSI8)
1
Enab
8
0.5
0
Disab
6
IDD(PWM1HSI4)
1
4
0.5
0
Disab
6
IDD(PWM1HSI2)
1
2
0.5
0
2.63
3.3
0.34
0.41
2.12
2.55
0.29
0.35
1.78
2.2
0.25
0.3
1.60
1.93
Disab
IDD(PWM6HSI4)
Enab
0.56
Disab
IDD(PWM6HSI8)
Enab
0.46
Disab
Disab
Disab
IDD(PWM6HSI2)
6
IDD(ADC1)
Disab
0
0
1
Enab
0
Disab
1.55
1.87
IDD(ADC2)
Disab
0
0
5.3
Enab
0
Disab
1.59
1.91
IDD(ADC3)
Enab
0
0
6
Enab
0
Disab
1.56
1.88
1. SMED frequency:
- 96 MHz and 6 MHz frequencies require the PLL enabled.
- Current table shows only a subset value of possible SMED frequencies.
2. PWM frequency:
- PWM toggle frequency is considered fixed to 500 kHz, close to the maximum applicative value.
3. ADC frequency:
- 6 MHz frequency requires the PLL enabled.
- Current table shows only a subset value of possible ADC frequencies
4. Number of active PWMs.
5. PWM pins are loaded with a CL (load capacitance) of 50 pF.
6. If enabled all DACs and comparator units are active.
7. ADC configured in circular mode.
8. Temperature operating: TA= 25 °C.
9. Data based on characterization results not tested in production.
IC peripheral current consumption (5 V)
The following table summarizes the peripheral current consumption measured on VDD/VDDA
supply pins.
Table 40. Peripheral supply current consumption at VDD/VDDA = 5 V
Symbol
76/98
Clock
PLL
Peripherals
fSMED(1) fPWM(2)
Consumption
fADC(3)
ADC(7)
PWM(4,5)
ACU(6)
MHz
MHz
Enb/Dis
Num
Enb/Dis
mA
mA
0
0
0
Disab
0
Disab
2.32
2.78
0
0
0
Disab
0
Enab
2.22
2.66
Op.
Mode
Enb/Dis
MHz
IDD(PLL)
Enab
IDD(ACU)
Disab
DocID024387 Rev 2
Typ(8) Max(8)
STLUX385A
Electrical characteristics
Table 40. Peripheral supply current consumption at VDD/VDDA = 5 V (continued)
Symbol
Clock
Peripherals
Consumption
1
IDD(PWM1PLL96)
Enab
96
0.5
0
Disab
IDD(PWM6PLL96)
6
1
IDD(PWM1PLL48)
Enab
48
0.5
0
Disab
IDD(PWM6PLL48)
1
Enab
24
0.5
0
Disab
1
IDD(PWM1PLL12)
Enab
12
0.5
0
Disab
IDD(PWM6PLL12)
1
Enab
6
0.5
0
Disab
IDD(PWM6PLL6)
1
Enab
16
0.5
0
Disab
IDD(PWM1HSI8)
1
Enab
8
0.5
0
Disab
IDD(PWM6HSI8)
1
Enab
4
0.5
0
Disab
IDD(PWM6HSI4)
1
Enab
2
0.5
0
Disab
IDD(PWM6HSI2)
8.26
0.79
0.95
4.73
5.68
0.58
0.7
3.66
4.4
0.49
0.6
3.11
3.75
0.56
0.67
3.13
3.78
0.49
0.58
2.56
3.1
0.39
0.47
2.33
2.78
0.47
0.54
2.1
2.49
Disab
6
IDD(PWM1HSI2)
6.88
Disab
6
IDD(PWM1HSI4)
1.42
Disab
6
IDD(PWM6HSI16)
1.18
Disab
6
IDD(PWM1HSI16)
12.59
Disab
6
IDD(PWM1PLL6)
10.49
Disab
6
IDD(PWM6PLL24)
2.17
Disab
6
IDD(PWM1PLL24)
1.81
Disab
Disab
6
IDD(ADC1)
Disab
0
0
1
Enab
0
Disab
2.11
2.54
IDD(ADC2)
Disab
0
0
5.3
Enab
0
Disab
2.16
2.6
IDD(ADC3)
Enab
0
0
6
Enab
0
Disab
2.17
2.61
1. SMED frequency:
- 96 MHz and 6 MHz frequencies require the PLL enabled.
- Current table shows only a subset value of possible SMED frequencies.
2. PWM frequency:
- PWM toggle frequency is considered fixed to 500 kHz, close to the maximum applicative value.
3. ADC frequency:
- 6 MHz frequency requires the PLL enabled.
- Current table shows only a subset value of possible ADC frequencies.
4. Number of active PWMs.
5. PWM pins are loaded with a CL (load capacitance) of 50 pF.
6. If enabled all DACs and comparator units are active.
7. ADC configured in circular mode.
8. Temperature operating: TA= 25 °C.
9. Data based on characterization results not tested in production.
PWM current consumption overview
The figures that follow provide an outline view of PWM current consumption results.The
consumptions are evaluated considering the maximum current at TA = 25 °C with different
SMED operating frequencies. The charts summarize the measurements carried out from
DocID024387 Rev 2
77/98
Electrical characteristics
STLUX385A
Table 39 and Table 40 allowing users to derive the PWM current consumption values.
Figure 13. PWM current consumption with fSMED=PLL fPWM=0.5 MHz at
VDD/VDDA=3.3V
,''3:0 P$
0+]
0+]
0+]
0+]
0+]
$FWLYH3:0QXPEHU
Figure 14. PWM current consumption with fSMED=PLL fPWM=0.5 MHz at VDD/VDDA=5V
, ''3:0 P$
0+]
0+]
0+]
0+]
78/98
$FWLYH3:0QXPEHU
DocID024387 Rev 2
STLUX385A
Electrical characteristics
Figure 15. PWM current consumption with fSMED=HSI fPWM=0.5 MHz at VDD/VDDA=3.3V
, ''3:0 P$
0+]
0+]
0+]
0+]
$FWLYH3:0QXPEHU
Figure 16. PWM current consumption with fSMED=HSI fPWM=0.5 MHz at VDD/VDDA=5V
,''3:0 P$
0+]
0+]
0+]
0+]
$FWLYH3:0QXPEHU
10.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for VDD and TA
Table 41. HSE user external clock characteristics
Symbol
fHSE_ext
Parameter
User external clock source
frequency
Conditions
Min.
Max.
Unit
-40 °C ≤TA ≤ 105 °C
0
16(1)
MHz
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Electrical characteristics
STLUX385A
Table 41. HSE user external clock characteristics (continued)
Symbol
Parameter
Conditions
VHSEH(2)
HSEOSCIN input pin high level
voltage
Min.
Max.
0.7 x VDD
VDD
Unit
V
VHSEL
(2)
ILEAKHSE(2)
HSEOSCIN input pin low level
voltage
HSEOSCIN input pin leakage
VSS
≤VIN ≤ VDD
VSS
0.3 x VDD
-1
+1
μA
1. In case fHSE is configured as direct clock for the SMED logics the maximum frequency can be 24 MHz.
2. Data based on characterization results, not tested in production.
Figure 17. HSE external clock source
VHSEH
VHSEL
fHSE
External clock
source
Hse Oscin
GIPD100520131400FSR
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 42. HSE crystal/ceramic resonator oscillator
Symbol
fHSE
RF
80/98
Parameter
Conditions
External high speed
oscillator frequency
Feedback resistor
Min.
Typ.
1
Max.
Unit
16(1)
MHz
220
kΩ
CL1, CL2(2)
Recommended load
capacitance(3)
20
pF
IDD(HSE)
HSE oscillator power
consumption
6(startup)
2(stabilized)
mA
DocID024387 Rev 2
STLUX385A
Electrical characteristics
Table 42. HSE crystal/ceramic resonator oscillator (continued)
Symbol
gm
tSU(HSE)(4)
Parameter
Conditions
Oscillator
transconductance
Startup time
Min.
Typ.
Max.
5
VDD is stabilized
Unit
mA/V
2.8
ms
1. In case fHSE is configured as direct clock for the SMED logic the maximum frequency can be 24 MHz
2. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load
capacitance (Cload) is (CL1 * CL2)/(CL1 + CL2). If CL1 = CL2, Cload = CL1 / 2. Some oscillators have
built-in load capacitors, CL1 and CL2.
3. The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small Rm value.
4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
Figure 18. HSE oscillator circuit diagram
HseOscin
HseOscout
HseOscout
GIPD100520131424FSR
The crystal characteristics have to be checked with the following formula:
g m » g mCritic
where gmCritic is calculated with the crystal parameters as follows:
g mCritic = ( 2 ⋅ π ⋅ f HSE )2 ⋅ R m ( 2C O + C )2
and where:
•
Rm: motional resistance(b)
•
Lm: motional inductance(b)
•
Cm: motional capacitance(b)
•
CO: shunt capacitance(b)
•
CL1 = CL2 = C: grounded external capacitance
b. Refer to application crystal specification.
DocID024387 Rev 2
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Electrical characteristics
10.3.4
STLUX385A
Internal clock sources and timing characteristics
HSI RC oscillator
Subject to general operating conditions for VDD and TA.
Table 43. HSI RC oscillator
Symbol
fHSI
ACCHSI
tSU(HSI)
Parameter
Conditions
Min.(1)
Frequency
Typ.
Max.(1)
16
Accuracy of HSI
oscillator (factory
calibrated)(1)(2)
MHz
VDD = 3.3V
TA= 25 ºC
-1%
+1%
VDD = 3.3V
-40 ºC ≤ TA ≤ 105 ºC
-4%
+4%
VDD = 5V
-40 ºC ≤ TA ≤ 105 ºC
-4%
+4%
HSI oscillator wakeup
time including
calibration
Unit
1
%
μs
1. Data based on characterization results, not tested in production.
2. Variation referred to fHSI nominal value.
LSI RC oscillator
Subject to general operating conditions for VDD and TA.
Table 44. LSI RC oscillator
Symbol
fLSI
Parameter
Conditions
Min.(1)
Frequency
Typ.
Max.(1)
153.6
3.3V ≤ VDD ≤ 5V
-40 ºC ≤ TA ≤ 105 ºC
ACCLSI
Accuracy of LSI
oscillator
tSU(LSI)
LSI oscillator wakeup
time
-10%
Unit
kHz
10%
7
%
μs
1. Guaranteed by design, not tested in production.
PLL internal source clock
Table 45. PLL internal source clock
Symbol
82/98
Parameter
fIN
Input frequency((2)
fOUT
Output frequency
tlock
PLL lock time
Conditions
Min.(1)
Typ.
Max.(1)
Unit
16
3.3V ≤ VDD ≤ 5V
-40 ºC ≤ TA ≤ 105 ºC
MHz
96
200
DocID024387 Rev 2
μs
STLUX385A
Electrical characteristics
1. Data based on characterization results, not tested in production.
2. PLL maximum input frequency 16 MHz.
10.3.5
Memory characteristics
Flash program and memory/data E2PROM memory
General conditions: TA = -40 °C to 105 °C.
Table 46. Flash program memory/data E2PROM memory
Symbol
Parameter
Conditions
Min.(1)
Typ.
Max.
6
6.6
Unit
Standard programming time
(including erase) for
byte/word/block
tPROG
ms
(1 byte/4 bytes/128 bytes)
tERASE
Fast programming time for 1
block (128 bytes)
3
3.3
Erase time for 1 block (128
bytes)
3
3.3
Erase/write cycles(2) (program
memory)
NWE
TA = 25 °C
10 K
TA = 85 °C
100 K
TA = 105 °C
35 K
Data retention (program
memory) after 10 K erase/write
cycles at TA= 25 °C
TRET = 85 °C
15
Data retention (program
memory) after 10 K erase/write
cycles at TA= 25 °C
TRET = 105 °C
11
ms
Cycles
Erase/write cycles(2) (data
memory)
Years
tRET
Data retention (data memory)
after 100 K erase/write cycles at
TA= 85 °C
TRET = 85 °C
15
Data retention (data memory)
after 35 K erase/write cycles at
TA= 105 °C
TRET = 105 °C
6
1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.
10.3.6
I/O port pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. Unused
input pins should not be left floating.
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Electrical characteristics
STLUX385A
Table 47. Voltage DC characteristics
Symbol
Description
VIL
Input low voltage
VIH
Input high voltage (1)
Min.
Typ.
Max.
-0.3
0.3 * VDD
0.7 * VDD
VDD
(2)(3)
VOL1
Output low voltage @ 3.3 V
VOL2
Output low voltage @ 5 V (2)(3)
VOL3
Output low voltage high sink @ 3.3 V / 5 V (1)(4)(5)
VOH1
Output high voltage @ 3.3 V (2)(3)
VOH2
Output high voltage @ 5 V (2)(3)
VOH3
Output high voltage high sink @ 3.3 V / 5 V (1)(4)(5)
HVS
Hysteresis input voltage (6)
RPU
Pull-up resistor
Unit
0.4(13)
0.5
0.6(13)
V
VDD0.4(13)
VDD-0.5
VDD0.6(13)
0.1 * VDD
30
45
60
kΩ
Max.
Unit
1. All signals are not 5 V tolerant (input signals can't be exceeded VDDX (VDDX = VDD, VDDA)).
2. Parameter applicable to signals: GPIO0[5:0] (high sink selectable by high speed config.).
3. Parameter applicable to signals: GPIO1[5:0]/PWM[5:0].
4. Parameter applicable to signal: SWIM.
5. Parameter applicable to signal: DIGIN[0]/CCO_clk
6. Applicable to any digital inputs.
Table 48. Current DC characteristics
Symbol
IOL1
IOL2
IOLhs1
IOLhs2
Description
Standard output low level current @ 3.3 V and VOL1
(1)(2)
Standard output low level current @ 5 V and VOL2
Min.
Typ.
1.5
(1)(2)
3
High sink output low level current @ 3.3 V and VOL3
5
(1)(3)(4)
High sink output low level current @ 5 V and VOL3
(1)(3)(4)
7.75
mA
IOH1
IOH2
IOHhs1
IOHhs2
84/98
Standard output high level current @ 3.3 V and VOH1
(1)(2)
Standard output high level current @ 5 V and VOLH2
1.5
(1)(2)
3
High sink output high level current @ 3.3 V and VOH3
5
((1)(3)(4)
High sink output high level current @ 5 V and VOH3
(1)(3)(4)
DocID024387 Rev 2
7.75
STLUX385A
Electrical characteristics
Table 48. Current DC characteristics
Symbol
ILKg
I_Inj
ΣI_Inj
Description
Min.
Typ.
Max.
Unit
(5)
±1
μA
Injection current (6)(7)
±4
Input leakage current digital - analog VSS ≤ VIN ≥ VDD
mA
Total injection current (sum of all I/O and control pins)
± 20
(6)
1. Parameter applicable to signals: GPIO0[5:0] (high sink selectable by high speed config.).
2. Parameter applicable to signals: GPIO1[5:0]/PWM[5:0].
3. Parameter applicable to signal: SWIM.
4. Parameter applicable to signal: DIGIN[0]/CCO_clk
5. Applicable to any digital inputs.
6. Maximum value must never be exceeded.
7. Negative injection current on the ADCIN[7:0] signals have to avoid since impact the ADC conversion
accuracy.
Table 49. Operating frequency characteristics
Symbol
Description
Min.
Typ.
Max.
fIL1
Digital input signal operating frequency (1)(2)(3)
12
fIH1
Analog input signal operating frequency (4)(5)
24
(6)(7)
fIH2
High speed input signal operating frequency
fOL1
Standard output signal operating frequency with 50 pF
max. load (1)
2
fOL2
High sink output signal operating frequency with
50 pF max. load (1)(2)
10
fOH1
High speed output signal operating frequency with
50 pF max. load (6)
12
fOH2
High speed output signal operating frequency with
50 pF max. load (7)
32
Unit
128
MHz
1. Parameter applicable to signals: GPIO0[5:0] (high sink selectable by high speed config.).
2. Parameter applicable to signal: SWIM.
3. Parameter applicable to signals: DIGIN[5:1].
4. Parameter applicable to signals: GPIO0[3:2] when configured as HSE_Oscin/Oscout
5. Parameter applicable to any analog signals: ADCIN[7:0], CPP[3:0] and CPM3.
6. Parameter applicable to signals: GPIO1[5:0]/PWM[5:0].
7. Parameter applicable to signal: DIGIN[0]/CCO_clk.
10.3.7
Typical output curves
The following figures show the typical output level curves measured with output on a single
pin.
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Electrical characteristics
10.3.8
STLUX385A
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 50. NRST pin characteristics
Symbol
Parameter
Conditions
Min.(1)
Typ.
Max.(1)
VIL(NRST)
NRST input low level voltage(1)
-0.3
0.3 x VDD
VIH(NRST)
NRST input high level voltage(1)
0.7 x
VDD
VDD + 0.3
VOL(NRST)
NRST output low level voltage(1)
RPU(NRST)
NRST pull-up resistor(2)
tIFP(NRST)
NRST input filtered pulse(3)
IOL= 2 mA
Unit
V
0.5
30
40
60
kΩ
75
ns
tINFP(NRST)
tOP(NRST)
NRST not input filtered
pulse(3)
500
NRST output filtered pulse(3)
15
μs
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design, not tested in production.
I2C interface characteristics
10.3.9
Table 51. I2C interface characteristics
Standard mode
Symbol
Fast mode(1)
Parameter
Unit
Min.(2)
Max.(2)
Min.(2)
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0(3)
0(3)
Max.(2)
μs
900(3)
tr(SDA) tr(SCL)
SDA and SCL rise time
(VDD = 3.3 to 5 V) (4)
1000
300
tf(SDA) tf(SCL)
SDA and SCL fall time
(VDD = 3.3 to 5 V) (4)
300
300
ns
th(STA)
START condition hold time
4.0
0.6
tsu(STA)
Repeated START condition setup
time
4.7
0.6
tsu(STO)
STOP condition setup time
4.0
0.6
μs
STOP to START condition time
(bus free)
4.7
1.3
μs
tw(STO:STA)
μs
Capacitive load for each bus line
Cb
50
(5)
1. fMASTER, must be at least 8 MHz to achieve maximum fast I2C speed (400 kHz).
86/98
DocID024387 Rev 2
50
pF
STLUX385A
Electrical characteristics
2. Data based on standard I2C protocol requirement, not tested in production.
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time.
4. I2C multifunction signals require the high sink pad configuration and the interconnection of 1 KΩ pull-up resistances.
5. 50 pF is the maximum load capacitance value to meet the I2C std timing specifications.
10.3.10
10-bit Sar ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise
specified.
Table 52. ADC characteristics
Symbol
N
Parameter
Conditions
Min.
Resolution
Typ.
Max.
10
bit
RADCIN
ADC input impedance
1
fADC
ADC Clock frequency
1
6(1)
VIN1
Conversion voltage
range for gain x1
0
1.25(2)(3)
VIN2
Conversion voltage
range for gain x4
0
0.3125(2)(3)
Vref
ADC main reference
voltage(4)
tS
MΩ
1.250
Sampling time
fADC = 6 MHz
Unit
MHz
V
0.50
tSTAB
Wakeup time from ADC
standby
tCONV1
Single conversion time
including sampling time
fADC = 6 MHz
2.42
tCONV2
Continuous conversion
time including sampling
time
fADC = 6 MHz
3
30
μs
1. Frequency generated selecting the PLL source clock.
2. Maximum input analog voltage cannot exceed VDDA.
3. Exceeding the maximum voltage on the ADCIN[7:0] signals for the related conversion scale must be
avoided since the ADC conversion accuracy can be impacted.
4. Exceeding the maximum voltage on the ADCIN[7:0] signals for the related conversion scale must be
avoided since the ADC conversion accuracy can be impacted.
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Electrical characteristics
STLUX385A
ADC accuracy characteristics at VDD/VDDA 3.3 V
Table 53. ADC accuracy characteristics at VDD/VDDA 3.3 V
Symbol
Parameter
Conditions(1)
Typ.(2) Min.(3) Max.(3)
|ET|
Total unadjusted error(4)(5)(6)
2.8
|EO|
(4)(5)(6)
0.3
Offset error
error(4)(5)(6)(7)
|EG|
Gain
EO+G
Offset + gain error(7)(8)
EO+G
Offset + gain
error(7)(9)
Offset + gain
error(7)(10)
EO+G
Unit
0.4
fADC = 6 MHz
gain 1
-8.5
9.3
-11
11
-14.3
11.3
error(2,3,4)
|ED|
Differential linearity
|EL|
Integral linearity error(4)(5)(6)
0.5
1.4
error((4)(5)(6)
|ET|
Total unadjusted
|EO|
Offset error(4)(5)(6)
0.3
|EG|
Gain error(4)(5)(6)(7)
0.4
EO+G
Offset + gain error(7)(8)
EO+G
Offset + gain error(5)(9)
EO+G
Offset + gain error(7)(10)
LSB
2.8
fADC = 6 MHz
gain 4
-12.7
15.5
-16.7
18.8
-19.2
18.8
|ED|
Differential linearity error(4)(5)(6)
0.5
|EL|
Integral linearity error(4)(5)(6)
1.4
1. Measured with RAIN<10 kΩ (RAIN external series resistance interconnected between the AC signal
generator and the ADC input pin).
2. Temperature operating: TA= 25 °C.
3. Data based on characterization results, not tested in production.
4. ADC accuracy vs. negative injection current. Injecting negative current on any of the analog input pins
should be avoided as this reduces the accuracy of the conversion being performed on another analog
input. It is recommended a Schottky diode (pin to ground) to be added to standard analog pins which may
potentially inject the negative current. Any positive injection current within the limits specified for IINJ(PIN)
and ΣIINJ(PIN) in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy
parameters may be also impacted exceeding the ADC maximum input voltage VIN1 or VIN2.
5. Results in manufacturing test mode.
6. Data aligned with trimming voltage parameters.
7. Gain error evaluation with two point method.
8. Temperature operating range: 0 ºC ≤ TA ≤ 85 ºC.
9. Temperature operating range: -25 ºC ≤ TA ≤ 105 ºC.
10. Temperature operating range: -40 ºC ≤ TA ≤ 105 ºC.
88/98
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STLUX385A
Electrical characteristics
ADC accuracy characteristics at VDD/VDDA 5 V
Table 54. ADC accuracy characteristics at VDD/VDDA 5 V
Symbol
Conditions(1)
Parameter
|ET|
Total unadjusted error(4)(5)(6)
|EO|
Offset error(4)(5)(6)
|EG|
Gain error
0.5
0.4
error(7)(8)
Offset + gain
EO+G
Offset + gain error(7)(9)
|ED|
Offset + gain error
Unit
TBD
(4)(5)(6)(7)
EO+G
EO+G
Typ.(2) Min.(3) Max.(3)
fADC = 6 MHz
gain 1
(7)(10)
Differential linearity error
(2,3,4)
-8.3
8.9
-10.9
10.9
-13.8
10.9
0.8
error(4)(5)(6)
|EL|
Integral linearity
|ET|
Total unadjusted error((4)(5)(6)
|EO|
Offset error(4)(5)(6)
1.2
|EG|
Gain error(4)(5)(6)(7)
0.2
EO+G
Offset + gain error(7)(8)
EO+G
Offset + gain error(5)(9)
EO+G
Offset + gain error(7)(10)
|ED|
Differential linearity error(4)(5)(6)
0.8
|EL|
Integral linearity error(4)(5)(6)
2.0
2.0
LSB
TBD
fADC = 6 MHz
gain 4
-12.2
15.3
-16.4
18.5
-18.8
18.5
1. Measured with RAIN<10 kΩ (RAIN external series resistance interconnected between the AC signal
generator and the ADC input pin).
2. Temperature operating: TA= 25 °C.
3. Data based on characterization results, not tested in production.
4. ADC accuracy vs. negative injection current. Injecting negative current on any of the analog input pins
should be avoided as this reduces the accuracy of the conversion being performed on another analog
input. It is recommended a Schottky diode (pin to ground) to be to added to standard analog pins which
may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN)
and ΣIINJ(PIN) in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy
parameters may be also impacted exceeding the ADC maximum input voltage VIN1 or VIN2.
5. Results in manufacturing test mode.
6. Data aligned with trimming voltage parameters.
7. Gain error evaluation with two point method.
8. Temperature operating range: 0 ºC ≤ TA ≤ 85 ºC.
9. Temperature operating range: -25 ºC ≤ TA ≤ 105 ºC.
10. Temperature operating range: -40 ºC ≤ TA ≤ 105 ºC.
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Electrical characteristics
10.3.11
STLUX385A
Analog comparator characteristics
Table 55. Analog comparator characteristics
Symbol
Parameter
Conditions
Min.(1)
Typ.
Max.(1)
Unit
Comparator input voltage
range
0
1.23(2)
V
VICPM3
Comparator 3 external input
voltage range
-40 ºC ≤ TA ≤ 105 ºC
0
1.23(2)(3)
V
Voffset
Comparator offset error
15
mV
tCOMP
Comparison delay time
50
ns
VIN
1. Data based on characterization results, not tested in production.
2. Maximum analog input voltage cannot exceed VDDA.
3. The comparator 3 can be configured with the external reference voltage signal CPM3.
10.3.12
DAC characteristics
Table 56. DAC characteristics
Symbol
Parameter
Conditions
Vfull scale DAC full scale
Voffset
Vdac
Min.(1)
Typ.
1.2
DAC offset
-40 ºC ≤ TA ≤ 105 ºC Voffset
DAC out voltage
LSB
INL
Unit
1.26
V
4
mV
Vfull scale
mV
82
Integral non linearity
mV
0.12
1. Data based on characterization results, not tested in production.
( V fullscale – V offset )
n[0,15]:Vdac(n) = ---------------------------------------------------- × ( n ) + Voffset
15
( V fullscale – V offset )
n[1-14]:Vdac(n) = ---------------------------------------------------- × ( n + INL ) + V offset
15
where:
90/98
Max.(1)
•
Vfullscale = Vfullscale(sample, T)
•
Voffset = Voffset(sample, T)
•
INL = INL(sample, n)
DocID024387 Rev 2
LSB
STLUX385A
Electrical characteristics
10.4
EMC characteristics
10.4.1
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin).
Table 57. ESD absolute maximum ratings
10.4.2
Symbol
Ratings
Conditions
Maximum
value
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = 25 °C, conforming to
JEDEC/JESD22-A114E
2000
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA = 25 °C, conforming to
ANSI/ESD STM 5.3.1 ESDA
500
VESD(MM)
Electrostatic discharge
voltage (machine model)
TA = 25 °C, conforming to
JEDEC/JESD-A115-A
200
Unit
V
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
A supply overvoltage (applied to each power supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are performed on each sample. This test
conforms to the EIA/JESD 78 IC latch-up standard.
Table 58. Electrical sensitivity
Symbol
LU
Parameter
Static latch-up class
DocID024387 Rev 2
Conditions
Level
TA = 105 °C
A
91/98
Thermal characteristics
11
STLUX385A
Thermal characteristics
The STLUX385A functionality cannot be guaranteed when the device is operating under the
maximum chip junction temperature (TJmax).
TJmax, in degrees Celsius, may be calculated using the following equation:
TJmax = TAmax + ( PDmax × Θ JA )
Where:
TAmax is the maximum ambient temperature in °C
ΘJA is the package junction-to-ambient thermal resistance in °C/W
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
PINTmax is the product of IDD and VDD, expressed in watts. This is the maximum chip internal
power.
PI/Omax represents the maximum power dissipation on output pins where: PI/Omax = Σ
(VOL*IOL) + Σ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH of the
I/Os at low and high level.
Table 59. Package thermal characteristics
Symbol
ΘJA
Parameter
Thermal resistance junction-to-ambient(1)
Value
Unit
80
°C/W
1. Thermal resistance are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.
92/98
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STLUX385A
12
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 60. TSSOP38 mechanical data
mm
Dim.
Min.
Typ.
A
Max.
1.20
A1
0.05
A2
0.80
b
0.17
0.27
c
0.09
0.20
D
9.60
9.70
9.80
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
e
L
1.00
1.05
0.50
0.45
L1
k
0.15
0.60
0.75
1.00
0
aaa
8
0.10
DocID024387 Rev 2
93/98
Package mechanical data
STLUX385A
Figure 19. TSSOP8 package drawing
0117861_C
94/98
DocID024387 Rev 2
STLUX385A
13
STLUX385A development tools
STLUX385A development tools
The development tool for the STLUX385A microcontroller is provided by Raisonance with
the C compiler and the integrated development environment (ride7), which provides start-tofinish control of application development including code editing, compilation, optimization
and debugging.
The hardware tool includes the RLink in-circuit debugger/programmer (USB/JTAG).
DocID024387 Rev 2
95/98
Order codes
14
STLUX385A
Order codes
Table 61. Ordering information
Order code
Package
STLUX385A
Packaging
Tube
TSSOP38
STLUX385ATR
96/98
Tape and reel
DocID024387 Rev 2
STLUX385A
15
Revision history
Revision history
Table 62. Document revision history
Date
Revision
Changes
04-Apr-2013
1
Initial release.
06-Jun-2013
2
Document status promoted from preliminary to production data.
DocID024387 Rev 2
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STLUX385A
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