STMICROELECTRONICS CD00253742

STM32F103xF
STM32F103xG
XL-density performance line ARM-based 32-bit MCU with 768 KB to
1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces
Target specification
Features
FBGA
■
Core: ARM 32-bit Cortex™-M3 CPU with MPU
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
■
Memories
– 768 Kbytes to 1 Mbyte of Flash memory
– 96 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
■
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
■
Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
■
3 × 12-bit, 1 µs A/D converters (up to 21
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
2 × 12-bit D/A converters
■
DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
SDIO, I2Ss, SPIs, I2Cs and USARTs
■
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
LFBGA144 10 × 10 mm
■
Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
■
Up to 17 timers
– Up to ten 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 × 16-bit motor control PWM timers with
dead-time generation and emergency stop
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
■
Up to 13 communication interfaces
– Up to 2 × I2C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I2S
interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
■
CRC calculation unit, 96-bit unique ID
■
ECOPACK® packages
Table 1.
Device summary
Reference
■
January 2012
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
Part number
STM32F103xF
STM32F103RF STM32F103VF
STM32F103ZF
STM32F103xG
STM32F103RG STM32F103VG
STM32F103ZG
Doc ID 16554 Rev 3
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/120
www.st.com
1
Contents
STM32F103xF, STM32F103xG
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2/120
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1
ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15
2.3.2
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.4
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
2.3.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.6
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
2.3.9
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.11
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19
2.3.18
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.19
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.20
Universal synchronous/asynchronous receiver transmitters (USARTs) 21
2.3.21
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.22
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.23
SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.24
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.25
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.26
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.27
ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.28
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Contents
2.3.29
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.30
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.31
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 42
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 42
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.10
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.12
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 82
5.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.16
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.18
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 100
Doc ID 16554 Rev 3
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Contents
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STM32F103xF, STM32F103xG
5.3.19
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.3.20
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.21
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 115
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F103xF and STM32F103xG features and peripheral counts . . . . . . . . . . . . . . . . . 11
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F103xF and STM32F103xG timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19
STM32F103xF and STM32F103xG pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 46
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 47
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 63
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 64
Asynchronous read muxed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 71
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Switching characteristics for PC Card/CF read and write cycles in
attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . 78
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Doc ID 16554 Rev 3
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List of tables
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
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STM32F103xF, STM32F103xG
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111
LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 113
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
STM32F103xF and STM32F103xG ordering information scheme . . . . . . . . . . . . . . . . . . 117
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
STM32F103xF and STM32F103xG performance line block diagram. . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F103xF and STM32F103xG XL-density performance line BGA144 ballout . . . . . . 25
STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout. . . . . . 26
STM32F103xF and STM32F103xG XL-density performance line LQFP100 pinout. . . . . . 27
STM32F103xF and STM32F103xG XL-density performance line
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 45
Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 45
Typical current consumption on VBAT with RTC on vs. temperature at different VBAT
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical current consumption in Stop mode with regulator in run mode
versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typical current consumption in Standby mode versus temperature at
different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 62
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 63
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 65
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 66
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 71
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 73
PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 74
PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 76
PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 77
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 79
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 80
Doc ID 16554 Rev 3
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List of figures
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
8/120
STM32F103xF, STM32F103xG
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 104
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 105
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Recommended PCB design rules (0.80/0.75 mm pitch BGA . . . . . . . . . . . . . . . . . . . . . . 109
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 112
Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 113
Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103xF and STM32F103xG XL-density performance line microcontrollers. For
more details on the whole STMicroelectronics STM32F103xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The XL-density STM32F103xx datasheet should be read in conjunction with the
STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
Doc ID 16554 Rev 3
9/120
Description
2
STM32F103xF, STM32F103xG
Description
The STM32F103xF and STM32F103xG performance line family incorporates the highperformance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM up to 96 Kbytes), and
an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer three 12-bit ADCs, ten general-purpose 16-bit timers plus two PWM timers, as
well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two
I2Ss, one SDIO, five USARTs, an USB and a CAN.
The STM32F103xx XL-density performance line family operates in the –40 to +105 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
These features make the STM32F103xx high-density performance line microcontroller
family suitable for a wide range of applications such as motor drives, application control,
medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems and video intercom.
10/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
2.1
Description
Device overview
The STM32F103xx XL-density performance line family offers devices in four different
package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
Figure 1 shows the general block diagram of the device family.
Table 2.
STM32F103xF and STM32F103xG features and peripheral counts
Peripherals
Flash memory
SRAM in Kbytes
FSMC
Timers
STM32F103Rx
768 KB
1 MB
96
No
STM32F103Vx
768 KB
1 MB
96
(1)
Yes
General-purpose
10
Advanced-control
2
Basic
2
SPI(I2S)(2)
STM32F103Zx
768 KB
1 MB
96
Yes
3(2)
2C
I
2
USART
5
USB
1
CAN
1
SDIO
1
Comm
GPIOs
51
80
112
12-bit ADC
Number of channels
3
16
3
16
3
21
12-bit DAC
Number of channels
2
2
CPU frequency
72 MHz
Operating voltage
Operating temperatures
Package
2.0 to 3.6 V
Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10)
Junction temperature: –40 to + 125 °C (see Table 10)
LQFP64
LQFP100
LQFP144, BGA144
1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a
multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND
Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available
in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the
I2S audio mode.
Doc ID 16554 Rev 3
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Description
TRACECLK
TRACED[0:3]
as AF
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDAT
JTDO
as AF
TPIU
SWJTAG
Flash obl
interface
STM32F103xF and STM32F103xG performance line block diagram
ETM
Trace/Trig
Ib u s
Cortex-M3 CPU
Fmax: 48/72 MHz
NVIC
Dbus
64 bit
Bus matrix
GP DMA1
64 bit
@VDDA
RC HS
SRAM
96 Kbyte
RC LS
IWDG
GP DMA2
5 channels
Reset &
clock
controller
PCLK1
PCLK2
PCLK3
HCLK
FCLK
SDIO
XTAL 32 kHz
RTC
AWU
GPIO port D
PE[15:0]
GPIO port E
PF[15:0]
GPIO port F
8 ADINs common
to the 3 ADCs
8 ADINs common
to the ADC1 & 2
5 ADINs on ADC3
VREF–
VREF+
APB2
APB1
GPIO port A
PD[15:0]
MOSI,MISO,
SCK,NSS as AF
RX,TX, CTS, RTS,
CK as AF
APB3
EXT.IT
WKUP
GPIO port B
1 channel as AF
V BAT=1.8V to 3.6V
Backup
reg
OSC32_IN
OSC32_OUT
TAMPER-RTC
(ALARM OUT)
Backup interface
GPIO port C
1 channel as AF
OSC_IN
OSC_OUT
@VSW
FSMC
PC[15:0]
2 channels as AF
NRST
VDDA
VSSA
PVD
@VDDA
@VDD
Standby
interface
PB[15:0]
PG[15:0]
4 channels
4 compl. channels
BKIN, ETR input as AF
4 channels
4 compl. channels
BKIN, ETR input as AF
POR
SUPPLY
Reset SUPERVISION
Int
POR / PDR
XTAL OSC
4-16 MHz
APB1 : Fmax=24 / 36 MHz
PA[15:0]
VDD =2 t o 3.6V
VSS
@VDD
7 channels
GPIO port G
APB2 : Fmax=48 / 72 MHz
112 AF
VOLT. REG.
3.3V TO 1.8V
PLL
AHB2
D[7:0], CMD
CK as AF
POWER
VDD
Flash2 512 KB
System
NVIC
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[3:0]
NBL[1:0]
NWAIT
NL
as AF
Flash1 512 KB
MPU
Flash obl
interface
Figure 1.
STM32F103xF, STM32F103xG
TIM2
4 Ch, ETR as AF
TIM3
4 Ch, ETR as AF
TIM4
4 Ch, ETR as AF
TIM5
4 Ch, ETR as AF
TIM12
2 channels as AF
TIM13
1 channel as AF
TIM14
1 channel as AF
USART2
USART3
UART4
TIM1
UART5
TIM8
SPI2/I2S2
TIM9
SPI3/I2S3
TIM10
TIM11
SPI1
WWDG
RX,TX, CTS, RTS,
CK as AF
RX,TX, CTS, RTS,
CK as AF
RX,TX as AF
RX,TX as AF
MOSI/SD,MISO,
SCK/CK,NSS/WS,
MCLK as AF
MOSI/SD,MISO,
SCK/CK,NSS/WS,
MCLK as AF
I2C1
SCL,SDA,SMBA
as AF
I2C2
SCL,SDA,SMBA
as AF
USART1
Temp sensor
SRAM 512B
bxCAN device
USB 2.0 FS device
USBDP/CAN_TX
USBDM/CAN_RX
12bit ADC1 IF
12bit ADC2 IF
TIM6
IF 12bit DAC1
IF
DAC1_OUT as AF
12bit ADC3 IF
TIM7
12bit DAC2
DAC2_OUT as AF
@VDDA
@VDDA
ai17352
1. TA = –40 °C to +85 °C (suffix 6, see Table 73) or –40 °C to +105 °C (suffix 7, see Table 73), junction temperature up to
105 °C or 125 °C, respectively.
2. AF = alternate function on I/O port pin.
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Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Figure 2.
Description
Clock tree
FLITFCLK
to Flash programming interface
USB
Prescaler
/1, 1.5
USBCLK
to USB interface
48 MHz
I2S3CLK
Peripheral clock
enable
8 MHz
HSI RC
I2S2CLK
to I2S2
Peripheral clock
enable
Peripheral clock
enable
HSI
SDIOCLK
FSMCCLK
Peripheral clock
enable
72 MHz max
/2
PLLSRC
to I2S3
/8
SW
PLLMUL
HSI
..., x16
x2, x3, x4
PLL
SYSCLK
72 MHz
max
PLLCLK
AHB
Prescaler
/1, 2..512
HSE
to Cortex System timer
FCLK Cortex
free running clock
36 MHz max
PCLK1
to APB1
peripherals
Peripheral Clock
Enable
to TIM2/3/4/5/12/13/14
and TIM6/7
TIMxCLK
TIM2,3,4,5,12,13,14,6,7
If (APB1 prescaler =1) x1
else x2
CSS
to FSMC
HCLK
to AHB bus, core,
memory and DMA
Clock
Enable
APB1
Prescaler
/1, 2, 4, 8, 16
to SDIO
Peripheral Clock
Enable
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
OSC_OUT
OSC_IN
4-16 MHz
HSE OSC
/2
OSC32_OUT
LSE OSC
32.768 kHz
to RTC
LSE
RTCCLK
to Independent Watchdog (IWDG)
LSI
ADC
Prescaler
/2, 4, 6, 8
/2
RTCSEL[1:0]
LSI RC
40 kHz
peripherals to APB2
Peripheral Clock
Enable
to TIM1/8
and TIM9/10/11
TIMxCLK
TIM1, 8, 9, 10, 11
If (APB2 prescaler =1) x1
else x2
/128
OSC32_IN
PCLK2
72 MHz max
Peripheral Clock
Enable
to ADC1, 2 or 3
ADCCLK
HCLK/2
To SDIO AHB interface
Peripheral clock
enable
IWDGCLK
Main
Clock Output
/2
MCO
PLLCLK
Legend:
HSE = High-speed external clock signal
HSI
HSI = High-speed internal clock signal
HSE
LSI = Low-speed internal clock signal
SYSCLK
LSE = Low-speed external clock signal
MCO
ai17354
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
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Description
2.2
STM32F103xF, STM32F103xG
Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are
identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as
medium-density devices, the STM32F103xC, STM32F103xD and STM32F103xE are
referred to as high-density devices and the STM32F103xF and STM32F103xG are called
XL-density devices.
Low-density, high-density and XL-density devices are an extension of the STM32F103x8/B
medium-density devices, they are specified in the STM32F103x4/6, STM32F103xC/D/E and
STM32F103xF/G datasheets, respectively. Low-density devices feature lower Flash
memory and RAM capacities, less timers and peripherals. High-density devices have higher
Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and
DAC. XL-density devices bring even more Flash and RAM memory, and extra features,
namely an MPU, a greater number of timers and a dual bank Flash structure while
remaining fully compatible with the other members of the family.
The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD, STM32F103xE,
STM32F103xF and STM32F103xG are a drop-in replacement for the STM32F103x8/B
devices, allowing the user to try different memory densities and providing a greater degree
of freedom during the development cycle.
Moreover, the STM32F103xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3.
STM32F103xx family
Low-density
devices
Pinout
Medium-density
devices
16 KB
Flash
32 KB
Flash(1)
64 KB
Flash
128 KB
Flash
256 KB
Flash
384 KB 512 KB
Flash
Flash
6 KB
RAM
10 KB
RAM
20 KB
RAM
20 KB
RAM
48 or
64 KB(2)
RAM
64 KB
RAM
144
100
64
48
High-density devices
2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I2C,
USB, CAN,
1 × PWM timer
2 × ADCs
3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs,
USB, CAN,
1 × PWM timer
2 × ADCs
64 KB
RAM
5 × USARTs
4 × 16-bit timers,
2 × basic timers
3 × SPIs, 2 × I2Ss, 2 × I2Cs
USB, CAN, 2 × PWM timers
3 × ADCs, 2 × DACs,
1 × SDIO
FSMC (100- and 144-pin
packages(3))
XL-density devices
768 KB Flash
1 MB Flash
96 KB RAM
96 KB RAM
5 × USARTs
10 × 16-bit timers,
2 × basic timers
3 × SPIs, 2 × I2Ss, 2 × I2Cs
USB, CAN, 2 × PWM timers
3 × ADCs, 2 × DACs, 1 × SDIO,
Cortex-M3 with MPU
FSMC (100- and 144-pin
packages(4)), dual bank Flash
memory
36
1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference
datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices.
2. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.
3. Ports F and G are not available in devices delivered in 100-pin packages.
4. Ports F and G are not available in devices delivered in 100-pin packages.
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STM32F103xF, STM32F103xG
Description
2.3
Overview
2.3.1
ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
With its embedded ARM core, STM32F103xF and STM32F103xG performance line family
is compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
2.3.2
Memory protection unit
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
2.3.3
Embedded Flash memory
768 Kbytes to 1 Mbyte of embedded Flash are available for storing programs and data. The
Flash memory is organized as two banks. The first bank has a size of 512 Kbytes. The
second bank is either 256 or 512 Kbytes depending on the device. This gives the device the
capability of writing to one bank while executing code from the other bank (read-while-write
capability).
2.3.4
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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Description
2.3.5
STM32F103xF, STM32F103xG
Embedded SRAM
96 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
2.3.6
FSMC (flexible static memory controller)
The FSMC is embedded in the STM32F103xF and STM32F103xG performance line family.
It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash,
SRAM, PSRAM, NOR and NAND.
Functionality overview:
2.3.7
●
The three FSMC interrupt lines are ORed in order to be connected to the NVIC
●
Write FIFO
●
Code execution from external memory except for NAND Flash and PC Card
●
The targeted frequency, fCLK, is HCLK/2, so external access is at 36 MHz when HCLK
is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.
2.3.8
Nested vectored interrupt controller (NVIC)
The STM32F103xF and STM32F103xG performance line embeds a nested vectored
interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16
interrupt lines of Cortex™-M3) and 16 priority levels.
●
Closely coupled NVIC gives low latency interrupt processing
●
Interrupt entry vector table address passed directly to the core
●
Closely coupled NVIC core interface
●
Allows early processing of interrupts
●
Processing of late arriving higher priority interrupts
●
Support for tail-chaining
●
Processor state automatically saved
●
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.9
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
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STM32F103xF, STM32F103xG
2.3.10
Description
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed
APB domain is 36 MHz. See Figure 2 for details on the clock tree.
2.3.11
Boot modes
At startup, boot pins are used to select one of three boot options:
●
Boot from user Flash: you have an option to boot from any of two memory banks. By
default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash
memory bank 2 by setting a bit in the option bytes.
●
Boot from system memory
●
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1.
2.3.12
Power supply schemes
●
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●
VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC
is used). VDDA and VSSA must be connected to VDD and VSS, respectively.
●
VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.
2.3.13
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
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Description
2.3.14
STM32F103xF, STM32F103xG
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
MR is used in the nominal regulation mode (Run)
●
LPR is used in the Stop modes.
●
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
2.3.15
Low-power modes
The STM32F103xF and STM32F103xG performance line supports three low-power modes
to achieve the best compromise between low power consumption, short startup time and
available wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.3.16
DMA
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management,
removing the need for user code intervention when the controller reaches the end of the
buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
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STM32F103xF, STM32F103xG
Description
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic
and advanced-control timers TIMx, DAC, I2S, SDIO and ADC.
2.3.17
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit
registers used to store 84 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.18
Timers and watchdogs
The XL-density STM32F103xx performance line devices include up to two advanced-control
timers, up to ten general-purpose timers, two basic timers, two watchdog timers and a
SysTick timer.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4.
STM32F103xF and STM32F103xG timer feature comparison
Timer
Counter Counter
resolution
type
Prescaler factor
DMA request Capture/compare Complementary
generation
channels
outputs
TIM1, TIM8
16-bit
Up,
Any integer between
down,
1 and 65536
up/down
Yes
4
Yes
TIM2, TIM3,
TIM4, TIM5
16-bit
Up,
Any integer between
down,
1 and 65536
up/down
Yes
4
No
TIM9, TIM12
16-bit
Up
Any integer between
1 and 65536
No
2
No
TIM10, TIM11
TIM13, TIM14
16-bit
Up
Any integer between
1 and 65536
No
1
No
TIM6, TIM7
16-bit
Up
Any integer between
1 and 65536
Yes
0
No
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Description
STM32F103xF, STM32F103xG
Advanced-control timers (TIM1 and TIM8)
The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase
PWM multiplexed on 6 channels. They have complementary PWM outputs with
programmable inserted dead-times. They can also be seen as a complete general-purpose
timer. The 4 independent channels can be used for:
●
Input capture
●
Output compare
●
PWM generation (edge or center-aligned modes)
●
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switch driven by these outputs.
Many features are shared with those of the general-purpose TIM timers which have the
same architecture. The advanced-control timer can therefore work together with the TIM
timers via the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)
There are10 synchronizable general-purpose timers embedded in the STM32F103xF and
STM32F103xG performance line devices (see Table 4 for differences).
●
TIM2, TIM3, TIM4, TIM5
There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)
embedded in the STM32F103xF and STM32F103xG access line devices.
These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler
and feature 4 independent channels each for input capture/output compare, PWM or
one-pulse mode output. This gives up to 16 input captures / output compares / PWMs
on the largest packages.
Their counter can be frozen in debug mode. Any of the general-purpose timers can be
used to generate PWM outputs. They all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
●
TIM10, TIM11 and TIM9
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10 and TIM11 feature one independent channel, whereas TIM9 has two
independent channels for input capture/output compare, PWM or one-pulse mode
output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured
general-purpose timers. They can also be used as simple time bases.
●
TIM13, TIM14 and TIM12
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13 and TIM14 feature one independent channel, whereas TIM12 has two
independent channels for input capture/output compare, PWM or one-pulse mode
output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured
general-purpose timers. They can also be used as simple time bases.
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STM32F103xF, STM32F103xG
Description
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
2.3.19
●
A 24-bit down counter
●
Autoreload capability
●
Maskable system interrupt generation when the counter reaches 0.
●
Programmable clock source
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
2.3.20
Universal synchronous/asynchronous receiver transmitters (USARTs)
The STM32F103xF and STM32F103xG performance line embeds three universal
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and
two universal asynchronous receiver transmitters (UART4 and UART5).
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other
available interfaces communicate at up to 2.25 Mbit/s.
USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.
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Description
2.3.21
STM32F103xF, STM32F103xG
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
All SPIs can be served by the DMA controller.
2.3.22
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be
operated in master or slave mode. These interfaces can be configured to operate with 16/32
bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to
48 kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
2.3.23
SDIO
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD
Memory Card Specifications Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital
protocol Rev1.1.
2.3.24
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
2.3.25
Universal serial bus (USB)
The STM32F103xF and STM32F103xG performance line embed a USB device peripheral
compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12
Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume
support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock
source must use a HSE crystal oscillator).
2.3.26
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.
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Description
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.3.27
ADC (analog to digital converter)
Three 12-bit analog-to-digital converters are embedded into STM32F103xF and
STM32F103xG performance line devices and each ADC shares up to 21 external channels,
performing conversions in single-shot or scan modes. In scan mode, automatic conversion
is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
●
Simultaneous sample and hold
●
Interleaved sample and hold
●
Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control
timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection
trigger, respectively, to allow the application to synchronize A/D conversion and timers.
2.3.28
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.
This dual digital Interface supports the following features:
●
two DAC converters: one for each output channel
●
8-bit or 12-bit monotonic output
●
left or right data alignment in 12-bit mode
●
synchronized update capability
●
noise-wave generation
●
triangular-wave generation
●
dual DAC channel independent or simultaneous conversions
●
DMA capability for each channel
●
external triggers for conversion
●
input voltage reference VREF+
Eight DAC trigger inputs are used in the STM32F103xF and STM32F103xG performance
line family. The DAC channels are triggered through the timer update outputs that are also
connected to different DMA channels.
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Description
2.3.29
STM32F103xF, STM32F103xG
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.3.30
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
2.3.31
Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F10xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.
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STM32F103xF, STM32F103xG
Pinouts and pin descriptions
3
Pinouts and pin descriptions
Figure 3.
STM32F103xF and STM32F103xG XL-density performance line BGA144 ballout
1
2
3
4
5
6
7
8
9
10
11
12
A
PC13TAMPER-RTC
PE3
PE2
PE1
PE0
PB4
JTRST
PB3
JTDO
PD6
PD7
PA15
JTDI
PA14
JTCK
PA13
JTMS
B
PC14OSC32_IN
PE4
PE5
PE6
PB9
PB5
PG15
PG12
PD5
PC11
PC10
PA12
C
PC15OSC32_OUT
VBAT
PF0
PF1
PB8
PB6
PG14
PG11
PD4
PC12
NC
PA11
D
OSC_IN
VSS_5
VDD_5
PF2
BOOT0
PB7
PG13
PG10
PD3
PD1
PA10
PA9
E
OSC_OUT
PF3
PF4
PF5
VSS_3
VSS_11
VSS_10
PG9
PD2
PD0
PC9
PA8
F
NRST
PF7
PF6
VDD_4
VDD_3
VDD_11
VDD_10
VDD_8
VDD_2
VDD_9
PC8
PC7
G
PF10
PF9
PF8
VSS_4
VDD_6
VDD_7
VDD_1
VSS_8
VSS_2
VSS_9
PG8
PC6
H
PC0
PC1
PC2
PC3
VSS_6
VSS_7
VSS_1
PE11
PD11
PG7
PG6
PG5
J
VSSA
PA0-WKUP
PA4
PC4
PB2/
BOOT1
PG1
PE10
PE12
PD10
PG4
PG3
PG2
K
VREF–
PA1
PA5
PC5
PF13
PG0
PE9
PE13
PD9
PD13
PD14
PD15
L
VREF+
PA2
PA6
PB0
PF12
PF15
PE8
PE14
PD8
PD12
PB14
PB15
M
VDDA
PA3
PA7
PB1
PF11
PF14
PE7
PE15
PB10
PB11
PB12
PB13
AI14798b
Doc ID 16554 Rev 3
25/120
Pinouts and pin descriptions
STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD_11
VSS_11
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD_10
VSS_10
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 4.
STM32F103xF, STM32F103xG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD_2
VSS_2
NC
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD_9
VSS_9
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD_8
VSS_8
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VSS_6
VDD_6
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS_5
VDD_5
PF6
PF7
PF8
PF9
PF10
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP
PA1
PA2
ai14667
26/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
STM32F103xF and STM32F103xG XL-density performance line LQFP100
pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 5.
Pinouts and pin descriptions
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP
PA1
PA2
ai14391
Doc ID 16554 Rev 3
27/120
Pinouts and pin descriptions
STM32F103xF and STM32F103xG XL-density performance line
LQFP64 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
Figure 6.
STM32F103xF, STM32F103xG
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
ai14392
28/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Table 5.
Pinouts and pin descriptions
STM32F103xF and STM32F103xG pin definitions
LQFP64
LQFP100
LQFP144
Type(1)
I / O level(2)
Alternate functions(4)
LFBGA144
Pins
Main
function(3)
(after reset)
A3
-
1
1
PE2
I/O
FT
PE2
TRACECK / FSMC_A23
A2
-
2
2
PE3
I/O
FT
PE3
TRACED0 / FSMC_A19
B2
-
3
3
PE4
I/O
FT
PE4
TRACED1/ FSMC_A20
B3
-
4
4
PE5
I/O
FT
PE5
TRACED2/ FSMC_A21
TIM9_CH1
B4
-
5
5
PE6
I/O
FT
PE6
TRACED3 / FSMC_A22
TIM9_CH2
C2
1
6
6
VBAT
S
VBAT
A1
2
7
7
PC13-TAMPERRTC(5)
I/O
PC13(6)
TAMPER-RTC
B1
3
8
8 PC14-OSC32_IN(5) I/O
PC14(6)
OSC32_IN
C1
4
9
9
PC15OSC32_OUT(5)
PC15(6)
OSC32_OUT
C3
-
-
10
PF0
I/O FT
PF0
FSMC_A0
C4
-
-
11
PF1
I/O FT
PF1
FSMC_A1
D4
-
-
12
PF2
I/O FT
PF2
FSMC_A2
E2
-
-
13
PF3
I/O FT
PF3
FSMC_A3
E3
-
-
14
PF4
I/O FT
PF4
FSMC_A4
E4
-
-
15
PF5
I/O FT
PF5
FSMC_A5
D2
-
10 16
VSS_5
S
VSS_5
D3
-
11 17
VDD_5
S
VDD_5
F3
-
-
18
PF6
I/O
PF6
ADC3_IN4 / FSMC_NIORD
TIM10_CH1
F2
-
-
19
PF7
I/O
PF7
ADC3_IN5 / FSMC_NREG
TIM11_CH1
G3
-
-
20
PF8
I/O
PF8
ADC3_IN6 / FSMC_NIOWR
TIM13_CH1
G2
-
-
21
PF9
I/O
PF9
ADC3_IN7 / FSMC_CD
TIM14_CH1
G1
-
-
22
PF10
I/O
PF10
ADC3_IN8 / FSMC_INTR
D1
5
12 23
OSC_IN
I
OSC_IN
PD0(7)
E1
6
13 24
OSC_OUT
O
OSC_OUT
PD1(7)
F1
7
14 25
NRST
I/O
NRST
H1
8
15 26
PC0
I/O
PC0
ADC123_IN10
H2
9
16 27
PC1
I/O
PC1
ADC123_IN11
H3 10 17 28
PC2
I/O
PC2
ADC123_IN12
H4 11 18 29
PC3
I/O
PC3
ADC123_IN13
J1
VSSA
S
VSSA
VREF-
S
VREF-
K1
12 19 30
-
20 31
Pin name
I/O
Doc ID 16554 Rev 3
Default
Remap
29/120
Pinouts and pin descriptions
STM32F103xF and STM32F103xG pin definitions (continued)
LQFP100
-
21 32
Pin name
Type(1)
LQFP64
L1
LQFP144
LFBGA144
Pins
I / O level(2)
Table 5.
STM32F103xF, STM32F103xG
Alternate functions(4)
Main
function(3)
(after reset)
VREF+
S
VREF+
M1 13 22 33
VDDA
S
VDDA
Default
PA0-WKUP
I/O
PA0
WKUP/USART2_CTS(8) /
ADC123_IN0 / TIM2_CH1_ETR /
TIM5_CH1 / TIM8_ETR
K2 15 24 35
PA1
I/O
PA1
USART2_RTS(7) / ADC123_IN1 /
TIM5_CH2 / TIM2_CH2(7)
L2 16 25 36
PA2
I/O
PA2
USART2_TX(7) / TIM5_CH3 /
ADC123_IN2 / TIM9_CH1 /
TIM2_CH3 (7)
USART2_RX(7) / TIM5_CH4 /
ADC123_IN3 / TIM2_CH4(7)/
TIM9_CH2
J2
14 23 34
Remap
M2 17 26 37
PA3
I/O
PA3
G4 18 27 38
VSS_4
S
VSS_4
F4 19 28 39
VDD_4
S
VDD_4
20 29 40
PA4
I/O
PA4
SPI1_NSS(7) / USART2_CK(7) /
DAC_OUT1 / ADC12_IN4
K3 21 30 41
PA5
I/O
PA5
SPI1_SCK(7) / DAC_OUT2 /
ADC12_IN5
PA6
SPI1_MISO(7) / TIM8_BKIN /
ADC12_IN6 / TIM3_CH1(7)/
TIM13_CH1
TIM1_BKIN
TIM1_CH1N
J3
L3 22 31 42
PA6
I/O
M3 23 32 43
PA7
I/O
PA7
SPI1_MOSI(7)/ TIM8_CH1N /
ADC12_IN7 / TIM3_CH2(7) /
TIM14_CH1
J4
24 33 44
PC4
I/O
PC4
ADC12_IN14
K4 25 34 45
PC5
I/O
PC5
ADC12_IN15
L4 26 35 46
PB0
I/O
PB0
ADC12_IN8 / TIM3_CH3 /
TIM8_CH2N
TIM1_CH2N
M4 27 36 47
PB1
I/O
PB1
ADC12_IN9 / TIM3_CH4(7) /
TIM8_CH3N
TIM1_CH3N
J5
PB2
I/O FT PB2/BOOT1
28 37 48
M5
-
-
49
PF11
I/O FT
PF11
FSMC_NIOS16
L5
-
-
50
PF12
I/O FT
PF12
FSMC_A6
H5
-
-
51
VSS_6
S
VSS_6
G5
-
-
52
VDD_6
S
VDD_6
K5
-
-
53
PF13
30/120
I/O FT
PF13
Doc ID 16554 Rev 3
FSMC_A7
STM32F103xF, STM32F103xG
STM32F103xF and STM32F103xG pin definitions (continued)
Alternate functions(4)
LQFP100
LQFP144
Default
LQFP64
Main
function(3)
(after reset)
LFBGA144
Type(1)
Pins
I / O level(2)
Table 5.
Pinouts and pin descriptions
M6
-
-
54
PF14
I/O FT
PF14
FSMC_A8
L6
-
-
55
PF15
I/O FT
PF15
FSMC_A9
K6
-
-
56
PG0
I/O FT
PG0
FSMC_A10
J6
-
-
57
PG1
I/O FT
PG1
FSMC_A11
M7
-
38 58
PE7
I/O FT
PE7
FSMC_D4
TIM1_ETR
L7
-
39 59
PE8
I/O FT
PE8
FSMC_D5
TIM1_CH1N
K7
-
40 60
PE9
I/O FT
PE9
FSMC_D6
TIM1_CH1
H6
-
-
61
VSS_7
S
VSS_7
G6
-
-
62
VDD_7
S
VDD_7
J7
-
41 63
PE10
I/O FT
PE10
FSMC_D7
TIM1_CH2N
H8
-
42 64
PE11
I/O FT
PE11
FSMC_D8
TIM1_CH2
J8
-
43 65
PE12
I/O FT
PE12
FSMC_D9
TIM1_CH3N
K8
-
44 66
PE13
I/O FT
PE13
FSMC_D10
TIM1_CH3
L8
-
45 67
PE14
I/O FT
PE14
FSMC_D11
TIM1_CH4
M8
-
46 68
PE15
I/O FT
PE15
FSMC_D12
TIM1_BKIN
M9 29 47 69
PB10
I/O FT
PB10
I2C2_SCL / USART3_TX(7)
TIM2_CH3
PB11
USART3_RX(7)
TIM2_CH4
Pin name
I/O FT
I2C2_SDA /
Remap
M10 30 48 70
PB11
H7 31 49 71
VSS_1
S
VSS_1
G7 32 50 72
VDD_1
S
VDD_1
M11 33 51 73
PB12
I/O FT
PB12
SPI2_NSS / I2S2_WS /
I2C2_SMBA / USART3_CK(7) /
TIM1_BKIN(7)
M12 34 52 74
PB13
I/O FT
PB13
SPI2_SCK / I2S2_CK /
USART3_CTS(7) / TIM1_CH1N
L11 35 53 75
PB14
I/O FT
PB14
SPI2_MISO / TIM1_CH2N /
USART3_RTS(7)/ TIM12_CH1
L12 36 54 76
PB15
I/O FT
PB15
SPI2_MOSI / I2S2_SD /
TIM1_CH3N(7) / TIM12_CH2
L9
-
55 77
PD8
I/O FT
PD8
FSMC_D13
USART3_TX
K9
-
56 78
PD9
I/O FT
PD9
FSMC_D14
USART3_RX
J9
-
57 79
PD10
I/O FT
PD10
FSMC_D15
USART3_CK
H9
-
58 80
PD11
I/O FT
PD11
FSMC_A16
USART3_CTS
L10
-
59 81
PD12
I/O FT
PD12
FSMC_A17
TIM4_CH1 /
USART3_RTS
Doc ID 16554 Rev 3
31/120
Pinouts and pin descriptions
STM32F103xF and STM32F103xG pin definitions (continued)
Alternate functions(4)
Remap
PD13
FSMC_A18
TIM4_CH2
K10
-
60 82
G8
-
-
83
VSS_8
S
VSS_8
F8
-
-
84
VDD_8
S
VDD_8
K11
-
61 85
PD14
I/O FT
PD14
FSMC_D0
TIM4_CH3
K12
-
62 86
PD15
I/O FT
PD15
FSMC_D1
TIM4_CH4
J12
-
-
87
PG2
I/O FT
PG2
FSMC_A12
J11
-
-
88
PG3
I/O FT
PG3
FSMC_A13
J10
-
-
89
PG4
I/O FT
PG4
FSMC_A14
H12
-
-
90
PG5
I/O FT
PG5
FSMC_A15
H11
-
-
91
PG6
I/O FT
PG6
FSMC_INT2
H10
-
-
92
PG7
I/O FT
PG7
FSMC_INT3
G11 -
-
93
PG8
I/O FT
PG8
G10 -
-
94
VSS_9
S
VSS_9
F10
-
95
VDD_9
S
VDD_9
-
LQFP144
LQFP100
Default
LQFP64
Main
function(3)
(after reset)
LFBGA144
Type(1)
Pins
I / O level(2)
Table 5.
STM32F103xF, STM32F103xG
Pin name
PD13
I/O FT
G12 37 63 96
PC6
I/O FT
PC6
I2S2_MCK / TIM8_CH1 /
SDIO_D6
TIM3_CH1
F12 38 64 97
PC7
I/O FT
PC7
I2S3_MCK / TIM8_CH2 /
SDIO_D7
TIM3_CH2
F11 39 65 98
PC8
I/O FT
PC8
TIM8_CH3 / SDIO_D0
TIM3_CH3
E11 40 66 99
PC9
I/O FT
PC9
TIM8_CH4 / SDIO_D1
TIM3_CH4
TIM1_CH1(7)
E12 41 67 100
PA8
I/O FT
PA8
USART1_CK /
MCO
D12 42 68 101
PA9
I/O FT
PA9
USART1_TX(7) / TIM1_CH2(7)
D11 43 69 102
PA10
I/O FT
PA10
USART1_RX(7) / TIM1_CH3(7)
C12 44 70 103
PA11
I/O FT
PA11
USART1_CTS / USBDM /
CAN_RX(7) / TIM1_CH4(7)
B12 45 71 104
PA12
I/O FT
PA12
USART1_RTS / USBDP /
CAN_TX(7) / TIM1_ETR(7)
A12 46 72 105
PA13
I/O FT
JTMSSWDIO
C11
-
73 106
PA13
Not connected
G9 47 74 107
VSS_2
S
VSS_2
F9 48 75 108
VDD_2
S
VDD_2
A11 49 76 109
PA14
32/120
/
I/O FT
JTCKSWCLK
Doc ID 16554 Rev 3
PA14
STM32F103xF, STM32F103xG
STM32F103xF and STM32F103xG pin definitions (continued)
Pin name
Type(1)
LQFP144
LQFP100
LQFP64
LFBGA144
Pins
I / O level(2)
Table 5.
Pinouts and pin descriptions
Alternate functions(4)
Main
function(3)
(after reset)
Default
Remap
A10 50 77 110
PA15
I/O FT
JTDI
SPI3_NSS / I2S3_WS
TIM2_CH1_ETR
PA15 / SPI1_NSS
B11 51 78 111
PC10
I/O FT
PC10
UART4_TX / SDIO_D2
USART3_TX
B10 52 79 112
PC11
I/O FT
PC11
UART4_RX / SDIO_D3
USART3_RX
C10 53 80 113
PC12
I/O FT
PC12
UART5_TX / SDIO_CK
USART3_CK
PD0
FSMC_D2(9)
CAN_RX
CAN_TX
E10
-
81 114
PD0
I/O FT
82 115
PD1
I/O FT
PD1
FSMC_D3(9)
E9 54 83 116
PD2
I/O FT
PD2
TIM3_ETR / UART5_RX /
SDIO_CMD
D9
-
84 117
PD3
I/O FT
PD3
FSMC_CLK
USART2_CTS
C9
-
85 118
PD4
I/O FT
PD4
FSMC_NOE
USART2_RTS
B9
-
86 119
PD5
I/O FT
PD5
FSMC_NWE
USART2_TX
E7
-
- 120
VSS_10
S
VSS_10
F7
-
- 121
VDD_10
S
VDD_10
A8
-
87 122
PD6
I/O FT
PD6
FSMC_NWAIT
USART2_RX
A9
-
88 123
PD7
I/O FT
PD7
FSMC_NE1 / FSMC_NCE2
USART2_CK
E8
-
- 124
PG9
I/O FT
PG9
FSMC_NE2 / FSMC_NCE3
D8
-
- 125
PG10
I/O FT
PG10
FSMC_NCE4_1 / FSMC_NE3
C8
-
- 126
PG11
I/O FT
PG11
FSMC_NCE4_2
B8
-
- 127
PG12
I/O FT
PG12
FSMC_NE4
D7
-
- 128
PG13
I/O FT
PG13
FSMC_A24
C7
-
- 129
PG14
I/O FT
PG14
FSMC_A25
E6
-
- 130
VSS_11
S
VSS_11
F6
-
- 131
VDD_11
S
VDD_11
B7
-
- 132
PG15
I/O FT
PG15
A7 55 89 133
PB3/
I/O FT
JTDO
SPI3_SCK / I2S3_CK/
PB3/TRACESWO
TIM2_CH2 /
SPI1_SCK
A6 56 90 134
PB4
I/O FT
NJTRST
SPI3_MISO
PB4 / TIM3_CH1
SPI1_MISO
B6 57 91 135
PB5
I/O
PB5
I2C1_SMBA / SPI3_MOSI /
I2S3_SD
TIM3_CH2 /
SPI1_MOSI
C6 58 92 136
PB6
I/O FT
PB6
I2C1_SCL(8)/ TIM4_CH1(8)
USART1_TX
D10
-
(8)
D6 59 93 137
PB7
I/O FT
PB7
I2C1_SDA / FSMC_NADV /
TIM4_CH2(8)
Doc ID 16554 Rev 3
USART1_RX
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Pinouts and pin descriptions
STM32F103xF and STM32F103xG pin definitions (continued)
Pin name
Type(1)
LQFP144
LQFP100
LQFP64
LFBGA144
Pins
I / O level(2)
Table 5.
STM32F103xF, STM32F103xG
Alternate functions(4)
Main
function(3)
(after reset)
I
Default
Remap
D5 60 94 138
BOOT0
BOOT0
C5 61 95 139
PB8
I/O FT
PB8
TIM4_CH3(8) / SDIO_D4 /
TIM10_CH1
I2C1_SCL/
CAN_RX
B5 62 96 140
PB9
I/O FT
PB9
TIM4_CH4(8) / SDIO_D5 /
TIM11_CH1
I2C1_SDA /
CAN_TX
A5
-
97 141
PE0
I/O FT
PE0
TIM4_ETR / FSMC_NBL0
A4
-
98 142
PE1
I/O FT
PE1
FSMC_NBL1
E5 63 99 143
VSS_3
S
VSS_3
F5 64 100 144
VDD_3
S
VDD_3
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144/BGA144
packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate
function I/O and debug configuration section in the STM32F10xxx reference manual.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
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Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Table 6.
Pinouts and pin descriptions
FSMC pin definition
FSMC
Pins
CF
CF/IDE
NOR/PSRAM/
NOR/PSRAM Mux NAND 16 bit
SRAM
LQFP100(1)
PE2
A23
A23
Yes
PE3
A19
A19
Yes
PE4
A20
A20
Yes
PE5
A21
A21
Yes
PE6
A22
A22
Yes
PF0
A0
A0
A0
-
PF1
A1
A1
A1
-
PF2
A2
A2
A2
-
PF3
A3
A3
-
PF4
A4
A4
-
PF5
A5
A5
-
PF6
NIORD
NIORD
-
PF7
NREG
NREG
-
PF8
NIOWR
NIOWR
-
PF9
CD
CD
-
PF10
INTR
INTR
-
PF11
NIOS16
NIOS16
-
PF12
A6
A6
-
PF13
A7
A7
-
PF14
A8
A8
-
PF15
A9
A9
-
PG0
A10
A10
-
A11
-
PG1
PE7
D4
D4
D4
DA4
D4
Yes
PE8
D5
D5
D5
DA5
D5
Yes
PE9
D6
D6
D6
DA6
D6
Yes
PE10
D7
D7
D7
DA7
D7
Yes
PE11
D8
D8
D8
DA8
D8
Yes
PE12
D9
D9
D9
DA9
D9
Yes
PE13
D10
D10
D10
DA10
D10
Yes
PE14
D11
D11
D11
DA11
D11
Yes
PE15
D12
D12
D12
DA12
D12
Yes
PD8
D13
D13
D13
DA13
D13
Yes
Doc ID 16554 Rev 3
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Pinouts and pin descriptions
Table 6.
STM32F103xF, STM32F103xG
FSMC pin definition (continued)
FSMC
Pins
NOR/PSRAM/
NOR/PSRAM Mux NAND 16 bit
SRAM
CF/IDE
PD9
D14
D14
D14
DA14
D14
Yes
PD10
D15
D15
D15
DA15
D15
Yes
PD11
A16
A16
CLE
Yes
PD12
A17
A17
ALE
Yes
PD13
A18
A18
Yes
PD14
D0
D0
D0
DA0
D0
Yes
PD15
D1
D1
D1
DA1
D1
Yes
PG2
A12
-
PG3
A13
-
PG4
A14
-
PG5
A15
-
PG6
INT2
-
PG7
INT3
-
PD0
D2
D2
D2
DA2
D2
Yes
PD1
D3
D3
D3
DA3
D3
Yes
CLK
CLK
PD3
Yes
PD4
NOE
NOE
NOE
NOE
NOE
Yes
PD5
NWE
NWE
NWE
NWE
NWE
Yes
PD6
NWAIT
NWAIT
NWAIT
NWAIT
NWAIT
Yes
PD7
NE1
NE1
NCE2
Yes
PG9
NE2
NE2
NCE3
-
NE3
NE3
PG10
NCE4_1
NCE4_1
PG11
NCE4_2
NCE4_2
-
PG12
NE4
NE4
-
PG13
A24
A24
-
PG14
A25
A25
-
PB7
NADV
NADV
Yes
PE0
NBL0
NBL0
Yes
PE1
NBL1
NBL1
Yes
1. Ports F and G are not available in devices delivered in 100-pin packages.
36/120
LQFP100(1)
CF
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
4
Memory mapping
Memory mapping
The memory map is shown in Figure 7.
Figure 7.
Memory map
Reserved
FSMC bank4 PCCARD
0xA000 1000 - 0xBFFF FFFF
0xA000 0000 - 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
FSMC bank3 NAND (NAND2)
0x8000 0000 - 0x8FFF FFFF
FSMC register
FSMC bank2 NAND (NAND1)
0x6C00 0000 - 0x6FFF FFFF
0x6800 0000 - 0x6BFF FFFF
0x6400 0000 - 0x67FF FFFF
FSMC bank1 NOR/PSRAM 2
FSMC bank1 NOR/PSRAM 1
0x4002 4400 - 0x5FFF FFFF
CRC
0x4002 3000 - 0x4002 33FF
Reserved
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
Reserved
0x4002 1400 - 0x4002 1FFF
RCC
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
Reserved
DMA2
DMA1
Reserved
SDIO
Reserved
TIM11
TIM10
TIM9
0xE000 0000
0xDFFF FFFF
512-Mbyte
block 7
Cortex-M3's
internal
peripherals
512-Mbyte
block 6
Not used
0xC000 0000
0xBFFF FFFF
512-Mbyte
block 5
FSMC register
0xA000 0000
0x9FFF FFFF
512-Mbyte
block 4
FSMC bank 3
& bank4
I2C2
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
UART5
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
USART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
Reserved
0x4000 4000 - 0x4000 43FF
SPI3/I2S3
0x4000 3C00 - 0x4000 3FFF
512-Mbyte
block 2
Peripherals
0x4000 0000
0x3FFF FFFF
0x2000 0000
0x1FFF FFFF
0x0000 0000
SRAM (96 KB aliased
by bit-banding)
Option bytes
System memory
Reserved
Flash memory bank 2
(256 KB or 512 KB)
Flash memory bank 1
(512 KB)
Reserved
Aliased to Flash or system
memory depending on
BOOT pins
0x3FFF FFFF
0x2001 8000
0x2001 7FFF
0x2000 0000
0x4001 2000 - 0x4001 23FF
0x4001 1C00 - 0x4001 1FFF
0x4001 1800 - 0x4001 1BFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0C00 - 0x4001 0FFF
0x4001 0800 - 0x4001 0BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 7800 - 0x4000 FFFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
SPI2/I2S2
Reserved
0x4000 3800 - 0x4000 3BFF
IWDG
0x4000 3000 - 0x4000 33FF
WWDG
0x4000 2C00 - 0x4000 2FFF
RTC
512-Mbyte
block 1
SRAM
Reserved
0x4001 5000 - 0x4001 53FF
0x4001 4C00 - 0x4001 4FFF
0x4001 4000 - 0x4001 4BFF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
512-Mbyte
block 3
FSMC bank1
& bank2
512-Mbyte
block 0
Code
0x4001 8400 - 0x4001 FFFF
0x4001 8000 - 0x4001 83FF
0x4001 5800 - 0x4001 7FFF
0x4001 5400 - 0x4001 57FF
Reserved
ADC3
USART1
TIM8
SPI1
TIM1
ADC2
ADC1
Port G
Port F
Port E
Port D
Port C
Port B
Port A
EXTI
AFIO
Reserved
DAC
PWR
BKP
Reserved
BxCAN
Shared USB/CAN SRAM 512
bytes
USB registers
0x8000 0000
0x7FFF FFFF
0x6000 0000
0x5FFF FFFF
0x6000 0000 - 0x63FF FFFF
Reserved
Flash interfaces 1 & 2
0xFFFF FFFF
0x7000 0000 - 0x7FFF FFFF
FSMC bank1 NOR/PSRAM 4
FSMC bank1 NOR/PSRAM 3
0x4000 3400 - 0x4000 37FF
0x4000 2800 - 0x4000 2BFF
Reserved
0x4000 2400 - 0x4000 27FF
TIM14
0x4000 2000 - 0x4000 23FF
TIM13
0x4000 1C00 - 0x4000 1FFF
TIM12
TIM7
0x4000 1800 - 0x4000 1BFF
TIM6
0x4000 1000 - 0x4000 13FF
TIM5
0x4000 0C00 - 0x4000 0FFF
TIM4
0x4000 0800 - 0x4000 0BFF
0x4000 1400 - 0x4000 17FF
TIM3
0x4000 0400 - 0x4000 07FF
TIM2
0x4000 0000 - 0x4000 03FF
0x1FFF F800 - 0x1FFF F80F
0x1FFF E000- 0x1FFF F7FF
0x0810 0000 - 0x1FFF DFFF
0x080F FFFF
0x0808 0000
0x0807 FFFF
0x0800 0000
0x0010 0000 - 0x07FF FFFF
0x000F FFFF
0x0000 0000
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ai17353
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Electrical characteristics
STM32F103xF, STM32F103xG
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8.
Pin loading conditions
Figure 9.
Pin input voltage
STM32F103xx pin
C = 50 pF
VIN
ai14141
38/120
STM32F103xx pin
Doc ID 16554 Rev 3
ai14142
STM32F103xF, STM32F103xG
5.1.6
Electrical characteristics
Power supply scheme
Figure 10. Power supply scheme
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Caution:
In Figure 10, the 4.7 µF capacitor must be connected to VDD3.
5.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
Doc ID 16554 Rev 3
39/120
Electrical characteristics
5.2
STM32F103xF, STM32F103xG
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics,
Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 7.
Symbol
VDD–VSS
VIN(2)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Voltage characteristics
Ratings
Min
Max
–0.3
4.0
Input voltage on five volt tolerant pin
VSS −0.3
VDD + 4.0
Input voltage on any other pin
VSS − 0.3
4.0
Variations between different VDD power pins
-
50
Variations between all the different ground pins
-
50
External main supply voltage (including VDDA
and VDD)(1)
Electrostatic discharge voltage (human body
model)
Unit
V
mV
see Section 5.3.12:
Absolute maximum ratings
(electrical sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum
allowed injected current values.
Table 8.
Symbol
IVDD
IVSS
IIO
IINJ(PIN)(2)
ΣIINJ(PIN)
Current characteristics
Ratings
Max.
Total current into VDD/VDDA power lines (source)(1)
Total current out of VSS ground lines
150
(sink)(1)
150
Output current sunk by any I/O and control pin
25
Output current source by any I/Os and control pin
−25
Injected current on five volt tolerant pins(3)
Injected current on any other
mA
-5/+0
pin(4)
Total injected current (sum of all I/O and control pins)
Unit
±5
(5)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note 3 below Table 65 on page 103.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage
values.
4.
A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
40/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Table 9.
Electrical characteristics
Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Table 10.
Value
Unit
–65 to +150
°C
150
°C
General operating conditions
Symbol
Parameter
fHCLK
Min
Max
Internal AHB clock frequency
0
72
fPCLK1
Internal APB1 clock frequency
0
36
fPCLK2
Internal APB2 clock frequency
0
72
Standard operating voltage
2
3.6
2
3.6
2.4
3.6
1.8
3.6
LQFP144
-
666
LQFP100
-
434
LQFP64
-
444
LFBGA144
-
500
WLCSP64
-
400
–40
85
VDD
VDDA
(1)
VBAT
PD
Analog operating voltage
(ADC not used)
Analog operating voltage
(ADC used)
Conditions
Must be the same potential
as VDD(2)
Backup operating voltage
Power dissipation at TA =
85 °C for suffix 6 or TA =
105 °C for suffix 7(3)
Unit
MHz
V
V
V
mW
Ambient temperature for 6
suffix version
Maximum power dissipation
Low power dissipation
–40
105
Ambient temperature for 7
suffix version
Maximum power dissipation
–40
105
Low power dissipation(4)
–40
125
6 suffix version
–40
105
7 suffix version
–40
125
(4)
°C
TA
TJ
°C
Junction temperature range
°C
1. When the ADC is used, refer to Table 62: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 114).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 114).
Doc ID 16554 Rev 3
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Electrical characteristics
5.3.2
STM32F103xF, STM32F103xG
Operating conditions at power-up / power-down
The parameters given in Table 11 are derived from tests performed under the ambient
temperature condition summarized in Table 10.
Table 11.
Operating conditions at power-up / power-down
Symbol
Parameter
tVDD
5.3.3
Conditions
Min
Max
VDD rise time rate
0
∞
VDD fall time rate
20
∞
Unit
µs/V
Embedded reset and power control block characteristics
The parameters given in Table 12 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
Table 12.
Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Programmable voltage
detector level selection
VPVD
VPVDhyst(2)
PVD hysteresis
VPOR/PDR
Power on/power down
reset threshold
VPDRhyst
(2)
TRSTTEMPO
(2)
Min
Typ
PLS[2:0]=000 (rising edge)
2.1
2.18
2.26
V
PLS[2:0]=000 (falling edge)
2
2.08
2.16
V
PLS[2:0]=001 (rising edge)
2.19
2.28
2.37
V
PLS[2:0]=001 (falling edge)
2.09
2.18
2.27
V
PLS[2:0]=010 (rising edge)
2.28
2.38
2.48
V
PLS[2:0]=010 (falling edge)
2.18
2.28
2.38
V
PLS[2:0]=011 (rising edge)
2.38
2.48
2.58
V
PLS[2:0]=011 (falling edge)
2.28
2.38
2.48
V
PLS[2:0]=100 (rising edge)
2.47
2.58
2.69
V
PLS[2:0]=100 (falling edge)
2.37
2.48
2.59
V
PLS[2:0]=101 (rising edge)
2.57
2.68
2.79
V
PLS[2:0]=101 (falling edge)
2.47
2.58
2.69
V
PLS[2:0]=110 (rising edge)
2.66
2.78
2.9
V
PLS[2:0]=110 (falling edge)
2.56
2.68
2.8
V
PLS[2:0]=111 (rising edge)
2.76
2.88
3
V
PLS[2:0]=111 (falling edge)
2.66
2.78
2.9
V
-
100
-
Unit
mV
Falling edge
1.8(1) 1.88
1.96
V
Rising edge
1.84
1.92
2.0
V
PDR hysteresis
-
40
-
mV
Reset temporization
1
2.5
4.5
mS
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
42/120
Max
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
5.3.4
Electrical characteristics
Embedded reference voltage
The parameters given in Table 13 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
Table 13.
Symbol
VREFINT
Embedded internal reference voltage
Parameter
Internal reference voltage
Conditions
Min
Typ
–40 °C < TA < +105 °C
1.16
1.20
1.26
V
–40 °C < TA < +85 °C
1.16
1.20
1.24
V
-
5.1
17.1(2)
µs
-
-
10
mV
-
-
100
ppm/°C
ADC sampling time when
TS_vrefint(1) reading the internal reference
voltage
Internal reference voltage
VRERINT(2) spread over the temperature
range
TCoeff(2)
VDD = 3 V ±10 mV
Temperature coefficient
Max
Unit
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except when explicitly mentioned
●
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
●
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
●
When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 14, Table 15 and Table 16 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Table 10.
Doc ID 16554 Rev 3
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Electrical characteristics
Table 14.
STM32F103xF, STM32F103xG
Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
External clock(2), all
peripherals enabled
IDD
Supply current in
Run mode
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz
68
69
48 MHz
51
51
36 MHz
41
41
24 MHz
29
30
16 MHz
22
22.5
8 MHz
12.5
14
72 MHz
39
39
48 MHz
29.5
30
24
24.5
17.5
19
16 MHz
14
15
8 MHz
8.5
10.5
External clock(3), all 36 MHz
peripherals disabled 24 MHz
mA
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15.
Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol
Parameter
Conditions
External clock(2), all
peripherals enabled
IDD
Supply current
in Run mode
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz
65
65.5
48 MHz
46.5
47
36 MHz
37
37
24 MHz
26.5
27
16 MHz
19
20
8 MHz
11.5
13
72 MHz
34.5
36
48 MHz
25
26
20.5
21
15
16
16 MHz
11
13
8 MHz
7.5
9
External clock(3), all 36 MHz
peripherals disabled 24 MHz
1. Data based on characterization results, tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Doc ID 16554 Rev 3
mA
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
#ONSUMPTIONM!
-(Z
-(Z
-(Z
-(Z
-(Z
-(Z
4EMPERATURE #
AI
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled
#ONSUMPTIONM!
-(Z
-(Z
-(Z
-(Z
-(Z
-(Z
4EMPERATURE #
AI
Doc ID 16554 Rev 3
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Electrical characteristics
Table 16.
STM32F103xF, STM32F103xG
Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max(1)
Symbol
Parameter
Conditions
External clock(2), all
peripherals enabled
IDD
Supply current
in Sleep mode
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz
47.5
48.5
48 MHz
34
35
36 MHz
27.5
27.5
24 MHz
20
20.5
16 MHz
15
16
8 MHz
9
11
72 MHz
9.5
11.2
48 MHz
7.7
9.5
36 MHz
6.9
8.5
24 MHz
5.9
7.8
16 MHz
5.4
7.2
8 MHz
4.7
6.4
mA
External clock(3), all
peripherals disabled
1. Based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
46/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Table 17.
Electrical characteristics
Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Symbol
IDD
IDD_VBAT
Parameter
Conditions
Max
VDD/VBAT VDD/VBAT VDD/VBAT TA =
TA =
= 2.0 V = 2.4 V = 3.3 V 85 °C 105 °C
Regulator in run mode, low-speed
and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog),
Supply current in f =8 MHz
CK
Stop mode
Regulator in low-power mode, lowspeed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
44.8
45.3
46.4
810
1680
37.4
37.8
38.7
790
1660
Low-speed internal RC oscillator
Supply current in
and independent watchdog OFF,
Standby mode
low-speed oscillator and RTC OFF
1.8
2.0
2.5
5(2)
8(2)
Backup domain
Low-speed oscillator and RTC ON
supply current
1.05
1.1
1.4
2(2)
2.3(2)
Unit
µA
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not tested in production.
Figure 14. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT
values
2.5
Consumption (µA)
2
1.8 V
1.5
2V
2.4 V
3.3 V
1
3.6 V
0.5
0
–45
25
85
Temperature (°C)
Doc ID 16554 Rev 3
105
ai17337
47/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 15. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different VDD values
#ONSUMPTIONμ!
6
6
6
6
6
#
#
#
#
4EMPERATURE #
AI
48/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 16. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different VDD values
#ONSUMPTION μ!
6
6
6
6
6
#
#
#
4EMPERATURE #
#
AI
Figure 17. Typical current consumption in Standby mode versus temperature at
different VDD values
#ONSUMPTIONμ!
6
6
6
6
6
#
#
#
4EMPERATURE #
Doc ID 16554 Rev 3
#
AI
49/120
Electrical characteristics
STM32F103xF, STM32F103xG
Typical current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load).
●
All peripherals are disabled except if it is explicitly mentioned.
●
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHZ and 2 wait states above).
●
Ambient temperature and VDD supply voltage conditions summarized in Table 10.
●
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4
Table 18.
Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Symbol
Parameter
Conditions
(3)
External clock
IDD
Supply
current in
Run mode
Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
frequency
fHCLK
All peripherals All peripherals
disabled
enabled(2)
72 MHz
52.5
33.5
48 MHz
36.6
23.8
36 MHz
28.5
18.7
24 MHz
24.1
12.8
16 MHz
14
9.2
8 MHz
7.7
5.4
4 MHz
4.6
3.4
2 MHz
3
2.3
1 MHz
2.2
1.8
500 kHz
1.7
1.5
125 kHz
1.4
1.3
64 MHz
45.5
28.6
48 MHz
35.1
22.4
36 MHz
27.5
17.5
24 MHz
18.9
11.6
16 MHz
12.2
8.2
8 MHz
7.2
4.8
4 MHz
4
2.7
2 MHz
2.3
1.7
1 MHz
1.5
1.2
500 kHz
1.1
0.9
125 kHz
0.75
0.7
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Doc ID 16554 Rev 3
Unit
mA
mA
STM32F103xF, STM32F103xG
Table 19.
Electrical characteristics
Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Symbol Parameter
Conditions
External clock
IDD
Supply
current in
Sleep mode
(3)
fHCLK
All peripherals All peripherals
enabled(2)
disabled
72 MHz
32.5
7
48 MHz
23
5
36 MHz
17.7
4
24 MHz
12.2
3.1
16 MHz
8.4
2.3
8 MHz
4.6
1.5
4 MHz
3
1.3
2 MHz
2.15
1.25
1 MHz
1.7
1.2
500 kHz
1.5
1.15
125 kHz
1.35
1.15
64 MHz
28.7
5.7
48 MHz
22
4.4
36 MHz
17
3.35
11.6
2.3
7.7
1.6
3.9
0.8
2.3
0.7
1.5
0.6
1 MHz
1.1
0.5
500 kHz
0.9
0.5
125 kHz
0.7
0.5
Unit
mA
24 MHz
Running on high
16 MHz
speed internal RC
(HSI), AHB prescaler 8 MHz
used to reduce the
4 MHz
frequency
2 MHz
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Doc ID 16554 Rev 3
51/120
Electrical characteristics
STM32F103xF, STM32F103xG
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed
under the following conditions:
●
all I/O pins are in input mode with a static value at VDD or VSS (no load)
●
all peripherals are disabled unless otherwise mentioned
●
the given value is calculated by measuring the current consumption
●
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Table 7
Table 20.
Peripheral current consumption(1)
Peripheral
APB1
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Typical consumption at 25 °C
TIM2
1.6
TIM3
1.5
TIM4
1.5
TIM5
1.5
TIM6
0.6
TIM7
0.6
TIM12
0.95
TIM13
0.7
TIM14
0.75
SPI2
0.6
SPI3
0.6
USART2
0.7
USART3
0.7
USART4
0.7
USART5
0.7
I2C1
0.65
I2C2
0.65
USB
0.9
CAN
0.9
DAC(2)
1.35
Doc ID 16554 Rev 3
Unit
mA
STM32F103xF, STM32F103xG
Table 20.
Electrical characteristics
Peripheral current consumption(1) (continued)
Peripheral
APB2
Typical consumption at 25 °C
GPIOA
0.55
GPIOB
0.55
GPIOC
0.55
GPIOD
0.6
GPIOE
0.6
GPIOF
0.55
GPIOG
0.55
TIM1
1.95
TIM8
1.9
TIM9
1
TIM10
0.8
TIM11
0.8
ADC1(3)
1.85
ADC2(3)
1.8
ADC3(3)
1.8
SPI1
0.45
USART1
0.8
Unit
mA
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for DAC: EN1, EN2 bits in the DAC_CR register are set to 1 and the converted value
set to 0x800.
3. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit
in the ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 10.
Doc ID 16554 Rev 3
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Electrical characteristics
Table 21.
STM32F103xF, STM32F103xG
High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1
8
25
MHz
fHSE_ext
User external clock source
frequency(1)
VHSEH
OSC_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
5
-
-
tr(HSE)
tf(HSE)
Cin(HSE)
ns
(1)
OSC_IN rise or fall time
-
-
20
OSC_IN input capacitance(1)
-
5
-
pF
45
-
55
%
-
-
±1
µA
DuCy(HSE) Duty cycle
IL
V
OSC_IN Input leakage current
VSS ≤VIN ≤VDD
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 22 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 10.
Table 22.
Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
32.768
1000
kHz
fLSE_ext
User External clock source
frequency(1)
VLSEH
OSC32_IN input pin high level
voltage
0.7VDD
-
VDD
VLSEL
OSC32_IN input pin low level
voltage
VSS
-
0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
450
-
-
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
-
-
50
OSC32_IN input capacitance(1)
-
5
-
pF
30
-
70
%
-
-
±1
µA
V
Cin(LSE)
ns
DuCy(LSE) Duty cycle
IL
OSC32_IN Input leakage current
VSS ≤VIN ≤VDD
1. Guaranteed by design, not tested in production.
54/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 18. High-speed external clock source AC timing diagram
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tW(HSE)
tW(HSE)
t
THSE
EXTER NAL
CLOCK SOURC E
fHSE_ext
OSC _IN
IL
STM32F103xx
ai14143
Figure 19. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE)
t
TLSE
EXTER NAL
CLOCK SOURC E
fLSE_ext
STM32F103xx
ai14144b
Doc ID 16554 Rev 3
55/120
Electrical characteristics
STM32F103xF, STM32F103xG
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 23. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 23.
HSE 4-16 MHz oscillator characteristics(1)(2)
Symbol
Min
Typ
Max
Unit
Oscillator frequency
4
8
16
MHz
RF
Feedback resistor
-
200
-
kΩ
C
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 Ω
-
30
-
pF
i2
HSE driving current
VDD= 3.3 V, VIN = VSS
with 30 pF load
-
-
1
mA
gm
Oscillator transconductance
Startup
25
-
mA/V
VDD is stabilized
-
-
ms
fOSC_IN
tSU(HSE)(4)
Parameter
Conditions
Startup time
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 20). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Figure 20. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
fHS E
OSC_IN
8 MH z
resonator
CL2
REXT(1)
RF
OSC_OU T
Bias
controlled
gain
STM32F103xx
ai14145
1. REXT value depends on the crystal characteristics.
56/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 24. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 24.
Symbol
LSE oscillator characteristics (fLSE = 32.768 kHz)(1)(2)
Parameter
RF
Feedback resistor
C(2)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)
I2
LSE driving current
gm
Oscillator transconductance
tSU(LSE)(3) Startup time
Conditions
Min
Typ
Max
Unit
-
5
-
MΩ
RS = 30 kΩ
-
-
15
pF
VDD = 3.3 V, VIN = VSS
-
-
1.4
µA
5
-
-
µA/V
TA = 50 °C
-
1.5
-
TA = 25 °C
-
2.5
-
TA = 10 °C
-
4
-
TA = 0 °C
-
6
-
TA = -10 °C
-
10
-
TA = -20 °C
-
17
-
TA = -30 °C
-
32
-
TA = -40 °C
-
60
-
VDD is
stabilized
s
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer, PCB
layout and humidity
Note:
For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 21).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Doc ID 16554 Rev 3
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Electrical characteristics
STM32F103xF, STM32F103xG
Figure 21. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fLSE
OSC32_IN
32.768 kH z
resonator
CL2
Bias
controlled
gain
RF
STM32F103xx
OSC32_OU T
ai14146
5.3.7
Internal clock source characteristics
The parameters given in Table 25 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
High-speed internal (HSI) RC oscillator
Table 25.
Symbol
HSI oscillator characteristics(1)
Parameter
Conditions
Min
Typ
Max
fHSI
Frequency
-
8
DuCy(HSI)
Duty cycle
45
-
55
%
-
-
1(3)
%
TA = –40 to 105 °C
–2
-
2.5
%
TA = –10 to 85 °C
–1.5
-
2.2
%
TA = 0 to 70 °C
–1.3
-
2
%
TA = 25 °C
–1.1
-
1.8
%
User-trimmed with the RCC_CR
register(2)
ACCHSI
Accuracy of the HSI
oscillator
Factorycalibrated(4)
MHz
tsu(HSI)(4)
HSI oscillator
startup time
1
-
2
µs
IDD(HSI)(4)
HSI oscillator power
consumption
-
80
100
µA
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
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Unit
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Low-speed internal (LSI) RC oscillator
Table 26.
LSI oscillator characteristics (1)
Symbol
fLSI(2)
Parameter
Frequency
Min
Typ
Max
Unit
30
40
60
kHz
tsu(LSI)(3)
LSI oscillator startup time
-
-
85
µs
IDD(LSI)(3)
LSI oscillator power consumption
-
0.65
1.2
µA
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 27 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 10.
Table 27.
Low-power mode wakeup timings
Symbol
tWUSLEEP(1)
tWUSTOP(1)
tWUSTDBY(1)
Parameter
Typ
Unit
Wakeup from Sleep mode
1.8
µs
Wakeup from Stop mode (regulator in run mode)
3.6
Wakeup from Stop mode (regulator in low power mode)
5.4
Wakeup from Standby mode
50
µs
µs
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Doc ID 16554 Rev 3
59/120
Electrical characteristics
5.3.8
STM32F103xF, STM32F103xG
PLL characteristics
The parameters given in Table 28 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
Table 28.
PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
1
8.0
25
MHz
PLL input clock duty cycle
40
-
60
%
fPLL_OUT
PLL multiplier output clock
16
-
72
MHz
tLOCK
PLL lock time
-
-
200
µs
Jitter
Cycle-to-cycle jitter
-
-
300
ps
fPLL_IN
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 29.
Symbol
tprog
tERASE
tME
IDD
Vprog
Flash memory characteristics
Min
Typ
Max(1)
Unit
16-bit programming time TA = –40 to +105 °C
40
52.5
70
µs
Page (2 KB) erase time
TA = –40 to +105 °C
20
-
40
ms
Mass erase time
TA = –40 to +105 °C
20
-
40
ms
Read mode
fHCLK = 72 MHz with 2 wait
states, VDD = 3.3 V
-
-
28
mA
Write mode
fHCLK = 72 MHz, VDD = 3.3 V
-
-
7
mA
Erase mode
fHCLK = 72 MHz, VDD = 3.3 V
-
-
5
mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
-
-
50
µA
2
-
3.6
V
Parameter
Supply current
Conditions
Programming voltage
1. Guaranteed by design, not tested in production.
60/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Table 30.
Electrical characteristics
Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
Min(1)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
1 kcycle
(2)
10 kcycles
at TA = 105 °C
10
(2)
20
at TA = 55 °C
Unit
kcycles
Years
1. Based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10
FSMC characteristics
Asynchronous waveforms and timings
Figure 22 through Figure 25 represent asynchronous waveforms and Table 31 through
Table 35 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
Note:
●
AddressSetupTime = 0
●
AddressHoldTime = 1
●
DataSetupTime = 1
On all tables, the tHCLK is the HCLK clock period.
Doc ID 16554 Rev 3
61/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
TW.%
&3-#?.%
T V./%?.%
T W./%
T H.%?./%
&3-#?./%
&3-#?.7%
TV!?.%
&3-#?!;=
T H!?./%
!DDRESS
TV",?.%
T H",?./%
&3-#?.",;=
T H$ATA?.%
T SU$ATA?./%
TH$ATA?./%
T SU$ATA?.%
$ATA
&3-#?$;=
T V.!$6?.%
TW.!$6
&3-#?.!$6 -36
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Note:
62/120
FSMC_BusTurnAroundDuration = 0.
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
Table 31.
Symbol
Parameter
Min
Max
Unit
5tHCLK + 0.5
5tHCLK + 2
ns
0.5
1.5
ns
5tHCLK – 1
5tHCLK + 1
ns
tw(NE)
FSMC_NE low time
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
tw(NOE)
FSMC_NOE low time
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
0
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
3
ns
th(A_NOE)
Address hold time after FSMC_NOE high
0
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0.5
-
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
2tHCLK - 1
-
ns
2tHCLK - 1
-
ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
0
ns
tw(NADV)
FSMC_NADV low time
-
tHCLK + 2
ns
1. CL = 15 pF.
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FSMC_NEx
FSMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:0]
th(A_NWE)
Address
tv(BL_NE)
FSMC_NBL[3:0]
th(BL_NWE)
NBL
tv(Data_NE)
th(Data_NWE)
Data
FSMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FSMC_NADV(1)
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Doc ID 16554 Rev 3
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Electrical characteristics
Table 32.
Symbol
STM32F103xF, STM32F103xG
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
3tHCLK + 0.5
3tHCLK + 1.5 ns
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
tHCLK + 0.5
tHCLK + 1.5
ns
tw(NWE)
FSMC_NWE low time
tHCLK – 0.5
tHCLK + 1
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
tHCLK – 0.5
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
0
ns
th(A_NWE)
Address hold time after FSMC_NWE high
tHCLK
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
1.5
ns
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tHCLK – 1.5
-
ns
tv(Data_NE)
FSMC_NEx low to Data valid
-
tHCLK
ns
th(Data_NWE)
Data hold time after FSMC_NWE high
tHCLK
-
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
0
ns
tw(NADV)
FSMC_NADV low time
-
tHCLK + 1.5
ns
Min
Max
1. CL = 15 pF.
Table 33.
Symbol
Asynchronous read muxed
Parameter
tw(NE)
FSMC_NE low time
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
tw(NOE)
FSMC_NOE low time
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
tv(A_NE)
3tHCLK + 0.5
4tHCLK – 1
7tHCLK + 2
3tHCLK + 1.5
4tHCLK + 1
0.5
-
FSMC_NEx low to FSMC_A valid
-
0
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
0
1
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 2
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC NADV high
tHCLK
-
th(A_NOE)
Address hold time after FSMC_NOE high
tHCLK – 2
-
th(BL_NOE)
FSMC_BL time after FSMC_NOE high
0.5
-
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0
tsu(Data_NE)
Data to FSMC_NEx high setup time
4tHCLK – 0.5
-
4tHCLK – 1
-
tsu(Data_NOE) Data to FSMC_NOE high setup time
64/120
7tHCLK + 0.5
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
Doc ID 16554 Rev 3
Unit
ns
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FSMC_NE
tv(NOE_NE)
t h(NE_NOE)
FSMC_NOE
t w(NOE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:16]
t h(A_NOE)
Address
tv(BL_NE)
th(BL_NOE)
FSMC_NBL[1:0]
NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE)
tsu(Data_NOE)
Address
FSMC_AD[15:0]
t v(NADV_NE)
th(Data_NOE)
Data
th(AD_NADV)
tw(NADV)
FSMC_NADV
ai14892b
Table 34.
Symbol
Asynchronous multiplexed PSRAM/NOR read timings(1)
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
7tHCLK + 0.5
7tHCLK + 2
ns
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
3tHCLK + 0.5
3tHCLK + 1.5
ns
tw(NOE)
FSMC_NOE low time
4tHCLK – 1
4tHCLK + 1
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
0.5
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
0
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
0
1
ns
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 2
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
tHCLK
-
ns
th(A_NOE)
Address hold time after FSMC_NOE high
tHCLK -2
-
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0.5
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
4tHCLK - 0.5
-
ns
4tHCLK - 1
-
ns
tsu(Data_NOE) Data to FSMC_NOE high setup time
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
1. CL = 15 pF.
Doc ID 16554 Rev 3
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Electrical characteristics
STM32F103xF, STM32F103xG
Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms
tw(NE)
FSMC_NEx
FSMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:16]
th(A_NWE)
Address
tv(BL_NE)
th(BL_NWE)
FSMC_NBL[1:0]
NBL
t v(A_NE)
t v(Data_NADV)
Address
FSMC_AD[15:0]
t v(NADV_NE)
th(Data_NWE)
Data
th(AD_NADV)
tw(NADV)
FSMC_NADV
ai14891B
Table 35.
Symbol
Asynchronous multiplexed PSRAM/NOR write timings(1)
Parameter
Max
Unit
5tHCLK + 0.5
5tHCLK + 2
ns
tHCLK + 1
tHCLK + 1.5
ns
tw(NE)
FSMC_NE low time
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
tw(NWE)
FSMC_NWE low time
3tHCLK + 0.5
3tHCLK + 1
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
tHCLK – 0.5
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
3.5
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
0
1
ns
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 1.5
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
tHCLK – 0.5
-
ns
th(A_NWE)
Address hold time after FSMC_NWE high
4tHCLK – 2
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0.5
ns
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tHCLK – 1.5
-
ns
-
tHCLK + 6
ns
tHCLK – 0.5
-
ns
tv(Data_NADV) FSMC_NADV high to Data valid
th(Data_NWE)
Data hold time after FSMC_NWE high
1. CL = 15 pF.
66/120
Min
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Synchronous waveforms and timings
Figure 26 through Figure 29 represent synchronous waveforms and Table 37 through
Table 39 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●
BurstAccessMode = FSMC_BurstAccessMode_Enable;
●
MemoryType = FSMC_MemoryType_CRAM;
●
WriteBurst = FSMC_WriteBurst_Enable;
●
CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
●
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 26. Synchronous multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&3-#?#,+
$ATALATENCY
TD#,+,.%X,
T D#,+,.%X(
&3-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&3-#?.!$6
TD#,+,!)6
TD#,+,!6
&3-#?!;=
TD#,+,./%,
TD#,+,./%(
&3-#?./%
TD#,+,!$)6
TSU!$6#,+(
TD#,+,!$6
&3-#?!$;=
!$;=
TH#,+(!$6
TSU!$6#,+(
$
TSU.7!)46#,+(
TH#,+(!$6
$
$
TH#,+(.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
AIH
Doc ID 16554 Rev 3
67/120
Electrical characteristics
Table 36.
STM32F103xF, STM32F103xG
Synchronous multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
Max
Unit
27.6
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0.5
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
1
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
1
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
0.5
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
1.5
-
ns
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
-
14
ns
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
1
-
ns
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
-
11
ns
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0.5
-
ns
tsu(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK
high
2
-
ns
th(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high
0
-
ns
1. CL = 15 pF.
68/120
Min
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 27. Synchronous multiplexed PSRAM write timings
"53452.
TW#,+
TW#,+
&3-#?#,+
$ATALATENCY
TD#,+,.%X,
TD#,+,.%X(
&3-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&3-#?.!$6
TD#,+,!6
TD#,+,!)6
&3-#?!;=
TD#,+,.7%,
TD#,+,.7%(
&3-#?.7%
TD#,+,!$)6
TD#,+,$ATA
TD#,+,!$6
&3-#?!$;=
TD#,+,$ATA
!$;=
$
$
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
TD#,+,.",(
&3-#?.",
AIG
Doc ID 16554 Rev 3
69/120
Electrical characteristics
Table 37.
STM32F103xF, STM32F103xG
Synchronous multiplexed PSRAM write timings(1)
Symbol
Parameter
Max
Unit
27.5
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_Nex low (x = 0...2)
-
0
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
1
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
1
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
1
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
1
-
ns
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
-
1
ns
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
1.5
-
ns
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
-
10
ns
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
1
-
ns
td(CLKL-Data)
FSMC_A/D[15:0] valid after FSMC_CLK low
-
6
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1
-
ns
1. CL = 15 pF.
70/120
Min
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&3-#?#,+
TD#,+,.%X,
TD#,+,.%X(
$ATALATENCY
&3-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&3-#?.!$6
TD#,+,!)6
TD#,+,!6
&3-#?!;=
TD#,+,./%,
TD#,+,./%(
&3-#?./%
TSU$6#,+(
TH#,+($6
TSU$6#,+(
$
&3-#?$;=
TSU.7!)46#,+(
TH#,+($6
$
$
TH#,+(.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
T H#,+(.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
AIG
Table 38.
Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
Min
Max
Unit
27.6
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
1.5
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
2
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
0.5
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
1
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 0...25)
2
-
ns
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
-
tHCLK + 1
ns
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
1.5
-
ns
tsu(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK high
3.5
-
ns
th(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high
0
-
ns
1. CL = 15 pF.
Doc ID 16554 Rev 3
71/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 29. Synchronous non-multiplexed PSRAM write timings
TW#,+
"53452.
TW#,+
&3-#?#,+
TD#,+,.%X,
TD#,+,.%X(
$ATALATENCY
&3-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&3-#?.!$6
TD#,+,!6
TD#,+,!)6
&3-#?!;=
TD#,+,.7%,
TD#,+,.7%(
&3-#?.7%
TD#,+,$ATA
&3-#?$;=
TD#,+,$ATA
$
$
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TD#,+,.",(
TH#,+(.7!)46
&3-#?.",
AIH
Table 39.
Synchronous non-multiplexed PSRAM write timings(1)
Symbol
Parameter
Max
Unit
27.6
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0.5
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
1.5
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
1
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
0.5
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
1.5
-
ns
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
-
1
ns
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
1.5
-
ns
td(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low
-
2.5
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
0.5
-
ns
1. CL = 15 pF.
72/120
Min
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
PC Card/CompactFlash controller waveforms and timings
Figure 30 through Figure 35 represent synchronous waveforms and Table 42 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●
COM.FSMC_SetupTime = 0x04;
●
COM.FSMC_WaitSetupTime = 0x07;
●
COM.FSMC_HoldSetupTime = 0x04;
●
COM.FSMC_HiZSetupTime = 0x00;
●
ATT.FSMC_SetupTime = 0x04;
●
ATT.FSMC_WaitSetupTime = 0x07;
●
ATT.FSMC_HoldSetupTime = 0x04;
●
ATT.FSMC_HiZSetupTime = 0x00;
●
IO.FSMC_SetupTime = 0x04;
●
IO.FSMC_WaitSetupTime = 0x07;
●
IO.FSMC_HoldSetupTime = 0x04;
●
IO.FSMC_HiZSetupTime = 0x00;
●
TCLRSetupTime = 0;
●
TARSetupTime = 0;
Figure 30. PC Card/CompactFlash controller waveforms for common memory read
access
FSMC_NCE4_2(1)
FSMC_NCE4_1
th(NCEx-AI)
tv(NCEx-A)
FSMC_A[10:0]
th(NCEx-NREG)
th(NCEx-NIORD)
th(NCEx-NIOWR)
td(NREG-NCEx)
td(NIORD-NCEx)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
FSMC_NWE
td(NCE4_1-NOE)
tw(NOE)
FSMC_NOE
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0]
ai14895b
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
Doc ID 16554 Rev 3
73/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 31. PC Card/CompactFlash controller waveforms for common memory write
access
FSMC_NCE4_1
FSMC_NCE4_2
High
tv(NCE4_1-A)
th(NCE4_1-AI)
FSMC_A[10:0]
th(NCE4_1-NREG)
th(NCE4_1-NIORD)
th(NCE4_1-NIOWR)
td(NREG-NCE4_1)
td(NIORD-NCE4_1)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
td(NCE4_1-NWE)
tw(NWE)
td(NWE-NCE4_1)
FSMC_NWE
FSMC_NOE
MEMxHIZ =1
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FSMC_D[15:0]
ai14896b
74/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 32. PC Card/CompactFlash controller waveforms for attribute memory read
access
FSMC_NCE4_1
tv(NCE4_1-A)
FSMC_NCE4_2
th(NCE4_1-AI)
High
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
td(NREG-NCE4_1)
th(NCE4_1-NREG)
FSMC_NREG
FSMC_NWE
td(NCE4_1-NOE)
tw(NOE)
td(NOE-NCE4_1)
FSMC_NOE
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0](1)
ai14897b
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
Doc ID 16554 Rev 3
75/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 33. PC Card/CompactFlash controller waveforms for attribute memory write
access
FSMC_NCE4_1
FSMC_NCE4_2
High
tv(NCE4_1-A)
th(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
td(NREG-NCE4_1)
th(NCE4_1-NREG)
FSMC_NREG
td(NCE4_1-NWE)
tw(NWE)
FSMC_NWE
td(NWE-NCE4_1)
FSMC_NOE
tv(NWE-D)
FSMC_D[7:0](1)
ai14898b
1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).
Figure 34. PC Card/CompactFlash controller waveforms for I/O space read access
FSMC_NCE4_1
FSMC_NCE4_2
th(NCE4_1-AI)
tv(NCEx-A)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIOWR
tw(NIORD)
td(NIORD-NCE4_1)
FSMC_NIORD
tsu(D-NIORD)
td(NIORD-D)
FSMC_D[15:0]
ai14899B
76/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 35. PC Card/CompactFlash controller waveforms for I/O space write access
&3-#?.#%?
&3-#?.#%?
TV.#%X!
TH.#%?!)
&3-#?!;=
&3-#?.2%'
&3-#?.7%
&3-#?./%
&3-#?.)/2$
TD.#%?.)/72
TW.)/72
&3-#?.)/72
!44X():
TV.)/72$
TH.)/72$
&3-#?$;=
AIB
Table 40.
Switching characteristics for PC Card/CF read and write cycles in
attribute/common space
Symbol
Parameter
Min
Max
tv(NCEx-A)
FSMC_NCEx low to FSMC_Ay valid
-
0
th(NCEx-AI)
FSMC_NCEx high to FSMC_Ax invalid
0
-
td(NREG-NCEx)
FSMC_NCEx low to FSMC_NREG valid
-
2
th(NCEx-NREG)
FSMC_NCEx high to FSMC_NREG invalid
tHCLK + 4
-
td(NCEx_NWE)
FSMC_NCEx low to FSMC_NWE low
-
5tHCLK + 1
td(NCEx_NOE)
FSMC_NCEx low to FSMC_NOE low
-
5tHCLK + 1
tw(NOE)
FSMC_NOE low width
8tHCLK - 0.5
8tHCLK + 1
td(NOE-NCEx
FSMC_NOE high to FSMC_NCEx high
5tHCLK - 0.5
-
tsu(D-NOE)
FSMC_D[15:0] valid data before FSMC_NOE high
32
-
th(NOE-D)
FSMC_NOE high to FSMC_D[15:0] invalid
tHCLK
-
tw(NWE)
FSMC_NWE low width
8tHCLK – 1
8tHCLK + 4
td(NWE_NCEx)
FSMC_NWE high to FSMC_NCEx high
5tHCLK + 1.5
-
td(NCEx-NWE)
FSMC_NCEx low to FSMC_NWE low
-
5tHCLK + 1
tv(NWE-D)
FSMC_NWE low to FSMC_D[15:0] valid
-
0
th(NWE-D)
FSMC_NWE high to FSMC_D[15:0] invalid
11tHCLK
-
td(D-NWE)
FSMC_D[15:0] valid before FSMC_NWE high
13tHCLK + 2.5
-
Doc ID 16554 Rev 3
Unit
ns
77/120
Electrical characteristics
Table 41.
STM32F103xF, STM32F103xG
Switching characteristics for PC Card/CF read and write cycles in I/O space
Symbol
Parameter
tw(NIOWR)
Min
Max
Unit
8 THCLK
-
ns
-
5 THCLK 4
ns
11THCLK 7
-
ns
FSMC_NIOWR low width
tv(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid
th(NIOWR-D)
FSMC_NIOWR high to FSMC_D[15:0] invalid
td(NCE4_1-NIOWR)
FSMC_NCE4_1 low to FSMC_NIOWR valid
-
5THCLK +
1
ns
th(NCEx-NIOWR)
FSMC_NCEx high to FSMC_NIOWR invalid
5THCLK 2.5
-
ns
td(NIORD-NCEx)
FSMC_NCEx low to FSMC_NIORD valid
-
5THCLK 0.5
ns
th(NCEx-NIORD)
FSMC_NCEx high to FSMC_NIORD) valid
5 THCLK 0.5
-
ns
8THCLK
-
ns
tw(NIORD)
FSMC_NIORD low width
tsu(D-NIORD)
FSMC_D[15:0] valid before FSMC_NIORD high
28
ns
td(NIORD-D)
FSMC_D[15:0] valid after FSMC_NIORD high
3
ns
NAND controller waveforms and timings
Figure 36 through Figure 39 represent synchronous waveforms and Table 43 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
78/120
●
COM.FSMC_SetupTime = 0x00;
●
COM.FSMC_WaitSetupTime = 0x02;
●
COM.FSMC_HoldSetupTime = 0x01;
●
COM.FSMC_HiZSetupTime = 0x00;
●
ATT.FSMC_SetupTime = 0x00;
●
ATT.FSMC_WaitSetupTime = 0x02;
●
ATT.FSMC_HoldSetupTime = 0x01;
●
ATT.FSMC_HiZSetupTime = 0x00;
●
Bank = FSMC_Bank_NAND;
●
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
●
ECC = FSMC_ECC_Enable;
●
ECCPageSize = FSMC_ECCPageSize_512Bytes;
●
TCLRSetupTime = 0;
●
TARSetupTime = 0;
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 36. NAND controller waveforms for read access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NWE
td(ALE-NOE)
th(NOE-ALE)
FSMC_NOE (NRE)
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0]
ai14901b
Figure 37. NAND controller waveforms for write access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NWE)
th(NWE-ALE)
FSMC_NWE
FSMC_NOE (NRE)
tv(NWE-D)
th(NWE-D)
FSMC_D[15:0]
ai14902b
Figure 38. NAND controller waveforms for common memory read access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE)
th(NOE-ALE)
FSMC_NWE
tw(NOE)
FSMC_NOE
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0]
ai14912b
Doc ID 16554 Rev 3
79/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 39. NAND controller waveforms for common memory write access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE)
tw(NWE)
th(NOE-ALE)
FSMC_NWE
FSMC_NOE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FSMC_D[15:0]
ai14913b
Table 42.
Symbol
Switching characteristics for NAND Flash read cycles(1)
Parameter
Min
Max
Unit
3tHCLK – 1
3tHCLK + 1
ns
tw(NOE)
FSMC_NOE low width
tsu(D-NOE)
FSMC_D[15:0] valid data before FSMC_NOE
high
13
-
ns
th(NOE-D)
FSMC_D[15:0] valid data after FSMC_NOE high
0
-
ns
td(ALE-NOE)
FSMC_ALE valid before FSMC_NOE low
-
2tHCLK
ns
th(NOE-ALE)
FSMC_NWE high to FSMC_ALE invalid
2tHCLK
-
ns
1. CL = 15 pF.
Table 43.
Symbol
Switching characteristics for NAND Flash write cycles(1)
Parameter
Max
Unit
3tHCLK
3tHCLK
ns
-
0
ns
tw(NWE)
FSMC_NWE low width
tv(NWE-D)
FSMC_NWE low to FSMC_D[15:0] valid
th(NWE-D)
FSMC_NWE high to FSMC_D[15:0] invalid
2tHCLK + 2
-
ns
td(ALE-NWE)
FSMC_ALE valid before FSMC_NWE low
-
3tHCLK + 1.5
ns
th(NWE-ALE)
FSMC_NWE high to FSMC_ALE invalid
3tHCLK + 8
-
ns
td(ALE-NOE)
FSMC_ALE valid before FSMC_NOE low
-
2tHCLK
ns
th(NOE-ALE)
FSMC_NWE high to FSMC_ALE invalid
2tHCLK
-
ns
1. CL = 15 pF.
80/120
Min
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
5.3.11
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 44. They are based on the EMS levels and classes
defined in application note AN1709.
Table 44.
EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3 V, LQFP144, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK = 72 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP144, TA = +25 °C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical Data corruption (control registers...)
Doc ID 16554 Rev 3
81/120
Electrical characteristics
STM32F103xF, STM32F103xG
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be appFlied directly on the device, over the range
of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 45.
Symbol
SEMI
5.3.12
EMI characteristics
Parameter
Peak level
Conditions
Max vs. [fHSE/fHCLK]
Monitored
frequency band
Unit
8/48 MHz 8/72 MHz
0.1 to 30 MHz
VDD = 3.3 V, TA = 25 °C,
30 to 130 MHz
LQFP144 package
compliant with IEC
130 MHz to 1GHz
61967-2
SAE EMI Level
8
12
31
21
28
33
4
4
dBµV
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 46.
Symbol
VESD(HBM)
ESD absolute maximum ratings
Ratings
Conditions
Class Maximum value(1) Unit
Electrostatic discharge
TA = +25 °C, conforming
2
voltage (human body model) to JESD22-A114
Electrostatic discharge
TA = +25 °C, conforming
II
VESD(CDM)
voltage (charge device model) to JESD22-C101
1. Based on characterization results, not tested in production.
82/120
Doc ID 16554 Rev 3
2000
V
500
STM32F103xF, STM32F103xG
Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 47.
Symbol
LU
5.3.13
Electrical sensitivities
Parameter
Static latch-up class
Conditions
Class
TA = +105 °C conforming to JESD78A
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 48
Table 48.
I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
Description
Negative
injection
Positive
injection
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0
+0
Injected current on all FT pins
-5
+0
Injected current on any other pin
-5
+5
Doc ID 16554 Rev 3
Unit
mA
83/120
Electrical characteristics
5.3.14
STM32F103xF, STM32F103xG
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL
compliant.
Table 49.
Symbol
VIL
VIH
Vhys
Ilkg
I/O static characteristics
Parameter
Min
Typ
Max
Unit
Standard IO input low
level voltage
–0.3
-
0.28*(VDD-2
V)+0.8 V
V
IO FT(1) input low level
voltage
–0.3
-
0.32*(VDD-2
V)+0.75 V
V
Standard IO input high
level voltage
0.41*(VDD-2
V)+1.3 V
-
VDD+0.3
V
0.42*(VDD-2
V)+1 V
-
Standard IO Schmitt
trigger voltage
hysteresis(2)
200
-
-
mV
IO FT Schmitt trigger
voltage hysteresis(2)
5% VDD(3)
-
-
mV
VSS ≤VIN ≤VDD
Standard I/Os
-
-
±1
VIN= 5 V, I/O FT
-
-
3
IO FT(1) input high level
voltage
Input leakage current (4)
Conditions
VDD > 2 V
VDD ≤2 V
5.5
V
5.2
µA
RPU
Weak pull-up equivalent
resistor(5)
VIN = VSS
30
40
50
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
30
40
50
kΩ
CIO
I/O pin capacitance
-
5
-
pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 40 and Figure 41 for standard I/Os, and
in Figure 42 and Figure 43 for 5 V tolerant I/Os.
84/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 40. Standard I/O input characteristics - CMOS port
6)(6),6
6 6 )( $$
6 $$
MENT6 )(
QUIRE
NDARDRE
TA
#-/3S
7)(MIN
7),MAX
6 ),6 ##
T6 ),6 $$
RDREQUIREMEN
#-/3STANDA
)NPUTRANGE
NOTGUARANTEED
6$$6
AIB
Figure 41. Standard I/O input characteristics - TTL port
6)(6),6
7)(MIN
44,REQUIREMENTS 6)( 6
6 6 )( $$
)NPUTRANGE
NOTGUARANTEED
7),MAX
6 ),6 $$
44,REQUIREMENTS 6),6
6$$6
AI
Doc ID 16554 Rev 3
85/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 42. 5 V tolerant I/O input characteristics - CMOS port
6)(6),6
6 $$
TS6 )(
UIREMEN
REQ
TANDARD
#-/3S
)NPUTRANGE
NOTGUARANTEED
6 ),6 $$
T6 ),6 $$
REQUIRMEN
/3STANDARD
#-
6 )(6 $$
6$$6
6$$
AIB
Figure 43. 5 V tolerant I/O input characteristics - TTL port
6)(6),6
44,REQUIREMENT6 )(6
6 6 )(
$$
7)(MIN
7),MAX
)NPUTRANGE
NOTGUARANTEED
6 ),
6 $$
44,REQUIREMENTS6 ),6
6$$6
AI
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxedVOL/VOH) except PC13, PC14 and PC15 which can sink
or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
86/120
●
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 8).
●
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 8).
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10. All I/Os are CMOS and TTL compliant.
Table 50.
Symbol
VOL(1)
VOH
(2)
VOL (1)
VOH
(2)
Output voltage characteristics
Parameter
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
VOL(1)(4)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
VOL(1)(4)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Conditions
Min
Max
TTL port(3)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
0.4
CMOS port(3)
IIO =+ 8mA
2.7 V < VDD < 3.6 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
IIO = +6 mA
2 V < VDD < 2.7 V
Unit
V
VDD–0.4
-
-
0.4
V
2.4
-
-
1.3
V
VDD–1.3
-
-
0.4
V
VDD–0.4
-
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
4. Based on characterization data, not tested in production.
Doc ID 16554 Rev 3
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Electrical characteristics
STM32F103xF, STM32F103xG
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 44 and
Table 51, respectively.
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10.
Table 51.
I/O AC characteristics(1)
MODEx[1:0]
Symbol
bit value(1)
Parameter
Conditions
Min
Max
Unit
-
2
MHz
-
125(3)
-
125(3)
-
10
-
25(3)
-
25(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30
MHz
CL = 50 pF, VDD = 2 V to 2.7 V
-
20
MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
10
-
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
10
tf(IO)out
Output high to low
level fall time
tr(IO)out
Output low to high
level rise time
CL = 50 pF, VDD = 2 V to 3.6 V
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
01
tf(IO)out
Output high to low
level fall time
tr(IO)out
Output low to high
level rise time
Fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
-
tEXTIpw
frequency(2)
Output high to low
level fall time
Output low to high
level rise time
ns
CL = 50 pF, VDD = 2 V to 3.6 V
Pulse width of
external signals
detected by the EXTI
controller
MHz
ns
ns
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 44.
3. Guaranteed by design, not tested in production.
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STM32F103xF, STM32F103xG
Electrical characteristics
Figure 44. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXT ERNAL
OUTPUT
ON 50pF
tr(I O)out
tr(I O)out
T
Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
5.3.15
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 49).
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10.
Table 52.
NRST pin characteristics
Symbol
Parameter
Min
Typ
Max
–0.5
-
0.8
VIH(NRST)(1) NRST Input high level voltage
2
-
VDD+0.5
NRST Schmitt trigger voltage
hysteresis
-
200
-
mV
30
40
50
kΩ
-
-
100
ns
300
-
-
ns
VIL(NRST)(1)
Conditions
NRST Input low level voltage
Vhys(NRST)
Weak pull-up equivalent resistor(2)
RPU
VF(NRST)(1)
NRST Input filtered pulse
VNF(NRST)(1)
NRST Input not filtered pulse
Unit
V
VIN = VSS
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 45. Recommended NRST pin protection
VDD
External
reset circuit(1)
NRST(2)
RPU
Internal Reset
Filter
0.1 µF
STM32F10xxx
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 52. Otherwise the reset will not be taken into account by the device.
Doc ID 16554 Rev 3
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Electrical characteristics
5.3.16
STM32F103xF, STM32F103xG
TIM timer characteristics
The parameters given in Table 53 are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 53.
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
TIMx(1) characteristics
Parameter
Conditions
Min
Max
Unit
1
-
tTIMxCLK
13.9
-
ns
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 72 MHz
0
fTIMxCLK/2
MHz
0
36
MHz
Timer resolution
-
16
bit
65536
tTIMxCLK
910
µs
-
65536 × 65536
tTIMxCLK
-
59.6
s
Timer resolution time
fTIMxCLK = 72 MHz
16-bit counter clock period
1
when internal clock is
fTIMxCLK = 72 MHz 0.0139
selected
tMAX_COUNT Maximum possible count
fTIMxCLK = 72 MHz
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
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STM32F103xF, STM32F103xG
5.3.17
Electrical characteristics
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions
summarized in Table 10.
The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG
performance line I2C interface meets the requirements of the standard I2C communication
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 54. Refer also to Section 5.3.14: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 54.
I2C characteristics
Standard mode I2C(1)
Symbol
Fast mode I2C(1)(2)
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
0(3)
-
0(4)
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
Cb
Capacitive load for each bus
line
-
400
-
400
pF
µs
ns
µs
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast
mode maximum clock speed of 400 kHz.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
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Electrical characteristics
STM32F103xF, STM32F103xG
Figure 46. I2C bus AC waveforms and measurement circuit
VDD
VDD
4 .7 k
4 .7 k
STM32F103xx
100
SDA
I2C bus
100
SCL
S TART REPEATED
S TART
S TART
tsu(STA)
SDA
tf(SDA)
tr(SDA)
th(STA)
SCL
tw(SCLH)
tsu(SDA)
tw(SCLL)
tr(SCL)
th(SDA)
tw(STO:STA)
S TOP
tsu(STO)
tf(SCL)
ai14149c
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 55.
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
0x801E
300
0x8028
200
0x803C
100
0x00B4
50
0x0168
20
0x0384
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
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STM32F103xF, STM32F103xG
Electrical characteristics
I2S - SPI characteristics
Unless otherwise specified, the parameters given in Table 56 for SPI or in Table 57 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 56.
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
DuCy(SCK)
SPI characteristics
Parameter
Conditions
Min
Max
Master mode
-
18
Slave mode
-
18
Capacitive load: C = 30 pF
-
8
ns
30
70
%
SPI clock frequency
SPI clock rise and fall
time
MHz
SPI slave input clock duty
Slave mode
cycle
tsu(NSS)(1)
NSS setup time
Slave mode
4tPCLK
-
th(NSS)(1)
NSS hold time
Slave mode
2tPCLK
-
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
Master mode
5
-
Slave mode
5
-
Master mode
5
-
Slave mode
4
-
(1)
tw(SCKH)
tw(SCKL)(1)
tsu(MI) (1)
tsu(SI)(1)
th(MI)
Data input setup time
(1)
th(SI)(1)
Data input hold time
ta(SO)(1)(2)
Data output access time
Slave mode, fPCLK = 20 MHz
0
3tPCLK
tdis(SO)(1)(3)
Data output disable time
Slave mode
2
10
(1)
Data output valid time
Slave mode (after enable edge)
-
25
tv(MO)(1)
Data output valid time
Master mode (after enable edge)
-
5
Slave mode (after enable edge)
15
-
Master mode (after enable edge)
2
-
tv(SO)
th(SO)(1)
th(MO)
(1)
Unit
ns
Data output hold time
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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Electrical characteristics
STM32F103xF, STM32F103xG
Figure 47. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tSU(NSS)
SCK Input
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
th(SI)
ai14134c
Figure 48. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tSU(NSS)
SCK Input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
B I T1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM32F103xF, STM32F103xG
Electrical characteristics
Figure 49. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
CPHA= 0
CPOL=0
SCK Input
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MS BIN
tr(SCK)
tf(SCK)
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics
Table 57.
STM32F103xF, STM32F103xG
I2S characteristics
Symbol
DuCy(SCK)
Parameter
Conditions
Min
Max
Unit
30
70
%
1.522
1.525
Slave mode
0
6.5
I2S slave input clock duty cycle Slave mode
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
fCK
1/tc(CK)
I S clock frequency
tr(CK)
tf(CK)
I2S clock rise and fall time
Capacitive load CL = 50 pF
-
8
tv(WS) (1)
WS valid time
Master mode
3
-
th(WS) (1)
I2S2
2
-
WS hold time
Master mode
I2S3
0
-
tsu(WS)
th(WS)
2
(1)
(1)
tw(CKH) (1)
tw(CKL)
(1)
WS setup time
Slave mode
4
-
WS hold time
Slave mode
0
-
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
312.5
-
CK high and low time
345
-
I2S2
2
-
I2S3
6.5
-
1.5
-
Master receiver
0
-
Slave receiver
0.5
-
tsu(SD_MR) (1)
Data input setup time
tsu(SD_SR) (1)
Data input setup time
th(SD_MR)
(1)(2)
th(SD_SR)
(1)(2)
MHz
Master receiver
Slave receiver
Data input hold time
tv(SD_ST) (1)(2)
Data output valid time
Slave transmitter (after enable
edge)
-
18
th(SD_ST) (1)
Data output hold time
Slave transmitter (after enable
edge)
11
-
tv(SD_MT) (1)(2)
Data output valid time
Master transmitter (after enable
edge)
-
3
th(SD_MT) (1)
Data output hold time
Master transmitter (after enable
edge)
0
-
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
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ns
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 50. I2S slave timing diagram (Philips protocol)(1)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
Bitn transmit
tsu(SD_SR)
LSB receive(2)
SDreceive
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 51. I2S master timing diagram (Philips protocol)(1)
tf(CK)
tr(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(2)
MSB transmit
LSB receive(2)
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
Bitn transmit
th(SD_MT)
MSB receive
Bitn receive
LSB receive
ai14884b
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Doc ID 16554 Rev 3
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Electrical characteristics
STM32F103xF, STM32F103xG
SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 10.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (D[7:0], CMD, CK).
Figure 52. SDIO high-speed mode
tf
tr
tC
tW(CKH)
tW(CKL)
CK
tOV
tOH
D, CMD
(output)
tISU
tIH
D, CMD
(input)
ai14887
Figure 53. SD default mode
CK
tOVD
tOHD
D, CMD
(output)
ai14888
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STM32F103xF, STM32F103xG
Table 58.
Electrical characteristics
SD / MMC characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
Clock frequency in data transfer
mode
CL ≤ 30 pF
0
48
tW(CKL)
Clock low time, fPP = 16 MHz
CL ≤ 30 pF
32
-
tW(CKH)
Clock high time, fPP = 16 MHz
CL ≤ 30 pF
30
-
tr
Clock rise time
CL ≤ 30 pF
-
4
tf
Clock fall time
CL ≤ 30 pF
-
5
fPP
ns
CMD, D inputs (referenced to CK)
tISU
Input setup time
CL ≤ 30 pF
2
-
tIH
Input hold time
CL ≤ 30 pF
0
-
ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
Output valid time
CL ≤ 30 pF
-
6
tOH
Output hold time
CL ≤ 30 pF
0
-
ns
CMD, D outputs (referenced to CK) in SD default mode(1)
tOVD
Output valid default time
CL ≤ 30 pF
-
7
tOHD
Output hold default time
CL ≤ 30 pF
0.5
-
ns
1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 59.
USB startup time
Symbol
tSTARTUP(1)
Parameter
USB transceiver startup time
Max
Unit
1
µs
1. Guaranteed by design, not tested in production.
Doc ID 16554 Rev 3
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Electrical characteristics
Table 60.
STM32F103xF, STM32F103xG
USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1)
Unit
3.0(3)
3.6
V
V
Input levels
VDD
(4)
USB operating voltage(2)
I(USBDP, USBDM)
0.2
VCM(4)
Differential common mode range Includes VDI range
0.8
2.5
VSE(4)
Single ended receiver threshold
1.3
2.0
VDI
Differential input sensitivity
Output levels
VOL
Static output level low
RL of 1.5 kΩ to 3.6 V(5)
VOH
Static output level high
RL of 15 kΩ to VSS(5)
0.3
V
2.8
3.6
1. All the voltages are measured from the local ground potential.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. Guaranteed by characterization, not tested in production.
5. RL is the load connected on the USB drivers
Figure 54. USB timings: definition of data signal rise and fall time
Crossover
points
Differen tial
data lines
VCRS
VS S
Table 61.
tr
tf
ai14137
USB: full-speed electrical characteristics
Driver characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tr
Rise time(2)
CL = 50 pF
4
20
ns
tf
(2)
CL = 50 pF
4
20
ns
tr/tf
90
110
%
1.3
2.0
V
trfm
VCRS
Fall Time
Rise/ fall time matching
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
5.3.18
CAN (controller area network) interface
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
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STM32F103xF, STM32F103xG
5.3.19
Electrical characteristics
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 62 are preliminary values derived
from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 10.
Note:
It is recommended to perform a calibration after each power-up.
Table 62.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
2.4
-
3.6
V
VREF+
Positive reference voltage
2.4
-
VDDA
V
IVREF
Current on the VREF input
pin
-
160
220(1)
µA
fADC
ADC clock frequency
0.6
-
14
MHz
fS(2)
Sampling rate
0.05
-
1
MHz
-
-
823
kHz
-
-
17
1/fADC
0 (VSSA or VREFtied to ground)
-
VREF+
V
-
-
50
kΩ
fTRIG(2)
VAIN
fADC = 14 MHz
External trigger frequency
Conversion voltage range(3)
See Equation 1 and
Table 63 for details
RAIN(2)
External input impedance
RADC(2)
Sampling switch resistance
-
-
1
kΩ
CADC(2)
Internal sample and hold
capacitor
-
-
8
pF
tCAL(2)
Calibration time
fADC = 14 MHz
tlat(2)
Injection trigger conversion
latency
fADC = 14 MHz
tlatr(2)
Regular trigger conversion
latency
fADC = 14 MHz
tS(2)
Sampling time
tSTAB(2)
Power-up time
tCONV(2)
Total conversion time
(including sampling time)
fADC = 14 MHz
fADC = 14 MHz
5.9
µs
83
1/fADC
-
-
0.214
µs
-
-
3(4)
1/fADC
-
-
0.143
µs
(4)
1/fADC
-
-
2
0.107
-
17.1
µs
1.5
-
239.5
1/fADC
0
0
1
µs
18
µs
1
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pinouts and pin descriptions for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 62.
Doc ID 16554 Rev 3
101/120
Electrical characteristics
STM32F103xF, STM32F103xG
Equation 1: RAIN max formula
TS
- – R ADC
R AIN < --------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 63.
RAIN max for fADC = 14 MHz(1)
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
0.11
0.4
7.5
0.54
5.9
13.5
0.96
11.4
28.5
2.04
25.2
41.5
2.96
37.2
55.5
3.96
50
71.5
5.11
NA
239.5
17.1
NA
1. Guaranteed by design, not tested in production.
Table 64.
Symbol
ADC accuracy - limited test conditions(1)(2)
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Test conditions
Typ
Max(3)
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
Measurements made after
ADC calibration
VREF+ = VDDA
±1.3
±2
±1
±1.5
±0.5
±1.5
±0.7
±1
±0.8
±1.5
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not
affect the ADC accuracy.
3. Based on characterisation, not tested in production.
102/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Table 65.
Electrical characteristics
ADC accuracy(1) (2)(3)
Symbol
Parameter
ET
Test conditions
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
Measurements made after
ADC calibration
Typ
Max(4)
±2
±5
±1.5
±2.5
±1.5
±3
±1
±2
±1.5
±3
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not
affect the ADC accuracy.
4. Preliminary values.
Figure 55. ADC accuracy characteristics
V
V
[1LSBIDEAL = REF+ (or DDA depending on package)]
4096
4096
EG
4095
4094
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4093
(2)
ET
(3)
7
(1)
6
5
4
EO
EL
3
ED
2
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
Doc ID 16554 Rev 3
ai14395b
103/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 56. Typical connection diagram using the ADC
VDD
RAIN(1)
VAIN
VT
0.6 V
AINx
Cparasitic
VT
0.6 V
IL±1 µA
STM32F103xx
Sample and hold ADC
converter
RADC(1)
12-bit
converter
CADC(1)
ai14150c
1. Refer to Table 62 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 57 or Figure 58,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F103xx
VREF+
(see note 1)
1 µF // 10 nF
VDDA
1 µF // 10 nF
VSSA /VREF–
(see note 1)
ai14388b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
104/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 58. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F103xx
VREF+/VDDA
(See note 1)
1 µF // 10 nF
VREF–/VSSA
(See note 1)
ai14389
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Doc ID 16554 Rev 3
105/120
Electrical characteristics
STM32F103xF, STM32F103xG
5.3.20
DAC electrical specifications
Table 66.
DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VDDA
Analog supply voltage
2.4
-
3.6
V
VREF+
Reference supply voltage
2.4
-
3.6
V
VSSA
Ground
0
-
0
V
Resistive load vs. VSSA with
buffer ON
5
-
-
kΩ
Resistive load vs. VDDA with
buffer ON
15
-
-
kΩ
RLOAD
(1)
Comments
VREF+ must always be below VDDA
RO(1)
Impedance output with buffer
OFF
-
-
15
When the buffer is OFF, the Minimum
resistive load between DAC_OUT
kΩ
and VSS to have a 1% accuracy is
1.5 MΩ
CLOAD(1)
Capacitive load
-
-
50
Maximum capacitive load at
pF DAC_OUT pin (when the buffer is
ON).
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V
and (0x155) and (0xEAB) at VREF+ =
2.4 V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
0.2
-
-
V
DAC_OUT Higher DAC_OUT voltage
with buffer ON
max(1)
-
-
VDDA – 0.2
V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
-
0.5
DAC_OUT Higher DAC_OUT voltage
with buffer OFF
max(1)
-
VREF+ –
10 mV
IDDVREF+
DAC DC current
consumption in quiescent
mode (Standby mode)
-
380
With no load, worst code (0x0E4) at
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
-
380
µA
IDDA
DAC DC current
consumption in quiescent
mode (Standby mode)
-
480
With no load, worst code (0xF1C) at
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
-
±0.5
LSB
Given for the DAC in 10-bit
configuration
-
±3
LSB
Given for the DAC in 12-bit
configuration
DNL(2)
106/120
Differential non linearity
Difference between two
consecutive code-1LSB)
mV
Doc ID 16554 Rev 3
It gives the maximum output
excursion of the DAC.
V
With no load, middle code (0x800) on
the inputs
STM32F103xF, STM32F103xG
Table 66.
DAC characteristics (continued)
Symbol
INL(2)
Electrical characteristics
Parameter
Min
Typ
Max
Unit
-
-
±1
LSB
Given for the DAC in 10-bit
configuration
-
-
±4
LSB
Given for the DAC in 12-bit
configuration
-
-
±10
mV
Given for the DAC in 12-bit
configuration
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
Comments
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
-
-
±3
LSB
Given for the DAC in 10-bit at VREF+
= 3.6 V
-
-
±12
LSB
Given for the DAC in 12-bit at VREF+
= 3.6 V
Gain error
-
-
±0.5
%
Given for the DAC in 12bit
configuration
Settling time (full scale: for a
10-bit input code transition
(2) between the lowest and the
tSETTLING
highest input codes when
DAC_OUT reaches final
value ±1LSB
-
3
4
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-
-
1
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Wakeup time from off state
tWAKEUP(2) (Setting the ENx bit in the
DAC Control register)
-
6.5
10
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and
highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
-
–67
–40
dB
No RLOAD, CLOAD = 50 pF
Offset(2)
Gain
error(2)
Update
rate(2)
1. Guaranteed by design, not tested in production.
2. Preliminary values.
Figure 59. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R LOAD
12-bit
digital to
analog
converter
DACx_OUT
C LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
Doc ID 16554 Rev 3
107/120
Electrical characteristics
5.3.21
STM32F103xF, STM32F103xG
Temperature sensor characteristics
Table 67.
TS characteristics
Symbol
TL(1)
Avg_Slope
V25
Parameter
Min
Typ
Max
Unit
-
±1
±2
°C
Average slope
4.0
4.3
4.6
mV/°C
Voltage at 25 °C
1.34
1.43
1.52
V
VSENSE linearity with temperature
(1)
(1)
tSTART(2)
Startup time
4
-
10
µs
TS_temp(3)(2)
ADC sampling time when reading the
temperature
-
-
17.1
µs
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
108/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Package characteristics
6
Package characteristics
6.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 60. Recommended PCB design rules (0.80/0.75 mm pitch BGA
Dpad
Dpad
0.37 mm
Dsm
0.52 mm typ. (depends on solder mask
registration tolerance
Solder paste
0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dsm
ai15469
Doc ID 16554 Rev 3
109/120
Package characteristics
STM32F103xF, STM32F103xG
Figure 61. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline
C Seating plane
A2
ddd
A4
C
A
A3
A1
B
D
D1
A
e
F
M
F
E1 E
e
Øb (144 balls)
Ball A1
Ø eee M C A
Ø fff M
B
C
X3_ME
1. Drawing is not to scale.
Table 68.
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package data
inches(1)
millimeters
Symbol
Min
Typ
A
A1
Max
Typ
1.70
0.21
Max
0.0669
0.0083
A2
1.07
0.0421
A3
0.27
0.0106
A4
0.85
0.0335
b
0.35
0.40
0.45
0.0138
0.0157
0.0177
D
9.85
10.00
10.15
0.3878
0.3937
0.3996
D1
E
8.80
9.85
10.00
0.3465
10.15
0.3878
0.3937
E1
8.80
0.3465
e
0.80
0.0315
F
0.60
0.0236
ddd
0.10
0.0039
eee
0.15
0.0059
fff
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
110/120
Min
Doc ID 16554 Rev 3
0.3996
STM32F103xF, STM32F103xG
Package characteristics
Figure 62. LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline(1)
Figure 63. Recommended
footprint(1)(2)
Seating plane
C
A
A2 A1
c
b
ccc
0.25 mm
gage plane
C
108
109
D
73
1.35
72
0.35
k
D1
0.5
A1
D3
L
73
108
L1
17.85
19.9
22.6
72
109
144
E1
E
37
1
36
E3
19.9
22.6
ai149
144
Pin 1
identification
37
36
1
e
ME_1A
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 69.
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
D
21.80
D1
Max
0.063
0.15
0.002
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
22.00
22.20
0.8583
0.8661
0.874
19.80
20.00
20.20
0.7795
0.7874
0.7953
E
21.80
22.00
22.20
0.8583
0.8661
0.874
E1
19.80
20.00
20.20
0.7795
0.7874
0.7953
D3
17.50
0.0059
0.0079
0.689
E3
17.50
0.689
e
0.50
0.0197
L
0.45
L1
k
ccc
0.60
0.75
0.0177
1.00
0°
3.5°
0.0236
0.0295
0.0394
7°
0.08
0°
3.5°
7°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 16554 Rev 3
111/120
Package characteristics
STM32F103xF, STM32F103xG
Figure 64. LQFP100, 14 x 14 mm 100-pin low-profile
quad flat package outline(1)
Figure 65. Recommended footprint(1)(2)
0.25 mm
0.10 inch
GAGE PLANE
k
75
51
D
L
D1
76
L1
D3
51
75
50
0.5
C
76
50
0.3
16.7
14.3
b
E3 E1 E
100
26
1.2
100
26
Pin 1
1
identification
1
25
ccc
25
C
12.3
e
A1
16.7
ai14906b
A2
A
SEATING PLANE
C
1L_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 70.
LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
D
15.80
D1
13.80
D3
Max
0.063
0.15
0.002
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
16.00
16.20
0.622
0.6299
0.6378
14.00
14.20
0.5433
0.5512
0.5591
12.00
0.0059
0.0079
0.4724
E
15.80
16.00
16.20
0.622
0.6299
0.6378
E1
13.80
14.00
14.20
0.5433
0.5512
0.5591
E3
12.00
e
L
0.50
0.45
L1
k
ccc
0.4724
0.60
0.0197
0.75
1.00
0°
3.5°
0.0236
0.0295
0.0394
7°
0.08
0°
3.5°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
112/120
0.0177
Doc ID 16554 Rev 3
7°
STM32F103xF, STM32F103xG
Package characteristics
Figure 67. Recommended footprint(1)(2)
Figure 66. LQFP64 – 10 x 10 mm 64 pin low-profile
quad flat package outline(1)
48
33
D
0.3
ccc C
D1
A
A2
D3
33
48
49
32
49
12.7
32
0.5
10.3
b
L1
10.3
E3 E1 E
64
L
A1
K
1.2
64
1
17
Pin 1
identification
16
1
17
c
16
7.8
5W_ME
12.7
ai14909
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 71.
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.170
c
0.090
D
11.800
D1
9.800
D.
Max
0.0630
0.150
0.0020
0.0059
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
12.000
12.200
0.4646
0.4724
0.4803
10.000
10.200
0.3858
0.3937
0.4016
0.0079
7.500
E
11.800
12.000
12.200
0.4646
0.4724
0.4803
E1
9.800
10.00
10.200
0.3858
0.3937
0.4016
e
0.500
0.0197
k
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.75
0.0177
0.0236
0.0295
L1
1.000
0.0394
ccc
0.080
0.0031
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 16554 Rev 3
113/120
Package characteristics
6.2
STM32F103xF, STM32F103xG
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 10: General operating conditions on page 41.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
●
TA max is the maximum ambient temperature in °C,
●
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
●
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
●
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 72.
Package thermal characteristics
Symbol
ΘJA
6.2.1
Parameter
Value
Thermal resistance junction-ambient
LFBGA144 - 10 × 10 mm / 0.8 mm pitch
40
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch
30
Unit
°C/W
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
46
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
114/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
6.2.2
Package characteristics
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 73: STM32F103xF and STM32F103xG ordering
information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F103xF and STM32F103xG at maximum
dissipation, it is useful to calculate the exact power consumption and junction temperature to
determine which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 72 TJmax is calculated as follows:
–
For LQFP100, 46 °C/W
TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 73: STM32F103xF and STM32F103xG ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
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Package characteristics
STM32F103xF, STM32F103xG
Using the values obtained in Table 72 TJmax is calculated as follows:
–
For LQFP100, 46 °C/W
TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C
This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 73: STM32F103xF and STM32F103xG ordering information scheme).
Figure 68. LQFP100 PD max vs. TA
700
PD (mW)
600
500
Suffix 6
400
Suffix 7
300
200
100
0
65
75
85
95
105
115
TA (°C)
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135
STM32F103xF, STM32F103xG
7
Part numbering
Part numbering
Table 73.
STM32F103xF and STM32F103xG ordering information scheme
Example:
STM32 F103 RF T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
103 = performance line
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Flash memory size
F = 768 Kbytes of Flash memory
G = 1 Mbyte of Flash memory
Package
H = BGA
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and real
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Revision history
8
STM32F103xF, STM32F103xG
Revision history
Table 74.
Document revision history
Date
Revision
27-Oct-2009
1
Initial release.
2
LQFP64 package mechanical data updated: see Figure 66: LQFP64 –
10 x 10 mm 64 pin low-profile quad flat package outline and Table 71:
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical
data.
Internal code removed from Table 73: STM32F103xF and
STM32F103xG ordering information scheme.
Updated note 2 below Table 54: I2C characteristics
Updated Figure 46: I2C bus AC waveforms and measurement circuit
Updated Figure 45: Recommended NRST pin protection
Updated note 1 below Table 49: I/O static characteristics
Updated Table 20: Peripheral current consumption
Updated Table 14: Maximum current consumption in Run mode, code
with data processing running from Flash
Updated Table 15: Maximum current consumption in Run mode, code
with data processing running from RAM
Updated Table 16: Maximum current consumption in Sleep mode, code
running from Flash or RAM
Updated Table 17: Typical and maximum current consumptions in Stop
and Standby modes
Updated Table 18: Typical current consumption in Run mode, code with
data processing running from Flash
Updated Table 19: Typical current consumption in Sleep mode, code
running from Flash or RAM
Updated Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz)
Updated Figure 22: Asynchronous non-multiplexed
SRAM/PSRAM/NOR read waveforms on page 62
Added Section 5.3.13: I/O current injection characteristics on page 83
3
Section 2.3.26: GPIOs (general-purpose inputs/outputs): modified text
of last sentence.
Table 5: STM32F103xF and STM32F103xG pin definitions: updated
pins PD0, PD1, OSC_IN, OSC_OUT, PB8, PB9, and PF8.
Table 7: Voltage characteristics: Removed the previous footnotes 2 and
3 and added current footnote 2.
Table 8: Current characteristics: updated footnotes 3, 4, and 5.
Table 21: High-speed external user clock characteristics: replaced the
tw(HSE) min value by 5 (instead of 16).
Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz): updated
symbols and footnotes.
15-Nov-2010
18-Jan-2012
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Changes
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STM32F103xF, STM32F103xG
Table 74.
Revision history
Document revision history
Date
18-Jan-2012
Revision
Changes
3
Asynchronous waveforms and timings: added notes about tHCLK clock
period and FSMC_BusTurnAroundDuration; updated conditions,
modified Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR
read timings, Table 32: Asynchronous non-multiplexed
SRAM/PSRAM/NOR write timings, Table 34: Asynchronous multiplexed
PSRAM/NOR read timings, and Table 35: Asynchronous multiplexed
PSRAM/NOR write timings; added Table 33: Asynchronous read
muxed.
Synchronous waveforms and timings: updated Figure 27: Synchronous
multiplexed PSRAM write timings; updated Table 36: Synchronous
multiplexed NOR/PSRAM read timings, Table 37: Synchronous
multiplexed PSRAM write timings, Table 38: Synchronous nonmultiplexed NOR/PSRAM read timings, and Table 39: Synchronous
non-multiplexed PSRAM write timings.
PC Card/CompactFlash controller waveforms and timings: updated
Figure 35: PC Card/CompactFlash controller waveforms for I/O space
write access; split switching characteristics into Table 40: Switching
characteristics for PC Card/CF read and write cycles in
attribute/common space and Table 41: Switching characteristics for PC
Card/CF read and write cycles in I/O space, modified values, and
removed footnote concerning preliminary values.
NAND controller waveforms and timings: updated conditions, split
switching characteristics into Table 42: Switching characteristics for
NAND Flash read cycles and Table 43: Switching characteristics for
NAND Flash write cycles, and values modified.
Section 5.3.14: I/O port characteristics: updated footnote1 of Table 49:
I/O static characteristics; updated Output driving current.
Table 50: Output voltage characteristics: swapped “TTL and “CMOS”
ports in the conditions column.
Table 54: I2C characteristics: updated footnote 2.
Updated Table 58: SD / MMC characteristics.
Table 62: ADC characteristics: updated footnote 1.
Table 64: ADC accuracy - limited test conditions: updated footnote 3.
Table 67: TS characteristics: updated footnote 1.
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STM32F103xF, STM32F103xG
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