VC-806 LVPECL, LVDS Crystal Oscillator Data Sheet VC-806 Description Vectron’s VC-806 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off either a 2.5 or 3.3 volt supply in a hermetically sealed 3.2x5 ceramic package. Features • • • • • • • Applications Ultra Low Jitter Performance, Fundamental or 3rd OT Crystal Design Output Frequencies to 320.000MHz <0.7 ps RMS jitter, 12kHz-20MHz Differential Output Enable/Disable -10/70°C or -40/85°C Operation Hermetically Sealed 3.2x5 Ceramic Package • Product is compliant to RoHS directive and fully compatible with lead free assembly • • • • • • • • • Storage Area Networking Telecom Ethernet, GE, SynchE Fiber Channel PON Driving A/D’s, D/A’s, FPGA’s Test and Measurement Medical COTS Block Diagram VDD Complementary Output Output Crystal Oscillator E/D or NC E/D or NC Gnd Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page1 Performance Specifications Table 1. Electrical Performance, LVPECL Option Parameter Symbol Min Typ Max Units 3.3 2.5 3.465 2.625 V 50 75 mA 320.000 MHz Supply Voltage1 VDD Current (No Load) IDD 3.135 2.375 Frequency Nominal Frequency2 fN 25 2,3 Stability (Ordering Option) ±25, ±50, ±100 ppm Outputs Output Logic Levels4, -10/70°C Output Logic High Output Logic Low VOH VOL VDD-1.025 VDD-1.810 VDD-0.880 VDD-1.620 Output Logic Levels4, -40/85°C Output Logic High Output Logic Low VOH VOL VDD-1.085 VDD-1.830 VDD-0.880 VDD-1.555 Output Rise and Fall Time4 Rise Time Fall Time V V tR tF ps ps 50 55 % 0.3 0.7 ps 50 ohms into VDD-1.3V Load Duty Cycle 600 600 5 45 6 Jitter (12 kHz - 20 MHz BW) 7 Period Jitter RMS P/P Random Jitter Deterministic Jitter фJ фJ 2.6 23 2.6 <0.2 RJ DJ ps ps ps ps Enable/Disable 8 Output Enabled Output Disabled VIH VIL Enable/Disable Time tD 0.7*VDD Enable/Disable Leakage Current Enable Pull-Up Resistor Output Enabled Output Disabled V V 200 ns ±200 uA 33 1 Start-Up Time tSU Operating Temp. (Ordering Option) TOP Package Size 0.3*VDD KOhm MOhm 10 ms -10/70 or -40/85 °C 3.2x5.0x1.3 mm 1. The VC-806 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor. 2. See Standard Frequencies and Ordering Information for more information. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Figure 2 defines these parameters and Figure 1 defines the test circuit. 5. Duty Cycle is defines as the On/Time Period. 6. Measured using an Agilent E5052, 156.25MHz. 7. Measured using a Wavecrest SIA3300C, 90K samples. 8. Outputs will be Enabled if Enable/Disable is left open. Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page2 Performance Specifications Table 2. Electrical Performance, LVDS Option Parameter Symbol Min Typ Max Units 3.3 2.5 3.465 2.625 V 60 mA Supply 1 Voltage VDD Current (No Load) IDD 3.135 2.375 Frequency 2 Nominal Frequency fN 80 Stability2,3 (Ordering Option) 320.000 ±25, ±50, ±100 MHz ppm Outputs Output Logic Levels Output Logic High Output Logic Low 4 V VOH VOL 1.6 0.9 1.43 1.10 Output Swing 247 330 454 Differential Output Swing 494 660 908 mV 50 mV 1.375 V Offset Voltage Error 50 mV Output Leakage Current 10 uA 600 600 ps ps Differential Output Error Offset Voltage 1.125 Output Rise and Fall Time Rise Time Fall Time 4 tR /tF Load Duty Cycle 1.25 mV 100 ohms differential 5 45 Jitter (12 kHz - 20 MHz BW)6 фJ Period Jitter7 RMS P/P Random Jitter Deterministic Jitter фJ Output Enabled8 Output Disabled VIH VIL Enable/Disable Time tD 50 55 % 0.35 0.8 ps 2.9 25.1 2.9 <0.2 RJ DJ ps ps ps ps Enable/Disable 0.7*VDD 0.3*VDD Enable/Disable Leakage Current Enable Pull-Up Resistor Output Enabled Output Disabled tSU Operating Temp. (Ordering Option) TOP Package Size 200 ns ±200 uA 33 1 Start-Up Time V V KOhm MOhm 10 ms -10/70 or -40/85 °C 3.2x5.0x1.3 mm 1. The VC-806 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor. 2. See Standard Frequencies and Ordering Information for more information. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Figure 2 defines these parameters and Figure 3 defines the test circuit. 5. Duty Cycle is defines as the On/Time Period. 6. Measured using an Agilent E5052, 156.250MHz. 7. Measured using a Wavecrest SIA3300C, 90K samples. 8. Outputs will be Enabled if Enable/Disable is left open. Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page3 Test Diagrams tR VDD -1.3V 1 6 2 5 3 4 0.8*Vamp NC 50% 0.2*Vamp NC On Time 50 ȍ -1.3V tF 50 ȍ Period Figure 1 Figure 2 Out 50 50 Out 0.01 uF 6 5 4 1 2 3 DC Figure 3 Package and Pinout Table 3. Pinout 6 5 4 VC-806 Frequency Date Code 1 2 Pin # Symbol Function 1 E/D or NC Enable Disable or No Connection 2 E/D or NC Enable Disable or No Connection 3 GND Electrical and Lid Ground 4 fO Output Frequency 5 CfO Complementary Output Frequency 6 VDD Supply Voltage 3.2±0.2 The Enable/Disable function is set at the factory on either pin 1 or pin 2 and is an ordering option. 1.3 max 3 5.0±0.2 0.9 0.64 2.2 2.2 1.4 1.27 1.0 1.27 0.38 2.54 Figure 3 Package Dimensions in mm Figure 4 Pad Layout Dimensions in mm Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page4 LVPECL Application Diagrams 140Ω Figure 5 Standard PECL Output Configuration 140Ω Figure 6 Single Resistor Termination Scheme Resistor values are typically 140 ohms for 3.3V operation. Resistor values are typically 84 for 2.5V operation. Figure 7 Pull-Up Pull Down Termination Resistor values are typically for 3.3V operation For 2.5V operation, the resistor to ground is 62 ohms and the resistor to supply is 240 ohms The VC-806 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 5. There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 6, and a pull-up/pull-down scheme as shown in Figure 7. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage. LVDS Application Diagrams VCC LVDS Driver 100ȍ LVDS Driver LVDS Receiver 100ȍ Receiver OUT+ OUT- Figure 9 LVDS to LVDS Connection, Internal 100ohm Some LVDS structures have an internal 100 ohm resistor on the input and do not need additional components. Figure 8 Standard LVDS Output Configuration Figure 10 LVDS to LVDS Connection External 100ohm and AC blocking caps Some input structures may not have an internal 100 ohm resistor on the input and will need an external 100ohm resistor for impedance matching. Also, the input may have an internal DC bias which may not be compatible with LVDS levels, AC blocking capacitors can be used. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. Environmental and IR Compliance Table 4. Environmental Compliance Parameter Condition Mechanical Shock MIL-STD-883 Method 2002 Mechanical Vibration MIL-STD-883 Method 2007 Temperature Cycle MIL-STD-883 Method 1010 Solderability MIL-STD-883 Method 2003 Fine and Gross Leak MIL-STD-883 Method 1014 Resistance to Solvents MIL-STD-883 Method 2015 Moisture Sensitivity Level MSL1 Contact Pads Gold over Nickel Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page5 S IR Compliance Table 5. Reflow Profile Parameter Symbol Value PreHeat Time ts 200 sec Max Ramp Up RUP 3°C/sec Max Time above 217°C tL 150 sec Max Time to Peak Temperature tAMB-P Time at 260°C tP 20 sec Max Time at 240°C tP2 60 sec Max Ramp down RDN 6°C/sec Max tL 260 Temperature (DegC) Suggested IR Profile Devices are built using lead free epoxy and can be subjected to standard lead free IR reflow conditions shown in Table 5. Contact pads are gold over nickel and lower maximum temperatures can also be used, such as 220C. RUP tP 217 200 RDN 150 tS tAMB-P 480 sec Max Reliability 25 Time (sec) S Maximum Ratings, Tape & Reel Absolute Maximum Ratings and Handling Precautions Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Although ESD protection circuitry has been designed into the VC-806, proper precautions should be taken when handling and mounting, VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes. Table 6. Maximum Ratings Parameter Symbol Rating Unit Storage Temperature TSTORE -55/125 °C Supply Voltage VDD -0.5 to 5.0 V Enable Disable Voltage E/D -0.5 to VDD+0.5 V ESD, Human Body Model 1500 V ESD, Charged Device Model 1000 V Table 7. Tape and Reel Information Tape Dimensions (mm) Reel Dimensions (mm) W F Do Po P1 A B C D N W1 W2 #/Reel 16 7.5 1.5 4 8 180 2 13 21 60 17 21 250 Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page6 Table 8. Standard Frequencies (MHz) 25.000 27.000 32.000 33.000 38.880 40.000 50.000 53.125 56.000 56.250 60.000 61.440 62.500 66.000 66.667 67.500 75.000 77.760 80.000 83.333 98.304 100.000 106.250 108.000 114.285 122.880 124.512 125.000 133.000 143.000 148.500 150.000 153.600 155.520 1562.50 156.253906 160.000 161.130 164.355 166.6286 166.6667 167.000 167.330 168.750 173.3707 180.000 186.667 187.500 190.000 200.000 212.500 218.750 250.000 312.500 Ordering Information VC-806- E C E - K A A N - xxxMxxxxxx Product XO Package 3.2x5mm Voltage Options E: +3.3 Vdc ±5% H: +2.5 Vdc ±5% Frequency in MHz Output C: LVPECL D: LVDS Enable/Disable Logic A: Enable High Temp Range W: -10/70°C E: -40/85°C Stability F: ±25ppm K: ±50ppm S: ±100ppm Other (Future Use) N: Standard Enable/Disable Pin A: Pin 1 B: Pin 2 *Note: not all combination of options are available. Other specifications may be available upon request. Example: VC-806-ECE-KAAN-155M520000 For Additional Information, Please Contact USA: Europe: Asia: Vectron International 267 Lowell Road Hudson, NH 03051 Tel: 1.888.328.7661 Fax: 1.888.329.8328 Vectron International Landstrasse, D-74924 Neckarbischofsheim, Germany Tel: +49 (0) 3328.4784.17 Fax: +49 (0) 3328.4784.30 VI Shanghai 1589 Century Avenue, the 19th Floor Chamtime International Financial Center Shanghai, China Tel: 86.21.6081.2888 Fax: 86.21.6163.3598 Disclaimer Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Rev: 06/17/2011 Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page7