MICROCHIP TC1302B

TC1302A/B
Low Quiescent Current Dual Output LDO
Features
Description
• Dual Output LDO:
- VOUT1 = 1.5V to 3.3V @ 300 mA
- VOUT2 = 1.5V to 3.3V @ 150 mA
• Output Voltage (See Table 8-1)
• Low Dropout Voltage:
- VOUT1 = 104 mV @ 300 mA Typical
- VOUT2 = 150 mV @ 150 mA Typical
• Low Supply Current: 116 µA Typical
TC1302A/B with both output voltages available
• Reference Bypass Input for Low-Noise Operation
• Both Output Voltages Stable with a Minimum of
1 µF Ceramic Output Capacitor
• Separate VOUT1 and VOUT2 SHDN pins
(TC1302B)
• Power-Saving Shutdown Mode of Operation
• Wake-up from SHDN: 5.3 µs. Typical
• Small 8-pin DFN or MSOP Package Options
• Operating Junction Temperature Range:
- -40°C to +125°C
• Overtemperature and Overcurrent Protection
The TC1302A/B combines two Low Dropout (LDO)
regulators into a single 8-pin MSOP or DFN package.
Both regulator outputs feature low dropout voltage,
104 mV @ 300 mA for VOUT1, 150 mV @ 150 mA for
VOUT2, low quiescent current consumption, 58 µA each
and a typical regulation accuracy of 0.5%. Several
fixed-output voltage combinations are available. A
reference bypass pin is available to further reduce
output noise and improve the power supply rejection
ratio of both LDOs.
The TC1302A/B is stable over all line and load
conditions, with a minimum of 1 µF of ceramic output
capacitance, and utilizes a unique compensation
scheme to provide fast dynamic response to sudden
line voltage and load current changes.
Additional features include an overcurrent limit and
overtemperature protection that combine to provide a
robust design for all load fault conditions.
Package Types
8-Pin DFN/MSOP
Applications
•
•
•
•
•
•
Cellular/GSM/PHS Phones
Battery-Operated Systems
Hand-Held Medical Instruments
Portable Computers/PDAs
Linear Post-Regulators for SMPS
Pagers
NC 1
© 2005 Microchip Technology Inc.
6 VOUT2
GND 3
Bypass 4
GND 3
Bypass 4
8 NC
7 VIN
VOUT1 2
GND 3
6 VOUT2
5 SHDN2 Bypass 4
DFN8
NC 1
VOUT1 2
MSOP8
NC 1
8 NC
7 VIN
VOUT1 2
Related Literature
• AN765, “Using Microchip’s Micropower LDOs”,
DS00765, Microchip Technology Inc., 2002
• AN766, “Pin-Compatible CMOS Upgrades to
BiPolar LDOs”, DS00766,
Microchip Technology Inc., 2002
• AN792, “A Method to Determine How Much
Power a SOT23 Can Dissipate in an Application”,
DS00792, Microchip Technology Inc., 2001
TC1302A
DFN8
TC1302B
NC 1
8 SHDN1
VOUT1 2
7 VIN
6 VOUT2
GND 3
5 SHDN2 Bypass 4
5 SHDN2
MSOP8
8 SHDN1
7 VIN
6 VOUT2
5 SHDN2
DS21333B-page 1
TC1302A/B
Functional Block Diagrams
TC1302B
TC1302A
VIN
VOUT1
VIN
VOUT1
LDO #1
300 mA
SHDN1
LDO #1
300 mA
SHDN2
LDO #2
150 mA
VOUT2
VOUT2
LDO #2
150 mA
SHDN2
GND
GND
Bandgap
Reference
1.2V
Bypass
Bypass
Bandgap
Reference
1.2V
Typical Application Circuits
TC1302A
1
2.8V @ 300 mA
COUT1
1 µF Ceramic
X5R
NC
2 V
OUT1
3
4
GND
8
NC
BATTERY
VIN 7
CIN
1 µF
VOUT2 6 2.6V @ 150 mA
5
Bypass SHDN2
(Note)
CBYPASS
10 nF Ceramic
COUT2
1 µF Ceramic
X5R
2.7V
to
4.2V
ON/OFF Control VOUT2
ON/OFF Control VOUT1
TC1302B
1
2.8V @ 300 mA
COUT1
1 µF Ceramic
X5R
2 V
OUT1
3
4
Note: CBYPASS is optional
DS21333B-page 2
NC
GND
SHDN1
8
BATTERY
VIN 7
VOUT2 6 2.6V @ 150 mA
Bypass SHDN2
5
CIN
1 µF
COUT2
1 µF Ceramic
X5R
2.7V
to
4.2V
ON/OFF Control VOUT2
© 2005 Microchip Technology Inc.
TC1302A/B
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Absolute Maximum Ratings †
VDD...................................................................................6.5V
Maximum Voltage on Any Pin ...... (VSS – 0.3) to (VIN + 0.3)V
Power Dissipation ..........................Internally Limited (Note 7)
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, TJ ........................... +150°C
Continuous Operating Temperature Range ..-40°C to +125°C
ESD protection on all pins, HBM, MM ..................... 4 kV, 400V
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF,
COUT1 = COUT2 = 1 µF, CBYPASS = 10 nF, SHDN > VIH, TA = +25°C.
Boldface type specifications apply for junction temperatures of -40°C to +125°C.
Parameters
Input Operating Voltage
Sym
Min
Typ
Max
Units
Conditions
VIN
2.7
—
6.0
V
Maximum Output Current
IOUT1Max
300
—
—
mA
VIN = 2.7V to 6.0V (Note 1)
Maximum Output Current
IOUT2Max
150
—
—
mA
VIN = 2.7V to 6.0V (Note 1)
Output Voltage Tolerance
(VOUT1 and VOUT2)
VOUT
VR – 2.5
TCVOUT
—
25
ΔVOUT/ΔVIN
—
Load Regulation, VOUT ≥ 2.5V
(VOUT1 and VOUT2)
ΔVOUT/
VOUT
Load Regulation, VOUT < 2.5V
(VOUT1 and VOUT2)
%
Note 2
—
ppm/°C
Note 3
0.02
0.2
%/V
-1
0.1
+1
%
IOUTX = 0.1 mA to IOUTMax, (Note 4)
ΔVOUT/
VOUT
-1.5
0.1
+1.5
%
IOUTX = 0.1 mA to IOUTMax, (Note 4)
ΔVOUT/ΔPD
—
0.04
—
%/W
VOUT1 > 2.7V
VIN – VOUT
—
104
180
mV
IOUT1 = 300 mA
VOUT2 > 2.6V
VIN – VOUT
—
150
250
mV
IOUT2 = 150 mA
TC1302A
IIN(A)
—
103
180
µA
SHDN2 = VIN, IOUT1 = IOUT2 = 0 mA
TC1302B
IIN(B)
—
114
180
µA
SHDN1 = SHDN2 = VIN,
IOUT1 = IOUT2 = 0 mA
Temperature Coefficient
(VOUT1 and VOUT2)
Line Regulation
(VOUT1 and VOUT2)
Thermal Regulation
VR±0.5 VR + 2.5
Note 1
(VR + 1V) ≤ VIN ≤ 6V
Note 5
Dropout Voltage (Note 6)
Supply Current
Note 1:
2:
3:
4:
5:
6:
7:
The minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VR + VDROPOUT.
VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2).
TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * ΔT).
Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested
over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating
effects are covered by the thermal regulation specification.
Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied,
excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for t = 10 msec.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
value measured at a 1V differential.
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation causes the device to initiate thermal shutdown.
© 2005 Microchip Technology Inc.
DS21333B-page 3
TC1302A/B
DC CHARACTERISTICS (Continued)
Electrical Specifications: Unless otherwise noted, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF,
COUT1 = COUT2 = 1 µF, CBYPASS = 10 nF, SHDN > VIH, TA = +25°C.
Boldface type specifications apply for junction temperatures of -40°C to +125°C.
Parameters
Sym
Min
Typ
Max
Units
Shutdown Supply Current
TC1302A
IIN_SHDNA
—
58
90
µA
SHDN2 = GND
Shutdown Supply Current
TC1302B
IIN_SHDNB
—
0.1
1
µA
SHDN1 = SHDN2 = GND
PSRR
—
58
—
dB
f ≤ 100 Hz, IOUT1 = IOUT2 = 50 mA,
CIN = 0 µF
eN
—
830
—
VOUT1
IOUTsc1
—
200
—
mA
RLOAD1 ≤ 1Ω
VOUT2
IOUTsc2
—
140
—
mA
RLOAD2 ≤ 1Ω
Power Supply Rejection Ratio
Output Noise
Conditions
nV/(Hz)½ f ≤ 1 kHz, IOUT1 = IOUT2 = 50 mA,
CIN = 0 µF
Output Short Circuit Current (Average)
SHDN Input High Threshold
VIH
45
—
—
%VIN
VIN = 2.7V to 6.0V
SHDN Input Low Threshold
VIL
—
—
15
%VIN
VIN = 2.7V to 6.0V
Wake Up Time (From SHDN
mode), (VOUT2)
tWK
—
5.3
20
µs
VIN = 5V, IOUT1 = IOUT2 = 30 mA,
See Figure 5-1
tS
—
50
—
µs
VIN = 5V, IOUT1 = IOUT2 = 50 mA,
See Figure 5-2
Thermal Shutdown Die
Temperature
TSD
—
150
—
°C
VIN = 5V, IOUT1 = IOUT2 = 100 µA
Thermal Shutdown Hysteresis
THYS
—
10
—
°C
VIN = 5V
Settling Time (From SHDN mode),
(VOUT2)
Note 1:
2:
3:
4:
5:
6:
7:
The minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VR + VDROPOUT.
VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2).
TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * ΔT).
Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested
over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating
effects are covered by the thermal regulation specification.
Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied,
excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for t = 10 msec.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
value measured at a 1V differential.
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation causes the device to initiate thermal shutdown.
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all limits are specified for: VIN = +2.7V to +6.0V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Operating Junction Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Maximum Junction Temperature
TJ
—
—
+150
°C
Thermal Resistance, MSOP8
θJA
—
208
—
°C/W
Typical 4-Layer Board
Thermal Resistance, DFN8
θJA
—
41
—
°C/W
Typical 4-Layer Board with Vias
Steady State
Transient
Thermal Package Resistances
DS21333B-page 4
© 2005 Microchip Technology Inc.
TC1302A/B
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),
CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25°C.
3.00
TJ = +25°C
IOUT1 = IOUT2 = 0 µA
VOUT1 Active
TC1302B
300
250
Output Voltage (V)
Quiescent Current (µA)
350
200
VOUT2 Active
150
VOUT2 SHDN
100
TJ = +25°C
IOUT1 = 100 mA
IOUT2 = 50 mA
2.90
VOUT1
2.80
2.70
VOUT2
50
0
2.60
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
Input Voltage (V)
Quiescent Current vs. Input
FIGURE 2-4:
Voltage.
Output Voltage vs. Input
2.90
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
2.85
Output Voltage (V)
SHDN Threshold (V)
FIGURE 2-1:
Voltage.
ON
OFF
VOUT1
2.80
2.75
2.70
VOUT2
2.65
TJ = +25°C
IOUT1 = 300 mA
IOUT2 = 100 mA
2.60
2.55
2.50
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
6
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
Input Voltage (V)
140
130
120
110
100
90
80
70
60
50
40
TC1302B
VOUT2 Active
VIN = 4.2V
IOUT1 = IOUT2 = 0 µA
VOUT1 Active
VOUT2 SHDN
-40 -25 -10
5
20 35 50 65 80 95 110 125
FIGURE 2-5:
Voltage.
140.0
Output Voltage vs. Input
VR1 = 2.8V
VR2 = 2.6V
IOUT2 = 100 µA
120.0
100.0
© 2005 Microchip Technology Inc.
TJ = +125°C
TJ = +25°C
80.0
TJ = - 40°C
60.0
40.0
20.0
0.0
0
50
100
150
200
250
300
IOUT1 (mA)
Junction Temperature (°C)
FIGURE 2-3:
Quiescent Current vs.
Junction Temperature.
6
Input Voltage (V)
Dropout Voltage V OUT1 (mV)
SHDN Voltage Threshold
FIGURE 2-2:
vs. Input Voltage.
Quiescent Current (µA)
6
Input Voltage (V)
FIGURE 2-6:
Current (VOUT1).
Dropout Voltage vs. Output
DS21333B-page 5
TC1302A/B
140
0.40
VR1 = 2.8V
VR2 = 2.6V
IOUT2 = 100 µA
120
IOUT1 = 300 mA
Load Regulation (%)
Dropout Voltage V OUT1 (mV)
Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),
CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25°C.
100
80
60
IOUT1 = 100 mA
40
IOUT1 = 50 mA
20
VOUT2
0.30
0.20
VOUT1
0.10
IOUT1 = 0.1 mA to 300 mA
0.00
-0.10
VR1 = 2.8V
VR2 = 2.6V
VIN = 4.2
-0.20
-0.30
-0.40
0
-40 -25 -10
-40 -25 -10
5
35
50
65
80
95 110 125
FIGURE 2-10:
VOUT1 and VOUT2 Load
Regulation vs. Junction Temperature.
0.045
VR1 = 2.8V
VR2 = 2.6V
IOUT1 = 100 µA
TJ = +125°C
Line Regulation (%/V)
Dropout Voltage, V OUT2 (mv)
20
Junction Temperature (125°C)
FIGURE 2-7:
Dropout Voltage vs.
Junction Temperature (VOUT1).
180
160
140
120
100
80
60
40
20
0
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
TJ = +25°C
TJ = - 40°C
VIN = 3.8V to 6.0V
VR1 = 2.8V, IOUT1 = 100 µA
VR2 = 2.6V, IOUT2 = 100 µA
0.040
0.035
VOUT2
0.030
0.025
0.020
VOUT1
0.015
0.010
0.005
0.000
0
30
60
90
120
150
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
IOUT2 (mA)
FIGURE 2-8:
Current (VOUT2).
Dropout Voltage vs. Output
FIGURE 2-11:
VOUT1 and VOUT2 Line
Regulation vs. Junction Temperature.
180
2.832
IOUT2 = 150 mA
160
140
VR1 = 2.8V
VR2 = 2.6V
IOUT1 = 100 µA
120
100
80
IOUT2 = 50 mA
60
40
IOUT2 = 10 mA
20
0
Output Voltage V OUT1 (V)
Dropout Voltage V OUT2 (mV)
IOUT2 = 0.1 mA to 150 mA
2.828
2.824
VIN = 4.2V
VR1 = 2.8V
VR2 = 2.6V, IOUT2 = 100 µA
IOUT1 = 100 mA
IOUT1 = 300 mA
2.820
2.816
IOUT1 = 100 µA
2.812
2.808
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
FIGURE 2-9:
Dropout Voltage vs.
Junction Temperature (VOUT2).
DS21333B-page 6
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
FIGURE 2-12:
Temperature.
VOUT1 vs. Junction
© 2005 Microchip Technology Inc.
TC1302A/B
Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),
CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25°C.
Output Voltage VOUT1 (V)
2.856
2.848
VR1 = 2.8V, IOUT1 = 300 mA
VR2 = 2.6V, IOUT2 = 100 µA
VIN = 3.0V
2.840
2.832
2.824
VIN = 4.2V
2.816
VIN = 6.0V
2.808
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
FIGURE 2-13:
Temperature.
VOUT1 vs. Junction
FIGURE 2-16:
Power Supply Rejection
Ratio vs. Frequency (without bypass capacitor).
Output Voltage VOUT2 (V)
2.645
IOUT2 = 100 µA
2.640
IOUT2 = 50 mA
2.635
2.630
IOUT2 = 150 mA
2.625
VIN = 4.2V
VR1 = 2.8V, IOUT1 = 100 µA
VR2 = 2.6V
2.620
2.615
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
VOUT2 vs. Junction
Output Voltage V OUT2 (V)
2.644
2.640
VR1 = 2.8V, IOUT1 = 100 µA
VR2 = 2.6V, IOUT2 = 150 mA
VOUT2
VIN = 6.0V
2.632
2.628
2.624
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
FIGURE 2-15:
Temperature.
VOUT2 vs. Junction
© 2005 Microchip Technology Inc.
10
VIN = 3.0V
VIN = 4.2V
2.636
FIGURE 2-17:
Power Supply Rejection
Ratio vs. Frequency (with bypass capacitor).
NOISE (μV/—Hz)
FIGURE 2-14:
Temperature.
1
0.1
VOUT1
VIN = 4.2V
VR1 = 2.8V
VR2=2.6V
IOUT1 = 150 mA
IOUT2 = 100 mA
CBYPASS = 0 nF
0.01
0.01
0.1
1
10
100
1000
Frequency (KHz)
FIGURE 2-18:
VOUT1 and VOUT2 Noise vs.
Frequency (without bypass capacitor).
DS21333B-page 7
TC1302A/B
Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),
CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25°C.
NOISE (μV/—Hz)
10
1
0.1
0.01
VOUT2
VOUT1
VIN = 4.2V
VR1 = 2.8V
VR2=2.6V
IOUT1 = 150 mA
IOUT2 = 100 mA
CBYPASS = 10 nF
0.001
0.01
0.1
1
10
100
1000
Frequency (KHz)
FIGURE 2-19:
VOUT1 and VOUT2 Noise vs.
Frequency (with bypass capacitor).
FIGURE 2-22:
VOUT1 and VOUT2 Power-up
from Input Voltage TC1302B.
FIGURE 2-20:
VOUT1 and VOUT2 Power-up
from Shutdown TC1302B.
FIGURE 2-23:
Dynamic Line Response.
FIGURE 2-21:
VOUT2 Power-up from
Shutdown Input TC1302A.
FIGURE 2-24:
VOUT1.
300 mA Dynamic Load Step
DS21333B-page 8
© 2005 Microchip Technology Inc.
TC1302A/B
Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),
CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25°C.
FIGURE 2-25:
VOUT2.
150 mA Dynamic Load Step
© 2005 Microchip Technology Inc.
DS21333B-page 9
TC1302A/B
3.0
TC1302A PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Pin No.
3.1
TC1302A PIN FUNCTION TABLE
Name
Function
1
NC
2
VOUT1
No connect.
Regulated output voltage #1, capable of 300 mA.
3
GND
Circuit ground pin.
4
Bypass
Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce
output noise and improve PSRR performance.
5
SHDN2
Output #2 shutdown control input.
6
VOUT2
Regulated output voltage #2, capable of 150 mA.
7
VIN
Unregulated input voltage pin.
8
NC
No connect.
Regulated Output Voltage #1
(VOUT1)
3.4
Output Voltage #2 Shutdown
(SHDN2)
Connect VOUT1 to the positive side of the VOUT1
capacitor and load. Capable of 300 mA maximum
output current. VOUT1 output is available when VIN is
available; there is no pin to turn it OFF. See TC1302B
if ON/OFF control of VOUT1 is desired.
ON/OFF control is performed by connecting SHDN2 to
its proper level. When the input of this pin is connected
to a voltage less than 15% of VIN, VOUT2 will be OFF. If
this pin is connected to a voltage that is greater than
45% of VIN, VOUT2 will be turned ON.
3.2
3.5
Circuit Ground Pin (GND)
Connect GND to the negative side of the input and
output capacitor. Only the LDO internal circuitry bias
current flows out of this pin (200 µA maximum).
3.3
Reference Bypass Input
By connecting an external 10 nF capacitor (typical) to
the Bypass Input, both outputs (VOUT1 and VOUT2) will
have less noise and improved Power Supply Ripple
Rejection (PSRR) performance. The LDO output
voltage start-up time will increase with the addition of
an external bypass capacitor. By leaving this pin
unconnected, the start-up time will be minimized.
DS21333B-page 10
Regulated Output Voltage #2
(VOUT2)
Connect VOUT2 to the positive side of the VOUT2
capacitor and load. This pin is capable of a maximum
output current of 150 mA. VOUT2 can be turned ON and
OFF using SHDN2.
3.6
Unregulated Input Voltage Pin
(VIN)
Connect the unregulated input voltage source to VIN. If
the input voltage source is located more than several
inches away or is a battery, a typical input capacitance
of 1 µF to 4.7 µF is recommended.
© 2005 Microchip Technology Inc.
TC1302A/B
4.0
TC1302B PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 4-1.
TABLE 4-1:
Pin No.
4.1
TC1302B PIN FUNCTION TABLE
Name
Function
1
NC
2
VOUT1
No connect.
Regulated output voltage #1, capable of 300 mA.
3
GND
Circuit ground pin.
4
Bypass
Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce
output noise and improve PSRR performance.
5
SHDN2
Output #2 shutdown control input.
6
VOUT2
Regulated output voltage #2, capable of 150 mA.
7
VIN
8
SHDN1
Unregulated Input voltage pin.
Output #1 shutdown control input.
Regulated Output Voltage #1
(VOUT1)
4.5
Regulated Output Voltage #2
(VOUT2)
Connect VOUT1 to the positive side of the VOUT1
capacitor and load. Capable of 300 mA maximum
output current. For the TC1302B, VOUT1 can be turned
ON and OFF using the SHDN1 input pin.
Connect VOUT2 to the positive side of the VOUT2
capacitor and load. This pin is capable of a maximum
output current of 150 mA. VOUT2 can be turned ON and
OFF using SHDN2.
4.2
4.6
Circuit Ground Pin (GND)
Connect GND to the negative side of the input and
output capacitor. Only the LDO internal circuitry bias
current flows out of this pin (200 µA maximum).
4.3
Reference Bypass Input
By connecting an external 10 nF capacitor (typical) to
the bypass input, both outputs (VOUT1 and VOUT2) will
have less noise and improved Power Supply Ripple
Rejection (PSRR) performance. The LDO output
voltage startup time will increase with the addition of an
external bypass capacitor. By leaving this pin
unconnected, the startup time will be minimized.
4.4
Output Voltage #2 Shutdown
(SHDN2)
Unregulated Input Voltage Pin
(VIN)
Connect the unregulated input voltage source to VIN. If
the input voltage source is located more than several
inches away, or is a battery, a typical minimum input
capacitance of 1 µF and 4.7 µF is recommended.
4.7
Output Voltage #1 Shutdown
(SHDN1)
ON/OFF control is performed by connecting SNDN1 to
its proper level. When this pin is connected to a voltage
less than 15% of VIN, VOUT1 will be OFF. If this pin is
connected to a voltage that is greater than 45% of VIN,
VOUT1 will be turned ON.
ON/OFF control is performed by connecting SHDN2 to
its proper level. When this pin is connected to a voltage
less than 15% of VIN, VOUT2 will be OFF. If this pin is
connected to a voltage that is greater than 45% of VIN,
VOUT2 will be turned ON.
© 2005 Microchip Technology Inc.
DS21333B-page 11
TC1302A/B
5.0
DETAILED DESCRIPTION
5.5
5.1
Device Overview
A minimum output capacitance of 1 µF for each of the
TC1302A/B LDO outputs is necessary for stability.
Ceramic capacitors are recommended because of their
size, cost and environmental robustness qualities.
Tantalum or aluminum electrolytic capacitors can be
used on the LDO outputs as well. The Equivalent
Series Resistance (ESR) requirements on the
electrolytic output capacitor’s are between 0 and 2
ohms. The output capacitor should be located as close
to the LDO output as is practical. Ceramic materials,
X7R and X5R, have low temperature coefficients and
are well within the acceptable ESR range required. A
typical 1 uF X5R 0805 capacitor has an ESR of 50 milliohms. Larger LDO output capacitors can be used with
the TC1302A/B to improve dynamic performance and
power supply ripple rejection performance. A maximum
of 10 µF is recommended. Aluminum electrolytic
capacitors are not recommended for low temperature
applications of < -25 °C.
The TC1302A/B is a combination device consisting of
one 300 mA LDO regulator with a fixed output voltage
VOUT1 (1.5V – 3.3V) and one 150 mA LDO regulator
with a fixed output voltage VOUT2 (1.5V – 3.3V).
For the TC1302A, the 300 mA output (VOUT1) is always
present, independent of the level of SHDN2. The
150 mA output (VOUT2) can be turned ON/OFF by
controlling the level of SHDN2.
For the TC1302B, VOUT1 and VOUT2 each have
independent shutdown input pins (SHDN1 and
SHDN2) to control their respective outputs.
5.2
LDO Output #1
LDO output #1 is rated for 300 mA of output current.
The typical dropout voltage for VOUT1 = 104 mV @
300 mA. A 1 µF (minimum) output capacitor is needed
for stability and should be located as close to the VOUT1
pin and ground as possible.
5.3
LDO Output #2
LDO output #2 is rated for 150 mA of output current.
The typical dropout voltage for VOUT2 = 150 mV. A 1 µF
(minimum) capacitor is needed for stability and should
be located as close to the VOUT2 pin and ground as
possible.
5.4
Input Capacitor
Low input source impedance is necessary for the two
LDO outputs to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications. When using large capacitors on the LDO
outputs, larger capacitance is recommended on the
LDO input. The capacitor should be placed as close to
the input of the LDO as is practical. Larger input
capacitors will help reduce the input impedance and
further reduce any high-frequency noise on the input
and output of the LDO.
5.6
Output Capacitor
Bypass Input
The Bypass pin is connected to the internal LDO
reference. By adding capacitance to this pin, the LDO
ripple rejection, input voltage transient response and
output noise performance are all increased. A typical
bypass capacitor between 470 pF to 10 nF is
recommended. Larger bypass capacitors can be used,
but result in a longer time period for the LDO outputs to
reach their rated output voltage when started from
SHDN or VIN.
5.7
GND
For the optimal noise and PSRR performance, the
GND pin of the TC1302A/B should be tied to a quiet
circuit ground. For applications that have switching or
noisy inputs, tie the GND pin to the return of the output
capacitor. Ground planes help lower inductance and
voltage spikes caused by fast transient load currents
and are recommended for applications that are
subjected to fast load transients.
5.8
SHDN1/SHDN2 Operation
The TC1302A SHDN2 pin is used to turn VOUT2 ON
and OFF. A logic-high level on SHDN2 will enable the
VOUT2 output, while a logic-low on the SHDN2 pin will
disable the VOUT2 output. For the TC1302A, VOUT1 is
not affected by SHDN2 and will be enabled as long as
the input voltage is present.
The TC1302B SHDN1 and SHDN2 pins are used to
turn VOUT1 and VOUT2 ON and OFF. They operate
independent of each other.
DS21333B-page 12
© 2005 Microchip Technology Inc.
TC1302A/B
5.9
TC1302A SHDN2 Timing
VOUT1 will rise independent of the level of SHDN2 for
the TC1302A. Figure 5-1 is used to define the wake-up
time from shutdown (tWK) and the settling time (tS). The
wake-up time is dependant upon the frequency of
operation. The faster the SHDN pin is pulsed, the
shorter the wake-up time will be.
VIN
5.11
5.11.1
twk
OVERCURRENT LIMIT
In the event of a faulted output load, the maximum
current the LDO output will permit to flow is limited
internally for each of the TC1302A/B outputs. The peak
current limit for VOUT1 is typically 1.1A, while the peak
current limit for VOUT2 is typically 0.5A. During shortcircuit operation, the average current is limited to
200 mA for VOUT1 and 140 mA for VOUT2.
5.11.2
ts
Device Protection
OVERTEMPERATURE
PROTECTION
If the internal power dissipation within the TC1302A/B
is excessive due to a faulted load or higher-thanspecified line voltage, an internal temperature-sensing
element will prevent the junction temperature from
exceeding approximately 150°C. If the junction
temperature does reach 150°C, both outputs will be
disabled until the junction temperature cools to
approximately 140°C and the device resumes normal
operation. If the internal power dissipation continues to
be excessive, the device will again shut off.
SHDN2
VOUT1
VOUT2
FIGURE 5-1:
5.10
TC1302A Timing.
TC1302B SHDN1/SHDN2 Timing
For the TC1302B, the SHDN1 input pin is used to
control VOUT1. The SHDN2 input pin is used to control
VOUT2, independent of the logic input on SHDN1.
VIN
ts
twk
SHDN1
VOUT1
SHDN2
VOUT2
FIGURE 5-2:
TC1302B Timing.
© 2005 Microchip Technology Inc.
DS21333B-page 13
TC1302A/B
6.0
APPLICATION CIRCUITS/
ISSUES
6.1
EQUATION 6-1:
P LDO = ( V IN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) )
Typical Application
PLDO
The TC1302A/B is used for applications that require
the integration of two LDOs.
TC1302A
1
2.8V @ 300 mA
COUT1
1 µF Ceramic
X5R
2
3
4
8
NC
NC
VOUT1
VIN 7
GND
VOUT2
Bypass SHDN2
BATTERY
1.8V
6 @ 150 mA
CIN
1 µF
5
COUT2
1 µF Ceramic
X5R
Cbypass
10 nF Ceramic
2.7V
to
4.2V
P I ( GND ) = VIN ( MAX ) × I VIN
ON/OFF Control VOUT1
PI(GND) = Total current in ground pin.
VIN(MAX) = Maximum input voltage.
IVIN
= Current flowing in the VIN pin with
no output current on either LDO output.
TC1302B
1
COUT1
1 µF Ceramic
X5R
3
4
SHDN1
NC
VOUT1
GND
8
BATTERY
VIN 7
VOUT2
Bypass SHDN2
1.8V
6 @ 150 mA
5
CIN
1 µF
COUT2
1 µF Ceramic
X5R
2.7V
to
4.2V
ON/OFF Control VOUT2
FIGURE 6-1:
TC1302A/B.
6.1.1
In addition to the LDO pass element power dissipation,
there is power dissipation within the TC1302A/B as a
result of quiescent or ground current. The power
dissipation, as a result of the ground current, can be
calculated using the following equation.
EQUATION 6-2:
ON/OFF Control VOUT2
2.8V @ 300 mA 2
= LDO Pass device internal power
dissipation
VIN(MAX) = Maximum input voltage
VOUT(MIN)= LDO minimum output voltage
Typical Application Circuit
APPLICATION INPUT CONDITIONS
Package Type = 3x3DFN8
Input Voltage Range = 2.7V to 4.2V
VIN maximum = 4.2V
VIN typical = 3.6V
VOUT1 = 300 mA maximum
The total power dissipated within the TC1302A/B is the
sum of the power dissipated in both of the LDOs and
the P(IGND) term. Because of the CMOS construction,
the typical IGND for the TC1302A/B is 116 µA.
Operating at a maximum of 4.2V results in a power
dissipation of 0.5 milliWatts. For most applications, this
is small compared to the LDO pass device power dissipation and can be neglected.
The maximum continuous operating junction
temperature specified for the TC1302A/B is +125°C. To
estimate the internal junction temperature of the
TC1302A/B, the total internal power dissipation is
multiplied by the thermal resistance from junction to
ambient (RθJA) of the device. The thermal resistance
from junction-to-ambient for the 3x3DFN8 pin package
is estimated at 41° C/W.
VOUT2 = 150 mA maximum
EQUATION 6-3:
6.2
6.2.1
Power Calculations
POWER DISSIPATION
The internal power dissipation within the TC1302A/B is
a function of input voltage, output voltage, output
current and quiescent current. The following equation
can be used to calculate the internal power dissipation
for each LDO.
DS21333B-page 14
T J ( MAX ) = P TOTAL × Rθ JA + T AMAX
TJ(MAX) = Maximum continuous junction
temperature.
PTOTAL = Total device power dissipation.
= Thermal resistance from junction
RθJA
to ambient.
TAMAX = Maximum Ambient Temperature.
© 2005 Microchip Technology Inc.
TC1302A/B
The maximum power dissipation capability for a
package can be calculated given the junction-toambient thermal resistance and the maximum ambient
temperature for the application. The following equation
can be used to determine the package maximum
internal power dissipation.
EQUATION 6-4:
( T J ( MAX ) – T A ( MAX ) )
P D ( MAX ) = --------------------------------------------------Rθ JA
PD(MAX) = maximum device power dissipation.
TJ(MAX) = maximum continuous junction
temperature.
TA(MAX) = maximum ambient temperature.
= Thermal resistance from junction to
RθJA
ambient.
Maximum Ambient Temperature
TA(MAX) = 50°C
Internal Power Dissipation
Internal power dissipation is the sum of the power
dissipation for each LDO pass device.
PLDO1(MAX) = (VIN(MAX) - VOUT1(MIN)) x
IOUT1(MAX)
PLDO1 = (4.2V - (0.975 x 2.8V)) x 300 mA
PLDO1 = 441.0 milliWatts
PLDO2 = (4.2V - (0.975 X 1.8V)) x 150 mA
PLDO2 = 366.8 milliWatts
PTOTAL = PLDO1 + PLDO2
PTOTAL= 807.8 milliWatts
Device Junction Temperature Rise
EQUATION 6-5:
T J ( RISE ) = P D ( MAX ) × Rθ JA
TJ(RISE) = Rise in device junction temperature over
the ambient temperature.
PD(MAX) = Maximum device power dissipation.
= Thermal resistance from junction-toRθJA
ambient.
EQUATION 6-6:
T J = T J ( RISE ) + T A
= Junction temperature.
TJ
TJ(RISE) = Rise in device junction temperature over
the ambient temperature.
= Ambient Temperature.
TA
6.3
Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power
dissipation, as a result of ground current, is small
enough to be neglected.
6.3.1
POWER DISSIPATION EXAMPLE
Package
Package Type = 3x3DFN8
Input Voltage
VIN = 2.7V to 4.2V
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction to ambient for the application. The
thermal resistance from junction to ambient (RθJA) is
derived from an EIA/JEDEC standard for measuring
thermal resistance for small surface-mount packages.
The EIA/JEDEC specification is JESD51-7 “High
Effective Thermal Conductivity Test Board for Leaded
Surface Mount Packages”. The standard describes the
test method and board specifications for measuring the
thermal resistance from junction to ambient. The actual
thermal resistance for a particular application can vary
depending on many factors, such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application”, (DS00792), for more information
regarding this subject.
TJ(RISE) = PTOTAL x RqJA
TJRISE = 807.8 milliWatts x 41.0° C/W
TJRISE = 33.1°C
Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below.
TJ = TJRISE + TA(MAX)
TJ = 83.1°C
Maximum Package Power Dissipation at 50°C
Ambient Temperature
LDO Output Voltages and Currents
VOUT1 = 2.8V
IOUT1 = 300 mA
VOUT2 = 1.8V
IOUT2 = 150 mA
3x3DFN8 (41°C/Watt RθJA)
PD(MAX) = (125°C - 50°C)/41° C/W
PD(MAX) = 1.83 Watts
MSOP8 (208°C/Watt RθJA)
PD(MAX) = (125°C - 50°C)/208° C/W
PD(MAX) = 0.360 Watts
© 2005 Microchip Technology Inc.
DS21333B-page 15
TC1302A/B
7.0
TYPICAL LAYOUT
8.0
ADDITIONAL OUTPUT
VOLTAGES
8.1
Output Voltage Options
Table 8-1 describes the range of output voltage options
available for the TC1302A/B. VOUT1 and VOUT2 can be
factory preset from 1.5V to 3.3V in 100 mV increments.
TABLE 8-1:
CUSTOM OUTPUT
VOLTAGES
VOUT1
VOUT2
1.5V to 3.3V
1.5V to 3.3V
For a listing of TC1302A/B standard parts, refer to the
Product Identification System on page 23.
FIGURE 7-1:
MSOP8 Silk-screen Layer.
When designing the physical layout for the TC1302A/B,
the highest priority should be placed on positioning the
input and output capacitors as close to the device pins
as is practical. Figure 7-1 above represents a typical
placement of the components when using the SMT0805
capacitors.
FIGURE 7-2:
Example.
DFN3x3 Silk-screen
Figure 7-2 above represents a typical placement of the
components when using the SMT0603 capacitors.
DS21333B-page 16
© 2005 Microchip Technology Inc.
TC1302A/B
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead MSOP
Example:
XXXXXX
YWWNNN
32AFH
542256
— 32A = TC1302A
— F = 2.8V VOUT1
— H = 2.6V VOUT2
X1 represents VOUT1 configuration:
8-Lead DFN
Example:
XXXX
YYWW
NNN
BFH
0542
256
X2 represents VOUT2 configuration:
Code
VOUT1
Code
VOUT1
Code
VOUT1
Code
VOUT2
Code
VOUT1
Code
VOUT2
A
3.3V
J
2.4V
S
1.5V
A
3.3V
J
2.4V
S
1.5V
B
3.2V
K
2.3V
T
1.65V
B
3.2V
K
2.3V
T
1.65V
C
3.1V
L
2.2V
U
2.85V
C
3.1V
L
2.2V
U
2.85V
D
3.0V
M
2.1V
V
2.65V
D
3.0V
M
2.1V
V
2.65V
E
2.9V
N
2.0V
W
1.85V
E
2.9V
N
2.0V
W
1.85V
F
2.8V
O
1.9V
X
—
F
2.8V
O
1.9V
X
—
G
2.7V
P
1.8V
Y
—
G
2.7V
P
1.8V
Y
—
H
2.6V
Q
1.7V
Z
—
H
2.6V
Q
1.7V
Z
—
I
2.5V
R
1.6V
I
2.5V
R
1.6V
For a listing of TC1302A/B standard parts, refer to the
Product Identification System on page 23.
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2005 Microchip Technology Inc.
DS21333B-page 17
TC1302A/B
8-Lead Plastic Micro Small Outline Package (UA) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
n
p
MIN
INCHES
NOM
MAX
MILLIMETERS*
NOM
8
0.65 BSC
0.75
0.85
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.40
0.60
0.95 REF
0°
0.08
0.22
5°
5°
-
MIN
8
Number of Pins
.026 BSC
Pitch
A
.043
Overall Height
A2
.030
.033
.037
Molded Package Thickness
A1
.000
.006
Standoff
E
.193 TYP.
Overall Width
E1
.118 BSC
Molded Package Width
D
.118 BSC
Overall Length
L
.016
.024
.031
Foot Length
Footprint (Reference)
F
.037 REF
φ
Foot Angle
0°
8°
c
Lead Thickness
.003
.006
.009
B
.009
.012
.016
Lead Width
α
5°
15°
Mold Draft Angle Top
β
5°
15°
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°
15°
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21333B-page 18
© 2005 Microchip Technology Inc.
TC1302A/B
8-Lead Plastic Dual Flat No Lead Package (MF) 3x3x0.9 mm Body (DFN)
E
p
b
n
L
D
D2
EXPOSED
METAL
PAD
2
1
E2
TOP VIEW
PIN 1
ID INDEX
AREA
(NOTE 2)
BOTTOM VIEW
A1
A3
A
EXPOSED
TIE BAR
(NOTE 1)
Number of Pins
Pitch
Overall Height
Standoff
Lead Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Lead Width
Lead Length
Units
Dimension Limits
n
p
(Note 4)
(Note 4)
A
A1
A3
E
E2
D
D2
b
L
MIN
.031
.000
INCHES
NOM
8
.026 BSC
.035
.001
.008 REF.
.118 BSC
.055
MAX
.039
.002
.096
.118 BSC
.047
.007
.012
.010
.019
.069
.015
.022
MILLIMETERS*
NOM
8
0.65 BSC
0.80
0.90
0.02
0.00
0.20 REF.
3.00 BSC
1.39
3.00 BSC
1.20
0.26
0.23
0.30
0.48
MIN
MAX
1.00
0.05
2.45
1.75
0.37
0.55
*Controlling Parameter
Notes:
1. Package may have one or more exposed tie bars at ends.
2. Pin 1 visual index feature may vary, but must be located within the hatched area.
3. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
4. Exposed pad dimensions vary with paddle size.
5. JEDEC equivalent: Pending
Drawing No. C04-062
© 2005 Microchip Technology Inc.
DS21333B-page 19
TC1302A/B
NOTES:
DS21333B-page 20
© 2005 Microchip Technology Inc.
TC1302A/B
APPENDIX A:
REVISION HISTORY
Revision B (January 2005)
The following is the list of modifications:
1.
2.
Correct the incorrect part number options shown
on the Product Identification System page and
change the “standard” output voltage and reset
voltage combinations.
Added Appendix A: Revision History.
Revision A (September 2003)
Original data sheet release.
© 2005 Microchip Technology Inc.
DS21333B-page 21
TC1302A/B
NOTES:
DS21333B-page 22
© 2005 Microchip Technology Inc.
TC1302A/B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X-
X
X
TC1302
Type
A/B
VOUT1
VOUT2
Standard
Configurations
Device:
X
XX
XX
Temp Package Tube
or
Range
Tape &
Reel
TC1302A: Dual Output LDO with Single Shutdown input.
TC1302B: Dual Output LDO with Dual Shutdown Inputs.
VOUT1/VOUT2
Configuration
Code
TC1302A
3.0/1.65
DT
TC1302B
3.0/1.65
2.6/1.8
2.5/1.8
DT
HP
IP
Standard
Configurations: *
Examples:
a)
TC1302ADTVMF:
3.0, 1.65,
8LD DFN pkg.
a)
TC1302BDTVMF:
b)
TC1302BHPVMFTR:
c)
TC1302BIPVUA:
3.0, 1.65,
8LD DFN pkg.
2.6, 1.8,
8LD DFN pkg,
Tape and Reel.
2.5, 1.8,
8LD MSOP pkg.
* Contact Factory for Alternate Output Voltage
Configurations.
Temperature Range:
V
= -40°C to +125°C
Package:
MF
UA
= Dual Flat, No Lead (3x3 mm body), 8-lead
= Plastic Micro Small Outline (MSOP), 8-lead
Tube or
Tape and Reel:
Blank
TR
= Tube
= Tape and Reel
© 2005 Microchip Technology Inc.
DS21333B-page 23
TC1302A/B
NOTES:
DS21333B-page 24
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21333B-page 25
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10/20/04
DS21333B-page 26
© 2005 Microchip Technology Inc.