TI SN75LVDM976DGG

SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
D
D
D
D
D
D
D
D
D
D
DGG PACKAGE
(TOP VIEW)
9 Channels for the Data and Control Paths
of the Small Computer Systems Interface
(SCSI)
Supports Single-Ended and Low-Voltage
Differential (LVD) SCSI
CMOS Input Levels (’LVDM976) or TTL
Input Levels (’LVDM977) Available
Includes DIFFSENS Comparators on CDE0
Single-Ended Receivers Include Noise
Pulse Rejection Circuitry
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
Low Disabled Supply Current 7 mA
Maximum
Power-Up/Down Glitch Protection
Bus is High-Impedance With VCC = 1.5 V
Pin-Compatible With the SN75976ADGG
High-Voltage Differential Transceiver
INV/NON
GND
GND
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
VCC
GND
GND
GND
GND
GND
VCC
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
description
The SN75LVDM976 and SN75LVDM977 have
nine transceivers for transmitting or receiving the
signals to or from a SCSI data bus. They offer
electrical compatibility to both the single-ended
signaling of X3.277:1996–SCSI–3 Parallel Interface (Fast–20) and the new low-voltage differential signaling method of proposed standard
1142–D SCSI Parallel Interface – 2 (SPI–2).
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CDE2
CDE1
CDE0
9B+
9B–
8B+
8B –
7B+
7B –
6B+
6B –
VCC
GND
GND
GND
GND
GND
VCC
5B+
5B –
4B+
4B –
3B+
3B –
2B+
2B –
1B+
1B –
The differential drivers are nonsymmetrical. The
SCSI bus uses a dc bias on the line to allow
terminated fail safe and wired-OR signaling. This bias can be as high as 125 mV and induces a difference in
the high-to-low and low-to-high transition times of a symmetrical driver. In order to reduce pulse skew, an LVD
SCSI driver’s output characteristics become nonsymmetrical. In other words, there is more assertion current
than negation current to or from the driver. This allows the actual differential signal voltage on the bus to be
symmetrical about 0 V. Even though the driver output characteristics are nonsymmetrical, the design of the
’LVDM976 drivers maintains balanced signaling. Balanced means that the current that flows in each signal line
is nearly equal but opposite in direction and is one of the keys to the low-noise performance of a differential bus.
AVAILABLE OPTIONS
PACKAGE
TA
0°C to 70°C
TSSOP
(DGG)
CMOS INPUT LEVELS
SN75LVDM976DGG
SN75LVDM976DGGR†
TSSOP
(DGG)
TTL INPUTS LEVELS
SN75LVDM977DGG
SN75LVDM977DGGR†
† The R suffix designates a taped and reeled package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
description (continued)
The signal symmetry requirements of the LVD-SCSI bus mean you can no longer obtain logical inversion of a
signal by simply reversing the differential signal connections. This requires the ability to invert the logic
convention through the INV/NON terminal. This input would be a low for SCSI controllers with active-high data
and high for active-low data. In either case, the B+ signals of the transceiver must be connected to the SIGNAL+
line of the SCSI bus and the B– of the transceiver to the SIGNAL– line.
The CDE0 input incorporates a window comparator to detect the status of the DIFFSENS line of a SCSI bus.
This line is below 0.5 V, if using single-ended signals, between 1.7 V and 1.9 V if low-voltage differential, and
between 2.4 V and 5.5 V if high-voltage differential. The outputs assume the characteristics of single-ended or
LVD accordingly or place the outputs into high-impedance, when HVD is detected. This, and the INV/NON input,
are the only differences to the trade-standard function of the SN75976A HVD transceiver.
Two options are offered to minimize the signal noise margins on the interface between the communications
controller and the transceiver. The SN75LVDM976 has logic input voltage thresholds of about 0.5 VCC. The
SN75LVDM977 has a fixed logic input voltage threshold of about 1.5 V. The input voltage threshold should be
selected to be near the middle of the output voltage swing of the corresponding driver circuit.
The SN75LVDM976 and SN75LVDM977 are characterized for operation over an free-air temperature range of
TA = 0°C to 70°C.
2
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SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
logic diagram (positive logic)
CDE1
+
–
LVD
B
SE
INV/NON
–
+
A
2.4 V
(Internal)
CDE0
0.5 V
(Internal)
1DEb
1DE/RE
1REb
1DEb
1DEa
1A
1B –
1DEa
1B +
1REa
1REb
1REa
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
2B –
2B +
3B –
3B +
4B –
4B +
Channel 2
Channel 3
Channel 4
INV/NON
SE
LVD
CDE2
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
5B –
5B +
6B –
6B +
7B –
7B +
8B –
8B +
Channel 5
Channel 6
Channel 7
Channel 8
INV/NON
SE
LVD
9DEb
9DE/RE
9A
9DEb
9DEa
9REb
9B –
9DEa
9B +
9REa
9REb
9REa
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3
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
logic diagrams and function tables
FUNCTION TABLE
Outputs
Inputs
B–
VID
B+
A
DE/RE
(B+ – B–)
DE/RE
A
B+
B–
A
VID ≥ 30 mV
– 30 mV < VID < 30 mV
L
NA
Z
Z
L
L
NA
Z
Z
?
VID –30 mV
Open circuit
L
NA
Z
Z
H
L
NA
Z
Z
?
NA
H
L
H
L
Z
NA
H
H
L
H
Z
Figure 1. Inverting LVD Transceiver
FUNCTION TABLE
A
B–
DE/RE
B+
Outputs
Inputs
B–
DE/RE
A
B+
B–
H
L
NA
L
Z
L
L
L
NA
L
Z
H
Open circuit
L
NA
L
Z
?
NA
H
L
L
H
Z
NA
H
H
L
L
Z
Figure 2. Inverting Single-Ended Transceiver
A
FUNCTION TABLE
B–
Outputs
Input
B+
A
B+
B–
L
L
H
H
L
L
Figure 3. Inverting Single-Ended Driver
FUNCTION TABLE
B–
Input
A
B+
Figure 4. Inverting LVD Driver
4
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• DALLAS, TEXAS 75265
Outputs
A
B+
B–
L
H
L
H
L
H
A
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
logic diagrams and function tables (continued)
FUNCTION TABLE
B–
Outputs
Input
A
B+
Figure 5. Noninverting LVD Driver
A
B+
B–
L
L
H
H
H
L
FUNCTION TABLE
A
Outputs
Inputs
B–
VID
B+
DE/RE
(B+ – B –)
DE/RE
A
B+
B–
A
VID ≥ 30 mV
– 30 mV < VID < 30 mV
L
NA
Z
Z
H
L
NA
Z
Z
?
VID ≤ –30 mV
Open circuit
L
NA
Z
Z
L
L
NA
Z
Z
?
NA
H
L
L
H
Z
NA
H
H
H
L
Z
Figure 6. Noninverting LVD Transceiver
A
FUNCTION TABLE
B–
Inputs
DE/RE
B+
Figure 7. Noninverting Single-Ended Transceiver
A
Outputs
B–
DE/RE
A
B+
B–
A
H
L
NA
L
Z
H
L
L
NA
L
Z
L
Open Circuit
L
NA
L
Z
?
NA
H
L
L
L
Z
NA
H
H
L
H
Z
B–
FUNCTION TABLE
Input
B+
Figure 8. Noninverting Single-Ended Driver
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Outputs
A
B+
B–
L
L
L
H
L
H
5
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1B–
1A
1B+
1DE/RE
1B+
1DE/RE
2B+
2DE/RE
3B–
3A
3B+
3DE/RE
2A
2B+
2DE/RE
3B–
3A
4B+
4DE/RE
5B–
5A
4B+
4DE/RE
5B–
5A
5B+
6B–
6A
6B+
6DE/RE
7B–
7A
6B+
7B–
7A
7B+
8B+
8DE/RE
9B–
9A
9B+
9DE/RE
Control Inputs
CDE0
0.7 V < VI < 1.9 V
L
INV/NON
CDE1
L
CDE2
L
(a)
8A
8B+
9B–
9A
9B+
9DE/RE
3B+
4B–
4A
4B+
5B–
5A
5B+
5DE/RE
6B–
6A
6B+
6DE/RE
7B–
7A
7B+
7DE/RE
8B–
8A
8B+
8DE/RE
9B–
9A
9B+
9DE/RE
Control Inputs
CDE0
0.7 V < VI < 1.9 V
L
INV/NON
CDE1
L
CDE2
H
Control Inputs
CDE0
0.7 V < VI < 1.9 V
L
INV/NON
CDE1
H
CDE2
L
(b)
(c)
Figure 9. Logic Diagrams
6
3B–
3A
8B–
8B–
8A
2B+
6B–
6A
7B+
7DE/RE
2B–
2A
4B–
4A
5B+
5DE/RE
1B+
3B+
3DE/RE
4B–
4A
1A
2B–
2B–
2A
1B–
1B–
1A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1B–
1A
1B+
2B–
2A
2B+
1B–
1A
1B+
1DE/RE
2B–
2A
2B+
2DE/RE
1B–
1A
1B+
1DE/RE
2B–
2A
2B+
2DE/RE
3B–
3B–
3B–
3A
3B+
4B–
4A
4B+
5B–
5A
5B+
6B–
6A
6B+
7B–
7A
7B+
8B–
8A
8B+
3A
3A
3B+
3DE/RE
4B–
4A
4B+
4DE/RE
5B–
5A
9B+
9DE/RE
5DE/RE
6B–
6A
6B+
6DE/RE
7B–
7A
(a)
4B+
4DE/RE
5B–
5A
5B+
6B–
6A
6B+
7B–
7A
7B+
7B+
7DE/RE
8B–
8A
8B+
8DE/RE
9B–
9A
9B+
9DE/RE
Control Inputs
CDE0
0.7 V < VI < 1.9 V
L
INV/NON
CDE1
H
CDE2
H
4B–
4A
5B+
9B–
9A
3B+
3DE/RE
Control Inputs
CDE0
0.7 V < VI < 1.9 V
H
INV/NON
CDE1
L
CDE2
L
(b)
8B–
8A
8B+
9B–
9A
9B+
9DE/RE
Control Inputs
CDE0
0.7 V < VI < 1.9 V
H
INV/NON
CDE1
L
CDE2
H
(C)
Figure 10. Logic Diagrams
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1A
1B–
1A
1B–
1DE/RE
1A
1B–
1DE/RE
1B+
1B+
2A
2B–
2A
2B–
2DE/RE
1B+
2A
2B–
2DE/RE
2B+
2B+
3B–
3A
3B–
3A
3DE/RE
2B+
3B–
3A
3DE/RE
3B+
3B+
4B–
4A
4B–
4A
4DE/RE
3B+
4B–
4A
4DE/RE
4B+
4B+
5A
5B–
5A
5B–
4B+
5B–
5A
5DE/RE
5B+
5B+
5B+
6A
6B–
6A
6B–
6A
6B–
6DE/RE
6B+
6B+
6B+
7A
7B–
7A
7B–
7B–
7A
7DE/RE
7B+
7B+
7B+
8A
8B–
8A
8B–
8B–
8A
8DE/RE
8B+
8B+
8B+
9A
9B–
9A
9B–
9DE/RE
9B+
9DE/RE
9B+
9B+
Control Inputs
CDE0
0.7 V < VI < 1.9 V
H
INV/NON
CDE1
H
CDE2
H
(a)
Control Inputs
CDE0
VI < 0.5 V
L
INV/NON
CDE1
L
CDE2
L
(b)
Figure 11. Logic Diagrams
8
9B–
9A
9DE/RE
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• DALLAS, TEXAS 75265
Control Inputs
CDE0
VI < 0.5 V
INV/NON
L
CDE1
L
CDE2
H
(c)
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1A
1B–
1A
1A
1B–
1B–
1DE/RE
1B+
1B+
1B+
2A
2B–
2A
2A
2B–
2B–
2DE/RE
2B+
2B+
2B+
3A
3B–
3B–
3A
3B–
3A
3DE/RE
3B+
3B+
3B+
4A
4B–
4A
4B–
4B–
4A
4DE/RE
4B+
4B+
4B+
5A
5B–
5A
5A
5B–
5DE/RE
5B–
5DE/RE
5B+
5B+
6A
6B–
5B+
6A
6A
6B–
6DE/RE
6B–
6DE/RE
6B+
6B+
7A
7B–
6B+
7A
7B–
7DE/RE
7B–
7A
7DE/RE
7B+
7B+
8A
8B–
7B+
8A
8B–
8DE/RE
8B–
8A
8DE/RE
8B+
8B+
9A
9B–
9DE/RE
8B+
9A
9B–
9DE/RE
9B+
Control Inputs
CDE0
VI < 0.5 V
L
INV/NON
CDE1
H
CDE2
L
(a)
9B–
9A
9DE/RE
9B+
9B+
Control Inputs
CDE0
VI < 0.5 V
INV/NON
L
CDE1
H
CDE2
H
(b)
Control Inputs
CDE0
VI < 0.5 V
INV/NON
H
CDE1
L
CDE2
L
(c)
Figure 12. Logic Diagrams
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1A
1B–
1B–
1A
1B–
1A
1DE/RE
1B+
1B+
1B+
2A
2B–
2B–
2A
2A
2B–
2DE/RE
2B+
2B+
2B+
3A
3B–
3B–
3A
3B–
3A
3DE/RE
3B+
3B+
3B+
4A
4B–
4B–
4A
4B–
4A
4DE/RE
4B+
4B+
4B+
5A
5B–
5B–
5A
5B–
5A
5DE/RE
5B+
5B+
5B+
6A
6B–
6B–
6A
6B–
6A
6DE/RE
6B+
6B+
6B+
7A
7B–
7B–
7A
7B–
7A
7DE/RE
7B+
7B+
7B+
8A
8B–
8B–
8A
8B–
8A
8DE/RE
8B+
8B+
8B+
9A
9B–
9B–
9A
9DE/RE
9DE/RE
Control Inputs
CDE0
VI < 0.5 V
H
INV/NON
CDE1
H
CDE2
L
POST OFFICE BOX 655303
Control Inputs
CDE0
VI < 0.5 V
H
INV/NON
CDE1
H
CDE2
H
(b)
(b)
Figure 13. Logic Diagrams
10
9B+
9B+
9B+
Control Inputs
CDE0
VI < 0.5 V
H
INV/NON
CDE1
L
CDE2
H
(a)
9B–
9A
9DE/RE
• DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1A
High Z
1B–
1B+
High Z
High Z
2A
High Z
2B–
2B+
High Z
High Z
3B–
3B+
3A
High Z
High Z
High Z
4A
High Z
4B–
4B+
High Z
High Z
5A
High Z
5B–
5B+
High Z
High Z
6A
High Z
6B–
6B+
High Z
High Z
7A
High Z
7B–
7B+
High Z
High Z
8A
High Z
8B–
8B+
High Z
High Z
9A
High Z
9B–
9B+
High Z
High Z
Control Inputs
CDE0
VI > 2.5 V
X
INV/NON
CDE1
X
CDE2
X
Figure 14. Logic Diagrams
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• DALLAS, TEXAS 75265
11
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
input and output equivalent schematic diagrams
CDE1, CDE2, DE/RE Inputs
A and INV/NON Inputs
VCC
VCC
10uA
Input
Input
10uA
CDE0 Input
A Output
VCC
VCC
Input
A
B+ Input
B– Input
Iref
Iref
37 Ω
37 Ω
BP
BN
Iref
Iref
113 Ω
113 Ω
VCC
15 Ω
12
VCC
VCC
15 Ω
15 Ω
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
113 Ω
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
Terminal Functions
TERMINAL
NAME
NO.
’LVDM976
Logic
Level
’LVDM977
Logic
Level
I/O
Termination
DESCRIPTION
1A – 9A
4,6,8,10,
19,21,23,
25,27
CMOS
TTL
I/O
Pullup
1A – 9A carry data to and from the communication controller.
1B – – 9B –
29,31,33,
35,37,46,
48,50,52
LVD or
TTL
LVD or
TTL
I/O
None
1B – to 9B – are the signals to and from the data bus. When
INV/NON is low, the logic sense is the opposite that of the A
input (inverted). When INV/NON is high, the logic sense is the
same as the A input (noninverted).
1B+ – 9B+
30,32,34,
36,38,47,
49,51,53
LVD or
GND
LVD or
GND
I/O
None
When in the LVD mode, 1B+ – 9B+ are signals to or from the
data bus and follow the same logic sense as the A input when
INV/NON is low (noninverted). The logic sense is opposite that
of the A input (inverted) when INV/NON is high. When in
single-ended mode, these terminals become a ground
connection through a transistor and do not switch.
CDE0
54
Trinary
Trinary
Input
None
CDE0 is the common driver enable 0. With the driver enabled
and the CDE0 input less than 0.5 V, the driver output is
single-ended mode. With the driver enabled and the CDE0
input between 0.7 V and 1.9 V the driver output is LVD mode.
All drivers are disabled when the input is greater than 2.4 V.
CDE1
55
CMOS
TTL
Input
Pulldown
CDE1 is the common driver enable 1. When CDE1 is high,
drivers 1 – 4 are enabled
CDE2
56
CMOS
TTL
Input
Pulldown
CDE2 is the common driver enable 2. When CDE2 is high,
drivers 5 to 8 are enabled.
1DE/RE –
9DE/RE
5,7,9,11,
20,22,24,
26,28
CMOS
TTL
Input
Pulldown
1DE/RE – 9DE/RE are direction controls that transmit data to
the bus when it is high and CDE0 is below 2.2 V. Data is
received from the bus when 1DE/RE – 9DE/RE, CDE1, and
CDE2 are low.
GND
2,3,13,14,
15,16,17,
40,41,42,
43,44
NA
NA
Power
NA
1
CMOS
CMOS
Input
Pullup
12,18,39,
45
NA
NA
Power
NA
INV/NON
VCC
POST OFFICE BOX 655303
GND is the circuit ground.
A high-level input to INV/NON inverts the logic to and
from the A terminals. (i.e., the voltage at A terminal and
the corresponding B – terminal are in phase.)
Supply voltage
• DALLAS, TEXAS 75265
13
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (A, INV/NON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
(DE/RE, B+, B–, CDE0, CDE1, CDE2) . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.25 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65_C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND unless otherwise noted.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DGG
978 mW
10.8 mW/°C
492 mW
recommended operating conditions (see Figure 15)
Supply voltage, VCC
High level input voltage,
voltage VIH
High-level
Low level input voltage,
Low-level
voltage VIL
Differential input voltage, |VID|
High level output current,
High-level
current IOH
Low level output current
Low-level
current, IOL
MAX
UNIT
4.75
5
5.25
V
0.7 VCC
SN75LVDM977
2
V
SN75LVDM976
0.3 VCC
SN75LVDM977
0.8
Differential receiver
Differential
0.03
3.6
0.7
1.8
–100
–125
Single-ended driver
–7
Receiver
–2
Single-ended driver
48
Receiver
2
Differential load impedance, ZL
Operating free-air temperature, TA
14
NOM
SN75LVDM976
Common-mode input voltage, VIC
Differential output voltage bias, VOD(bias)
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
V
mV
mA
mA
40
65
Ω
0
70
°C
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IIH
High level input current
High-level
IIL
Low level input current
Low-level
TEST CONDITIONS
MIN
TYP†
CDE1 and CDE2
50
INV/NON
–50
CDE1 and CDE2
50
INV/NON
– 50
Disabled
ICC Supply current
CI
Input capacitance
Bus terminal
MAX
UNIT
µA
µA
7
LVD drivers enabled,
No load
26
Single-ended drivers enabled,
No load
10
LVD receivers enabled,
No load
26
Singled-ended receivers enabled,
No load
mA
7
VI = 0.2 sin (2 π (1E06)t) + 0.5 ± 0.01 V
9.5
∆CI Difference in input capacitance between B+ and B–
† All typical values are at VCC = 5 V, TA = 25°C.
pF
F
0.2
DIFFSENS (CDE0) receiver electrical characteristics over recommended operating free-air
temperature range (unless otherwise noted)
MIN
TYP†
MAX
VIT1
VIT2
Input threshold voltage
0.5
0.6
0.7
Input threshold voltage
1.9
2.1
2.4
II
Input current
PARAMETER
TEST CONDITIONS
0 V ≤ VI ≤ 2.7 V
II(OFF) Power-off input current
† All typical values are at VCC = 5 V, TA = 25°C.
VCC = 0,
POST OFFICE BOX 655303
0 V ≤ VI ≤ 2.7 V
• DALLAS, TEXAS 75265
UNIT
V
±1
µA
±1
µA
15
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
LVD driver electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
Driver differential high-level
g
output voltage
VOD(H)
Driver differential low-level output
voltage
VOD(L)
MIN
TYP†
MAX
270
460
780
0.69|VOD(L) |+ 50
270
500
1.45|VOD(L) |– 65
780
TEST CONDITIONS
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state commonmode output voltage between
logic states
VOC(PP)
Peak-to-peak common-mode
output voltage
IIH
High level input current
High-level
IIL
Low level input current
Low-level
IO(OFF)
IOS
Power-off output current
VI(1) = 0.96 V,, VI(2) = 0.53 V,,
See Figure 16
VI(1) = 1.96 V,, VI(2) = 1.53 V,,
See Figure 16
0.69|VOD(L) |+ 50
A
A
DE/RE
Short-circuit output current
mV
1.45|VOD(L) |– 65
VI(1) = 0.96 V, VI(2) = 0.53 V,
See Figure 16
– 260
– 400
– 640
VI(1) = 1.96 V, VI(2) = 1.53 V,
See Figure 16
– 260
– 400
– 640
mV
1.1
VI(1) = 1.41 V, VI(2) = 0.99 V,
See Figure 17
1.2
1.5
V
± 50
± 120
mV
150
mV
80
DE/RE
UNIT
–7
VIH = 3.3 V (’976)
(
)
VIH = 2 V (’977)
µA
50
– 30
VIL = 1.6 V ((’976))
VIL = 0.8 V (’977)
µA
8
VCC = 0, 0 V ≤ VO ≤ 2.5 V
0 V ≤ VO ≤ 2.5 V
IOZ
High-impedance output current
VO = 0 or 2.5 V
† All typical values are at VCC = 5 V, TA = 25°C.
±1
µA
± 24
mA
±1
µA
LVD driver switching characteristics over recommended operating conditions (unless otherwise
noted) (See Figure 16)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high level output
2.9
8.8
ns
Propagation delay time, high-to-low level output
2.9
8.8
ns
tr
tf
Differential output signal rise time
tsk(p)
tsk(lim)
Pulse skew (|tPHL – tPLH|)
Skew limit‡
V
VCC = 5 V,
VI2 = 0
0.99
99 V,
V
Differential output signal fall time
1 41 V,
V
VI1 = 1.41
TA = 25°C
25 C
1
3
6
ns
1
3
6
ns
3.7
ns
5.9
ns
tPHZ
Propagation delay time, high-level to high-impedance output VI1 = 1.41 V,
50
ns
VI2 = 0.99 V,
See Figure 18
ten
Enable time, receiver to driver
33
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same
ambient temperature.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
single-ended driver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
VOH
High level output voltage
High-level
TEST CONDITIONS
B output
B–
B– output
VOL
Low-level output voltage
IIH
High level input current
High-level
IIL
Low level input current
Low-level
IO(OFF)
IOZ
Power-off output current
B+
A
DE/RE
A
DE/RE
B–
High-impedance output current
IOH = –7 mA,
IOH = 0 mA
See Figure 19
VCC = 5 V,
IOL = –25 mA
IOL = 48 mA
MIN
TYP
2
UNIT
3.24
V
3.7
V
0.5
V
–0.5
IOL = 25 mA
0.5
–7
VIH = 3.3 V ((’976),
),
VIH = 2 V (’977)
50
–30
VIL = 1.6 V ((’976),
),
VIL = 0.8 V (’977)
VCC = 0,
VO = 0 or VCC
MAX
8
0 V ≤ VO ≤ 5.25 V
V
µA
µA
±1
µA
±1
µA
single-ended driver switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high level output
2.7
8.2
ns
Propagation delay time, high-to-low level output
2.7
8.2
ns
tr
tf
Differential output signal rise time
0.5
4
ns
0.5
4
ns
tsk(p)
tsk(lim)
Pulse skew (|tPHL – tPLH|)
Skew limit‡
3.4
ns
5.5
ns
Differential output signal fall time
VCC = 5 V,
TA = 25°C,
See Figure 19
ten
Enable time, receiver to driver
50
ns
See Figure 20
tPLZ
Propagation delay time, low-level to high-impedance output
30
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same
ambient temperature.
LVD receiver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
VIT–
Positive-going differential input voltage threshold
VOH
VOL
High-level output voltage
II
II(OFF)
Input current, B+ or B–
IIH
High-level input current, DE/RE
VIH = 3.3 V (’976),
VIH = 2 V (’977)
IIL
Low-level input current, DE/RE
VIL = 1.6 V (’976),
VIL = 0.8 V (’977)
IOZ
High-impedance output current
VO = 0 or VCC
Negative-going differential input voltage threshold
See Figure 21
IOH = –2 mA
IOL = 2 mA
Low-level output voltage
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
30
mV
–30
mV
3.7
VI = 0 V to 2.5 V
VCC = 0,
VI = 0 V to 2.5 V
Power-off Input current, B+ or B–
TYP
V
0.5
V
±1
µA
±1
µA
50
µA
µA
8
± 30
µA
17
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
LVD receiver switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high level output
tsk(p)
tr
Pulse skew (|tPHL – tPLH|)
tf
tsk(lim)
Output signal fall time
Skew limit‡
tPHZ
tPLZ
Propagation delay time, high-level to high-impedance output
42
ns
20
ns
Propagation delay time, high-to-low level output
VCC = 5 V,
TA = 25°C,
See Figure 21
Output signal rise time
4.5
10
ns
4.5
10
ns
3
ns
8
ns
8
ns
5.5
ns
See Figure 18
Propagation delay time, low-level to high-impedance output
ten
Enable time, driver to receiver
26
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same
ambient temperature.
single-ended receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIT+
VIT–
Positive-going input voltage threshold
B–
Negative-going input voltage threshold
B–
VOH
VOL
High-level output voltage
II
Input current
B–
II(OFF)
Power-off Input current
B–
IIH
High-level input current
DE/RE
VIH = 3.3 V (’976),
VIH = 2 V (’977)
IIL
Low-level input current
DE/RE
VIL = 1.6 V (’976),
VIL = 0.8 V (’977)
IOZ
High-impedance output current
IOH = –2 mA
IOL = 2 mA
Low-level output voltage
MIN
TYP
MAX
1.6
1.9
UNIT
V
1
1.1
V
3.7
4.6
V
0.3
VI = 0 to VCC
VCC = 0 V,
VI = 0 to 5.25 V
0.5
V
±1
µA
±1
µA
50
µA
µA
8
VO = 0 or VCC
–30
µA
single-ended receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high level output
7
12.5
ns
Propagation delay time, high-to-low level output
7
12.5
ns
tsk(p)
tr
Pulse skew (|tPHL – tPLH|)
3.5
ns
8
ns
tf
tsk(lim)
Output signal fall time
Skew limit†
8
ns
5.5
ns
tPHZ
tPLZ
Propagation delay time, high-level to high-impedance output
20
ns
30
ns
VCC = 5 V,
TA = 25°C,
See Figure 22
Output signal rise time
Propagation delay time, low-level to high-impedance output
See Figure 20
ten
Enable time, driver to receiver
48
ns
† tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same
ambient temperature.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
B+
II
IOB+
A
IOB–
VOD
OB
) ) VOB*
2
VOB+
B–
VI
V
VOC
VOB–
Figure 15. Voltage and Current Definitions
50 Ω
100 Ω
Input
5V
1.3 V
Open
Open
0 V or 5 V
A
DE/RE
CDE0
CDE1
CDE2
INV/NON
B–
V1
CL = 10 pF
+
–
75 Ω
VOD
B+
100 Ω
CL = 10 pF
0.7 VCC (’976)
2 V (’977)
INPUT
tPLH
tPHL
0.3 VCC (’976)
0.8 V (’977)
V2
+
–
Solid line is INV/NON at 0 V.
Dashed line is INV/NON at 5 V.
100%
80%
VOD(H)
OUTPUT
0V
VOD(L)
20%
0%
tf
tr
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 10 Mpps,
pulsewidth = 50 ns ± 5 ns, Zo = 50 Ω .
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 16. Differential Output Signal Test Circuit, Timing, and Voltage Definitions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V1
50 Ω
100 Ω
Input
5V
1.3 V
Open
Open
0 V or 5 V
A
DE/RE
CDE0
CDE1
CDE2
INV/NON
B–
37.5 Ω
B+
37.5 Ω
VOC
CL = 50 pF
100 Ω
V2
0.7 VCC (’976)
2 V (’977)
Input
0.3 VCC (’976)
0.8 V (’977)
VOC(PP)
VOC(SS)
Output
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 10 Mpps,
pulsewidth = 50 ns ± 5 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
C. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 17. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V1
100 Ω
CL = 50 pF
CL = 50 pF
V
620 Ω
Input
1.3 V
Open
Open
0 V or 5 V
B–
A
DE/RE
CDE0
CDE1
CDE2
INV/NON
37.5 Ω
VOD
37.5 Ω
B+
CL = 50 pF
100 Ω
V2
TEST CIRCUIT
V at 5 V, INV/NON at 0 V
V at 0 V, INV/NON at 5 V
0.7 VCC (’976)
2 V (’977)
Input
0.7 VCC (’976)
2 V (’977)
50%
50%
0.3 VCC (’976)
0.8 V (’977)
ten(d)
VOD
ten(d)
VA
tPHZ(d)
0.3 VCC (’976)
0.8 V (’977)
ten(d)
tPHZ(d)
≈ 0.4 V
≈ 0.4 V
0V
0V
≈ –0.12 V
≈ –0.12 V
ten(r)
ten(d)
ten(r)
5V
5V
1.4 V
1.4 V
≈ 0.2 V
≈ 0.2 V
VOLTAGE WAVEFORMS
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps,
pulsewidth = 500 ns ± 50 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 18. LVD Transceiver Enable and Disable Time Test Circuit and Definitions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
50 Ω
Input
0V
0V
Open
Open
0 V or 5 V
A
DE/RE
CDE0
CDE1
CDE2
INV/NON
IO
47 Ω
B–
CL = 10 pF
0.7 VCC (’976)
2 V (’977)
INPUT
0.3 VCC (’976)
0.8 V (’977)
tPLH
+
–
VO
2.5 V
Solid line is INV/NON
at a high-level input.
Dashed line is INV/NON
at a low-level input.
tPHL
100%
80%
OUTPUT
1.4 V
20%
0%
tf
tr
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 10 Mpps,
pulsewidth = 50 ns ± 5 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 19. Single-Ended Driver Switching Test Circuit
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
CL = 50 pF
VA
V
620 Ω
Input
0V
Open
Open
0 V or 5 V
47 Ω
B–
A
DE/RE
CDE0
CDE1
CDE2
INV/NON
CL = 10 pF
+
–
VB
2.5 V
TEST CIRCUIT
V and INV/NON at 5 V
V and INV/NON at 0 V
Input
ten(r)
0.7 VCC
0.7 VCC
50%
50%
0.3 VCC
0.3 VCC
tPHZ(r)
ten(r)
tPLZ(r)
VOL
VA
0.5 V
VOL
0.5 V
tPLZ(d)
ten(d)
tPLZ(d)
ten(d)
VB
VOL
VOL
0.5 V
0.5 V
VOLTAGE WAVEFORMS
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps,
pulsewidth = 500 ns ± 50 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 20. Single-Ended Transceiver Enable and Disable Timing Measurements
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
50 Ω
IIB+
IO
VID
VIB
50 Ω
VIB–
0V
1.3 V
Open
Open
0 or 5 V
CL = 15 pF
VO
IIB–
DE/RE
CDE0
CDE1
CDE2
INV/NON
TEST CIRCUIT
VIB
1.4 V
VIB–
1V
0.4 V
VID
0V
–0.4 V
tPLH
tPHL
VO
VOH
50%
VOL
80%
20%
tf
tr
Solid line is INV/NON
at a high-level input.
Dashed line is INV/NON
at a low-level input.
VOLTAGE WAVEFORMS
NOTES: A. Note: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 10 Mpps, pulsewidth = 50 ns ± 5 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 21. LVD Receiver Switching Characteristic Test Circuit
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
Input
GND
GND
Open
Open
GND or VCC
B–
DE/RE
CDE0
CDE1
CDE2
INV/NON
IO
A
CL = 15 pF
VO
2V
Solid line is INV/NON at a high-level input.
1.4 V
0.8 V Dashed line is INV/NONat a low-level input.
INPUT
tPLH
tPHL
VOH
100%
80%
OUTPUT
–1.4 V
20%
VOL
0%
tr
tf
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 10 Mpps,
pulsewidth = 50 ns ± 5 ns.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 22. Single-Ended Receiver Timing Test Circuit
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25
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
APPLICATION INFORMATION
U1
‘LVDM976
8.2 kΩ, 1/8 W, 5%
CDE0
U2
‘LVDM976
DIFFSENS
0.022 µF, 6 V, 10%
CDE0
U3
‘LVDM976
CDE0
Figure 23. Low-Pass Filter for Connecting DIFFSENS to CDE0
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
1,20 MAX
0,05 MIN
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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