TI SN65LVDM176

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
D
D
D
D
D
D
D
D
D
D
D
Low-Voltage Differential Driver and
Receiver for Half-Duplex Operation
Designed for Signaling Rates of 400 Mbit/s
ESD Protection Exceeds 15 kV on Bus Pins
Operates from a Single 3.3 V Supply
Low–Voltage Differential Signaling with
Typical Output Voltages of 350 mV and a
50Ω Load
Propagation Delay Times
– Driver: 1.7 ns Typ
– Receiver: 3.7 ns Typ
Power Dissipation at 200 MHz
– Driver: 50 mW Typical
– Receiver: 60 mW Typical
LVTTL Levels are 5 V Tolerant
Bus Pins are High Impedance When
Disabled or With VCC Less Than 1.5 V
Open-Circuit Fail-Safe Receiver
Surface-Mount Packaging
– D Package (SOIC)
– DGK Package (MSOP)
SN65LVDM176D (Marked as DM176 or LVM176)
SN65LVDM176DGK (Marked as M76)
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
logic diagram (positive logic)
DE
D
RE
R
3
4
2
6
1
7
A
B
description
The SN65LVDM176 is a differential line driver and receiver configured as a transceiver that uses low-voltage
differential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. These circuits are similar to
TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers
is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50Ω
load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference
of less than 100 mV with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for half-duplex or multiplex baseband data
transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The
transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and
distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to
the environment, and other application specific characteristics).
The SN65LVDM176 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D) †
MSOP
(DGK) †
– 40°C to 85°C
SN65LVDM176D
SN65LVDM176DGK
† The D package is available taped and reeled. Add the suffix R to the device type
(e.g., SN65LVDM176DR).
Function Tables
DRIVER
OUTPUTS
INPUT
D
ENABLE
DE
A
B
L
H
L
H
H
H
H
L
Open
H
L
H
X
L
Z
Z
H = high level, L = low level, X = irrelevant,
Z = high impedance
RECEIVER
DIFFERENTIAL INPUTS
VID = VA – VB
ENABLE
RE
OUTPUT
R
VID ≥ 100 mV
– 100 mV < VID < 100 mV
L
H
L
?
VID ≤ – 100 mV
Open
L
L
L
H
X
H
Z
H = high level, L = low level, X = irrelevant,
Z = high impedance
2
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
equivalent input and output schematic diagrams
VCC
VCC
VCC
300 kΩ
50 Ω
5Ω
10 kΩ
D or RE
Input
Y or Z
Output
50 Ω
DE
Input
7V
7V
7V
300 kΩ
VCC
VCC
300 kΩ
300 kΩ
5Ω
A Input
R Output
B Input
7V
7V
7V
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3
SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Voltage range (D, R, DE, RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
Electrostatic discharge (A, B , and GND) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . CLass 3, A:15 kV, B:600 V
All terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B:500 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D
725 mW
5.8 mW/°C
377 mW
DGK
424 mW
3.4 mW/°C
220 mW
recommended operating conditions
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
Low-level input voltage, VIL
MAX
UNIT
3.6
V
V
0.8
Ť Ť
Magnitude of differential input voltage, VID
0.1
V
ID
2
Common–mode input voltage, VIC (see Figure 1)
Operating free–air temperature, TA
4
–40
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2.4
Ť Ť
V
0.6
V
* V2ID
V
VCC–0.8
85
°C
SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
V IC – Common-Mode Input Voltage – V
Max at VCC > 3.15 V
Max at VCC = 3 V
2
1.5
1
0.5
Min
0
0
0.1
0.2
0.3
0.4
0.5
0.6
|VID| – Differential Input Voltage – V
Figure 1
device electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Driver and receiver enabled, No receiver load,
Driver RL = 50 Ω
ICC
Supply
Su
ly current
Driver enabled, Receiver disabled, RL = 50 Ω
Driver disabled, Receiver enabled, No load
Disabled
† All typical values are at 25°C and with a 3.3-V supply.
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MIN
TYP†
MAX
10
15
9
15
1.8
5
0.5
2
UNIT
mA
5
SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude between logic
states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage between
logic states
VOC(PP)
Peak-to-peak common-mode output voltage
IIH
High level input current†
High-level
IIL
Low level input current†
Low-level
IOS
Short circuit output current†
Short-circuit
DE
D
DE
D
RL = 50Ω,
50Ω
See Figure 2 and Figure 3
See Figure 4
MIN
TYP
MAX
247
340
454
UNIT
mV
–50
50
1.125
1.375
–50
50
mV
mV
VIH = 5 V
VIL = 0
0.8
8V
50
150
0.5
10
2
20
– 0.5
–10
2
10
VOA or VOB = 0 V
VOD = 0 V
–10
–10
V
µA
µA
mA
CI
Input capacitance
3
pF
† The non-algebraic convention, where the more positive (least negative) limit is designated maximum, is used in this data sheet for this parameter.
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VITH+
VITH–
Positive-going differential input voltage threshold
VOH
VOL
High-level output voltage
II
Input current (A or B inputs)‡
II(OFF)
IIH
Power-off input current (A or B inputs)
Negative-going differential input voltage threshold
See Figure 6
IOH = –8 mA
IOL = 8 mA
Low-level output voltage
VI = 0 V
VI = 2.4 V
High-level input current (enables)
VCC = 0 V or 1.8 V
VIH = 5 V
MIN
TYP†
MAX
100
–100
2.4
mV
V
0.4
–2
UNIT
–20
–1.2
V
µA
20
µA
10
µA
IIL
Low-level input current (enables)
VIL = 0.8 V
10
µA
IOZ
High-impedance output current‡
VO = 0 V or 5 V
±1
µA
† All typical values are at 25°C and with a 3.3-V supply.
‡ The non-algebraic convention, where the more positive (least negative) limit is designated maximum, is used in this data sheet for this parameter.
6
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low-to-high-level output
tsk(p)
tr
Pulse skew (|tpHL – tpLH|)
tf
tPZH
Differential output signal fall time
tPZL
tPHZ
Propagation delay time, high-to-low-level output
RL = 50Ω,
CL = 10 pF,
See Figure 3
Differential output signal rise time
MIN
TYP†
MAX
0.5
1.7
2.7
0.5
1.7
2.7
0.2
1
0.6
1
Propagation delay time, high-impedance-to-high-level output
8
12
Propagation delay time, high-impedance-to-low-level output
7
10
3
10
4
10
Propagation delay time, high-level-to-high-impedance output
tpLZ
Propagation delay time, low-level-to-high-impedance output
† All typical values are at 25°C and with a 3.3 V supply.
‡ tsk(lim) is the maximum delay time difference between drivers over temperature, VCC, and process.
ns
ns
0.6
See Figure 5
UNIT
ns
ns
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
2.3
3.7
4.5
2.3
3.7
4.5
tPLH
tPHL
Propagation delay time, low-to-high-level output
tsk(p)
tr
Pulse skew (|tpHL – tpLH|)
Output signal rise time
0.8
1.5
tf
tPZH
Output signal fall time
0.8
1.5
3
10
tPZL
tPHZ
Propagation delay time, low-level-to-low-impedance output
3
10
4
10
6
10
Propagation delay time, high-to-low-level output
F
CL = 10 pF,
See Figure 7
ns
0.4
Propagation delay time, high-level-to-high-impedance output
See Figure 8
Propagation delay time, high-impedance-to-high-level output
UNIT
tPLZ
Propagation delay time, low-impedance-to-high-level output
† All typical values are at 25°C and with a 3.3-V supply.
‡ tsk(lim) is the maximum delay time difference between drivers over temperature, VCC, and process.
ns
ns
PARAMETER MEASUREMENT INFORMATION
driver
IOA
Driver Enabled
A
II
D
IOB
VOD
V
VOA
B
VI
OA
) VOB
2
VOC
VOB
Figure 2. Driver Voltage and Current Definitions
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
driver (continued)
Driver Enabled
A
VOD
Input
50 Ω
±1%
B
CL = 10 pF
(2 Places)
2V
1.4 V
0.8 V
Input
tPHL
tPLH
100%
80%
VOD(H)
Output
0V
VOD(L)
20%
0%
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T.
Figure 3. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
25 Ω, ±1% (2 Places)
Driver Enabled
A
3V
D
D
Input
0V
B
VOC
VOC(PP)
CL = 10 pF
(2 Places)
VOC(SS)
VO
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T. The measurement of
VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
8
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
driver (continued)
25 Ω, ±1% (2 Places)
A
0.8 V or 2 V
B
DE
1.2 V
CL = 10 pF
(2 Places)
VOA
VOB
2V
1.4 V
0.8 V
DE
~1.4 V
1.25 V
1.2 V
VOA
tPZH
tPHZ
1.2 V
1.15 V
~1 V
VOB
tPZL
tPLZ
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver
A
V
IA
) VIB
R
VID
2
VIA
B
VIC
VO
VIB
Figure 6. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
(V)
10
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMONMODE INPUT VOLTAGE
(V)
VIA
1.215
VIB
1.185
VID
30
VIC
1.2
1.185
1.215
– 30
1.2
2.4
2.37
30
2.385
2.37
2.4
– 30
2.385
0.03
0
30
0.015
0
0.03
– 30
0.015
1.5
0.9
600
1.2
0.9
1.5
– 600
1.2
2.4
1.8
600
2.1
1.8
2.4
– 600
2.1
0.6
0
600
0.3
0
0.6
– 600
0.3
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
VID
VIA
VIB
CL
10 pF
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
– 0.4 V
tPHL
VO
tPLH
VOH
2.4 V
1.4 V
0.4 V
VOL
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T.
Figure 7. Timing Test Circuit and Waveforms
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
1.2 V
B
500 Ω
A
Inputs
RE
CL
10 pF
+
–
VO
VTEST
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 5000 ± 10 ns. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T.
2.5 V
VTEST
A
1V
2V
1.4 V
RE
0.8 V
tPZL
tPZL
tPLZ
2.5 V
1.4 V
R
VOL +0.5 V
VOL
0V
VTEST
A
1.4 V
2V
RE
1.4 V
0.8 V
tPZH
R
tPZH
tPHZ
VOH
1.4 V
VOH –0.5 V
0V
Figure 8. Enable/Disable Time Test Circuit and Waveforms
12
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
TA = 25°C
V OH – High-Level Output Voltage – V
V OL – Low-Level Output Voltage – V
4
3
2
1
3
2.5
2
1.5
1
.5
0
0
0
4
2
6
8
10
12
0
IOL – Low-Level Output Current – mA
–2
Figure 9
–6
–8
Figure 10
RECEIVER
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
4
VCC = 3.3 V
TA = 25°C
VOL – Low-Level Output Votlage – V
VCC = 3.3 V
TA = 25°C
VOH – High-Level Output Voltage – V
–4
IOH – High-Level Output Current – mA
3
2
1
4
3
2
1
0
0
0
–20
–40
–60
IOH – High-Level Output Current – mA
–80
0
10
20
30
40
50
IOL – Low-Level Output Current – mA
60
Figure 12
Figure 11
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2
t PLH – Low-To-High Propagation Delay Time – ns
t PLH – High-To-Low Propagation Delay Time – ns
2.5
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
1.5
–50
–30
10
–10
50
30
70
TA – Free-Air Temperature – °C
90
2.5
2
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
1.5
–50
–30
RECEIVER
RECEIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE–AIR TEMPERATURE
4.5
VCC = 3.3 V
4
VCC = 3 V
3.5
VCC = 3.6 V
3
2.5
–50
–30
–10
10
50
30
70
TA – Free–Air Temperature – °C
90
4.5
VCC = 3 V
4
VCC = 3.3 V
3.5
VCC = 3.6 V
3
2.5
–50
–30
Figure 15
14
90
Figure 14
t PLH – Low-To-High Level Propagation Delay Time – ns
t PLH – High-To-Low Level Propagation Dealy Time – ns
Figure 13
10
–10
50
30
70
TA – Free-Air Temperature – °C
10
–10
50
30
70
TA – Free-Air Temperature – °C
Figure 16
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the
power and dual supply requirements.
Transmission Distance – m
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
100M
Data Rate – Hz
Figure 17. Data Transmission Distance Versus Rate
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SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100
mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it
handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
VIT ≈ 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pull-up currents from the receiver and the fail-safe feature.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
APPLICATIONS INFORMATION
A
100 Ω
D
A
100 Ω
D
B
DE
B
DE
RE
RE
R
+
_
+
_
R
Bidirectional Half-Duplex Applications
D/R
D/R
D/R
D/R
100 Ω
100 Ω
D/R
D/R
D/R
D/R
Multipoint Bus Applications
Note A: Keep drivers and receivers as close to the LVDS bus side connector as possible.
Figure 19. Bidirectional Half-Duplex and Multipoint Bus Applications
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
18
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
SLLS320C – DECEMBER 1998 – REVISED MARCH 2000
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°– 6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15 MIN
0,10
4073329/A 02/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-187
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
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