TI SN65LVDS1050

SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
D
D
D
D
D
D
D
D
D
D
D
Typically Meets or Exceeds ANSI
TIA/EIA-644-1995 Standard
Operates From a Single 2.4-V to 3.6-V
Supply
Signaling Rates up to 400 Mbit/s
Bus-Terminal ESD Exceeds 12 kV
Low-Voltage Differential Signaling With
Typical Output Voltages of 285 mV and a
100 Ω Load
Propagation Delay Times
– Driver: 1.7 ns Typ
– Receiver: 3.7 ns Typ
Power Dissipation at 200 MHz
– Driver: 25 mW Typical
– Receiver: 60 mW Typical
LVTTL Input Levels Are 5 V Tolerant
Driver Is High Impedance When Disabled or
With VCC < 1.5 V
Receiver Has Open-Circuit Fail Safe
Available in Thin Shink Outline Packaging
With 20-mil Lead Pitch
SN65LVDS1050PW
(Marked as DL1050 or DLS1050)
(TOP VIEW)
1B
1A
1R
RE
2R
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
14
15
1D
13
12
DE
VCC
1D
1Y
1Z
DE
2Z
2Y
2D
10
9
11
2D
2
3
1
1R
4
RE
6
5
7
2R
1Y
1Z
2Y
2Z
1A
1B
2A
2B
DRIVER FUNCTION TABLE
INPUTS
OUTPUTS
D
DE
Y
Z
L
H
L
H
H
H
H
L
Open
H
L
H
X
L
Z
Z
H = high level, L = low level, Z = high impedance,
X = don’t care
description
The SN65LVDS1050 is similar to the
SN65LVDS050 except that it is characterized for
operation with a lower supply voltage range and
packaged in the thin shrink outline package for
portable battery-powered applications.
The differential line drivers and receivers use
low-voltage differential signaling (LVDS) to
achieve signaling rates as high as 400 Mbps. The
drivers provide a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
and receipt of 100-mV signals with up to 1 V of
ground potential difference between a transmitter
and receiver.
RECEIVER FUNCTION TABLE
INPUTS
OUTPUT
VID = VA – VB
VID ≥ 100 mV
RE
R
L
H
–100 MV < VID < 100 mV
L
?
VID ≤ –100 mV
Open
L
L
L
H
X
H
Z
H = high level, L = low level, Z = high impedance,
X = don’t care
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media
may be printed-circuit board traces, backplanes, or cables. Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of the media, the noise coupling to the environment and other
application-specific characteristics.
The SN65LVDS1050 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
equivalent input and output schematic diagrams
VCC
VCC
VCC
300 kΩ
50 Ω
5Ω
10 kΩ
D or RE
Input
Y or Z
Output
50 Ω
DE
Input
7V
7V
7V
300 kΩ
VCC
VCC
300 kΩ
300 kΩ
5Ω
A Input
R Output
B Input
7V
7V
2
7V
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Voltage range (D, R, DE, RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Voltage range (Y, Z, A, and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge: Y, Z, A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . . CLass 3, A:12 kV, B:600 V
All terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B:500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PW
774 mW
6.2 mW/°C
402 mW
recommended operating conditions (see Note 3)
Supply voltage, VCC
MIN
NOM
2.4
2.7
High-level input voltage, VIH
MAX
UNIT
3.6
V
2
V
Low-level input voltage, VIL
0.8
Magnitude of differential input voltage, VID
0.1
0
g VIC (see
(
g
Common–mode input voltage,
Figure
8))
Operating free–air temperature, TA
–40
2.4
Ť Ť
V
0.6
V
* V2ID
V
VCC–0.8
85
°C
NOTE 3: The common-mode input voltage, VIC, is not fully 644 compliant when VCC = 2.4 V.
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
device electrical characteristics over recommended operating conditions (unless otherwise
noted)
TYP†
MAX
Driver and receiver enabled, No receiver load,
Driver RL = 100 Ω
12
20
Driver enabled, Receiver disabled, RL = 100 Ω
10
16
3
6
0.5
1
PARAMETER
ICC
TEST CONDITIONS
Supply
Su
ly current
MIN
Driver disabled, Receiver enabled, No load
Disabled
† All typical values are at 25°C and with a 2.7-V supply.
UNIT
mA
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude between logic
states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage between
logic states
VOC(PP)
Peak-to-peak common-mode output voltage
IIH
High level input current
High-level
IIL
Low level input current
Low-level
IOS
Short circuit output current
Short-circuit
VOY or VOZ = 0 V
VOD = 0 V
IOZ
High impedance output current
High-impedance
VOD = 600 mV
VO = 0 V or VCC
IO(OFF)
CIN
Power-off output current
VCC = 0 V, VO = 3.6 V
DE
D
DE
D
100Ω
RL = 100Ω,
See Figure 1 and Figure 2
See Figure 3
MIN
TYP
MAX
247
285
454
UNIT
mV
–50
50
1.125
1.375
–50
50
mV
50
150
mV
– 0.5
– 20
2
20
– 0.5
–10
2
20
3
10
3
10
VIH = 5 V
VIL = 0
0.8
8V
±1
±1
±1
Input capacitance
3
V
µA
µA
mA
µA
µA
pF
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VITH+
VITH–
Positive-going differential input voltage threshold
VOH
VOL
High-level output voltage
II
Input current (A or B inputs)
II(OFF)
IIH
Power-off input current (A or B inputs)
Negative-going differential input voltage threshold
IOH = –8 mA
IOL = 8 mA
Low-level output voltage
VI = 0
VI = 2.4 V
High-level input current (enables)
IIL
Low-level input current (enables)
IOZ
High-impedance output current
† All typical values are at 25°C and with a 2.7-V supply.
4
See Figure 5
POST OFFICE BOX 655303
MIN
TYP†
MAX
100
–100
2
mV
V
0.4
–2
UNIT
–20
–1.2
V
µA
VCC = 0
VIH = 5 V
±20
µA
±10
µA
VIL = 0.8 V
VO = 0 or 5 V
±10
µA
±10
µA
• DALLAS, TEXAS 75265
SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
1.7
2.7
ns
1.7
3
ns
0.8
1
ns
0.8
1
ns
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
tr
tf
Differential output signal rise time
tsk(p)
tsk(o)
Pulse skew (|tpHL – tpLH|)
300
Channel-to-channel output skew‡
150
tPZH
tPZL
Propagation delay time, high-impedance-to-high-level output
7.8
10
ns
7.3
10
ns
tPHZ
tpLZ
Propagation delay time, high-level-to-high-impedance output
5.2
10
ns
6.6
10
ns
Propagation delay time, high-to-low-level output
RL = 100Ω,
CL = 10 pF,
pF
See Figure 2
Differential output signal fall time
Propagation delay time, high-impedance-to-low-level output
See Figure 4
Propagation delay time, low-level-to-high-impedance output
ps
ps
† All typical values are at 25°C and with a 2.7-V supply.
‡ tsk(o) is the maximum delay time difference between drivers on the same device.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
3.7
5.2
ns
Propagation delay time, high-to-low-level output
3.7
4.5
ns
tsk(p)
tr
Pulse skew (|tpHL – tpLH|)
Output signal rise time
0.8
1.5
ns
tf
tPZH
Output signal fall time
0.8
1.5
ns
Propagation delay time, high-level-to-high-impedance output
5.4
ns
tPZL
tPHZ
Propagation delay time, low-level-to-low-impedance output
6.3
ns
6.1
ns
6.9
ns
CL = 10 pF,
F
See Figure 6
0.3
See Figure 7
Propagation delay time, high-impedance-to-high-level output
tPLZ
Propagation delay time, low-impedance-to-high-level output
† All typical values are at 25°C and with a 2.7-V supply.
ns
PARAMETER MEASUREMENT INFORMATION
driver
IOY
Driver Enable
Y
II
A
IOZ
VOD
V
VOY
Z
VI
OY
) VOZ
2
VOC
VOZ
Figure 1. Driver Voltage and Current Definitions
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
driver (continued)
Driver Enable
Y
VOD
Input
100 Ω
±1%
Z
CL = 10 pF
(2 Places)
2V
1.4 V
0.8 V
Input
tPHL
tPLH
100%
80%
VOD(H)
Output
0V
VOD(L)
20%
0%
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
49.9 Ω, ±1% (2 Places)
Driver Enable
3V
Y
Input
0V
Z
VOC
VOC(PP)
CL = 10 pF
(2 Places)
VOC(SS)
VOC
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
6
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
driver (continued)
49.9 Ω, ±1% (2 Places)
Y
0.8 V or 2 V
Z
DE
1.2 V
CL = 10 pF
(2 Places)
VOY
VOZ
2V
1.4 V
0.8 V
DE
VOY or VOZ
tPZH
~1.4 V
1.25 V
1.2 V
D at 2 V and input to DE
1.2 V
1.15 V
~1 V
D at 0.8 V and input to DE
tPHZ
VOZ or VOY
tPZL
tPLZ
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver
A
V
IA
) VIB
R
VID
2
VIA
B
VIC
VO
VIB
Figure 5. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
(V)
8
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMONMODE INPUT VOLTAGE
(V)
VIA
1.25
VIB
1.15
VID
100
VIC
1.2
1.15
1.25
– 100
1.2
2.4
2.3
100
2.35
2.3
2.4
– 100
2.35
0.1
0
100
0.05
0
0.1
– 100
0.05
1.5
0.9
600
1.2
0.9
1.5
– 600
1.2
2.4
1.8
600
2.1
1.8
2.4
– 600
2.1
0.6
0
600
0.3
0
0.6
– 600
0.3
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
VID
VIA
VIB
CL
10 pF
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
– 0.4 V
tPHL
VO
tPLH
VOH
2.4 V
1.4 V
0.4 V
VOL
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 6. Timing Test Circuit and Waveforms
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
1.2 V
B
500 Ω
A
Inputs
RE
CL
10 pF
+
–
VO
VTEST
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
2.5 V
VTEST
A
1V
2V
1.4 V
RE
0.8 V
tPZL
tPZL
tPLZ
2.5 V
1.4 V
R
VOL +0.5 V
VOL
0V
VTEST
A
1.4 V
2V
RE
1.4 V
0.8 V
tPZH
R
tPZH
tPHZ
VOH
1.4 V
VOH –0.5 V
0V
Figure 7. Enable/Disable Time Test Circuit and Waveforms
10
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
RECEIVER
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
3
VIC – Common-Mode Input Voltage – V
2.5
VCC = 3.6 V
VCC = 2.7 V
2
1.5
VCC = 2.4 V
1
0.5
MIN
0
0
0.1
0.2
0.3
0.4
0.6
0.5
0.7
0.8
|VID|– Differential Input Voltage – V
Figure 8
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
VCC = 2.4 V
TA = 25°C
VOH – High-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
4
3
2
1
0
0
1
2
3
4
IOL – Low-Level Output Current – mA
VCC = 2.4 V
TA = 25°C
3
2.5
2
1.5
1
0.5
0
–4
–3
–2
–1
0
IOH – High-Level Output Current – mA
Figure 9
Figure 10
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
VCC = 2.4 V
TA = 25°C
VCC = 2.4 V
TA = 25°C
VOH – High-Level Output Voltage – V
VOL – Low-Level Output Votlage – V
3
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
2
1
2
1
0
–50
0
0
10
20
30
IOL – Low-Level Output Current – mA
40
–10
–30
–20
IOH – High-Level Output Current – mA
Figure 12
Figure 11
DRIVER
DRIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2
t PLH – Low-To-High Propagation Delay Time – ns
t PLH – High-To-Low Propagation Delay Time – ns
2.5
VCC = 3.3 V
VCC = 2.7 V
VCC = 3.6 V
1.5
–50
–30
–10
10
50
30
70
TA – Free-Air Temperature – °C
90
2.5
2
VCC = 3.3 V
VCC = 2.7 V
VCC = 3.6 V
1.5
–50
–30
Figure 13
12
0
–40
10
–10
50
30
70
TA – Free-Air Temperature – °C
Figure 14
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
RECEIVER
RECEIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE–AIR TEMPERATURE
4.5
VCC = 3.3 V
4
VCC = 2.7 V
3.5
VCC = 3.6 V
3
2.5
–50
–30
–10
10
50
30
70
TA – Free–Air Temperature – °C
90
t PLH – Low-To-High Level Propagation Delay Time – ns
t PLH – High-To-Low Level Propagation Dealy Time – ns
TYPICAL CHARACTERISTICS
4.5
VCC = 2.7 V
4
VCC = 3.3 V
3.5
VCC = 3.6 V
3
2.5
–50
–30
Figure 15
10
–10
50
30
70
TA – Free-Air Temperature – °C
90
Figure 16
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SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the
power and dual supply requirements.
Transmission Distance – m
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
Data Rate – Hz
Figure 17. Data Transmission Distance Versus Rate
14
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100M
SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and
100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level, regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt
100 Ω Typ
Y
B
VIT ≈ 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
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15
SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS343A – APRIL 1999 – REVISED MARCH 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
16
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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