CY54FCT543T, CY74FCT543T 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCCS030A – MAY 1994 – REVISED OCTOBER 2001 D D D D D D D D D D D D Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully Compatible With TTL Input and Output Logic Levels 3-State Outputs ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Separation Controls for Data Flow in Each Direction Back-to-Back Latches for Storage CY54FCT543T – 48-mA Output Sink Current – 12-mA Output Source Current CY74FCT543T – 64-mA Output Sink Current – 32-mA Output Source Current CY54FCT543T . . . D PACKAGE CY74FCT543T . . . Q OR SO PACKAGE (TOP VIEW) LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CEBA B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB description The ’FCT543T octal latched transceivers contain two sets of eight D-type latches with separate latch-enable (LEAB, LEBA) and output-enable (OEAB, OEBA) inputs for each set to permit independent control of input and output in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB) input must be low in order to enter data from A or to take data from B, as indicated in the function table. With CEAB low, a low signal on the A-to-B latch-enable (LEAB) input makes the A-to-B latches transparent; a subsequent low-to-high transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB low, the 3-state B-output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEBA, LEBA, and OEBA inputs. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY54FCT543T, CY74FCT543T 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCCS030A – MAY 1994 – REVISED OCTOBER 2001 PIN DESCRIPTION NAME DESCRIPTION OEAB A-to-B output-enable input (active low) OEBA B-to-A output-enable input (active low) CEAB A-to-B enable input (active low) CEBA B-to-A enable input (active low) LEAB A-to-B latch-enable input (active low) LEBA B-to-A latch-enable input (active low) A A-to-B data inputs or B-to-A 3-state outputs B B-to-A data inputs or A-to-B 3-state outputs ORDERING INFORMATION QSOP – Q SOIC – SO QSOP – Q –40°C to 85°C SOIC – SO QSOP – Q SOIC – SO –55°C 55°C to 125°C SPEED (ns) PACKAGE† TA CDIP – D ORDERABLE PART NUMBER Tape and reel 5.3 CY74FCT543CTQCT Tube 5.3 CY74FCT543CTSOC Tape and reel 5.3 CY74FCT543CTSOCT Tape and reel 6.5 CY74FCT543ATQCT Tube 6.5 CY74FCT543ATSOC Tape and reel 6.5 CY74FCT543ATSOCT Tape and reel 8.5 CY74FCT543TQCT Tube 8.5 CY74FCT543TSOC Tape and reel 8.5 CY74FCT543TSOCT Tube 10 CY54FCT543TDMB Tube 10 TOP-SIDE MARKING FCT543C FCT543C FCT543A FCT543A FCT543 FCT543 CY54FCT543TLMB † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE‡ INPUTS LEAB OEAB LATCH A TO B§ H X X Storing Z X H X Storing X X X H X Z L L L Transparent Current A inputs L H L Storing Previous A inputs CEAB OUTPUT B H = High logic level, L = Low logic level, X = Don’t care, Z = High-impedance state ‡ A-to-B data flow shown; B-to-A flow control is the same, except uses CEBA, LEBA, and OEBA. § Before LEAB low-to-high transition 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY54FCT543T, CY74FCT543T 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCCS030A – MAY 1994 – REVISED OCTOBER 2001 logic diagram (positive logic) OEBA CEBA LEBA OEAB CEAB LEAB A0 2 23 1 13 11 14 LE 3 Q 22 D B0 LE Q D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) CY54FCT543T CY74FCT543T MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –32 mA IOL TA Low-level output current 48 64 mA 85 °C High-level input voltage 2 Operating free-air temperature –55 2 125 –40 V V NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY54FCT543T, CY74FCT543T 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCCS030A – MAY 1994 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH CY54FCT543T TYP† MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.75 V, IIN = –18 mA IIN = –18 mA VCC = 4.5 V, IOH = –12 mA IOH = –32 mA VCC = 4 4.75 75 V MIN –0.7 –1.2 –0.7 2.4 2.4 Vhys All inputs II VCC = 5.5 V, VCC = 5.25 V, VIN = VCC VIN = VCC 5 IIH VCC = 5.5 V, VCC = 5.25 V, VIN = 2.7 V VIN = 2.7 V ±1 IIL VCC = 5.5 V, VCC = 5.25 V, VIN = 0.5 V VIN = 0.5 V ±1 IOZH VCC = 5.5 V, VCC = 5.25 V, VOUT = 2.7 V VOUT = 2.7 V 10 IOZL VCC = 5.5 V, VCC = 5.25 V, VOUT = 0.5 V VOUT = 0.5 V –10 IOS‡ VCC = 5.5 V, VCC = 5.25 V, VOUT = 0 V VOUT = 0 V VCC = 0 V, VCC = 5.5 V, VOUT = 4.5 V VIN ≤ 0.2 V, ∆ICC ICCD¶ 0.3 3.3 0.55 IOL = 64 mA 0.3 0.2 0.55 0.2 ±1 ±1 10 –10 –120 –225 –60 –120 ±1 VIN ≥ VCC – 0.2 V VIN ≥ VCC – 0.2 V VCC = 5.25 V, VIN ≤ 0.2 V, VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.1 0.5 VCC = 5.5 V, Outputs open, One input switching at 50% duty cycle, CEAB and OEAB = low, CEBA = high, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VCC = 5.25 V, Outputs open, One input switching at 50% duty cycle, CEAB and OEAB = low, CEBA = high, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.06 V V 5 –60 V V 2 IOH = –15 mA IOL = 48 mA VCC = 4.5 V, VCC = 4.75 V, ICC –1.2 UNIT 3.3 VOL Ioff CY74FCT543T TYP† MAX MIN –225 ±1 0.2 0.1 0.2 0.5 2 2 µA µA µA µA µA mA µA mA mA 0.12 mA/ MHz 0.06 0.12 † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶ This parameter is derived for use in total power-supply calculations. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY54FCT543T, CY74FCT543T 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCCS030A – MAY 1994 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER One bit switching at f1 = 5 MHz at 50% duty cycle IC# CY54FCT543T TYP† MAX TEST CONDITIONS VCC = 5.5 V, f0 = 10 MHz, Outputs open,, CEAB and OEAB = Eight bits low, CEBA = high, switching f0 = LEAB = 10 MHz at f = 5 MHz 1 at 50% duty cycle One bit switching at f1 = 5 MHz at 50% duty cycle VCC = 5.25 V, f0 = 10 MHz, Outputs open,, CEAB and OEAB = Eight bits low, CEBA = high, switching f0 = LEAB = 10 MHz at f = 5 MHz 1 at 50% duty cycle MIN VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.7 1.4 VIN = 3.4 V or GND 1.2 3.4 VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 2.8 5.6|| VIN = 3.4 V or GND 5.1 14.6|| CY74FCT543T TYP† MAX MIN UNIT mA VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.7 1.4 VIN = 3.4 V or GND 1.2 3.4 VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 2.8 5.6|| VIN = 3.4 V or GND 5.1 14.6|| Ci Co † Typical values are at VCC = 5 V, TA = 25°C. # IC = ICC + ∆ICCDHNT + ICCD(f0/2 + f1N1) ICC = Quiescent current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. 5 10 5 10 pF 9 12 9 12 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY54FCT543T PARAMETER MIN MAX CY74FCT543T MIN MAX CY74FCT543AT MIN MAX CY74FCT543CT MIN MAX UNIT tw tsu Pulse duration, LEAB or LEBA 5 5 5 5 ns Setup time, data before LEAB↓ or LEBA↓ 3 2 2 2 ns th Hold time, data after LEAB↓ or LEBA↓ 2 2 2 2 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CY54FCT543T, CY74FCT543T 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCCS030A – MAY 1994 – REVISED OCTOBER 2001 switching characteristics over operating free-air temperature range (see Figure 1) 6 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LEBA or LEAB A or B tPZH tPZL OEBA or OEAB A or B tPZH tPZL CEBA or CEAB A or B tPHZ tPLZ OEBA or OEAB A or B tPHZ tPLZ CEBA or CEAB A or B CY54FCT543T CY74FCT543T CY74FCT543AT CY74FCT543CT MIN MAX MIN MAX MIN MAX MIN MAX 2 10 2.5 8.5 2.5 6.5 2.5 5.3 2 10 2.5 8.5 2.5 6.5 2.5 5.3 2.5 14 2.5 12.5 2.5 8 2.5 7 2.5 14 2.5 12.5 2.5 8 2.5 7 2 14 2 12 2 9 2 8 2 14 2 12 2 9 2 8 2 14 2 12 2 9 2 8 2 14 2 12 2 9 2 8 2 13 2 9 2 7.5 2 6.5 2 13 2 9 2 7.5 2 6.5 2 13 2 9 2 7.5 2 6.5 2 13 2 9 2 7.5 2 6.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns CY54FCT543T, CY74FCT543T 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCCS030A – MAY 1994 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω TEST S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V Timing Input tw tsu 3V 1.5 V Input 1.5 V 0V th 3V Data Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9222101M3A ACTIVE LCCC FK 28 1 TBD 5962-9222101MLA ACTIVE CDIP JT 24 1 TBD CY54FCT543TDMB ACTIVE CDIP JT 24 1 TBD CY54FCT543TLMB ACTIVE LCCC FK 28 1 TBD CY74FCT543ATQCT ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543ATQCTE4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543ATQCTG4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543ATSOC ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543ATSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543ATSOCG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543ATSOCT ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543ATSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543ATSOCTG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543CTQCT ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543CTQCTE4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543CTQCTG4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543CTSOC ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543CTSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543CTSOCG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543CTSOCT ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543CTSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543CTSOCTG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543TQCT ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543TQCTE4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543TQCTG4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CY74FCT543TSOC ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT543TSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type A42 SNPB N / A for Pkg Type POST-PLATE N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CY74FCT543TSOCG4 ACTIVE SOIC DW 24 CY74FCT543TSOCT ACTIVE SOIC DW CY74FCT543TSOCTE4 ACTIVE SOIC CY74FCT543TSOCTG4 ACTIVE SOIC Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CY74FCT543ATQCT Package Package Pins Type Drawing SSOP/ QSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT543ATSOCT SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CY74FCT543CTQCT SSOP/ QSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT543CTSOCT SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CY74FCT543TQCT SSOP/ QSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT543TSOCT SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CY74FCT543ATQCT SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 CY74FCT543ATSOCT SOIC DW 24 2000 346.0 346.0 41.0 CY74FCT543CTQCT SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 CY74FCT543CTSOCT SOIC DW 24 2000 346.0 346.0 41.0 CY74FCT543TQCT SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 CY74FCT543TSOCT SOIC DW 24 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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