Ordering number : ENA2129 Monolithic Linear IC LA72703V For US TV BTSC Decoder Overview The LA72703V is a US TV BTSC Decoder. Features • With SIF circuit, alignment-free* STEREO channel separation. * When Base Band signal input, separation is adjusted by input level. • Dual Slave address (80h, 84h). Functions • SIF FM-Demodulator. • STEREO decoder. • dbx Noise Reduction. • STEREO detection. • STEREO detection sensitivity change function. • SAP demodulator. • SAP detection. • SAP output select 2-levels. • SAP detection sensitivity change function. Specifications Maximum Ratings at Ta = 25°C Parameter Maximum power supply voltage Symbol Conditions VCCH max Ta ≤ 85°C * Ratings Unit 7.0 V 290 mW Allowable power dissipation Pd max Operating temperature Topr -20 to +85 °C Storage temperature Tstg -55 to +150 °C ∗ When mounted on a 114.3mm×76.1mm×1.6mm glass epoxy board. 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O0312NKPC 20080821-S00007 No.A2129-1/12 LA72703V Operating Condition at Ta = 25°C Parameter Symbol Recommended operating voltage VCC Allowable operating voltage range VCCHop Conditions Ratings Unit 5.0 V 4.5 to 5.5 V Electrical Characteristics at Ta = 25°C, VCC = 5.0V Parameter Symbol Ratings Conditions min Current dissipation ICC No signal Inflow current at pin 19, default condition SIF input level VILIM fc = 4.5MHz (Reference) typ Unit max 30 40 50 (80) (90) (100) dBμV mA dBV Deviation MONO (300Hz, Mod = 100%, Pre-emphasis ON) → ±25kHz Base band input level VILIMB (Reference) 100% Modulation MONO(L+R) : 530mVp-p (300Hz, Pre-emphasis ON) SUB(L-R) : 380mVp-p (300Hz, dbx-NR ON), Pilot : 110mVp-p SAP : 300mVp-p (300Hz, dbx-NR ON) MONO output level VOMON fm = 1kHz, 100% Mod, 15kHz LPF MONO distortion THDMON fm = 1kHz, 100% Mod, 15kHz LPF MONO frequency characteristics FCM1 fm = 3kHz, 30% Mod, Pre-em. ON MONO S/N ratio SNM S = VOMON, N = 0% Mod, 15kHz LPF STEREO output level VOST fm = 1kHz, 100% Mod, 15kHz LPF STEREO distortion THDS fm = 1kHz, 100% Mod, 15kHz LPF STEREO frequency characteristics FCS1 fm = 3kHz, 30% Mod, 15kHz LPF STEREO S/N ratio SNS STEREO separation 1 STEREO separation 2 STEREO Detection level-1 -7.0 -2 -5.5 -4.0 0.15 0.6 % 0 2 dB * Measure ratio from fm = 1kHz level. 55 65 -7.0 -5.5 -4.0 dB dBV 0.5 1.0 % -2 0 2 dB S = VOST, N = 0% Mod, 15kHz LPF 50 60 dB STSE1 f = 300Hz (R/L), 30% Mod, 15kHz LPF 20 25 dB STSE2 f = 3kHz (R/L), 30% Mod, 15kHz LPF 20 25 VINSD1 Except Stereo Detection → Stereo Detection 30 38 45 % 40 47 55 % 10 20 30 % -14.0 -11.0 -8.0 dBV -7.5 -5.5 -3.5 dBV 0.7 1.5 % * Measure ratio from fm = 1kHz level. dB * serial control 1 “SENS HI” Pilot (fH) = 15.73kHz * Measure Pilot level. STEREO Detection level-2 VINSD2 Except Stereo Detection → Stereo Detection * serial control “SENS LO” STEREO Detection hysteresis HYST Input Mod. Difference at Stereo/Except Stereo Det. * serial control 1 “SENS HI” SAP output level-1 VOSA1 fm = 1kHz, 100% Mod, 15kHz LPF * SAP-1 (serial control) SAP output level-2 VOSA2 fm = 1kHz, 100% Mod, 15kHz LPF * SAP-2 (serial control) SAP distortion THDSA fm = 1kHz, 100% Mod, 15kHz LPF SAP S/N ratio SNSA S = VOSA, N = 0% Mod, 15kHz LPF 50 60 SAP detection level-1 VINSA1 Except SAP → SAP Det. 10 22 35 % 17 30 42 % 2 5 10 % dB * serial control 1 “SENS HI” SAP Carrier = 5fH only * Measure Output level. SAP detection level-2 VINSA2 Except SAP → SAP Det. * serial control 1 “SENS LO” * Measure Output level. SAP detection hysteresis HYSA Input Mod. Difference at SAP/Except SAP Det. * SAP carrier only. * serial control 1 “SENS HI” MODE output MONO MODMO Input = MONO : f = 1kHz, 0% Mod 0.7 1 1.3 V MODE output SAP MODSA Input = SAP : Carrier 1.6 1.9 2.2 V MODE output STEREO MODST Input = STEREO : Pilot 2.5 2.8 3.1 V MODE output ST + SAP MODSS Input = STEREO : Pilot, 3.5 3.8 4.2 V SAP : Carrier * Normally measurement condition is Input = SIF mode (90dBμV) * " Reference " items are reference levels, their specs are no-guarantee. Continued on next page. No.A2129-2/12 LA72703V Continued from preceding page. Parameter Symbol Ratings Conditions min Stereo detect speed STDT Input = STEREO : Pilot Unit typ max (480) (1000) ms (350) (1000) ms I2C data no-send (Reference) Measure pin 20 voltage change to 2.8V timing from Power ON SAP detect speed SAPDT SAP : Carrier I2C data no-send (Reference) Measure pin 20 voltage change to 1.9V timing from Power ON Package Dimensions unit : mm (typ) 3175C 7.8 24 0.5 5.6 7.6 13 12 1 0.65 0.15 1.5max (1.3) 0.22 0.1 (0.33) SANYO : SSOP24(275mil) No.A2129-3/12 + 1μF + 1 PILOT DET STEREO PLL 24 3 1μF to 0.33μF 2 SAP BPF 4 + SIF SIGNAL from Tuner 4.5M BPF 0.1μF 5 SIF DEMOD 4.7μF + LPF SAP DEMOD L-R DEMOD MODE OUT 20 47μF PILOT CANCELLER REGULATOR 21 2.2μF + -6dB 22 1μF + PILOT LEVEL DET 23 1μF + 0.1μF * SAP sensitivity measure only pin 7 Resisotor remove 4.7kΩ 6 GND ST/SAP SW MUTE MUTE 19 8 Address 14 I2C CLOCK 10 11 2.2μF + ST SAP Offset Cancell dbx processor 13 + 4.7μF 12 22μF + 22μF + Slave Address = 80h (1000 000*) : Pin8 = OPEN/GND Slave Address = 84h (1000 010*) : Pin8 = H I2C DATA 9 I2C DECODE + 4.7μF 15 SYSTEM CONTROL 16 Control 4.7μF 33nF + L-R/SAP Address Control 0.1μF 560kΩ * 7 SAP DET LPF 17 33nF MATRIX L+R LPF 18 0.1μF 100μF 10μF + 10μF + Offset Cancel 1μF Spectral In VCC 5V Wide RMS DET OUT(R) Spectral DET OUT(L) Spectral RMS DET MODE Monitor out LA72703V Block Diagram and Application No.A2129-4/12 LA72703V Pin Functions Pin No. Pin Name Function DC voltage Equivalent Circuit AC level 1 PCPLDET Pilot level detect For Stero Detection DC : 2.4V 40kΩ 1 40kΩ 1kΩ 160kΩ 2 PC_DC_IN AC coupling (Input) DC : 2.4V AC : 2.4Vp-p 3 PC_DCOUT AC coupling (Output) DC : 2.4V 3 500Ω 2 1kΩ AC : 2.4Vp-p 4 PC FIL SIF offset cancel DC : 2.6V 1kΩ 1kΩ 4 5 PISIF Signal input DC : 3.7V Common input at SIF, Base band 5 10kΩ 500Ω 1kΩ 6 GND 7 CSAPDET SAP carrier level detect For SAP detection DC : 2.8V 70kΩ 1kΩ 2kΩ 1kΩ 1kΩ 7 8 ADDSEL Slave Address change control OPEN/GND : 80h 5V DC : 0V 8 : 84h 1kΩ 100kΩ Continued on next page. No.A2129-5/12 LA72703V Continued from preceding page. Pin No. Pin Name Function DC voltage Equivalent Circuit AC level 9 SDA 5V Serial data input 9 1kΩ 0V 10 SCL 5V Serial clock input 10 1kΩ 0V 11 PC DBXIN Offset cancel Feedback filter DC : 2.4V 11 12 PCDETSPE Spectral band RMS detect 5kΩ DC : 2.3V 1kΩ 200Ω 12 13 PCTIMSPE dbx spectral detect DC : 2.4V 13 14 PCTNWID Wide band RMS detect 5kΩ DC : 2.4V 1kΩ 200Ω 14 15 PCSPECIN dbx main signal V/I convert filter DC : 2.4V 15 10kΩ 16 PC_KE6B Offset cancel filter DC : 2.4V AC : 220mVp-p 250Ω 500Ω 16 500Ω Continued on next page No.A2129-6/12 LA72703V Continued from preceding page. Pin No. Pin Name Function DC voltage Equivalent Circuit AC level 17 PORCH Line out R DC : 2.4V AC : 1.4Vp-p 50kΩ 300Ω 300Ω 17 50kΩ 18 POLCH Line out L DC : 2.4V AC : 1.4Vp-p 50kΩ 300Ω 300Ω 18 50kΩ 19 VCC 20 POLED MONO = 0.9V DC : See Right SAP = 2.0V AC STEREO = 3.0V Test only 20 STEREO + SAP = 3.8V 1kΩ Mode out 21 PCREG Reference Voltage DC : 2.4V 10kΩ 9.6kΩ 500Ω 21 1kΩ 22 PMAINOUT Offset cancel Feedback filter DC : 1.6V 450kΩ 22 500Ω 23 PCPLC Pilot level detect DC : 2.4V For Pilot canceller 40kΩ 40kΩ 1kΩ 160kΩ 23 24 PCPTFILT Pilot level detect DC : 2.4V For ST PLL filter 40kΩ 40kΩ 1kΩ 160kΩ 24 No.A2129-7/12 LA72703V I2C BUS serial interface specification (1) Data Transfer Manual This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial clock) and SDA (serial data).At first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes “H”, this IC pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 Defined by SCL rise down SDA during “H” period. *2 Defined by SCL rise up SDA during “H” period. (2) Transfer Data Format After transfer start condition, transfers slave address (1000 000*) to SDA terminal, control data, then, stop condition (See figure 1). Slave address is made up of 7bits,*3 8th bit shows the direction of transferring data, if it is “L”, takes write mode (As this IC side, this is input operation mode), and in case of “H”, reading mode (As this IC side, this is output operation mode). Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled the transfer dates. *3 It is called R/W bit. Fig.1 DATA STRUCTURE “WRITE” mode START Condition Slave Address R/WL ACK Control data ACK STOP condition ACK Internal Data * ACK STOP condition Fig.2 DATA STRUCTURE “READ” mode START condition Slave Address R/WH * After data outputs, ACK outputs. Output data as follows ; bit8 is result of STERO DET (H : STEREO), bit7 is result of SAP DET (H : SAP), bit6 to bit1 are fixed to “L” No.A2129-8/12 LA72703V (3) Initialize This IC is initialized for circuit protection. Initial condition is “0 (All bits) ”. Reference Parameter Symbol LOW level input voltage min max unit VIL -0.5 1.5 HIGH level input voltage VIH 2.5 5.5 V LOW level output current IOL 3.0 mA 100 kHz 0 V SCL clock frequency fSCL Set-up time for a repeated START condition tSU : STA 4.7 μs Hold time START condition. After this period, the first clock pulse is generated tHD : STA 4.0 μs LOW period of the SCL clock tLOW 4.7 Rise time of both SDA and SDL signals tR 0 μs 1.0 μs μs HIGH period of the SCL clock tHIGH Fall time of both SDA and SDL signals tF 4.0 0 Data hold time : tHD : DAT 0 Data set-up time tSU : DAT 250 ns Set-up time for STOP condition tSU : STO 4.0 μs BUS free time between a STOP and START condition tBUF 4.7 μs 1.0 μs μs Definition of timing tR t HI G H tF S CL t HD : S TA t SU : S TA t LO W t HD : D AT A t SU : D AT t SU : S TO t BU F S DA No.A2129-9/12 LA72703V I2C Control Table Grp-1 (Normally use : group-1 only) D8 D7 D6 D5 D4 D3 * * * D2 D1 Condition 0 0 Stereo 0 1 SAP 1 0 Both 1 1 MUTE 0 Normal (Auto det) 1 Forced Mono 0 SAP SENS LO 1 * * * * SAP SENS HI 0 Stereo SENS LO 1 Stereo SENS HI 0 SAP Level-1 1 SAP Level-2 0 SIF mode 1 Base Band mode 0 Fix 1 Prohibit (TEST MODE) * : Shows Initial condition Read out data D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 Condition Fixed 0 Normal 1 SAP det 0 Normal 1 Stereo det Test mode condition (Reference) When STOP condition transform at Grp-1 data-end, controlled NORMAL mode. Grp-2 is only test condition. Usually, these data are no-need. Their data are no guarantee, except all L condition. D8 D7 D6 D5 0 0 0 0 D4 D3 D2 D1 Condition/Monitor position 0 0 0 0 Normal (Usually, Fixed) 0 0 0 1 TEST-1 SIF output 0 0 1 0 TEST-2 SAP BPF 0 0 1 1 TEST-3 (reserved) 0 1 0 0 TEST-4 ST VCO 0 1 0 1 TEST-5 (reserved) 0 1 1 0 TEST-6 SAP monitor 0 1 1 1 TEST-7 ST monitor 1 0 0 0 TEST-8 Pilot cancel monitor 1 0 0 1 TEST-9 Dbx 2.19k LPF 1 0 1 0 TEST-10 Dbx 408 LPF 1 0 1 1 TEST-11 Dbx DET 10k LPF 1 1 0 0 TEST-12 Dbx SPEC 7.6k LPF 1 1 0 1 TEST-13 Dbx SPEC output 1 1 1 0 TEST-14 L+R/L-R monitor 1 1 1 1 TEST-15 Dbx 2.09k LPF Blanc Bit are no-care Slave addresses are 80h (1000 000*, at pin8 Open/GND) and 84h (1000 010*, at pin8 H). No.A2129-10/12 LA72703V Mode Condition I2C data in Signal Rch Mode pin17 condition 0 L R Stereo 0 1 SAP SAP SAP-1 0 1 SAP SAP SAP-2 0 1 0 L+R SAP MULTI-1 0 1 0 L+R SAP MULTI-2 1 0 0 L+R L+R F-MONO 1 0 1 L+R L+R F-MONO 1 1 0 L+R L+R F-MONO * 1 1 Off Off MUTE (1) 0 0 0 L R Stereo Hi 0 0 1 L R Stereo D7 D6 D5 D4 D3 D2 D1 (0) (0) * (0) (0) 0 0 S I F 0 S T E R E O S A P 0 F 0 S E N S Lo I Stereo Lch pin18 D8 1 0 X 1 + SAP * * * S E N S Lo * Stereo (1) * B A S E * b a n d (1) Hi I2C out Output mode * 0 1 0 L R Stereo * 1 0 0 L+R L+R F-MONO * 1 0 1 L+R L+R F-MONO * 1 1 0 L+R L+R F-MONO * * 1 1 Off Off MUTE * * 0 0 L+R L+R MONO 0 0 0 1 SAP SAP SAP-1 Mono 1 0 0 1 SAP SAP SAP-2 + SAP 0 0 1 0 L+R SAP MULTI-1 1 0 1 0 L+R SAP MULTI-2 * * 1 1 Off Off MUTE * * 0 0 L+R L+R MONO * * 0 1 L+R L+R MONO * * 1 0 L+R L+R MONO * * 1 1 Off Off MUTE MONO Mode D8 D7 1 1 3.8V 1 0 2.8V 0 1 1.9V 0 0 1.0V pin20 * : no care No.A2129-11/12 LA72703V SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. Regarding monolithic semiconductors, if you should intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a confirmation. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. 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Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2012. Specifications and information herein are subject to change without notice. PS No.A2129-12/12