Ordering number : ENA0979 LA72702NV Monolithic Linear IC BTSC Decoder for US TV http://onsemi.com Overview The LA72702NV is a US TV BTSC Decoder. Features • With SIF circuit, alignment-free* STEREO channel separation. * When base band signal input, separation is adjusted by input level. • Dual slave address(80h, 84h). Functions • SIF FM-Demodulator • STEREO detection • STEREO decoder • STEREO detection sensitivity change function • dbx Noise Reduction • SAP demodulator • SAP detection • SAP output select 2-levels • SAP detection sensitivity change function Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum power supply voltage VCCH max Allowable power dissipation Pd max Conditions Ratings Ta≤85°C, Mounted on a specified board* Unit 7.0 V 290 mW Operating temperature Topr -20 to +85 °C Storage temperature Tstg -55 to +150 °C * Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy board Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Operating Conditions at Ta = 25°C Parameter Symbol Recommended operating voltage vacate Allowable operating voltage range VCCH op Semiconductor Components Industries, LLC, 2013 July, 2013 Conditions Ratings Unit 5.0 V 4.5 to 5.5 V N2807 TI IM 20070112-S00005 No.A0979-1/10 LA72702NV Electrical Characteristics at Ta = 25°C, VDD = 5.0V Parameter Symbol Ratings Conditions min Current dissipation SIF input level (Reference) ICC VILIM No signal Inflow current at pin 19, default condition fc = 4.5MHz typ Unit max 30 40 50 (80) (90) (100) dBμV mA -5.5 -4.5 dBV 0.15 0.6 % 0 2 dB Deviation MONO (300Hz, Mod = 100%, Pre-emphasis ON) Æ ±25kHz Base band input level (Reference) VILIMB 100% Modulation MONO(L+R) : 530mVp-p (300Hz, Pre-emphasis ON) MONO output level MONO distortion VOMON THDMON SUB(L-R) : 380mVp-p (300Hz, dbx-NR ON), Pilot : 110mVp-p SAP : 300mVp-p (300Hz, dbx-NR ON) fm=1kHz, 100% Mod, 15kHz LPF -7.0 fm=1kHz, 100% Mod, 15kHz LPF MONO frequency characteristics FCM1 fm=3kHz, 30% Mod, Pre-emphasis ON MONO S/N ratio SNM S=VOMON, N=0% Mod, 15kHz LPF STEREO output level VOST fm=1kHz, 100% Mod, 15kHz LPF STEREO distortion THDS fm=1kHz, 100% Mod, 15kHz LPF STEREO frequency characteristics FCS1 -2 * Measure ratio from fm=1kHz level. fm=3kHz, 30% Mod, 15kHz LPF 55 65 -7.0 -5.5 -4.5 dBV dB 0.5 1.0 % -2 0 2 dB 50 60 * Measure ratio from fm=1kHz level. STEREO S/N ratio SNS S=VOST, N=0% Mod, 15kHz LPF dB STEREO separation 1 STSE1 f=300Hz (R/L), 30% Mod, 15kHz LPF 20 25 dB STEREO separation 2 STSE2 f=3kHz (R/L), 30% Mod, 15kHz LPF 20 25 dB STEREO Detection level-1 VINSD1 Except Stereo Detection Æ Stereo Detection 30 38 45 % 38 47 53 % 10 20 30 % -14.0 -11.0 -8.0 dBV -7.5 -5.5 -3.5 dBV 0.7 1.5 * Serial control “SENS HI” Pilot (fH)=15.73kHz * Measure pilot level. STEREO Detection level-2 VINSD2 Except Stereo Detection Æ Stereo Detection * Serial control “SENS LO” STEREO Detection hysteresis HYST Input Mod. Difference at Stereo/Except Stereo Det. * Serial control “SENS HI” SAP output level-1 VOSA1 fm=1kHz, 100% Mod, 15kHz LPF * SAP-1 (serial control) SAP output level-2 VOSA2 fm=1kHz, 100% Mod, 15kHz LPF * SAP-2 (serial control) SAP distortion THDSA SAP S/N ratio SNSA SAP detection level-1 VINSA1 fm=1kHz, 100% Mod, 15kHz LPF % S=VOSA2, N=0% Mod, 15kHz LPF 50 60 dB Except SAP → SAP Det. 10 17 24 % 17 24 31 % 2 5 10 % V * Serial control “SENS HI” SAP Carrier=5fH only * Measure output level. SAP detection level-2 VINSA2 Except SAP → SAP Det. * Serial control “SENS LO” * Measure output level. SAP detection hysteresis HYSA Input Mod. Difference at SAP/Except SAP Det. * SAP carrier only. * Serial control “SENS HI” MODE output MONO MODMO Input=MONO : f=1kHz, 0% Mod 0.7 1 1.3 MODE output SAP MODSA Input=SAP : Carrier 1.6 1.9 2.2 V MODE output STEREO MODST Input=STEREO : Pilot 2.5 2.8 3.1 V MODE output ST + SAP MODSS Input=STEREO : Pilot, SAP : Carrier 3.5 Stereo detect speed (Reference ) STDT Input=STEREO : Pilot 3.8 4.2 (480) (1000) ms V (350) (1000) ms I2C data no-send Measure pin 20 voltage change to 2.8V timing from Power ON SAP detect speed (Reference ) SAPDT SAP : Carrier I2C data no-send Measure pin 20 voltage change to 1.9V timing from Power ON * Normally measurement condition is Input = SIF mode (90dBμV) * " Reference " Items are reference levels, their specs are no-guarantee. No.A0979-2/10 LA72702NV Package Dimensions unit : mm (typ) 3175C 7.8 24 0.5 5.6 7.6 13 12 1 0.65 (0.33) 0.15 1.5max 0.1 (1.3) 0.22 SANYO : SSOP24(275mil) Mode Condition I2C data in I2C out Output mode Signal D4 D3 D2 D1 Lch pin18 Rch pin17 Mode condition D8 D7 Mode pin20 (0) (0) 0 0 0 L R Stereo 1 1 3.8V 0 STEREO SAP 0 0 1 SAP SAP SAP-1 1 SENS SENS 0 0 1 SAP SAP SAP-2 Lo Lo 0 1 0 L+R SAP MULTI-1 (1) (1) 0 1 0 L+R SAP MULTI-2 Hi Hi 1 0 0 L+R L+R F-MONO ∗ 1 0 1 L+R L+R F-MONO ∗ 1 1 0 L+R L+R F-MONO ∗ ∗ 1 1 Off Off MUTE ∗ 0 0 0 L R Stereo 1 0 2.8V ∗ 0 0 1 L R Stereo ∗ 0 1 0 L R Stereo ∗ 1 0 0 L+R L+R F-MONO ∗ 1 0 1 L+R L+R F-MONO ∗ 1 1 0 L+R L+R F-MONO ∗ ∗ 1 1 Off Off MUTE Mono ∗ ∗ 0 0 L+R L+R MONO 0 1 1.9V + SAP 0 0 0 1 SAP SAP SAP-1 1 0 0 1 SAP SAP SAP-2 0 0 1 0 L+R SAP MULTI-1 1 0 1 0 L+R SAP MULTI-2 ∗ ∗ 1 1 Off Off MUTE ∗ ∗ 0 0 L+R L+R MONO 0 0 1.0V ∗ ∗ 0 1 L+R L+R MONO ∗ ∗ 1 0 L+R L+R MONO ∗ ∗ 1 1 Off Off MUTE D8 D7 D6 ∗ Stereo (0) (0) + SAP FIX SIF (1) BASE band 0 1 ∗ Stereo MONO D5 * : no care No.A0979-3/10 LA72702NV 2 I C Control Table Grp-1 (Normally use : group-1 only) D8 D7 D6 D5 D4 D3 * * D2 D1 Condition 0 0 Stereo 0 1 SAP 1 0 Both 1 1 MUTE 0 Normal (Auto DET) 1 * Forced Mono 0 SAP SENS LO 1 * * * * SAP SENS HI 0 Stereo SENS LO 1 Stereo SENS HI 0 SAP Level-1 1 SAP Level-2 0 SIF mode 1 Base Band mode 0 Fix 1 Prohibit (TEST MODE) * : Shows Initial condition Read out data D8 D7 D6 D5 D4 D3 D2 D1 Condition 0 0 0 0 0 0 Fixed 0 Normal 1 SAP det 0 Normal 1 Stereo det Test mode condition(Reference) When STOP condition transform at Grp-1 data-end, controlled NORMAL mode. Grp-2 is only test condition. Usually, these data are no-need. Their data are no guarantee, except all L condition. D8 D7 D6 D5 0 0 0 0 D4 D3 D2 D1 Condition/Monitor position 0 0 0 0 Normal (Usually, Fixed) 0 0 0 1 TEST-1 SIF output 0 0 1 0 TEST-2 SAP BPF 0 0 1 1 TEST-3 (reserved) 0 1 0 0 TEST-4 ST VCO 0 1 0 1 TEST-5 (reserved) 0 1 1 0 TEST-6 SAP monitor 0 1 1 1 TEST-7 ST monitor 1 0 0 0 TEST-8 Pilot cancel monitor 1 0 0 1 TEST-9 dbx 2.19k LPF 1 0 1 0 TEST-10 dbx 408 LPF 1 0 1 1 TEST-11 dbx DET 10k LPF 1 1 0 0 TEST-12 dbx SPEC 7.6k LPF 1 1 0 1 TEST-13 dbx SPEC output 1 1 1 0 TEST-14 L+R/lL-R monitor 1 1 1 1 TEST-15 dbx 2.09k LPF Blank Bits are no-care Slave addresses are 80h (1000 000*, at pin8 Open/GND) and 84h (1000 010*, at pin8 H). No.A0979-4/10 4.7kΩ 1μF + 1 PILOT DET STEREO PLL 24 2 SAP BPF 4 + SIF SIGNAL from Tuner 4.5M BPF 0.1μF 5 SIF DEMOD 4.7μF + 1μF to 0.33μF 3 LPF SAP DEMOD L-R DEMOD MODE OUT 20 47μF PILOT CANCELLER REGULATOR 21 2.2μF + -6dB 22 1μF + PILOT LEVEL DET 23 1μF + 0.1μF *: SAP Sensitivity only pin7. Resistor remove. + 6 GND ST/SAP SW MUTE MUTE 19 0.1μF 7 8 16 Control 14 I2C CLOCK 10 2.2μF ST SAP 11 Offset Cancell dbx processor 13 + 4.7μF 12 22μF + 22μF + SLAVE ADDRESS = 80h (1000 000 *) : Pin8 = OPEN/GND SLAVE ADDRESS = 84h (1000 010 *) : Pin8 = H I2C DATA 9 I2C DECODE + 4.7μF 15 SYSTEM CONTROL L-R/SAP Address 17 Address Control *560kΩ SAP DET LPF L+R MATRIX LPF 18 10μF 10μF 4.7μF + + + 0.1μF 0.033μF 0.033μF 100μF Offset Cancel 1μF Spectral In OUT(R) Wide RMS DET OUT(L) Spectral DET VCC 5V Spectral RMS DET MODE Monitor out LA72702NV Block Diagram and Application No.A0979-5/10 LA72702NV Pin Functions Pin No. 1 Pin Name PCPLDET Function Pilot level detect for stero detection DC: voltage Equivalent Circuit AC: level DC : 2.4V 40kΩ 1 40kΩ 1kΩ 160kΩ 2 PC_DC_IN AC coupling (Input) DC : 2.4V AC : 2.4Vp-p 3 PC_DCOUT AC coupling (Output) DC : 2.4V 3 500Ω 2 1kΩ AC : 2.4Vp-p 4 PC FIL SIF offset cancel DC : 2.6V 1kΩ 1kΩ 4 5 PISIF Signal input DC : 3.7V Common input at SIF, Base band 10kΩ 5 500Ω 1kΩ 6 GND 7 CSAPDET SAP carrier level detect for SAP detection DC : 2.8V 70kΩ 1kΩ 2kΩ 1kΩ 1kΩ 7 8 ADDSEL Slave address change control OPEN/GND : 80h 5V DC : 0V 8 : 84h 1kΩ 100kΩ Continued on next page. No.A0979-6/10 LA72702NV Continued from preceding page. Pin No. 9 Pin Name SDA Function DC: voltage Equivalent Circuit AC: level Serial data input 5V 9 1kΩ 0V 10 SCL Serial clock input 5V 10 1kΩ 0V 11 PC DBXIN Offset cancel feedback filter DC: 2.4V 11 12 PCDETSPE Spectral band RMS detect 5kΩ DC: 2.3V 1kΩ 200Ω 12 13 PCTIMSPE dbx spectral detect DC: 2.4V 13 14 PCTNWID Wide band RMS detect 5kΩ DC: 2.4V 1kΩ 200Ω 14 15 PCSPECIN dbx main signal V/I convert filter DC: 2.4V 15 10kΩ 16 PC KE6B Offset cancel feedback filter DC: 2.4V AC: 220mVp-p 250Ω 500Ω 16 500Ω Continued on next page. No.A0979-7/10 LA72702NV Continued from preceding page. Pin No. 17 Pin Name PORCH Function Line out R DC: voltage Equivalent Circuit AC: level DC: 2.4V AC: 1.4Vp-p 50kΩ 300Ω 300Ω 17 50kΩ 18 POLCH Line out L DC: 2.4V AC: 1.4Vp-p 50kΩ 300Ω 300Ω 18 50kΩ 19 VCC 20 POLED Mode out DC: See Right MONO = 0.9V SAP = 2.0V STEREO = 3.0V AC: Test only 20 1kΩ STEREO + SAP = 3.8V 21 PCREG Reference voltage DC: 2.4V 500Ω 10kΩ 9.6kΩ 21 1kΩ 22 PMAINOUT Offset cancel feedback filter DC: 1.6V 450kΩ 500Ω 23 PCPLC Pilot level detect for pilot canceller 22 DC: 2.4V 40kΩ 40kΩ 1kΩ 160kΩ 23 Continued on next page. No.A0979-8/10 LA72702NV Continued from preceding page. Pin No. 24 Pin Name PCPTFILT DC: voltage Function Equivalent Circuit AC: level Pilot level detect for ST PLL filter DC: 2.4V 40kΩ 40kΩ 1kΩ 160kΩ 24 I2C BUS Serial Interface Specification (1) Data transfer manual This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial clock) and SDA (serial data).At first, set up*1 the condition of starting data transfer, and after that, input 8 bit data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this IC pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 Defined by SCL rise down SDA during ‘H’ period. *2 Defined by SCL rise up SDA during ‘H’ period. (2) Transfer data format After transfer start condition, transfers slave address (1000 000*) to SDA terminal, control data, then, stop condition (See figure 1). Slave address is made up of 7bits, *38th bit shows the direction of transferring data, if it is ‘L’ takes write mode (As this IC side, this is input operation mode), and in case of ‘H’ reading mode (As this IC side, this is output operation mode). Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled the transfer dates. *3 It is called R/W bit. Fig.1 DATA STRUCTURE “WRITE” mode START Condition Slave Address R/W L ACK Control data ACK STOP condition ACK Internal Data * ACK STOP condition Fig.2 DATA STRUCTURE “READ” mode START condition Slave Address R/W H ∗ The output data synchronizes with the clock of SCL pin. Then, the ACK output is made after the output data. bit8 is result of STERO DET (H : STEREO) bit7 is result of SAP DET (H : SAP) bit6 to bit1 are fixed to ‘L’ (3) Initialize This IC is initialized for circuit protection. Initial condition is “0 (All bits) ”. No.A0979-9/10 LA72702NV Reference Parameter Symbol min max unit LOW level input voltage VIL -0.5 1.5 HIGH level input voltage VIH 2.5 5.5 V LOW level output current IOL 3.0 mA 100 kHz SCL clock frequency fSCL 0 V Set-up time for a repeated START condition tSU : STA 4.7 μs Hold time START condition. After this period, the first clock pulse is generated tHD : STA 4.0 μs tLOW 4.7 μs LOW period of the SCL clock Rise time of both SDA and SDL signals tR HIGH period of the SCL clock 0 tHIGH Fall time of both SDA and SDL signals tF 1.0 0 μs μs 4.0 1.0 μs μs Data hold time tHD : DAT 0 Data set-up time tSU : DAT 250 ns Set-up time for STOP condition tSU : STO 4.0 μs tBUF 4.7 μs BUS free time between a STOP and START condition Definition of timing tR t HI G H tF S CL t HD : S TA t SU : S TA t LO W t HD : D AT A t SU : D AT t SU : S TO t BU F S DA ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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