ESDAVLC8-1BU2 Single-line low capacitance Transil™, transient surge voltage suppressor (TVS) for bidirectional ESD protection Datasheet − production data Features ■ Bidirectional device ■ Withstands multiple ESD strikes ■ Very low diode capacitance: 5 pF typ. at 0 V ■ Low leakage current ■ 0201 SMD package size compatible ■ Ultra small PCB area: 0.18 mm2 ■ RoHS compliant Pin 2 available in different forms ST0201 package Benefits ■ High ESD protection level ■ High integration ■ Suitable for high density boards ■ MSL1 Figure 1. Functional diagram (top view) Complies with the following standards: ■ IEC 61000-4-2 level 4 – 15 kV (air discharge) – 8 kV (contact discharge) Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Portable multimedia players and accessories ■ Notebooks ■ Digital cameras and camcorders ■ Communication systems ■ Cellular phone handsets and accessories Description The ESDAVLC8-1BU2 is a bidirectional single line TVS diode designed to protect the data lines or other I/O ports against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required. TM: Transil is a trademark of STMicroelectronics May 2012 This is information on a product in full production. Doc ID 16546 Rev 2 1/11 www.st.com 11 Characteristics ESDAVLC8-1BU2 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Value Unit VPP Peak pulse voltage: IEC 61000-4-2 contact discharge EC 61000-4-2 air discharge ± 15 ± 16 kV IPP Peak pulse current (8/20 µs) 1.5 A Tj Junction temperature 125 °C - 55 to +150 °C 260 °C -40 to +125 °C Max. Unit Tstg Parameter Storage temperature range TL Maximum lead temperature for soldering during 10 s Top Operating junction temperature range Figure 2. Electrical characteristics (definitions) Symbol VBR VCL IRM VRM IF IPP IR VF Rd aT Table 2. Parameter Breakdown voltage Clamping voltage Leakage current @ VRM Stand-off voltage Forward current Peak pulse current Breakdown current Forward voltage drop Dynamic impedance Voltage temperature Electrical characteristics (values, Tamb = 25 °C) Symbol VBR = = = = = = = = = = Test Condition Min. Typ. From pin1 to pin 2, IR = 1 mA 8.5 11 From pin 2 to pin1, IR = 1 mA 14.5 17 V IRM VRM = 3 V Rd Square pulse, IPP = 1 A tp = 2.5 µs αT ΔVBR = αT(Tamb - 25 °C) x VBR (25 °C) Cline VR = 0 V, Fosc = 1 MHz, Vosc = 30 mV 2/11 100 nA 6 10-4/°C 7 pF Ω 2.5 Doc ID 16546 Rev 2 5 ESDAVLC8-1BU2 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. Peak pulse power versus exponential pulse duration PPP(W) PPP[T j initial] / PPP [T j initial=25°C] 1000 1.1 Tj initial = 25°C 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 tP(µs) T j(°C) 0.1 0.0 10 0 25 Figure 5. 50 75 100 125 150 Junction capacitance versus reverse applied voltage (typical values) 1 Figure 6. C(pF) 5 10 100 1000 Relative variation of leakage current versus junction temperature (typical values) IR [T j] / IR [T j=25°C] 100 F=1MHz VOSC=30mVRMS Tj=25°C 4 VR =3V 3 10 2 1 T j(°C) VR (V) Figure 7. 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 -2.0 -3.0 -4.0 -5.0 0 ESD response to IEC 61000-4-2 (+8 kV contact discharge) 10 V/Div 1 25 Figure 8. 50 75 100 125 ESD response to IEC 61000-4-2 (-8 kV contact discharge) 10 V/Div 20 ns/Div Doc ID 16546 Rev 2 20 ns/Div 3/11 Characteristics Figure 9. ESDAVLC8-1BU2 S21 attenuation measurement results dB 0.00 - 6.00 -12.00 -18.00 -24.00 F (Hz) - 30.00 100.0k 1.0M 10.0M 100.0M 1.0G Figure 10. Static characteristic (pin 2 to GND) 5 mA 4 3 2 1 0 -1 -2 -3 -4 V -5 4/11 -25 -20 -15 -10 -5 0 Doc ID 16546 Rev 2 5 10 15 20 25 ESDAVLC8-1BU2 2 Ordering information scheme Ordering information scheme Figure 11. Ordering information scheme ESDA VLC 8 - 1B U2 ESD array Very low capacitance Breakdown voltage 8 = 8.5 V min Direction B = Bidirectional Package U2 = ST0201 Doc ID 16546 Rev 2 5/11 Package information 3 ESDAVLC8-1BU2 Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 3. ST0201 dimensions Dimensions D Ref. Millimeters Inches E Min. Typ. Max. Min. Top A Side b1 b2 L1 Typ. Max. A 0.23 0.28 0.33 0.009 0.011 0.013 b1 0.13 0.18 0.23 0.005 0.007 0.009 b2 0.14 0.19 0.24 0.006 0.007 0.009 D 0.55 0.60 0.65 0.022 0.024 0.026 E 0.25 0.30 0.35 0.010 0.012 0.014 e - 0.35 L1 0.20 0.25 0.30 0.008 0.010 0.012 L2 0.20 0.25 0.30 0.008 0.010 0.012 L2 Bottom Pin 2 b1 e b2 L1 L2 Bottom e Pin 2 available in different forms - - 0.014 - Figure 12. Footprint (dimensions in mm) Figure 13. Marking 1.05 0.425 0.425 0.30 Pin1 V2 Pin 2 0.20 Note: 6/11 Product marking may be rotated by multiples of 180° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Doc ID 16546 Rev 2 ESDAVLC8-1BU2 Package information Figure 14. Tape and reel specifications Bar indicates Pin 1 Ø 1.55 ± 0.05 4.0 ± 0.1 0.20 ± 0.05 3.5 ±- 0.05 V2 V2 0.37 +0.03, -0.02 V2 V2 V2 V2 V2 All dimensions in mm 0.67 ± 0.03 8.0 ± 0.3 0.34 ± 0.03 1.75 ± 0.1 2.0 ± 0.05 2.0 ± 0.1 User direction of unreeling Doc ID 16546 Rev 2 7/11 Recommendation on PCB assembly ESDAVLC8-1BU2 4 Recommendation on PCB assembly 4.1 Stencil opening design Figure 15. Recommended stencil windows position 1.05 0.425 0.425 0.225 0.30 0.038 0.040 0.065 0.20 Footprint 4.2 8/11 0.320 0.038 Stencil window Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed 4. Solder paste with fine particles: powder particle size is 20-45 µm. Doc ID 16546 Rev 2 ESDAVLC8-1BU2 4.3 4.4 4.5 Recommendation on PCB assembly Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Reflow profile Figure 16. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s to -3 °C/s -6 °C/s max 2 - 3 °C/s 60 sec (90 max) 200 150 100 0.9 °C/s 50 Time (s) 0 Note: 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 16546 Rev 2 9/11 Ordering information 5 ESDAVLC8-1BU2 Ordering information Table 4. Ordering information Order code Marking Weight Base qty Delivery mode ESDAVLC8-1BU2 V2(1) 0.124 mg 15000 Tape and reel 1. The marking can be rotated by multiples of 180° to differentiate assembly location 6 Revision history Table 5. Document revision history Date Revision 03-Mar-2011 1 Initial release. 2 Updated Figure 10 for flow polarity. Updated graphic in Table 3 for pin 2 form. Updated note under Figure 13 and Table 4 for marking rotation. Updated Figure 16 for recommended soldering reflow. Updated marking in Table 4. 15-May-2012 10/11 Changes Doc ID 16546 Rev 2 ESDAVLC8-1BU2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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