ESDALC6V1-1M2 Single line low capacitance Transil™ for ESD protection Features ■ Single line low capacitance Transil diode ■ Unidirectional ESD protection ■ ESD protection > 30 kV (IEC 61000-4-2 contact discharge) ■ Breakdown voltage VBR = 6.1 V min. ■ Low diode capacitance (22 pF @ 0 V) ■ Low leakage current (< 100 nA @ 3 V) ■ Very small PCB area (0.6 mm2) ■ RoHS compliant Benefits ■ High ESD protection level ■ High integration ■ Suitable for high density boards SOD882 Package Figure 1. Functional diagram I/O1 Complies with the following standards: ■ ■ IEC 61000-4-2 level 4 – 15 kV (air discharge) – 8 kV (contact discharge) GND I/O2 3 GND MIL STD 883G - Method 3015-7: class 3B – HBM (Human body model) Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems ■ Cellular phone handsets and accessories ■ Video equipment Description The ESDALC6V1-1M2 is a unidirectional single line TVS diode designed to protect the data lines or other I/O ports against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required. TM: Transil is a trademark of STMicroelectronics November 2007 Rev 5 1/10 www.st.com Characteristics ESDALC6V1-1M2 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value Unit VPP ESD discharge - IEC 61000-4-2 contact discharge ±30 kV PPP Peak pulse power dissipation (8/20 µs) (1) 50 W IPP Repetitive peak pulse current (8/20 µs) 6 A Tj Junction temperature 125 °C Tstg Storage temperature - 55 to +150 °C 260 °C - 40 to + 125 °C TL TOP Tj initial = Tamb Maximum lead temperature for soldering during 10 s at 5 mm for case Operating temperature range 1. For a surge greater than the maximum values, the diode will fail in short-circuit Table 2. Electrical characteristics Symbol Parameter VRM Stand-of voltage VBR Breakdown voltage VCL Clamping voltage I IF VF VCL VBR VRM V I RM IRM Leakage current @ VRM IPP Peak pulse current αT Voltage temperature coefficient VF Forward voltage drop IR VBR @ IR Slope= 1/ Rd I PP IRM @ VRM RD VF @ 10 mA αT C@0V Order code Vmin Vmax mA ESDALC6V1-1M2 Figure 2. 6.1 7.2 nA max V Ω typ V max 10-4/°C max pF typ 100 3 0.5 1 4.5 22 1 Peak power dissipation versus initial junction temperature Figure 3. PPP[T j initial] / PPP [T j initial=25°C] 1000 1.1 Peak pulse power versus exponential pulse duration PPP(W) 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 tP(µs) T j(°C) 0.0 10 0 2/10 25 50 75 100 125 150 1 10 100 ESDALC6V1-1M2 Figure 4. 100.0 Characteristics Clamping voltage versus peak pulse current, rectangular waveform Figure 5. IPP(A) Forward voltage drop versus peak forward current (typical values) IFM(A) 1.E+00 8/20 µs Tj initial =25 °C Tj =25 °C 1.E-01 Tj =125 °C 10.0 Tj =-40 °C 1.E-02 1.0 1.E-03 VCL(V) VFM(V) 0.1 1.E-04 0 Figure 6. 5 10 15 20 25 30 35 40 0.2 Capacitance versus reverse applied Figure 7. voltage (typical values) C(pF) 0.4 0.6 0.8 1.0 1.2 1.4 Relative variation of the leakage current versus junction temperature (typical values) IR [T j] / IR [T j=25°C] 25 100 F=1 MHz VOSC=30 mVRMS Tj=25 °C 20 VR =3V 15 10 10 5 VR(V) T j(°C) 0 1 0 Figure 8. 1 2 3 4 ESD response to IEC 61000-4-2 (+15 kV air discharge) on each channel 5 25 Figure 9. 50 75 100 125 150 ESD response to IEC 61000-4-2 (-15 kV air discharge) on each channel 21V - 15V 3/10 Ordering information scheme ESDALC6V1-1M2 Figure 10. S21 attenuation measurement result Attenuation APLAC 7.91 User: ST Microelectronics Apr 04 2006 0.00 - 3 dB 270 MHz -10.00 -20.00 -30.00 1.81 GHz -40.00 100.0k 1.0M 10.0M 100.0M 1.0G f/Hz ESDALC6V1-1M2 2 Ordering information scheme Figure 11. Ordering information scheme ESDA LC 6V1 - 1M2 ESD Array Low Capacitance Breakdown Voltage 6V1 = 6.1 Volts min Package M2 = SOD882 4/10 ESDALC6V1-1M2 3 Package information Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST (also) offers these devices in ECOPACK® packages. ECOPACK® packages are Lead-free. The category of second level Interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. SOD882 dimensions Dimensions D Ref E INDEX AREA (D/2 xE/2) Millimetres Inches Min Typ Max Min Typ Max A 0.40 0.47 0.50 0.016 0.019 0.020 A1 0.00 b1 0.20 0.25 0.30 0.008 0.010 0.012 b2 0.20 0.25 0.30 0.008 0.010 0.012 A1 A TOP VIEW SIDE VIEW b1 0.002 D 1.00 0.039 E 0.60 0.024 e 0.65 0.026 b2 L2 L1 INDEX AREA (D/2 xE/2) OPTIONAL PIN#1 ID e BOTTOM VIEW Note: 0.05 0.000 L1 0.45 0.50 0.55 0.018 0.020 0.022 L2 0.45 0.50 0.55 0.018 0.020 0.022 Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 12. Footprint (dimensions in mm) Figure 13. Marking 0.55 0.55 0.50 Pin1 N Pin2 2 Pin 0.40 5/10 Package information ESDALC6V1-1M2 Figure 14. Tape and reel specifications Cathode bar Ø 1.55 ± 0.05 4.0 ± 0.1 0.20 ± 0.05 3.5 ±- 0.05 1.10 ± 0.05 2.0 ± 0.1 0.55 ± 0.1 (3M) All dimensions in mm 6/10 User direction of unreeling N N N 0.68 ± 0.05 N N N N 8.0 ± 0.3 0.66 ± 0.05 (C-PAK) 1.75 ± 0.1 2.0 ± 0.05 ESDALC6V1-1M2 Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 15. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio - between 60% and 65%. Figure 16. Recommended stencil windows position Package footprint Lead footprint on PCB Lead footprint on PCB Stencil window position 0.39 mm Stencil window position 0.45 mm 0.05 mm 4.2 0.05 mm Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed 4. Solder paste with fine particles: powder particle size is 20-45 µm. 7/10 Recommendation on PCB assembly 4.3 4.4 4.5 ESDALC6V1-1M2 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Reflow profile Figure 17. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 8/10 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. ESDALC6V1-1M2 5 Ordering information Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC6V1-1M2 N(1) SOD882 0.92 mg 3000 Tape and reel 1. The marking can be rotated by 90° to diferentiate assembly location 6 Revision history Table 5. Document revision history Date Revision Changes 23-May-2006 1 Initial release 16-Jun-2006 2 Updated tape and reel illustration (Figure 13). 11-Oct-2006 3 Corrected formatting errors on page 1. No technical changes. 10-May-2007 4 Updated Functional diagram to single diode. Added Section 4: Recommendation on PCB assembly. 26-Nov-2007 5 Corrected 2: Ordering information scheme. Updated Figure 14: Tape and reel specifications. Added Figure 16: Recommended stencil windows position. Reformatted to current standards. 9/10 ESDALC6V1-1M2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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