SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407A – APRIL 1998 – REVISED JUNE 1998 D D D D D EPIC (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) SN54LV373A . . . J OR W PACKAGE SN74LV373A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 2D 2Q 3Q 3D 4D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND LE 5Q 5D While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. 20 2 SN54LV373A . . . FK PACKAGE (TOP VIEW) description The ’LV373A devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. 1 1D 1Q OE VCC 8Q D A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54LV373A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV373A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407A – APRIL 1998 – REVISED JUNE 1998 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1 OE LE 1D 2D 3D 4D 5D 6D 7D 8D 11 3 EN C1 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE LE 1 11 C1 1D 3 2 1D To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407A – APRIL 1998 – REVISED JUNE 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407A – APRIL 1998 – REVISED JUNE 1998 recommended operating conditions (see Note 4) SN54LV373A VCC VIH High level input voltage High-level VIL Low level input voltage Low-level VI Input voltage VO IOH IOL ∆t/∆v MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 High or low state 0 3-state 0 UNIT V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 VCC 5.5 VCC × 0.3 5.5 0 0 V V VCC 5.5 V µA VCC = 2 V VCC = 2.3 V to 2.7 V –50 –50 –2 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V –8 –8 –16 –16 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V Input transition rise or fall rate 2 VCC × 0.7 VCC × 0.7 0 Low level output current Low-level MAX 1.5 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V High level output current High-level MIN 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V Output voltage SN74LV373A MIN mA µA mA 16 0 200 0 200 0 100 0 100 ns/V VCC = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL SN54LV373A TEST CONDITIONS IOH = –50 µA IOH = –2 mA VCC 2 V to 5.5 V IOL = 50 µA IOL = 2 mA VI = VCC or GND VO = VCC or GND ICC Ioff VI = VCC or GND, VI or VO = 0 to 5.5 V Ci VI = VCC or GND IO = 0 2.48 2.48 4.5 V 3.8 TYP MAX UNIT V 3.8 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 5.5 V ±1 ±1 µA 5.5 V ±5 ±5 µA 5.5 V 20 20 µA 5 µA 0V 3.3 V POST OFFICE BOX 655303 MIN 3V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN74LV373A MAX VCC–0.1 2 2 V to 5.5 V IOL = 8 mA IOL = 16 mA II IOZ TYP VCC–0.1 2 2.3 V IOH = –8 mA IOH = –16 mA MIN • DALLAS, TEXAS 75265 5 2.9 2.9 V pF SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407A – APRIL 1998 – REVISED JUNE 1998 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54LV373A MIN MAX SN74LV373A MIN MAX UNIT tw Pulse duration, LE high 6 6.5 6.5 ns tsu Setup time, data before LE↓ High or low 4.5 5 5 ns th Hold time, data after LE↓ High or low 1.5 1.5 1.5 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ SN54LV373A MIN MAX SN74LV373A MIN MAX UNIT 5 5 5 ns High or low 4 4 4 ns High or low 1 1 1 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54LV373A MIN MAX SN74LV373A MIN MAX UNIT tw Pulse duration, LE high 5 5 5 ns tsu Setup time, data before LE↓ High or low 4 4 4 ns th Hold time, data after LE↓ High or low 1 1 1 ns switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd d* FROM (INPUT) TO (OUTPUT) D Q LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN74LV373A MIN MAX MIN MAX 8.3 15.2 1 17 1 17 9.1 15.7 1 19 1 19 8.9 15.8 1 19 1 19 12.6 1 15 1 15 LE Q ten* OE Q tdis* OE Q 6.2 CL = 15 pF SN54LV373A D Q 10.4 18 1 21 1 21 LE Q 11.1 18.6 1 22 1 22 ten OE Q 10.9 18.8 1 22 1 22 tdis OE Q 8.3 17.4 1 19 1 19 tpd d CL = 50 pF tsk(o)† 2 UNIT ns ns 2 * On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407A – APRIL 1998 – REVISED JUNE 1998 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tpd d* FROM (INPUT) TO (OUTPUT) D Q LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN54LV373A MAX MIN MAX 11.4 1 13.5 1 13.5 6.4 11 1 13 1 13 6.3 11.4 1 13.5 1 13.5 12 1 12 5.8 LE Q ten* OE Q tdis* OE Q 4.7 10 1 CL = 15 pF SN74LV373A MIN D Q 7.3 14.9 1 17 1 17 LE Q 7.8 14.5 1 16.5 1 16.5 ten OE Q 7.7 14.9 1 17 1 17 tdis OE Q 6 13.2 1 15 1 15 tpd d CL = 50 pF tsk(o)† 1.5 UNIT ns ns 1.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd d* FROM (INPUT) TO (OUTPUT) D Q LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN54LV373A SN74LV373A MIN MAX MIN MAX 4.1 7.2 1 8.5 1 8.5 4.5 7.2 1 8.5 1 8.5 4.5 8.1 1 9.5 1 9.5 LE Q ten* OE Q tdis* OE Q 3.3 7.2 1 8.5 1 8.5 D Q 5.1 9.2 1 10.5 1 10.5 5.5 9.2 1 10.5 1 10.5 5.5 10.1 1 11.5 1 11.5 4 9.2 1 10.5 1 10.5 tpd d LE Q ten OE Q tdis OE Q CL = 15 pF CL = 50 pF tsk(o)† 1 UNIT ns ns 1 * On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV373A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.58 0.8 V Quiet output, minimum dynamic VOL –0.56 –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 2.86 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 19.5 operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation dissi ation ca capacitance acitance TEST CONDITIONS Outputs Out uts enabled CL = 50 pF F, PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz 17.4 pF F SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407A – APRIL 1998 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH VOH 50% VCC VOL 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control tPLZ 50% VCC tPZH ≈ VCC VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated