RF捷变收发器 AD9361 特性 功能框图 RX1B_P, RX1B_N AD9361 RX1A_P, RX1A_N ADC RX1C_P, RX1C_N RX2A_P, RX2A_N ADC RX2C_P, RX2C_N RX LO TX_MON1 TX LO TX1A_P, TX1A_N DAC DATA INTERFACE RX2B_P, RX2B_N P0_[D11:D0]/ TX_[D5:D0] P1_[D11:D0]/ RX_[D5:D0] TX1B_P, TX1B_N TX_MON2 TX2A_P, TX2A_N SPI CTRL DAC TX2B_P, TX2B_N DAC DAC ADC 集成12位DAC和ADC的RF 2×2收发器 频段：70 MHz至6.0 GHz 支持TDD和FDD 可调谐通道带宽：<200 kHz至56 MHz 双通道接收器：6路差分或12路单端输入 出色的接收器灵敏度，噪声系数为2 dB(800 MHz，本振(LO)) RX增益控制 实时监控和控制信号用于手动增益 独立的自动增益控制 双发射器：4路差分输出 高线性度宽带发射器 TX EVM：≤− 40 dB TX噪声：≤−157 dBm/Hz本底噪声 TX监控器：动态范围≥66 dB，精度=1 dB 集成小数N分频频率合成器 最大LO步长：2.4 Hz 多器件同步 CMOS/LVDS数字接口 CTRL GPO RADIO SWITCHING PLLs CLK_OUT NOTES 1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0], AND RADIO SWITCHING CONTAIN MULTIPLE PINS. 点对点通信系统 毫微微蜂窝/微微蜂窝/微蜂窝基站 通用无线电系统 10453-001 AUXADC AUXDACx XTALP XTALN 应用 图1. 概述 AD9361是一款面向3G和4G基站应用的高性能、高集成度 的射频(RF)Agile Transceiver™捷变收发器。该器件的可编程 性和宽带能力使其成为多种收发器应用的理想选择。该器 件集RF前端与灵活的混合信号基带部分为一体，集成频率 合成器，为处理器提供可配置数字接口，从而简化设计导 入。AD9361工作频率范围为70 MHz至6.0 GHz，涵盖大部 分特许执照和免执照频段，支持的通道带宽范围为不到 200 kHz至56 MHz。 两个独立的直接变频接收器拥有首屈一指的噪声系数和线 性度。每个接收(RX)子系统都拥有独立的自动增益控制 (AGC)、直流失调校正、正交校正和数字滤波功能，从而 消除了在数字基带中提供这些功能的必要性。AD9361还拥 有灵活的手动增益模式，支持外部控制。每个通道搭载两 个高动态范围ADC，先将收到的I信号和Q信号进行数字化 处理，然后将其传过可配置抽取滤波器和128抽头有限脉 冲响应(FIR)滤波器，结果以相应的采样率生成12位输出 信号。 Rev. D 发射器采用直接变频架构，可实现较高的调制精度和超低 的噪声。这种发射器设计带来了行业最佳的TX EVM，数值 不到<−40 dB，可为外部功率放大器的选择留出可观的系统 裕量。板载发射(TX)功率监控器可以用作功率检测器，从 而实现高度精确的TX功率测量。 完全集成的锁相环(PLL)可针对所有接收和发射通道提供低 功耗的小数N分频频率合成。设计中集成了频分双工(FDD) 系统需要的通道隔离。还集成了所有VCO和环路滤波器 器件。 AD9361的心核可以直接用1.3 V稳压器供电。IC通过一个标 准四线式串行端口和四个实时I/O控制引脚进行控制。全 面的省电模式可将正常使用情况下的功耗降至最低。 AD9361采用10 mm × 10 mm、144引脚芯片级球栅阵列封装 (CSP_BGA)。 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADI中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI不对翻译中存在的差异或由此产生的错误负责。如需确认任何词语的准确性，请参考ADI提供 的最新英文版数据手册。 AD9361 目录 特性.................................................................................................. 1 应用.................................................................................................. 1 功能框图 ......................................................................................... 1 概述.................................................................................................. 1 修订历史 ......................................................................................... 2 技术规格 ......................................................................................... 3 功耗—VDD接口 ...................................................................... 8 功耗—VDDD1P3_DIG和VDDAx (全部1.3 V电源相结合) ........................................................ 10 绝对最大额定值..................................................................... 15 回流温度曲线 ......................................................................... 15 热阻 .......................................................................................... 15 ESD警告................................................................................... 15 引脚配置和功能描述 ................................................................. 16 典型性能参数 .............................................................................. 20 800 MHz频段 .......................................................................... 20 2.4 GHz频段 ............................................................................ 25 5.5 GHz频段 ............................................................................ 29 工作原理 ....................................................................................... 33 一般特性.................................................................................. 33 接收器 ...................................................................................... 33 发射器 ...................................................................................... 33 时钟输入选项 ......................................................................... 33 频率合成器 ............................................................................. 34 数字数据接口 ......................................................................... 34 使能状态机 ............................................................................. 34 SPI接口..................................................................................... 35 控制引脚.................................................................................. 35 GPO引脚(GPO_3至GPO_0)................................................ 35 辅助转换器 ............................................................................. 35 AD9361的供电 ....................................................................... 35 封装和订购信息.......................................................................... 36 外形尺寸.................................................................................. 36 订购指南.................................................................................. 36 修订历史 2013年11月—修订版C至修订版D 更改“订购指南”........................................................................... 36 2013年9月—修订版C：初始版 Rev. D | Page 2 of 36 AD9361 规格 除非另有说明，电气特性在VDD_GPO = 3.3 V，VDD_INTERFACE = 1.8 V，所有其他VDDx引脚= 1.3 V，TA = 25°C下测得。 表1. 参数1 接收器，一般 中心频率 增益 最小值 最大值 增益步进 接收信号强度指示器 档位 准确度 接收器，800 MHz 噪声系数 三阶输入交调载点 二阶输入交调载点 本振(LO)泄漏 正交 增益误差 相位误差 调制精度(EVM) 输入S11 RX1至RX2隔离 RX1A至RX2A，RX1C至RX2C RX1B至RX2B RX2至RX1隔离 RX2A至RX1A，RX2C至RX1C RX2B至RX1B 接收器，2.4 GHz 噪声系数 三阶输入交调载点 二阶输入交调载点 本振(LO)泄漏 正交 增益误差 相位误差 调制精度(EVM) 输入S11 RX1至RX2隔离 RX1A至RX2A，RX1C至RX2C RX1B至RX2B RX2至RX1隔离 RX2A至RX1A，RX2C至RX1C RX2B至RX1B 符号 最小值 典型值 70 最大值 件 6000 MHz 0 74.5 73.0 72.0 dB dB dB dB 65.5 1 dB dB 100 ±2 dB dB 2 −18 40 −122 dB dBm dBm dBm 0.2 0.2 −42 −10 % 度 dB dB 70 55 dB dB 70 55 dB dB 3 −14 45 −110 dB dBm dBm dBm 0.2 0.2 −42 −10 % 度 dB dB 65 50 dB dB 65 50 dB dB 测试条件/注释 800 MHz 2300 MHz (RX1A, RX2A) 2300 MHz (RX1B, RX1C, RX2B, RX2C) 5500 MHz (RX1A, RX2A) RSSI NF IIP3 IIP2 NF IIP3 IIP2 Rev. D | Page 3 of 36 最大RX增益 最大RX增益 最大RX增益 RX前端输入 19.2 MHz参考时钟 最大RX增益 最大RX增益 最大RX增益 接收器前端输入 40 MHz参考时钟 AD9361 参数1 接收器，5.5 GHz 噪声系数 三阶输入交调载点 二阶输入交调载点 符号 最小值 NF IIP3 IIP2 本振(LO)泄漏 正交 增益误差 相位误差 调制精度(EVM) 输入S11 RX1A至RX2A隔离 RX2A至RX1A隔离 发射器—一般 中心频率 功率控制范围 功率控制分辨率 发射器，800 MHz 输出S22 最大输出功率 调制精度(EVM) 三阶输出交调载点 载波泄漏 本底噪声 隔离 TX1至TX2 TX2至TX1 发射器，2.4 GHz 输出S22 最大输出功率 调制精度(EVM) 三阶输出交调载点 载波泄漏 本底噪声 隔离 TX1至TX2 TX2至TX1 件 测试条件/注释 3.8 −17 42 dB dBm dBm 最大RX增益 最大RX增益 最大RX增益 −95 dBm RX前端输入 0.2 0.2 −37 % 度 dB −10 52 52 dB dB dB 70 OIP3 OIP3 本底噪声 隔离 TX1至TX2 TX2至TX1 发射器，5.5 GHz 输出S22 最大输出功率 调制精度(EVM) 三阶输出交调载点 载波泄漏 典型值 OIP3 最大值 90 0.25 6000 MHz dB dB −10 8 −40 23 −50 −32 −157 dB dBm dB dBm dBc dBc dBm/Hz 50 50 dB dB −10 7.5 −40 19 −50 −32 −156 dB dBm dB dBm dBc dBc dBm/Hz 50 50 dB dB −10 6.5 −36 dB dBm dB 17 −50 −30 −151.5 dBm dBc dBc dBm/Hz 50 50 dB dB Rev. D | Page 4 of 36 40 MHz参考时钟 (针对RF频率 合成器内部加倍) 1 MHz信号音(50 Ω负载) 19.2 MHz参考时钟 0 dB衰减 40 dB衰减 90 MHz偏移 1 MHz信号音(50 Ω负载) 40 MHz参考时钟 0 dB衰减 40 dB衰减 90 MHz偏移 7 7 MHz信号音(50 Ω负载) 40 MHz参考时钟 (针对RF频率 合成器内部加倍) 0 dB衰减 40 dB衰减 90 MHz偏移 AD9361 参数1 TX监控器输入(TX_MON1, TX_MON2) 最大输入电平 动态范围 准确度 LO频率合成器 LO频率阶跃 符号 最小值 典型值 最大值 件 测试条件/注释 4 66 1 dBm dB dB 2.4 Hz 2.4 GHz，40 MHz 参考时钟 积分相位噪声 800 MHz 0.13 ° rms 2.4 GHz 0.37 ° rms 5.5 GHz 0.59 ° rms 100 Hz至100 MHz， 30.72 MHz参考时钟 (针对RF频率合成器 内部加倍) 100 Hz至100 MHz， 40 MHz参考时钟 100 Hz至100 MHz， 40 MHz参考时钟 (针对RF频率合成器 内部加倍) REF_CLK要么为XTALP/ XTALN引脚的输入， 要么为直接连接 XTALN引脚的线路 参考时钟(REF_CLK) 输入 频率范围 信号电平 辅助转换器 ADC 分辨度 输入电压 最小值 最大值 DAC 分辨度 输出电压 最小值 最大值 输出电流 数字规格(CMOS) 逻辑输入 输入电压 高 低 输入电流 高 低 逻辑输出 输出电压 高 低 数字规格(LVDS) 逻辑输入 输入电压范围 输入差分电压阈值 接收机差分输入阻抗 19 10 50 80 1.3 MHz MHz V p-p 12 位 0.05 VDDA1P3_BB − 0.05 V V 10 位 0.5 VDD_GPO − 0.3 10 V V mA VDD_INTERFACE × 0.8 0 VDD_INTERFACE VDD_INTERFACE × 0.2 −10 −10 +10 +10 VDD_INTERFACE × 0.8 VDD_INTERFACE × 0.2 825 −100 1575 +100 100 Rev. D | Page 5 of 36 晶振输入 外部振荡器 交流耦合外部振荡器 V V V V mV mV Ω 对中的各差分输入 AD9361 参数1 逻辑输出 输出电压 高 低 输出差分电压 输出失调电压 通用输出 输出电压 高 低 输出电流 SPI时序 SPI_CLK 周期 脉冲宽度 SPI_ENB建立至第一SPI_CLK 上升沿 最后SPI_CLK下降沿至 SPI_ENB保持 SPI_DI 数字输入建立至SPI_CLK 数据输入保持至SPI_CLK SPI_CLK上升沿至输出数据延迟 4线模式 3线模式 总线周转时间，读 总线周转时间，读 数字数据时序(CMOS)， VDD_INTERFACE = 1.8 V DATA_CLK时钟周期 DATA_CLK和FB_CLK脉冲宽度 TX数据 建立至FB_CLK 保持至FB_CLK DATA_CLK至数据总线输出延迟 DATA_CLK至RX_FRAME延迟 脉冲宽度 使能 TXNRX TXNRX建立至ENABLE 总线周转时间 RX前 RX后 容性负载 容性输入 符号 最小值 典型值 最大值 件 1375 mV mV mV mV 1025 150 1200 VDD_GPO × 0.8 VDD_GPO × 0.2 10 测试条件/注释 可分75 mV个阶跃编程 V V mA VDD_INTERFACE = 1.8 V tCP tMP tSC 20 9 1 ns ns ns tHC 0 ns tS tH 2 1 ns ns tCO tCO tHZM tHZS 3 3 tH 0 8 8 tCO (max) tCO (max) ns ns ns ns tCP tMP 16.276 tCP的45% tCP的55% ns ns 1.5 1.0 ns ns ns ns 1 0 0 0 tENPW tTXNRXPW tTXNRXSU tCP tCP 0 ns ns ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF Rev. D | Page 6 of 36 61.44 MHz TX_FRAME，P0_D和 P1_D tSTX tHTX tDDRX tDDDV 3 3 BBP驱动最后地址位后 AD9361驱动最后数据 位后 FDD独立ENSM模式 TDD ENSM模式 TDD模式 TDD模式 AD9361 参数1 数字数据时序(CMOS)， VDD_INTERFACE = 2.5 V DATA_CLK时钟周期 DATA_CLK和FB_CLK脉冲宽度 TX数据 符号 最小值 tCP tMP 16.276 tCP的45% 建立至FB_CLK 保持至FB_CLK DATA_CLK至数据总线输出延迟 DATA_CLK至RX_FRAME延迟 脉冲宽度 使能 TXNRX TXNRX建立至ENABLE 总线周转时间 RX前 RX后 容性负载 容性输入 数字数据时序(LVDS) DATA_CLK时钟周期 DATA_CLK和FB_CLK脉冲宽度 TX数据 建立至FB_CLK 保持至FB_CLK DATA_CLK至数据总线输出延迟 DATA_CLK至RX_FRAME延迟 脉冲宽度 使能 TXNRX TXNRX建立至ENABLE 总线周转时间 RX前 RX后 容性负载 容性输入 电源特性 1.3 V电源电压 VDD_INTERFACE电源额定设置 CMOS LVDS VDD_INTERFACE容差 VDD_GPO电源标称设置 VDD_GPO容差 电流消耗 VDDx，休眠模式 VDD_GPO tSTX tHTX tDDRX tDDDV 1 0 0 0 tENPW tTXNRXPW tTXNRXSU tCP tCP 0 ns ns ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF TDD模式 TDD模式 ns ns 245.76 MHz tCP的55% 1.25 1.25 ns ns ns ns 1 典型值 最大值 件 测试条件/注释 ns ns 61.44 MHz tCP的55% 1.2 1.0 ns ns ns ns 3 3 TX_FRAME，P0_D和 P1_D tCP tMP 4.069 tCP的45% tSTX tHTX tDDRX tDDDV 1 0 0.25 0.25 tENPW tTXNRXPW tTXNRXSU tCP tCP 0 ns ns ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF 3 3 1.267 1.3 1.2 1.8 −5 1.3 −5 180 50 FDD独立ENSM模式 TDD ENSM模式 TX_FRAME和TX_D 1.33 V 2.5 2.5 +5 3.3 +5 V V % V % FDD独立ENSM模式 TDD ENSM模式 容差适用于任何电压设置 未用时，必须设为1.3 V 容差适用于任何电压设置 所有输入电流之和 无负载 指参数中多功能引脚的单个功能时，只会列出引脚名称中与规格相关的部分。要了解多功能引脚的全部引脚名称，请参见“引脚配置和功能描述”部分。 Rev. D | Page 7 of 36 AD9361 功耗——VDD_INTERFACE 表2.VDD_INTERFACE = 1.2 V 参数 休眠模式 1RX, 1TX, DDR LTE10 单端口 双端口 LTE20 双端口 2RX, 2TX, DDR LTE3 双端口 LTE10 单端口 双端口 LTE20 双端口 GSM 双端口 WiMAX 8.75 双端口 WiMAX 10 单端口 TDD RX TDD TX FDD WiMAX 20 双端口 FDD 最小值 典型值 45 最大值 件 µA 测试条件/注释 加电，器件禁用 2.9 2.7 mA mA 30.72 MHz数据时钟，CMOS 15.36 MHz数据时钟，CMOS 5.2 mA 30.72 MHz数据时钟，CMOS 1.3 mA 7.68 MHz数据时钟，CMOS 4.6 5.0 mA mA 61.44 MHz数据时钟，CMOS 30.72 MHz数据时钟，CMOS 8.2 mA 61.44 MHz数据时钟，CMOS 0.2 mA 1.08 MHz数据时钟，CMOS 3.3 mA 20 MHz数据时钟，CMOS 0.5 3.6 3.8 mA mA mA 22.4 MHz数据时钟，CMOS 22.4 MHz数据时钟，CMOS 44.8 MHz数据时钟，CMOS 6.7 mA 44.8 MHz数据时钟，CMOS 表3.VDD_INTERFACE = 1.8 V 参数 休眠模式 1RX, 1TX, DDR LTE10 单端口 双端口 LTE20 双端口 2RX, 2TX, DDR LTE3 双端口 LTE10 单端口 双端口 LTE20 双端口 GSM 双端口 WiMAX 8.75 双端口 最小值 典型值 84 最大值 件 A 测试条件/注释 加电，器件禁用 4.5 4.1 mA mA 30.72 MHz数据时钟，CMOS 15.36 MHz数据时钟，CMOS 8.0 mA 30.72 MHz数据时钟，CMOS 2.0 mA 7.68 MHz数据时钟，CMOS 8.0 7.5 mA mA 61.44 MHz数据时钟，CMOS 30.72 MHz数据时钟，CMOS 14.0 mA 61.44 MHz数据时钟，CMOS 0.3 mA 1.08 MHz数据时钟，CMOS 5.0 mA 20 MHz数据时钟，CMOS Rev. D | Page 8 of 36 AD9361 参数 WiMAX 10 单端口 TDD RX TDD TX FDD WiMAX 20 双端口 FDD P-P56 75 mV差分输出 300 mV差分输出 450 mV差分输出 最小值 典型值 最大值 件 测试条件/注释 0.7 5.6 6.0 mA mA mA 22.4 MHz数据时钟，CMOS 22.4 MHz数据时钟，CMOS 44.8 MHz数据时钟，CMOS 10.7 mA 44.8 MHz数据时钟，CMOS 14.0 35.0 47.0 mA mA mA 240 MHz数据时钟，LVDS 240 MHz数据时钟，LVDS 240 MHz数据时钟，LVDS 件 µA 测试条件/注释 加电，器件禁用 6.5 6.0 mA mA 30.72 MHz数据时钟，CMOS 15.36 MHz数据时钟，CMOS 11.5 mA 30.72 MHz数据时钟，CMOS 3.0 mA 7.68 MHz数据时钟，CMOS 11.5 10.0 mA mA 61.44 MHz数据时钟，CMOS 30.72 MHz数据时钟，CMOS 20.0 mA 61.44 MHz数据时钟，CMOS 0.5 mA 1.08 MHz数据时钟，CMOS 7.3 mA 20 MHz数据时钟，CMOS 1.3 8.0 8.7 mA mA mA 22.4 MHz数据时钟，CMOS 22.4 MHz数据时钟，CMOS 44.8 MHz数据时钟，CMOS 15.3 mA 44.8 MHz数据时钟，CMOS 26.0 45.0 58.0 mA mA mA 240 MHz数据时钟，LVDS 240 MHz数据时钟，LVDS 240 MHz数据时钟，LVDS 表4.VDD_INTERFACE = 2.5 V 参数 休眠模式 1RX, 1TX, DDR LTE10 单端口 双端口 LTE20 双端口 2RX, 2TX, DDR LTE3 双端口 LTE10 单端口 双端口 LTE20 双端口 GSM 双端口 WiMAX 8.75 双端口 WiMAX 10 单端口 TDD RX TDD TX FDD WiMAX 20 双端口 FDD P-P56 75 mV差分输出 300 mV差分输出 450 mV差分输出 最小值 典型值 150 最大值 Rev. D | Page 9 of 36 AD9361 功耗——VDDD1P3_DIG和VDDAx(全部1.3 V电源组合) 表5.800 MHz，TDD模式 参数 1RX 5 MHz带宽 10 MHz带宽 20 MHz带宽 2RX 5 MHz带宽 10 MHz带宽 20 MHz带宽 1TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 2TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 最小值 典型值 最大值 件 测试条件/注释 180 210 260 mA mA mA 连续RX 连续RX 连续RX 265 315 405 mA mA mA 连续RX 连续RX 连续RX 340 190 mA mA 连续TX 连续TX 360 220 mA mA 连续TX 连续TX 400 250 mA mA 连续TX 连续TX 550 260 mA mA 连续TX 连续TX 600 310 mA mA 连续TX 连续TX 660 370 mA mA 连续TX 连续TX Rev. D | Page 10 of 36 AD9361 表6.TDD模式，2.4 GHz 参数 1RX 5 MHz带宽 10 MHz带宽 20 MHz带宽 2RX 5 MHz带宽 10 MHz带宽 20 MHz带宽 1TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 2TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 最小值 典型值 最大值 件 测试条件/注释 175 200 240 mA mA mA 连续RX 连续RX 连续RX 260 305 390 mA mA mA 连续RX 连续RX 连续RX 350 160 mA mA 连续TX 连续TX 380 220 mA mA 连续TX 连续TX 410 260 mA mA 连续TX 连续TX 580 280 mA mA 连续TX 连续TX 635 330 mA mA 连续TX 连续TX 690 390 mA mA 连续TX 连续TX 件 测试条件/注释 175 275 mA mA 连续RX 连续RX 270 445 mA mA 连续RX 连续RX 400 240 mA mA 连续TX 连续TX 490 385 mA mA 连续TX 连续TX 650 335 mA mA 连续TX 连续TX 820 500 mA mA 连续TX 连续TX 表7.TDD模式，5.5 GHz 参数 1RX 5 MHz带宽 40 MHz带宽 2RX 5 MHz带宽 40 MHz带宽 1TX 5 MHz带宽 7 dBm −27 dBm 40 MHz带宽 7 dBm −27 dBm 2TX 5 MHz带宽 7 dBm −27 dBm 40 MHz带宽 7 dBm −27 dBm 最小值 典型值 最大值 Rev. D | Page 11 of 36 AD9361 表8.FDD模式，800 MHz 参数 1RX, 1TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 2RX, 1TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 1RX, 2TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 2RX, 2TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 最小值 典型值 最大值 件 490 345 mA mA 540 395 mA mA 615 470 mA mA 555 410 mA mA 625 480 mA mA 740 600 mA mA 685 395 mA mA 755 465 mA mA 850 570 mA mA 790 495 mA mA 885 590 mA mA 1020 730 mA mA Rev. D | Page 12 of 36 测试条件/注释 AD9361 表9.FDD模式，2.4 GHz 参数 1RX, 1TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 2RX, 1TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 1RX, 2TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27dBm 20 MHz带宽 7 dBm −27 dBm 2RX, 2TX 5 MHz带宽 7 dBm −27 dBm 10 MHz带宽 7 dBm −27 dBm 20 MHz带宽 7 dBm −27 dBm 最小值 典型值 最大值 件 500 350 mA mA 540 390 mA mA 620 475 mA mA 590 435 mA mA 660 510 mA 770 620 mA mA mA 730 425 mA mA 800 500 mA mA 900 600 mA mA mA 820 515 mA 900 595 mA mA 1050 740 mA mA Rev. D | Page 13 of 36 测试条件/注释 AD9361 表10.FDD模式，5.5 GHz 参数 1RX, 1TX 5 MHz带宽 7 dBm −27 dBm 2RX, 1TX 5 MHz带宽 7 dBm −27 dBm 1RX, 2TX 5 MHz带宽 7 dBm −27 dBm 2RX, 2TX 5 MHz带宽 7 dBm −27 dBm 最小值 典型值 最大值 件 550 385 mA mA 645 480 mA mA 805 480 mA mA 895 575 mA mA Rev. D | Page 14 of 36 测试条件/注释 AD9361 绝对最大额定值 热阻 表11. 参数 VDDx至VSSx VDD_INTERFACE至VSSx VDD_GPO至VSSx 逻辑输入和输出至VSSx 输入电流至除电源引脚外的 任何引脚 RF输入(峰值功率) TX监控器输入功率 (峰值功率) 封装功耗 最大结温(TJMAX) 工作温度范围 存储温度范围 评分 −0.3 V至+1.4 V −0.3 V至+3.0 V −0.3 V至+3.9 V −0.3 V至VDD_INTERFACE + 0.3 V ±10 mA 2.5 dBm 9 dBm θJA针对最差条件，即器件焊接在电路板上实现表贴封装。 表12.热阻 封装类型 144引脚 CSP_BGA 1 2 (TJMAX − TA)/θJA 110°C −40°C至+85°C −65°C至+150°C 3 4 气流 速度 (m/s) 0 1.0 2.5 θJA1, 2 32.3 29.6 27.8 θJC1, 3 9.6 θJB1, 4 20.2 ΨJT1, 2 0.27 0.43 0.57 件 °C/W °C/W °C/W 按照JEDEC JESD51-7，加上JEDEC JESD51-5 2S2P测试板。 按照JEDEC JESD51-2(静止空气)或JEDEC JESD51-6(流动空气)。 按照MIL-STD 883、方法1012.1。 按照JEDEC JESD51-8(静止空气)。 ESD警告 ESD(静电放电)敏感器件。 注意，超出上述绝对最大额定值可能会导致器件永久性 损坏。这只是额定最值，并不能以这些条件或者在任何其 它超出本技术规范操作章节中所示规格的条件下，推断器 件能否正常工作。长期在绝对最大额定值条件下工作会影 响器件的可靠性。 回流温度曲线 AD9361回流温度曲线依据的是JEDEC JESD20无铅器件标准。 最大回流温度为260°C。 Rev. D | Page 15 of 36 带电器件和电路板可能会在没有察觉的情况下放电。 尽管本产品具有专利或专有保护电路，但在遇到高 能量ESD时，器件可能会损坏。因此，应当采取适当 的ESD防范措施，以避免器件性能下降或功能丧失。 AD9361 引脚配置和功能描述 1 2 3 4 5 6 7 8 9 10 11 12 A RX2A_N RX2A_P NC VSSA TX_MON2 VSSA TX2A_N TX2A_P TX2B_N TX2B_P VDDA1P1_ TX_VCO TX_EXT_ LO_IN B VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO VDDA1P3_ TX_LO VDDA1P3_ TX_VCO_ LDO TX_VCO_ LDO_OUT VSSA AUXDAC2 TEST/ ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA CTRL_IN3 CTRL_IN2 P0_D9/ TX_D4_P P0_D7/ TX_D3_P P0_D5/ TX_D2_P P0_D3/ TX_D1_P P0_D1/ TX_D0_P VSSD P0_D11/ TX_D5_P P0_D8/ TX_D4_N P0_D6/ TX_D3_N P0_D4/ TX_D2_N P0_D2/ TX_D1_N P0_D0/ TX_D0_N VSSD P0_D10/ TX_D5_N VSSD FB_CLK_P VSSD VDDD1P3_ DIG RX_ FRAME_N RX_ FRAME_P TX_ FRAME_P FB_CLK_N DATA_ CLK_P VSSD TX_ FRAME_N VSSD DATA_ CLK_N VDD_ INTERFACE C RX2C_P VSSA D RX2C_N VDDA1P3_ RX_RF VDDA1P3_ CTRL_OUT0 RX_TX E RX2B_P VDDA1P3_ RX_LO VDDA1P3_ TX_LO_ CTRL_OUT1 CTRL_OUT2 CTRL_OUT3 BUFFER F RX2B_N VDDA1P3_ RX_VCO_ LDO VSSA G RX_EXT_ LO_IN RX_VCO_ LDO_OUT VDDA1P1_ RX_VCO CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 CTRL_OUT7 EN_AGC ENABLE RX1B_P VSSA VSSA TXNRX SYNC_IN VSSA VSSD J RX1B_N VSSA VDDA1P3_ RX_SYNTH SPI_DI SPI_CLK CLK_OUT P1_D10/ RX_D5_N P1_D9/ RX_D4_P P1_D7/ RX_D3_P P1_D5/ RX_D2_P P1_D3/ RX_D1_P P1_D1/ RX_D0_P K RX1C_P VSSA VDDA1P3_ TX_SYNTH VDDA1P3_ BB RESETB SPI_ENB P1_D8/ RX_D4_N P1_D6/ RX_D3_N P1_D4/ RX_D2_N P1_D2/ RX_D1_N P1_D0/ RX_D0_N VSSD L RX1C_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA M RX1A_P RX1A_N NC VSSA TX_MON1 VSSA TX1A_P TX1A_N TX1B_P TX1B_N XTALP XTALN ANALOG I/O DIGITAL I/O NO CONNECT 10453-002 H P1_D11/ RX_D5_P DC POWER GROUND 图2.引脚配置(顶视图) 表13.引脚功能描述 引脚编号 A1, A2 类型1 I 引脚名称 RX2A_N, RX2A_P A3, M3 A4, A6, B1, B2, B12, C2, C7 to C12, F3, H2, H3, H6, J2, K2, L2, L3, L7 to L12, M4, M6 A5 A7, A8 A9, A10 NC I NC VSSA 不连接。请勿连接到这些引脚。 模拟地。将这些引脚直接连接至印刷电路板上的VSSD数字地(一个接地层)。 I O O TX_MON2 TX2A_N, TX2A_P TX2B_N, TX2B_P 发射通道2功率监控输入。若未使用此引脚，则将其接地。 发射通道2差分输出A。将未使用的引脚连接至1.3 V。 发射通道2差分输出B。将未使用的引脚连接至1.3 V。 A11 A12 B3 B4至B7 B8 I I O O I VDDA1P1_TX_VCO TX_EXT_LO_IN AUXDAC1 GPO_3 to GPO_0 VDD_GPO B9 B10 B11 C1, D1 I I O I VDDA1P3_TX_LO VDDA1P3_TX_VCO_LDO TX_VCO_LDO_OUT RX2C_P, RX2C_N 发射VCO电源输入。连接至B11。 外部发射LO输入。若未使用此引脚，则将其接地。 辅助DAC 1输出。 支持3.3 V的通用输出。 2.5 V至3.3 V电源，支持AUXDAC和通用输出引脚。不使用VDD_GPO电源时， 必须将该电源设为1.3 V。 发射LO 1.3 V电源输入。 发射VCO LDO 1.3 V电源输入。连接至B9。 发射VCO LDO输出。连接至A11，将一个1 µF旁路电容与一个1 Ω电阻串联接地。 接收通道2差分输入C。每个引脚都可作为单端输入或者结合形成差分对。 这些输入在3 GHz以上时性能会下降。将未使用的引脚接地。 说明 接收通道2差分输入A。或者，每个引脚都可作为单端输入或者结合形 成差分对。将未使用的引脚接地。 Rev. D | Page 16 of 36 AD9361 引脚编号 C3 C4 C5, C6, D5, D6 D2 D3 D4，E4至E6， F4至F6，G4 类型1 O I I I I O D7 I/O 引脚名称 AUXDAC2 测试/使能 CTRL_IN0至CTRL_IN3 VDDA1P3_RX_RF VDDA1P3_RX_TX CTRL_OUT0，CTRL_OUT1至 CTRL_OUT3，CTRL_OUT6至 CTRL_OUT4，CTRL_OUT7 P0_D9/TX_D4_P D8 I/O P0_D7/TX_D3_P D9 I/O P0_D5/TX_D2_P D10 I/O P0_D3/TX_D1_P D11 I/O P0_D1/TX_D0_P D12, F7, F9, F11, G12, H7, H10, K12 E1, F1 I VSSD I RX2B_P, RX2B_N E2 E3 E7 I I I/O VDDA1P3_RX_LO VDDA1P3_TX_LO_BUFFER P0_D11/TX_D5_P E8 I/O P0_D8/TX_D4_N E9 I/O P0_D6/TX_D3_N E10 I/O P0_D4/TX_D2_N E11 I/O P0_D2/TX_D1_N E12 I/O P0_D0/TX_D0_N 说明 辅助DAC 2输出。 测试输入。正常工作时，将该引脚接地。 控制输入。用于手动RX增益和TX衰减控制。 接收器1.3 V电源输入。连接至D3。 1.3 V电源输入。 控制输出。这些引脚是多功能输出，具有可编程功能。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D9， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D4_P)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D7， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D3_P)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D5， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D2_P)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D3， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D1_P)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D1， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D0_P)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字地。将这些引脚直接连接至印刷电路板上的VSSA模拟地(一个接地层)。 接收通道2差分输入B。每个引脚都可作为单端输入或者相结合从而形 成差分对。这些输入在3 GHz以上时性能会下降。将未使用的引脚接地。 接收LO 1.3 V电源输入。 1.3 V电源输入。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D11， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D5_P)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D8， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D4_N)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D6， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D3_N)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D4， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D2_N)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D2， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D1_N)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D0， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D0_N)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 Rev. D | Page 17 of 36 AD9361 引脚编号 F2 F8 类型1 I I/O 引脚名称 VDDA1P3_RX_VCO_LDO P0_D10/TX_D5_N F10, G10 I FB_CLK_P, FB_CLK_N F12 G1 G2 I I O VDDD1P3_DIG RX_EXT_LO_IN RX_VCO_LDO_OUT G3 G5 G6 G7, G8 I I I O VDDA1P1_RX_VCO EN_AGC 使能 RX_FRAME_N, RX_FRAME_P G9, H9 I TX_FRAME_P, TX_FRAME_N G11, H11 O DATA_CLK_P, DATA_CLK_N H1, J1 I RX1B_P, RX1B_N H4 I TXNRX H5 I SYNC_IN H8 I/O P1_D11/RX_D5_P H12 J3 J4 J5 J6 I I I I O VDD_INTERFACE VDDA1P3_RX_SYNTH SPI_DI SPI_CLK CLK_OUT J7 I/O P1_D10/RX_D5_N J8 I/O P1_D9/RX_D4_P J9 I/O P1_D7/RX_D3_P J10 I/O P1_D5/RX_D2_P 说明 接收VCO LDO 1.3 V电源输入。连接至E2。 数字数据端口P0/发射差分输入总线。这是双功能引脚。对于P0_D10， 它充当12位双向并行CMOS电平数据端口0的一部分。或者，该引脚 (TX_D5_N)也可作为LVDS 6位TX差分输入总线(带内部LVDS端子)的一部分。 反馈时钟。这些引脚接收作为TX数据时钟的FB_CLK信号。在CMOS模 式中，以FB_CLK_P为输入，将FB_CLK_N接地。 1.3 V数字电源输入。 外部接收LO输入。若未使用此引脚，则将其接地。 接收VCO LDO输出。将该引脚直接连至G3，将一个1 µF旁路电容与一个 1 Ω电阻串联接地。 接收VCO电源输入。将该引脚只直接连至G2。 用于自动增益控制(AGC)的手动控制输入。 控制输入。该引脚使器件在各种运行状态之间移动。 接收数字数据帧输出信号。这些引脚发射RX_FRAME信号，用于指示RX 输 出 数 据 是 否 有 效 。 在 CMOS模 式 下 ， 以 RX_FRAME_P为 输 出 ， 使 RX_FRAME_N保持断开状态。 发射数字数据帧输入信号。这些引脚接收用于指示TX数据何时有效的 TX_FRAME信 号 。 在 CMOS模 式 中 ， 以 TX_FRAME_P为 输 入 ， 将 TX_FRAME_N接地。 接收数据时钟输出。这些引脚发射DATA_CLK信号，BBP用这些信号为 RX数 据 提 供 时 钟 。 在 CMOS模 式 下 ， 以 DATA_CLK_P为 输 出 ， 使 DATA_CLK_N保持断开状态。 接收通道1差分输入B。另外，每个引脚均可用作单端输入。这些输入 在3 GHz以上时性能会下降。将未使用的引脚接地。 使能状态机控制信号。该引脚控制数据端口总线方向。逻辑低电平选 择RX方向，逻辑高电平选择TX方向。 用于同步多个AD9361器件之间数字时钟的输入。若未使用此引脚，则 将其接地。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D11， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D5_P)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字I/O引脚，1.2 V至2.5 V电源(LVDS模式下为1.8 V至2.5 V)。 1.3 V电源输入。 SPI串行数据输入。 SPI时钟输入。 输出时钟。可将该引脚配置为输出缓冲版外部输入时钟DCXO，或者输 出分频版内部ADC_CLK。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D10， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D5_N)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D9， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D4_P)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D7， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D3_P)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D5， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D2_P)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 Rev. D | Page 18 of 36 AD9361 引脚编号 J11 类型1 I/O 引脚名称 P1_D3/RX_D1_P J12 I/O P1_D1/RX_D0_P K1, L1 I RX1C_P, RX1C_N K3 K4 K5 K6 K7 I I I I I/O VDDA1P3_TX_SYNTH VDDA1P3_BB RESETB SPI_ENB P1_D8/RX_D4_N K8 I/O P1_D6/RX_D3_N K9 I/O P1_D4/RX_D2_N K10 I/O P1_D2/RX_D1_N K11 I/O P1_D0/RX_D0_N L4 L5 L6 M1, M2 I I O I RBIAS AUXADC SPI_DO RX1A_P, RX1A_N M5 M7, M8 M9, M10 M11, M12 I O O I TX_MON1 TX1A_P, TX1A_N TX1B_P, TX1B_N XTALP, XTALN 1 说明 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D3， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D1_P)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D1， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D0_P)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 接收通道1差分输入C。另外，每个引脚均可用作单端输入。这些输入 在3 GHz以上时性能会下降。将未使用的引脚接地。 1.3 V电源输入。 1.3 V电源输入。 异步复位。逻辑低电平复位器件。 SPI使能输入。将该引脚设为逻辑低电平，以使能SPI总线。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D8， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D4_N)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D6， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D3_N)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D4， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D2_N)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D2， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D1_N)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 数字数据端口P1/接收差分输出总线。这是双功能引脚。对于P1_D0， 它充当12位双向并行CMOS电平数据端口1的一部分。或者，该引脚 (RX_D0_N)也可作为LVDS 6位RX差分输出总线(带内部LVDS端子)的一部分。 偏置输入参考。通过一个14.3 kΩ (1%容差)电阻将此引脚接地。 辅助ADC输入。若未使用此引脚，则将其接地。 4线模式的SPI串行数据输出，或者3线模式下的高Z。 接收通道1差分输入A。另外，每个引脚均可用作单端输入。将未使用 的引脚接地。 发射通道1功率监控输入。未使用此引脚时，将其接地。 发射通道1差分输出A。将未使用的引脚连接至1.3 V。 发射通道1差分输出B。将未使用的引脚连接至1.3 V。 参考频率晶振连接。使用晶振时，将其连接于这两个引脚之间。使用 外部时钟源时，将其连接至XTALN，使XTALP保持断开。 I为输入，O为输出，I/O为输入/输出，NC为未连接。 Rev. D | Page 19 of 36 AD9361 典型性能参数 800 MHz频段 0 4.0 –40°C +25°C +85°C –10 3.0 –15 RX EVM (dB) 2.5 2.0 1.5 –20 –25 –35 0.5 –40 0 700 750 800 850 900 RF FREQUENCY (MHz) –45 –75 –35 –30 –25 RX EVM (dB) –20 –25 –30 –1 –35 –2 –80 –70 –60 –50 –40 –30 –20 –10 RX INPUT POWER (dBm) –45 –90 10453-004 –90 –80 –70 –60 –50 –40 –30 –20 –10 RX INPUT POWER (dBm) 10453-007 –40 图7.RX EVM与RX输入功率的关系 (GSM模式，30.72 MHz REF_CLK，RF频率合成器内部加倍) 图4.RSSI误差与RX输入功率的关系 (LTE 10 MHz调制，折合至−50 dBm输入功率，800 MHz) 0 –40°C +25°C +85°C –5 1 –40°C +25°C +85°C RX EVM (dB) –10 0 –15 –20 –2 –25 –3 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 RX INPUT POWER (dBm) –10 10453-005 –1 –30 –72 –68 –64 –60 –56 –52 –48 –44 –40 –36 INTERFERER POWER LEVEL (dBm) 图8.RX EVM与干扰功率水平的关系 (LTE 10 MHz目标信号，PIN = −82 dBm， 5 MHz OFDM阻塞，7.5 MHz失调) 图5.RSSI误差与RX输入功率的关系 (Edge调制，折合至−50 dBm输入功率，800 MHz) Rev. D | Page 20 of 36 –32 10453-008 RSSI ERROR (dB) –40 –15 0 RSSI ERROR (dB) –45 –40°C +25°C +85°C –10 1 2 –50 –5 2 3 –55 0 3 –3 –100 –60 图6.RX EVM与RX输入功率的关系 (64 QAM LTE 10 MHz模式，19.2 MHz REF_CLK) –40°C +25°C +85°C 4 –65 RX INPUT POWER (dBm) 图3.RX噪声系数与RF频率的关系 5 –70 10453-006 –30 1.0 10453-003 RX NOISE FIGURE (dB) 3.5 –40°C +25°C +85°C –5 AD9361 0 20 –40°C +25°C +85°C 15 10 –4 IIP3 (dBm) RX EVM (dB) 5 –8 0 –5 –40°C +25°C +85°C –10 –12 –15 –54 –52 –50 –48 –46 –44 –42 –40 –38 –25 10453-009 –16 –56 –36 INTERFERER POWER LEVEL (dBm) 20 图9.RX EVM与干扰功率水平的关系 (LTE 10 MHz目标信号，PIN = -90 dBm，5 MHz OFDM阻塞，17.5 MHz失调) 44 52 RX GAIN INDEX 60 68 76 100 –40°C +25°C +85°C 90 80 10 70 IIP2 (dBm) RX NOISE FIGURE (dB) 36 图12.三阶输入交调截点(IIP3)与增益指数的关系 (f1 = 1.45 MHz，f2 = 2.89 MHz，GSM模式) 14 12 28 10453-012 –20 8 6 –40°C +25°C +85°C 60 50 40 30 4 20 2 –35 –31 –27 –23 INTERFERER POWER LEVEL (dBm) 0 20 –100 –105 RX LO LEAKAGE (dBm) RX GAIN (dB) 76 74 72 70 52 60 68 76 900 –40°C +25°C +85°C –110 –115 –120 –125 750 800 850 900 RX LO FREQUENCY (MHz) 10453-011 68 66 700 44 图13.二阶输入交调截点(IIP2)与增益指数的关系 (f1 = 2.00 MHz，f2 = 2.01 MHz，GSM模式) –40°C +25°C +85°C 78 36 RX GAIN INDEX 图10.RX噪声系数与干扰功率水平的关系 (Edge目标信号，PIN = −90 dBm，CW阻塞、3 MHz失调，增益指数 = 64) 80 28 10453-013 –39 10453-014 –43 10453-010 0 –47 10 图11.RX增益与RX LO频率的关系(增益指数 = 76，最大设置) –130 700 750 800 850 RX LO FREQUENCY (MHz) 图14.RX本振(LO)泄漏与RX LO频率的关系 Rev. D | Page 21 of 36 AD9361 –20 –40 –60 –80 –100 2000 4000 6000 8000 10000 12000 FREQUENCY (MHz) 图15.LNA输入端的RX发射(直流至12 GHz，fLO_RX = 800 MHz， LTE 10 MHz，fLO_TX = 860 MHz) –5 0 5 10 15 FREQUENCY OFFSET (MHz) 图16.TX输出功率与TX LO频率的关系(衰减设置 = 0 dB，单音输出) 1.6 1.4 1.2 1.0 0.8 0.6 –100 0.4 –80 FREQUENCY OFFSET (MHz) 10453-019 TX LO FREQUENCY (MHz) –60 0 900 –40 0.2 850 –20 –0.2 800 ATT 0dB ATT 3dB ATT 6dB 0 –0.4 750 10453-016 6.5 图19.TX频谱与相对载波频率的频率失调的关系 (fLO_TX = 800 MHz，GSM 下行链路，展示的是数字衰减变化，3 MHz范围) 20 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 10 20 30 40 ATTENUATION SETTING (dB) 图17.TX功率控制线性度误差与衰减设置的关系 50 0 ATT 0dB ATT 3dB ATT 6dB –20 –40 –60 –80 –100 –120 –6 –4 –2 0 2 FREQUENCY OFFSET (MHz) 4 6 10453-020 TRANSMITTER OUTPUT POWER (dBm/30kHz) –40°C +25°C +85°C 10453-017 STEP LINEARITY ERROR (dB) –10 –0.6 7.0 0 –90 –0.8 7.5 –0.5 –80 –1.0 8.0 0.4 –70 –100 –15 TRANSMITTER OUTPUT POWER (dBm/30kHz) TX OUTPUT POWER (dBm) 8.5 0.5 –60 20 9.0 6.0 700 –50 图18.TX频谱与相对载波频率的频率失调的关系 (fLO_TX = 800 MHz，LTE 10 MHz下行链路，展示的是数字衰减变化) –40°C +25°C +85°C 9.5 –40 –1.2 10.0 –30 –1.4 0 –20 –1.6 –120 ATT 0dB ATT 3dB ATT 6dB –10 10453-018 TRANSMITTER OUTPUT POWER (dBm/100kHz) 0 10453-015 POWER AT LNA INPUT (dBm/750kHz) 0 图20.TX频谱与相对载波频率的频率失调的关系 (fLO_TX = 800 MHz，GSM 下行链路，展示的是数字衰减变化，12 MHz范围) Rev. D | Page 22 of 36 AD9361 0.30 –40°C +25°C +85°C INTEGRATED PHASE NOISE (°rms) –25 –35 –40 0 5 10 15 20 25 30 35 40 TX ATTENUATION SETTING (dB) 0.15 0.10 0.05 0 700 –30 –35 TX CARRIER AMPLITUDE (dBc) –40°C +25°C +85°C TX EVM (dB) –30 –35 –40 –45 900 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 10 20 30 40 50 –70 700 10453-022 0 TX ATTENUATION SETTING (dB) –40°C +25°C +85°C 0.4 0.3 0.2 750 800 850 900 FREQUENCY (MHz) 10453-023 0.1 0 700 800 850 900 900 图25.TX载波抑制与频率的关系 TX SECOND-ORDER HARMONIC DISTORTION (dBc) 0.5 750 FREQUENCY (MHz) 图22.TX EVM与TX衰减设置的关系(fLO_TX = 800 MHz， GSM调制，30.72 MHz REF_CLK，RF频率合成器内部加倍) INTEGRATED PHASE NOISE (°RMS) 850 图24.集成TX LO相位噪声与频率的关系 (30.72 MHz REF_CLK，RF频率合成器内部加倍) –20 –50 800 FREQUENCY (MHz) 图21.TX EVM与TX衰减设置的关系(fLO_TX = 800 MHz， LTE 10 MHz，64 QAM调制，19.2 MHz REF_CLK) –25 750 10453-025 –50 10453-021 –45 0.20 10453-026 TX EVM (dB) –30 –40°C +25°C +85°C 0.25 10453-024 –20 图23.集成TX LO相位噪声与频率的关系(19.2 MHz REF_CLK) –50 –55 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –60 –65 –70 –75 –80 700 750 800 850 FREQUENCY (MHz) 图26.TX二次谐波失真(HD2)与频率的关系 Rev. D | Page 23 of 36 –20 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –25 170 ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C 165 TX SNR (dB/Hz) –30 –35 –40 –45 160 150 750 800 850 900 140 TX SINGLE SIDEBAND AMPLITUDE (dBc) TX OIP3 (dBm) –30 20 15 10 0 4 8 12 16 20 TX ATTENUATION SETTING (dB) 10453-028 5 0 图28.TX三阶输出交调截点(OIP3)与TX衰减设置的关系 170 160 155 150 0 3 6 9 12 15 TX ATTENUATION SETTING (dB) 10453-029 145 140 12 16 –35 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C 20 900 ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 –70 700 750 800 850 FREQUENCY (MHz) 图31.TX单边带(SSB)抑制与频率的关系 (1.5375 MHz失调) –40°C +25°C +85°C 165 8 图30.TX信噪比(SNR)与TX衰减设置的关系 (GSM目标信号，噪声于20 MHz失调条件下测量) –40°C +25°C +85°C 25 4 TX ATTENUATION SETTING (dB) 图27.TX三次谐波失真(HD3)与频率的关系 30 0 10453-030 –60 700 10453-031 145 –55 FREQUENCY (MHz) TX SNR (dB/Hz) –40°C +25°C +85°C 155 –50 10453-027 TX THIRD-ORDER HARMONIC DISTORTION (dBc) AD9361 图29.TX信噪比(SNR)与TX衰减设置的关系 (LTE 10 MHz目标信号，噪声于90 MHz失调条件下测量) Rev. D | Page 24 of 36 AD9361 2.4 GHz频段 0 4.0 –5 –40°C +25°C +85°C 3.0 –10 2.5 RX EVM (dB) RX NOISE FIGURE (dB) 3.5 2.0 1.5 –15 –20 1.0 –40°C +25°C +85°C 1900 2000 2100 2200 2300 2400 2500 2600 2700 RF FREQUENCY (MHz) –64 –60 –56 –52 –48 –44 –40 –36 –32 –28 INTERFERER POWER LEVEL (dBm) 0 –40°C +25°C +85°C 4 –68 图35.RX EVM与干扰功率水平的关系(LTE 20 MHz目标信号， PIN = -75 dBm，LTE 20 MHz阻塞，20 MHz失调) 图32.RX噪声系数与RF频率的关系 5 –30 –72 10453-032 0 1800 10453-035 –25 0.5 –5 –40°C +25°C +85°C –10 2 RX EVM (dB) RSSI ERROR (dB) 3 1 0 –15 –20 –1 –90 –80 –70 –60 –50 –40 –30 –20 –10 RX INPUT POWER (dBm) –50 –45 –40 –35 –30 –25 –20 INTERFERER POWER LEVEL (dBm) 80 –40°C +25°C +85°C –5 –55 图36.RX EVM与干扰功率水平的关系(LTE 20 MHz目标信号， PIN = -75 dBm，LTE 20 MHz阻塞，40 MHz失调) 图33.RSSI误差与RX输入功率的关系 (折合至−50 dBm输入功率，2.4 GHz) 0 –30 –60 10453-033 –3 –100 10453-036 –25 –2 78 –40°C +25°C +85°C –10 76 RX GAIN (dB) –20 –25 74 72 –30 70 –35 –45 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30 INPUT POWER (dBm) –25 图34.RX EVM与输入功率的关系 (64 QAM LTE 20 MHz模式，40 MHz REF_CLK) 66 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 RX LO FREQUENCY (MHz) 图37.RX增益与RX LO频率的关系(增益指数 = 76，最大设置) Rev. D | Page 25 of 36 10453-037 68 –40 10453-034 RX EVM (dB) –15 AD9361 0 15 POWER AT LNA INPUT (dBm/750kHz) –40°C +25°C +85°C 10 IIP3 (dBm) 5 0 –5 –10 –15 –25 20 28 36 44 52 60 68 76 RX GAIN INDEX –80 –100 0 2000 4000 6000 8000 10000 12000 FREQUENCY (MHz) 10.0 –40°C +25°C +85°C –40°C +25°C +85°C 9.5 TX OUTPUT POWER (dBm) 70 60 IIP2 (dBm) –60 图41.LNA输入端的RX发射(直流至12 GHz，fLO_RX = 2.4 GHz， LTE 20 MHz，fLO_TX = 2.46 GHz) 图38.三阶输入交调截点(IIP3)与增益指数的关系 (f1 = 30 MHz，f2 = 61 MHz) 80 –40 –120 10453-038 –20 –20 10453-041 20 50 40 9.0 8.5 8.0 7.5 7.0 30 28 36 44 52 60 68 76 RX GAIN INDEX 2000 2100 2200 2300 2400 2500 2600 2700 TX LO FREQUENCY (MHz) 0.5 –40°C +25°C +85°C –40°C +25°C +85°C 0.4 STEP LINEARITY ERROR (dB) –105 –110 –115 –120 –125 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –130 1800 1900 2000 2100 2200 2300 2400 2500 2600 RX LO FREQUENCY (MHz) 2700 图40.RX本振(LO)泄漏与RX LO频率的关系 –0.5 0 10 20 30 40 ATTENUATION SETTING (dB) 图43.TX功率控制线性度误差与衰减设置的关系 Rev. D | Page 26 of 36 50 10453-043 –0.4 10453-040 RX LO LEAKAGE (dBm) 1900 图42.TX输出功率与TX LO频率的关系(衰减设置 = 0 dB，单音输出) 图39.二阶输入交调截点(IIP2)与增益指数的关系 (f1 = 60 MHz，f2 = 61 MHz) –100 6.0 1800 10453-039 20 20 10453-042 6.5 AD9361 –30 ATT 0dB ATT 3dB ATT6dB –35 TX CARRIER AMPLITUDE (dBc) –20 –40 –60 –80 –100 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –40 –45 –50 –55 –60 –10 –5 0 5 10 15 20 25 –70 1800 1900 –25 TX EVM (dB) –30 –35 –40 0 5 10 15 20 25 30 35 40 ATTENUATION SETTING (dB) 10453-045 –45 –50 –55 0.3 0.2 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) 10453-046 0.1 2000 2500 2600 2700 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –65 –70 –75 –80 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2700 FREQUENCY (MHz) TX THIRD-ORDER HARMONIC DISTORTION (dBc) –40°C +25°C +85°C 1900 2400 图48.TX二次谐波失真(HD2)与频率的关系 0.4 0 1800 2300 –60 图45.TX EVM与发射器衰减设置的关系 (40 MHz REF_CLK，LTE 20 MHz，64 QAM调制) 0.5 2200 图47.TX载波抑制与频率的关系 TX SECOND-ORDER HARMONIC DISTORTION (dBc) –40°C +25°C +85°C 2100 FREQUENCY (MHz) 图44.TX频谱与相对载波频率于的频率失调的关系 (fLO_TX = 2.3 GHz，LTE 20 MHz下行链路，展示的是数字衰减变化) –20 2000 10453-047 –15 10453-048 –20 FREQUENCY OFFSET (MHz) INTEGRATED PHASE NOISE (°rms) ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C 10453-049 –120 –25 –50 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C –65 10453-044 TRANSMITTER OUTPUT POWER (dBm/100kHz) 0 图46.集成TX LO相位噪声与频率的关系(40 MHz REF_CLK) –20 –25 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –30 –35 –40 –45 –50 –55 –60 1800 1900 2000 2100 2200 2300 2400 2500 2600 FREQUENCY (MHz) 图49.TX三次谐波失真(HD3)与频率的关系 Rev. D | Page 27 of 36 AD9361 TX SINGLE SIDEBAND AMPLITUDE (dBc) 25 TX OIP3 (dBm) –30 –40°C +25°C +85°C 20 15 10 0 0 4 8 12 16 20 TX ATTENUATION SETTING (dB) 10453-050 5 –40°C +25°C +85°C 158 156 152 150 148 146 144 142 0 3 6 9 12 15 TX ATTENUATION SETTING (dB) 10453-051 TX SNR (dB/Hz) 154 140 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 –70 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) 图52.TX单边带(SSB)抑制与频率的关系(3.075 MHz失调) 图50.TX三阶输出交调截点(OIP3)与TX衰减设置的关系 160 –35 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C 图51.TX信噪比(SNR)与TX衰减设置的关系 (LTE 20 MHz目标信号，噪声于90 MHz失调条件下测量) Rev. D | Page 28 of 36 10453-052 30 AD9361 6 5 5 0 4 –5 RX EVM (dB) 3 –40°C +25°C +85°C 2 –10 –40°C +25°C +85°C –15 –20 1 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 RF FREQUENCY (GHz) –25 –72 10453-053 0 5.0 –67 –62 –57 –52 –47 –42 –37 –32 INTERFERER POWER LEVEL (dBm) 10453-056 RX NOISE FIGURE (dB) 5.5 GHz频段 图56.RX EVM与干扰功率水平的关系(WiMAX 40 MHz目标信号， PIN = −74 dBm，WiMAX 40 MHz阻塞，40 MHz失调) 图53.RX噪声系数与RF频率的关系 5 5 4 0 2 –40°C +25°C +85°C –5 RX EVM (dB) RSSI ERROR (dB) 3 1 0 –10 –40°C +25°C +85°C –15 –1 –80 –70 –60 –50 –40 –30 –20 –10 RX INPUT POWER (dBm) –25 –60 10453-054 –3 –90 –55 –50 –45 –40 –35 –30 –25 INTERFERER POWER LEVEL (dBm) 图54.RSSI误差与RX输入功率的关系(折合至−50 dBm输入功率，5.8 GHz) 10453-057 –20 –2 图57.RX EVM与干扰功率水平的关系(WiMAX 40 MHz目标信号， PIN = −74 dBm，WiMAX 40 MHz阻塞，80 MHz失调) 0 70 –5 –20 –25 66 64 –30 –40°C +25°C +85°C 62 –40 –74 –68 –62 –56 –50 –44 –38 RX INPUT POWER (dBm) –32 –26 –20 10453-055 –35 图55.RX EVM与RX输入功率的关系(64 QAM WiMAX 40 MHz模式， 40 MHz REF_CLK，RF频率合成器内部加倍) Rev. D | Page 29 of 36 60 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 FREQUENCY (GHz) 图58.RX增益与频率的关系(增益指数 = 76，最大设置) 6.0 10453-058 –15 RX GAIN (dB) RX EVM (dB) 68 –40°C +25°C +85°C –10 AD9361 20 0 5 –40°C +25°C +85°C 0 –5 –10 6 16 26 36 46 56 66 76 RX GAIN INDEX –40 –60 –80 –100 –120 0 70 9 TX OUTPUT POWER (dBm) 10 IIP2 (dBm) 60 –40°C +25°C +85°C 40 30 20 25 30 –40°C +25°C +85°C 8 7 6 5 28 36 44 52 60 68 76 4 5.0 10453-060 20 RX GAIN INDEX –92 0.4 –94 0.3 STEP LINEARITY ERROR (dB) 0.5 –96 –98 –40°C +25°C +85°C –102 –104 –106 5.3 5.4 5.5. 5.6 5.7 5.8 5.9 6.0 0.2 0.1 0.0 –0.1 –0.2 –40°C +25°C +85°C –0.3 –0.4 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 FREQUENCY (GHz) 5.9 6.0 10453-061 –108 –110 5.0 5.2 图63.TX输出功率与频率的关系(衰减设置 = 0 dB，单音) –90 –100 5.1 FREQUENCY (GHz) 图60.二阶输入交调截点(IIP2)与增益指数的关系 (f1 = 70 MHz，f2 = 71 MHz) RX LO LEAKAGE (dBm) 15 图62.LNA输入端的RX发射(直流至26 GHz， fLO_RX = 5.8 GHz，WiMAX 40 MHz) 80 20 10 FREQUENCY (GHz) 图59.三阶输入交调截点(IIP3)与增益指数的关系 (f1 = 50 MHz，f2 = 101 MHz) 50 5 10453-063 –20 10453-059 –15 –20 图61.RX本振(LO)泄漏与频率的关系 –0.5 0 10 20 30 40 50 60 70 80 ATTENUATION SETTING (dB) 图64.TX功率控制线性度误差与衰减设置的关系 Rev. D | Page 30 of 36 90 10453-064 IIP3 (dBm) 10 10453-062 POWER AT LNA INPUT (dBm/150kHz) 15 AD9361 0 –10 –10 –20 TX CARRIER AMPLITUDE (dBc) ATT 0dB ATT 3dB ATT 6dB –30 –40 –50 –60 –70 –20 –30 –40 –50 –20 –10 0 10 20 30 40 50 –70 5.0 5.1 –34 –36 –40°C +25°C +85°C 4 6 8 10 TX ATTENUATION SETTING (dB) 10453-066 TX EVM (dB) –32 2 0.7 0.6 0.5 0.4 –40°C +25°C +85°C 0.2 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 FREQUENCY (GHz) 6.0 5.7 5.8 5.9 6.0 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –55 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –60 –65 –70 –75 –80 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 图69.TX二次谐波失真(HD2)与频率的关系 10453-067 0.1 5.1 5.6 FREQUENCY (GHz) TX THIRD-ORDER HARMONIC DISTORTION (dBc) 0.8 0 5.0 5.5 –50 图66.TX EVM与TX衰减设置的关系(WiMAX 40 MHz，64 QAM调制， fLO_TX = 5.495 GHz，40 MHz REF_CLK，RF频率合成器内部加倍) 0.3 5.4 图68.TX载波抑制与频率的关系 TX SECOND-ORDER HARMONIC DISTORTION (dBc) –30 0 5.3 FREQUENCY (GHz) 图65.TX频谱与相对载波频率于的频率失调的关系 (fLO_TX = 5.8 GHz，WiMAX 40 MHz下行链路，展示的是数字衰减变化) –38 5.2 10453-068 –30 10453-069 –40 FREQUENCY OFFSET (MHz) INTEGRATED PHASE NOISE (°RMS) ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C 图67.集成TX LO相位噪声与频率的关系 (40 MHz REF_CLK，RF频率合成器内部加倍) –10 –15 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –20 –25 –30 –35 –40 –45 –50 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 FREQUENCY (GHz) 图70.TX三次谐波失真(HD3)与频率的关系 Rev. D | Page 31 of 36 6.0 10453-070 –90 –50 –40 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –60 –80 10453-065 TRANSMITTER OUTPUT POWER (dBm/1MHz) 0 AD9361 20 TX OIP3 (dBm) 16 12 –40°C +25°C +85°C 8 4 –4 0 4 8 12 16 20 TX ATTENUATION SETTING (dB) 10453-071 0 150 149 TX SNR (dB/Hz) 148 147 146 –40°C +25°C +85°C 144 0 3 6 9 12 15 TX ATTENUATION SETTING (dB) 10453-072 143 142 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 –70 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 FREQUENCY (GHz) 图73.TX单边带(SSB)抑制与频率的关系(7 MHz失调) 图71.TX三阶输出交调截点(OIP3)与TX衰减设置的关系 (fLO_TX = 5.8 GHz) 145 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –35 图72.TX信噪比(SNR)与TX衰减设置的关系 (WiMAX 40 MHz目标信号，噪声于90 MHz失调条件下测量， fLO_TX = 5.745 GHz) Rev. D | Page 32 of 36 10453-073 TX SINGLE SIDEBAND AMPLITUDE (dBc) –30 AD9361 工作原理 一般特性 发射器 AD9361是一款高集成度的射频(RF)收发器，能够配置用于 广泛应用，在单个器件中集成了提供所有收发器功能的所 有必要RF、混合信号和数字模块。可编程能力使这款宽带 收发器可以适用于多种通信标准，包括频分双工(FDD)和 时分双工(TDD)系统。此外，这种可编程能力还允许通过 单通道12位并行数据端口、双通道12位并行数据端口或12 位低电压差分信令(LVDS)接口，与各种基带处理器(BBP) 相连接。 发射器部分含有两个相同的、独立控制的通道，提供了所 有必要的数字处理、混合信号和RF模块，可以实现一个直 接变频系统，同时共用一个通用型频率合成器。从BBP收 到的数字数据通过一个不带插值选项的完全可编程128抽 头FIR滤波器。FIR输出被发送到一系列插值滤波器，在输 出到达DAC之前，提供额外的滤波和数据速率插值处理。 每个12位DAC都拥有可调的采样速率。I和Q通道都馈入RF 模块以进行上变频。 AD9361还提供了自我校准和自动增益控制(AGC)系统，可 以在多种温度和输入信号条件下维持高性能水平。另外， 器件还包括几种测试模式，允许系统设计师插入测试音， 创建内部回送模式，以便用于在原型制作过程中对设计进 行调试，并针对具体应用优化无线电配置。 当转换为基带模拟信号时，I和Q信号将进行滤波，以移除 采样伪像，然后馈入上变频混频器。这里，I和Q信号将重 新组合起来，并在载波频率下进行调制，以便传输到输出 级。组合信号还会通过模拟滤波器，由它们提供额外的频 带整形处理，然后再将信号传输至输出放大器。每个发射 通道都提供了较宽的细粒度衰减调整范围，以帮助设计师 优化信噪比(SNR)。 接收器 接收器部分含有所有必要模块，用于接收RF信号并将其转 换成可供BBP使用的数字数据。有两个独立控制的通道， 可以接收来自不同源的信号，使器件可以用于多输入、多 输出(MIMO)系统，同时还可共享一个通用频率合成器。 每个通道都有三个输入，可以多路复用至信号链，使 AD9361可以用于搭载多个天线输入的分集系统。接收器是 一个直接变频系统，含有一个低噪声放大器(LNA)，其后 是匹配相内(I)和正交(Q)放大器、混频器和频带整形滤波 器，该滤波器可以将接收到的信号下变频为基带，以便进 行数字化。外部LNA也可连接至该器件，给设计师带来了 极大的灵活性，使其可以针对具体应用定制接收器前端。 依据预编程增益指数映射，可实现增益控制，该映射将增 益分配于各模块之间，从而实现各电平下的性能优化。这 可以通过在快速或慢速模式下使能内部AGC来实现，也可 通过手动增益控制来实现，使BBP可以根据需要调整增 益。此外，各个通道还拥有独立的RSSI测量功能、直流失 调跟踪功能和进行自我校准的所有必要电路。 接收器包括12位、Σ-Δ ADC和可调采样速率，可以从收到 的信号产生数据流。数字化信号可以通过一系列抽取滤波 器和一个完全可编程的128抽头FIR滤波器(带有额外的抽取 设置)进一步调理。各个数字滤波器模块的采样速率可以通 过更改抽取系数来进行调整，从而产生需要的输出数据 速率。 每个发射通道内置自我校准电路，以支持自动实时调整。 发射器模块同时为每个通道提供一个TX监控器模块。该模 块监控发射器输出，并通过一个未使用的接收器通道将其 送回BBP，以实现信号监控。TX监控器模块仅在接收器空 闲的TDD模式下可用。 时钟输入选项 AD9361运行时使用的参考时钟可由两个不同时钟源提供。 第一个选择是使用一个专门的晶振，其频率在19 MHz和50 MHz 之前，连接于XTALP和XTALN引脚之间。第二个选择是将 一个外部振荡器或时钟分配器件(如AD9548)连接至XTALN 引脚(其中，XTALP引脚保持断开状态)。如果使用外部振 荡器，则频率可在10 MHz和80 MHz之间变化。该参考时钟 用于为频率合成器模块提供电源，这些模块在器件内部生 成所有数据时钟、采样时钟和本振。 利用数字可编程、数字控制晶振(DCXO)功能来调节片内 可变电容，则可消除晶振频率误差。该电容可以调谐系统 中的晶振频率变化，结果产生精度更高的参考时钟，而所 有其他频率就是从这些时钟生成的。该功能也可配合片内 温度检测功能使用，以便在正常运行中提供振荡器频率温 度补偿。 Rev. D | Page 33 of 36 AD9361 RX_FRAME信号 频率合成器 RF PLL AD9361含有两个完全相同的频率合成器，用于为RF信号 路径生成需要的LO信号：一个用于接收器，一个用于发射 器。锁相环(PLL)频率合成器采用小数N设计，融入了完全 集成式电压控制振荡器(VCO)和环路滤波器。在TDD运行 模式下，频率合成器会根据RX和TX帧的需要开启和关闭。在 FDD模式下，TX PLL和RX PLL可以同时激活。这些PLL不 需要外部元件。 BB PLL AD9361还含有一个基带PLL频率合成器，用于生成所有基 带相关时钟信号。这些包括ADC和DAC采样时钟、DATA_ CLK信号(见“数字数据接口”部分)和所有数据帧信号。该 PLL的编程频率范围为700 MHz至1400 MHz，具体取决于系 统的数据速率和采样速率要求。 数字数据接口 AD9361数据接口采用并行数据端口(P0和P1)来在器件和 BBP之间传输数据。数据端口可以配置为单端CMOS格式 或差分LVDS格式。这两种格式都可以配置为多种方式， 以满足数据排序和数据端口连接的系统需求。具体包括单 端口数据总线、双端口数据总线、单数据速率、双数据速 率和各种数据排序组合，以在适当的时间将来自不同通道 的数据传过总线。 总线传输是通过简单的硬件握手信令来控制的。两个端口 可以工作于双向(TDD)模式或全双工(FDD)模式，在后一 种模式下，一半位数用于发射数据、一半用于接收数据。 接口也可配置为，只将其中一个数据端口用于不需要高数 据速率而且倾向于使用较少接口引脚的应用。 DATA_CLK信号 RX数据提供DATA_CLK信号，BBP可以在接收数据时使用 后者。DATA_CLK可以设为提供单数据速率(SDR)时序的 速率(其中，数据在各上升时钟沿采样)，也可设为提供双 数据速率(DDR)时序(其中，同时在上升沿和下降沿捕获数 据)。该时序适用于使用单端口或两个端口的运行模式。 FB_CLK信号 对于发射数据，接口以FB_CLK信号作为时序参考。对于 突发控制信号，FB_CLK允许源与上升沿捕获时序同步， 而对于发射信号突发，则允许与上升沿(SDR模式)或双沿 捕 获 (DDR模 式 )时 序 同 步 。 FB_CLK信 号 必 须 具 有 与 DATA_CLK的频率和占空比。 每 当 接 收 器 输 出 有 效 数 据 时 ， 器 件 都 会 生 成 一 个 RX_ FRAME输出信号。该信号有两个模式：电平模式(RX_ FRAME在 数 据 有 效 期 间 保 持 高 电 平 )和 脉 冲 模 式 (RX_ FRAME以50%的占空比脉动)。类似地，BBP必须提供一个 TX_FRAME信号，以上升沿来指示有效数据传输的开始。 与RX_FRAME相似，TX_FRAME信号可能在整个突发过程 中保持高电平，或者，可能以50%的占空比脉动。 使能状态机 AD9361收发器包括一个使能状态机(ENSM)，允许对器件 的当前状态进行实时控制。在正常运行过程中，器件可以 置于多种不同状态，包括 • • • • • • 待机—节能，频率合成器被禁用 休眠—待机，所有时钟/BB PLL被禁用 TX—TX信号链被使能 RX—RX信号链被使能 FDD—TX和RX信号链被使能 报警—频率合成器被使能 ENSM有两种可能的控制方法：SPI控制和引脚控制。 SPI控制模式 在SPI控制模式下，通过写SPI寄存器，从当前状态进入下 一状态，从而实现对ENSM的异步控制。SPI控制被认为与 DATA_CLK异步，因为SPI_CLK可能派生自一个不同的参 考时钟，而且仍然能正常工作。当不需要对频率合成器进 行实时控制时，推荐采用SPI控制ENSM法。只要BBIC能够 精确执行SPI写操作，SPI控制就可以用于实时控制。 引脚控制模式 在引脚控制模式下，ENABLE引脚和TXNRX引脚的使能功 能允许对当前状态进行实时控制。ENSM支持TDD或FDD 运行模式，具体取决于相应SPI寄存器的配置。如果BBIC 有可以实时控制的额外控制输出，允许用一个简单的双线 接口来控制器件状态，则建议使用ENABLE和TXNRX引脚 控制方法。为了使ENSM的当前状态进入下一状态，可以 通过一个脉冲(边沿在内部检测)或电平来鸡翅ENABLE引脚 的使能功能。 使用脉冲时，其最小脉冲宽度必须为一个FB_CLK周期。 在电平模式下，ENABLE和TXNRX引脚同样由AD9361检测 其边沿，而且必须符合相同的最小脉冲宽度要求，即一个 FB_CLK周期。 Rev. D | Page 34 of 36 AD9361 在FDD模式下，ENABLE和TXNRX引脚必须重新映射，作 为实时RX和TX数据传输控制信号。在该模式下，ENABLE 引脚使能或禁用接收信号路径，TXNRX引脚使能或禁用发 射信号路径。在该模式下，ENSM将从系统中移除，以便 由这些引脚控制所有数据流。 SPI接口 AD9361通过一个串行外设接口(SPI)与BBP通信。该接口可 以配置为4线接口，带有专门的接收和发射端口，也可以 配置为3线接口，带一个双向数据通信端口。该总线允许 BBP通过一种简单地址数据串行总线协议，设置所有器件 控制参数。 写命令遵循一种24位格式。前6位用于设置总线方向和需 要传输的字节数。接下来的10位数据的写入地址。最后8 位是将被传输至指定寄存器地址(MSB至LSB)的数据。 AD9361还支持LSB优先格式，允许命令以LSB至MSB格式 写入。在该模式下，对于多字节写命令，寄存器地址将 递增。 读命令遵循相似的格式，区别在于，前16位在SPI_DI引脚 上传输，最后8位从AD9361中读取，如果是4线模式，则在 SPI_DO引脚上完成，如果是3线模式，则在SPI_DI引脚上 完成。 辅助转换器 AUXADC AD9361含有一个辅助ADC，可以用来监控温度、功率输 出等系统功能。转换器为12位宽，输入范围为0 V至1.25 V。 使能时，ADC处于自由运行状态。SPI读操作提供在ADC 输出端锁存的最后值。借助位于ADC之前的一个多路复用 器，用户可以在AUXADC输入引脚与内置温度传感器之间 进行选择。 AUXDAC1和AUXDAC2 AD9361含有两个完全相同的辅助DAC，可以提供功率放 大器(PA)偏置或其他系统功能。辅助DAC为10位宽，输出 电压范围为0.5 V至VDD_GPO − 0.3 V，电流驱动为10 mA， 可以通过内部使能状态机直接控制。 AD9361的供电 AD9361必须通过以下三种电源供电：模拟电源(VDDD1P3_ DIG/VDDAx = 1.3 V)、接口电源(VDD_INTERFACE = 1.8 V) 和GPO电源(VDD_GPO = 3.3 V)。 对于要求优化噪声性能的应用，建议用低噪声、低压差 (LDO)稳压器分离和提供1.3 V电源。图74展示的是建议方法。 3.3V 控制引脚 ADP2164 1.8V 控制输入(CTRL_IN[3:0]) ADP1755 1.3V_A ADP1755 1.3V_B 图74.面向AD9361的低噪声电源解决方案 对于注重电路板空间并且最佳噪声性能不构成绝对要求的 应用，1.3 V模块电轨可以直接由一个开关提供，并且可以 采取一种集成程度更高的电源管理装置(PMU)。图75显示 了这种方法。 AD9361提供4个边沿检测控制输入引脚。在手动增益模式 下，BBP可以用这些引脚来实时更改增益表索引。在发射 模式下，BBP可以使用两个这些引脚来实时更改发射增益。 GPO引脚(GPO_3至GPO_0) AD9361提供4个支持3.3 V的通用逻辑输出引脚：GPO_3、 GPO_2、GPO_1和GPO_0。这些引脚可以用于通过AD9361 SPI总线控制其他外设器件，比如稳压器、开关等，或者， 也可充当内部AD9361状态机的从机。 Rev. D | Page 35 of 36 ADP5040 1.2A BUCK ADP1755 1.3V LDO VDDD1P3_DIG/VDDAx AD9361 300mA LDO 1.8V 300mA LDO 3.3V VDD_INTERFACE VDD_GPO 图75.面向AD9361的空间优化型电源解决方案 10453-075 AD9361提供8个同步实时输出信号，用作BBP的中断。这 些输出可以配置为输出一些内部设置和测量值，BBP在监 控收发器在不同情况下的性能时可以使用这些设置和测量 值。控制输出指针寄存器选择将哪些信息输出到这些引 脚，而控制输出使能寄存器则决定BBP将激活哪些信号以 便监控。用于手动增益模式的信号、校准标志、状态机状 态和ADC输出都是可以在这些引脚上监控的部分输出。 10453-074 控制输出(CTRL_OUT[7:0]) AD9361 封装和订购信息 外形尺寸 A1 BALL CORNER 10.10 10.00 SQ 9.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 8.80 SQ E F G H 0.80 J K L M 0.60 REF TOP VIEW BOTTOM VIEW DETAIL A 1.70 MAX DETAIL A 1.00 MIN 0.32 MIN 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1. 11-18-2011-A SEATING PLANE 图76.144引脚芯片级封装球栅阵列[CSP_BGA] (BC-144-7) 图示尺寸单位：毫米 订购指南 型号1 AD9361BBCZ AD9361BBCZ-REEL 1 温度范围 −40°C至+85°C −40°C至+85°C 封装描述 144引脚CSP_BGA封装 144引脚CSP_BGA封装 Z = 符合RoHS标准的器件。 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10453sc-0-11/13(D) Rev. D | Page 36 of 36 封装选项 BC-144-7 BC-144-7 AD9361 封装和订购信息 外形尺寸 A1 BALL CORNER 10.10 10.00 SQ 9.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 8.80 SQ E F G H 0.80 J K L M 0.60 REF TOP VIEW BOTTOM VIEW DETAIL A 1.70 MAX DETAIL A 1.00 MIN 0.32 MIN 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1. 11-18-2011-A SEATING PLANE 图76.144引脚芯片级封装球栅阵列[CSP_BGA] (BC-144-7) 图示尺寸单位：毫米 订购指南 型号1 AD9361BBCZ AD9361BBCZ-REEL 1 温度范围 −40°C至+85°C −40°C至+85°C 封装描述 144引脚CSP_BGA封装 144引脚CSP_BGA封装 Z = 符合RoHS标准的器件。 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10453sc-0-11/13(D) Rev. D | Page 36 of 36 封装选项 BC-144-7 BC-144-7 AD9361 封装和订购信息 外形尺寸 A1 BALL CORNER 10.10 10.00 SQ 9.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 8.80 SQ E F G H 0.80 J K L M 0.60 REF TOP VIEW BOTTOM VIEW DETAIL A 1.70 MAX DETAIL A 1.00 MIN 0.32 MIN 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1. 11-18-2011-A SEATING PLANE 图76.144引脚芯片级封装球栅阵列[CSP_BGA] (BC-144-7) 图示尺寸单位：毫米 订购指南 型号1 AD9361BBCZ AD9361BBCZ-REEL 1 温度范围 −40°C至+85°C −40°C至+85°C 封装描述 144引脚CSP_BGA封装 144引脚CSP_BGA封装 Z = 符合RoHS标准的器件。 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10453sc-0-11/13(D) Rev. D | Page 36 of 36 封装选项 BC-144-7 BC-144-7 RF Agile Transceiver AD9361 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM RX1B_P, RX1B_N AD9361 RX1A_P, RX1A_N ADC RX1C_P, RX1C_N RX2A_P, RX2A_N ADC RX2C_P, RX2C_N RX LO TX_MON1 TX LO TX1A_P, TX1A_N DAC DATA INTERFACE RX2B_P, RX2B_N P0_[D11:D0]/ TX_[D5:D0] P1_[D11:D0]/ RX_[D5:D0] TX1B_P, TX1B_N TX_MON2 TX2A_P, TX2A_N SPI CTRL DAC TX2B_P, TX2B_N DAC DAC ADC CTRL GPO RADIO SWITCHING PLLs CLK_OUT AUXADC AUXDACx XTALP XTALN NOTES 1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0], AND RADIO SWITCHING CONTAIN MULTIPLE PINS. APPLICATIONS Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems 10453-001 RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs Band: 70 MHz to 6.0 GHz Supports TDD and FDD operation Tunable channel bandwidth: <200 kHz to 56 MHz Dual receivers: 6 differential or 12 single-ended inputs Superior receiver sensitivity with a noise figure of 2 dB at 800 MHz local oscillator (LO) RX gain control Real-time monitor and control signals for manual gain Independent automatic gain control Dual transmitters: 4 differential outputs Highly linear broadband transmitter TX EVM: ≤−40 dB TX noise: ≤−157 dBm/Hz noise floor TX monitor: ≥66 dB dynamic range with 1 dB accuracy Integrated fractional-N synthesizers 2.4 Hz maximum LO step size Multichip synchronization CMOS/LVDS digital interface Figure 1. GENERAL DESCRIPTION The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361 operates in the 70 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported. The two independent direct conversion receivers have state-of-theart noise figure and linearity. Each receive (RX) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9361 also has flexible manual gain modes that can be externally controlled. Two high dynamic range ADCs per channel digitize the received I and Q signals and pass them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate sample rate. Rev. D The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best in class TX EVM of <−40 dB, allowing significant system margin for the external PA selection. The on-board transmit (TX) power monitor can be used as a power detector, enabling highly accurate TX power measurements. The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by frequency division duplex (FDD) systems, is integrated into the design. All VCO and loop filter components are integrated. The core of the AD9361 can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and four real-time I/O control pins. Comprehensive power-down modes are included to minimize power consumption during normal use. The AD9361 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9361 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 33 Applications ....................................................................................... 1 General......................................................................................... 33 Functional Block Diagram .............................................................. 1 Receiver........................................................................................ 33 General Description ......................................................................... 1 Transmitter .................................................................................. 33 Revision History ............................................................................... 2 Clock Input Options .................................................................. 33 Specifications..................................................................................... 3 Synthesizers ................................................................................. 34 Current Consumption—VDD_Interface .................................. 8 Digital Data Interface................................................................. 34 Current Consumption—VDDD1P3_DIG and VDDAx (Combination of all 1.3 V Supplies)......................................... 10 Enable State Machine ................................................................. 34 Absolute Maximum Ratings ..................................................... 15 Control Pins ................................................................................ 35 Reflow Profile .............................................................................. 15 GPO Pins (GPO_3 to GPO_0) ................................................. 35 Thermal Resistance .................................................................... 15 Auxiliary Converters .................................................................. 35 ESD Caution ................................................................................ 15 Powering the AD9361................................................................ 35 Pin Configuration and Function Descriptions ........................... 16 Packaging and Ordering Information ......................................... 36 Typical Performance Characteristics ........................................... 20 Outline Dimensions ................................................................... 36 800 MHz Frequency Band......................................................... 20 Ordering Guide .......................................................................... 36 SPI Interface ................................................................................ 35 2.4 GHz Frequency Band .......................................................... 25 5.5 GHz Frequency Band .......................................................... 29 REVISION HISTORY 11/13—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 36 9/13—Revision C: Initial Version Rev. D | Page 2 of 36 Data Sheet AD9361 SPECIFICATIONS Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins = 1.3 V, TA = 25°C, unless otherwise noted. Table 1. Parameter 1 RECEIVERS, GENERAL Center Frequency Gain Minimum Maximum Gain Step Received Signal Strength Indicator Range Accuracy RECEIVERS, 800 MHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input S11 RX1 to RX2 Isolation RX1A to RX2A, RX1C to RX2C RX1B to RX2B RX2 to RX1 Isolation RX2A to RX1A, RX2C to RX1C RX2B to RX1B RECEIVERS, 2.4 GHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input S11 RX1 to RX2 Isolation RX1A to RX2A, RX1C to RX2C RX1B to RX2B RX2 to RX1 Isolation RX2A to RX1A, RX2C to RX1C RX2B to RX1B Symbol Min Typ 70 Max Unit 6000 MHz Test Conditions/ Comments 0 74.5 73.0 72.0 dB dB dB dB 65.5 1 dB dB 100 ±2 dB dB NF IIP3 2 −18 dB dBm Maximum RX gain Maximum RX gain IIP2 40 dBm Maximum RX gain −122 dBm At RX front-end input 0.2 0.2 −42 −10 % Degrees dB dB 70 55 dB dB 70 55 dB dB NF IIP3 3 −14 dB dBm Maximum RX gain Maximum RX gain IIP2 45 dBm Maximum RX gain −110 dBm At receiver front-end input 0.2 0.2 −42 −10 % Degrees dB dB 65 50 dB dB 65 50 dB dB At 800 MHz At 2300 MHz (RX1A, RX2A) At 2300 MHz (RX1B, RX1C, RX2B, RX2C) At 5500 MHz (RX1A, RX2A) RSSI Rev. D | Page 3 of 36 19.2 MHz reference clock 40 MHz reference clock AD9361 Parameter 1 RECEIVERS, 5.5 GHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input S11 RX1A to RX2A Isolation RX2A to RX1A Isolation TRANSMITTERS—GENERAL Center Frequency Power Control Range Power Control Resolution TRANSMITTERS, 800 MHz Output S22 Maximum Output Power Modulation Accuracy (EVM) Third-Order Output Intermodulation Intercept Point Carrier Leakage Noise Floor Isolation TX1 to TX2 TX2 to TX1 TRANSMITTERS, 2.4 GHz Output S22 Maximum Output Power Modulation Accuracy (EVM) Third-Order Output Intermodulation Intercept Point Carrier Leakage Data Sheet Symbol Noise Floor Isolation TX1 to TX2 TX2 to TX1 Typ Max Unit Test Conditions/ Comments NF IIP3 3.8 −17 dB dBm Maximum RX gain Maximum RX gain IIP2 42 dBm Maximum RX gain −95 dBm At RX front-end input 0.2 0.2 −37 % Degrees dB −10 52 52 dB dB dB 70 OIP3 OIP3 Noise Floor Isolation TX1 to TX2 TX2 to TX1 TRANSMITTERS, 5.5 GHz Output S22 Maximum Output Power Modulation Accuracy (EVM) Third-Order Output Intermodulation Intercept Point Carrier Leakage Min OIP3 6000 40 MHz reference clock (doubled internally for RF synthesizer) 90 0.25 MHz dB dB −10 8 −40 23 dB dBm dB dBm 1 MHz tone into 50 Ω load 19.2 MHz reference clock −50 −32 −157 dBc dBc dBm/Hz 0 dB attenuation 40 dB attenuation 90 MHz offset 50 50 dB dB −10 7.5 −40 19 dB dBm dB dBm 1 MHz tone into 50 Ω load 40 MHz reference clock −50 −32 −156 dBc dBc dBm/Hz 0 dB attenuation 40 dB attenuation 90 MHz offset 50 50 dB dB −10 6.5 −36 dB dBm dB 17 dBm −50 −30 −151.5 dBc dBc dBm/Hz 50 50 dB dB Rev. D | Page 4 of 36 7 MHz tone into 50 Ω load 40 MHz reference clock (doubled internally for RF synthesizer) 0 dB attenuation 40 dB attenuation 90 MHz offset Data Sheet Parameter 1 TX MONITOR INPUTS (TX_MON1, TX_MON2) Maximum Input Level Dynamic Range Accuracy LO SYNTHESIZER LO Frequency Step AD9361 Symbol Min Typ Max Unit Test Conditions/ Comments 4 66 1 dBm dB dB 2.4 Hz 2.4 GHz, 40 MHz reference clock 0.13 ° rms 2.4 GHz 0.37 ° rms 5.5 GHz 0.59 ° rms 100 Hz to 100 MHz, 30.72 MHz reference clock (doubled internally for RF synthesizer) 100 Hz to 100 MHz, 40 MHz reference clock 100 Hz to 100 MHz, 40 MHz reference clock (doubled internally for RF synthesizer) REF_CLK is either the input to the XTALP/XTALN pins or a line directly to the XTALN pin Integrated Phase Noise 800 MHz REFERENCE CLOCK (REF_CLK) Input Frequency Range 19 10 50 80 Signal Level AUXILIARY CONVERTERS ADC Resolution Input Voltage Minimum Maximum DAC Resolution Output Voltage Minimum Maximum Output Current DIGITAL SPECIFICATIONS (CMOS) Logic Inputs Input Voltage High Low Input Current High Low Logic Outputs Output Voltage High Low DIGITAL SPECIFICATIONS (LVDS) Logic Inputs Input Voltage Range Input Differential Voltage Threshold Receiver Differential Input Impedance 1.3 MHz MHz V p-p 12 Bits 0.05 VDDA1P3_BB − 0.05 V V 10 Bits 0.5 VDD_GPO − 0.3 10 V V mA VDD_INTERFACE × 0.8 0 VDD_INTERFACE VDD_INTERFACE × 0.2 V V −10 −10 +10 +10 μA μA VDD_INTERFACE × 0.2 V V 825 1575 mV −100 +100 mV VDD_INTERFACE × 0.8 100 Rev. D | Page 5 of 36 Ω Crystal input External oscillator AC-coupled external oscillator Each differential input in the pair AD9361 Parameter 1 Logic Outputs Output Voltage High Low Output Differential Voltage Output Offset Voltage GENERAL-PURPOSE OUTPUTS Output Voltage High Low Output Current SPI TIMING SPI_CLK Period Pulse Width SPI_ENB Setup to First SPI_CLK Rising Edge Last SPI_CLK Falling Edge to SPI_ENB Hold SPI_DI Data Input Setup to SPI_CLK Data Input Hold to SPI_CLK SPI_CLK Rising Edge to Output Data Delay 4-Wire Mode 3-Wire Mode Bus Turnaround Time, Read Data Sheet Symbol Min Typ Max Unit 1375 mV mV mV 1025 150 1200 Test Conditions/ Comments Programmable in 75 mV steps mV VDD_GPO × 0.8 VDD_GPO × 0.2 10 V V mA VDD_INTERFACE = 1.8 V tCP tMP tSC 20 9 1 ns ns ns tHC 0 ns tS tH 2 1 ns ns tCO tCO tHZM 3 3 tH 8 8 tCO (max) ns ns ns Bus Turnaround Time, Read tHZS 0 tCO (max) ns DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 1.8 V DATA_CLK Clock Period DATA_CLK and FB_CLK Pulse Width TX Data tCP tMP 16.276 45% of tCP 55% of tCP ns ns After BBP drives the last address bit After AD9361 drives the last data bit 61.44 MHz TX_FRAME, P0_D, and P1_D Setup to FB_CLK Hold to FB_CLK DATA_CLK to Data Bus Output Delay DATA_CLK to RX_FRAME Delay Pulse Width ENABLE TXNRX tSTX tHTX tDDRX 1 0 0 1.5 ns ns ns tDDDV 0 1.0 ns tENPW tTXNRXPW tCP tCP ns ns TXNRX Setup to ENABLE Bus Turnaround Time Before RX After RX Capacitive Load Capacitive Input tTXNRXSU 0 ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF 3 3 Rev. D | Page 6 of 36 FDD independent ENSM mode TDD ENSM mode TDD mode TDD mode Data Sheet Parameter 1 DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 2.5 V DATA_CLK Clock Period DATA_CLK and FB_CLK Pulse Width TX Data Setup to FB_CLK Hold to FB_CLK DATA_CLK to Data Bus Output Delay DATA_CLK to RX_FRAME Delay Pulse Width ENABLE TXNRX TXNRX Setup to ENABLE Bus Turnaround Time Before RX After RX Capacitive Load Capacitive Input DIGITAL DATA TIMING (LVDS) DATA_CLK Clock Period DATA_CLK and FB_CLK Pulse Width TX Data Setup to FB_CLK Hold to FB_CLK DATA_CLK to Data Bus Output Delay DATA_CLK to RX_FRAME Delay Pulse Width ENABLE TXNRX TXNRX Setup to ENABLE Bus Turnaround Time Before RX After RX Capacitive Load Capacitive Input SUPPLY CHARACTERISTICS 1.3 V Main Supply Voltage VDD_INTERFACE Supply Nominal Settings CMOS LVDS VDD_INTERFACE Tolerance VDD_GPO Supply Nominal Setting VDD_GPO Tolerance Current Consumption VDDx, Sleep Mode VDD_GPO 1 AD9361 Symbol Min tCP tMP 16.276 45% of tCP Typ Max Unit 55% of tCP ns ns Test Conditions/ Comments 61.44 MHz TX_FRAME, P0_D, and P1_D tSTX tHTX tDDRX 1 0 0 1.2 ns ns ns tDDDV 0 1.0 ns tENPW tTXNRXPW tCP tCP ns ns tTXNRXSU 0 ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF TDD mode TDD mode ns ns 245.76 MHz 55% of tCP 3 3 tCP tMP 4.069 45% of tCP tSTX tHTX tDDRX 1 0 0.25 1.25 ns ns ns tDDDV 0.25 1.25 ns tENPW tTXNRXPW tCP tCP ns ns tTXNRXSU 0 ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF FDD independent ENSM mode TDD ENSM mode TX_FRAME and TX_D 3 3 1.267 1.3 1.33 V 1.2 1.8 −5 2.5 2.5 +5 V V % 1.3 3.3 V −5 +5 % 180 50 μA μA FDD independent ENSM mode TDD ENSM mode Tolerance is applicable to any voltage setting When unused, must be set to 1.3 V Tolerance is applicable to any voltage setting Sum of all input currents No load When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Rev. D | Page 7 of 36 AD9361 Data Sheet CURRENT CONSUMPTION—VDD_INTERFACE Table 2. VDD_INTERFACE = 1.2 V Parameter SLEEP MODE 1RX, 1TX, DDR LTE10 Single Port Dual Port LTE20 Dual Port 2RX, 2TX, DDR LTE3 Dual Port LTE10 Single Port Dual Port LTE20 Dual Port GSM Dual Port WiMAX 8.75 Dual Port WiMAX 10 Single Port TDD RX TDD TX FDD WiMAX 20 Dual Port FDD Min Typ 45 Max Unit µA Test Conditions/Comments Power applied, device disabled 2.9 2.7 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 5.2 mA 30.72 MHz data clock, CMOS 1.3 mA 7.68 MHz data clock, CMOS 4.6 5.0 mA mA 61.44 MHz data clock, CMOS 30.72 MHz data clock, CMOS 8.2 mA 61.44 MHz data clock, CMOS 0.2 mA 1.08 MHz data clock, CMOS 3.3 mA 20 MHz data clock, CMOS 0.5 3.6 3.8 mA mA mA 22.4 MHz data clock, CMOS 22.4 MHz data clock, CMOS 44.8 MHz data clock, CMOS 6.7 mA 44.8 MHz data clock, CMOS Table 3. VDD_INTERFACE = 1.8 V Parameter SLEEP MODE 1RX, 1TX, DDR LTE10 Single Port Dual Port LTE20 Dual Port 2RX, 2TX, DDR LTE3 Dual Port LTE10 Single Port Dual Port LTE20 Dual Port GSM Dual Port WiMAX 8.75 Dual Port Min Typ 84 Max Unit μA Test Conditions/Comments Power applied, device disabled 4.5 4.1 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 8.0 mA 30.72 MHz data clock, CMOS 2.0 mA 7.68 MHz data clock, CMOS 8.0 7.5 mA mA 61.44 MHz data clock, CMOS 30.72 MHz data clock, CMOS 14.0 mA 61.44 MHz data clock, CMOS 0.3 mA 1.08 MHz data clock, CMOS 5.0 mA 20 MHz data clock, CMOS Rev. D | Page 8 of 36 Data Sheet Parameter WiMAX 10 Single Port TDD RX TDD TX FDD WiMAX 20 Dual Port FDD P-P56 75 mV Differential Output 300 mV Differential Output 450 mV Differential Output AD9361 Min Typ Max Unit Test Conditions/Comments 0.7 5.6 6.0 mA mA mA 22.4 MHz data clock, CMOS 22.4 MHz data clock, CMOS 44.8 MHz data clock, CMOS 10.7 mA 44.8 MHz data clock, CMOS 14.0 35.0 47.0 mA mA mA 240 MHz data clock, LVDS 240 MHz data clock, LVDS 240 MHz data clock, LVDS Unit μA Test Conditions/Comments Power applied, device disabled 6.5 6.0 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 11.5 mA 30.72 MHz data clock, CMOS 3.0 mA 7.68 MHz data clock, CMOS 11.5 10.0 mA mA 61.44 MHz data clock, CMOS 30.72 MHz data clock, CMOS 20.0 mA 61.44 MHz data clock, CMOS 0.5 mA 1.08 MHz data clock, CMOS 7.3 mA 20 MHz data clock, CMOS 1.3 8.0 8.7 mA mA mA 22.4 MHz data clock, CMOS 22.4 MHz data clock, CMOS 44.8 MHz data clock, CMOS 15.3 mA 44.8 MHz data clock, CMOS 26.0 45.0 58.0 mA mA mA 240 MHz data clock, LVDS 240 MHz data clock, LVDS 240 MHz data clock, LVDS Table 4. VDD_INTERFACE = 2.5 V Parameter SLEEP MODE 1RX, 1TX, DDR LTE10 Single Port Dual Port LTE20 Dual Port 2RX, 2TX, DDR LTE3 Dual Port LTE10 Single Port Dual Port LTE20 Dual Port GSM Dual Port WiMAX 8.75 Dual Port WiMAX 10 Single Port TDD RX TDD TX FDD WiMAX 20 Dual Port FDD P-P56 75 mV Differential Output 300 mV Differential Output 450 mV Differential Output Min Typ 150 Max Rev. D | Page 9 of 36 AD9361 Data Sheet CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) Table 5. 800 MHz, TDD Mode Parameter 1RX 5 MHz Bandwidth 10 MHz Bandwidth 20 MHz Bandwidth 2RX 5 MHz Bandwidth 10 MHz Bandwidth 20 MHz Bandwidth 1TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm 2TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm Min Typ Max Unit Test Conditions/Comments 180 210 260 mA mA mA Continuous RX Continuous RX Continuous RX 265 315 405 mA mA mA Continuous RX Continuous RX Continuous RX 340 190 mA mA Continuous TX Continuous TX 360 220 mA mA Continuous TX Continuous TX 400 250 mA mA Continuous TX Continuous TX 550 260 mA mA Continuous TX Continuous TX 600 310 mA mA Continuous TX Continuous TX 660 370 mA mA Continuous TX Continuous TX Rev. D | Page 10 of 36 Data Sheet AD9361 Table 6. TDD Mode, 2.4 GHz Parameter 1RX 5 MHz Bandwidth 10 MHz Bandwidth 20 MHz Bandwidth 2RX 5 MHz Bandwidth 10 MHz Bandwidth 20 MHz Bandwidth 1TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm 2TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm Min Typ Max Unit Test Conditions/Comments 175 200 240 mA mA mA Continuous RX Continuous RX Continuous RX 260 305 390 mA mA mA Continuous RX Continuous RX Continuous RX 350 160 mA mA Continuous TX Continuous TX 380 220 mA mA Continuous TX Continuous TX 410 260 mA mA Continuous TX Continuous TX 580 280 mA mA Continuous TX Continuous TX 635 330 mA mA Continuous TX Continuous TX 690 390 mA mA Continuous TX Continuous TX Unit Test Conditions/Comments 175 275 mA mA Continuous RX Continuous RX 270 445 mA mA Continuous RX Continuous RX 400 240 mA mA Continuous TX Continuous TX 490 385 mA mA Continuous TX Continuous TX 650 335 mA mA Continuous TX Continuous TX 820 500 mA mA Continuous TX Continuous TX Table 7. TDD Mode, 5.5 GHz Parameter 1RX 5 MHz Bandwidth 40 MHz Bandwidth 2RX 5 MHz Bandwidth 40 MHz Bandwidth 1TX 5 MHz Bandwidth 7 dBm −27 dBm 40 MHz Bandwidth 7 dBm −27 dBm 2TX 5 MHz Bandwidth 7 dBm −27 dBm 40 MHz Bandwidth 7 dBm −27 dBm Min Typ Max Rev. D | Page 11 of 36 AD9361 Data Sheet Table 8. FDD Mode, 800 MHz Parameter 1RX, 1TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm 2RX, 1TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm 1RX, 2TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm 2RX, 2TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm Min Typ Max Unit 490 345 mA mA 540 395 mA mA 615 470 mA mA 555 410 mA mA 625 480 mA mA 740 600 mA mA 685 395 mA mA 755 465 mA mA 850 570 mA mA 790 495 mA mA 885 590 mA mA 1020 730 mA mA Rev. D | Page 12 of 36 Test Conditions/Comments Data Sheet AD9361 Table 9. FDD Mode, 2.4 GHz Parameter 1RX, 1TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm 2RX, 1TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm 1RX, 2TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27dBm 20 MHz Bandwidth 7 dBm −27 dBm 2RX, 2TX 5 MHz Bandwidth 7 dBm −27 dBm 10 MHz Bandwidth 7 dBm −27 dBm 20 MHz Bandwidth 7 dBm −27 dBm Min Typ Max Unit 500 350 mA mA 540 390 mA mA 620 475 mA mA 590 435 mA mA 660 510 mA 770 620 mA mA mA 730 425 mA mA 800 500 mA mA 900 600 mA mA mA 820 515 mA 900 595 mA mA 1050 740 mA mA Rev. D | Page 13 of 36 Test Conditions/Comments AD9361 Data Sheet Table 10. FDD Mode, 5.5 GHz Parameter 1RX, 1TX 5 MHz Bandwidth 7 dBm −27 dBm 2RX, 1TX 5 MHz Bandwidth 7 dBm −27 dBm 1RX, 2TX 5 MHz Bandwidth 7 dBm −27 dBm 2RX, 2TX 5 MHz Bandwidth 7 dBm −27 dBm Min Typ Max Unit 550 385 mA mA 645 480 mA mA 805 480 mA mA 895 575 mA mA Rev. D | Page 14 of 36 Test Conditions/Comments Data Sheet AD9361 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 11. Parameter VDDx to VSSx VDD_INTERFACE to VSSx VDD_GPO to VSSx Logic Inputs and Outputs to VSSx Input Current to Any Pin Except Supplies RF Inputs (Peak Power) TX Monitor Input Power (Peak Power) Package Power Dissipation Maximum Junction Temperature (TJMAX) Operating Temperature Range Storage Temperature Range Rating −0.3 V to +1.4 V −0.3 V to +3.0 V −0.3 V to +3.9 V −0.3 V to VDD_INTERFACE + 0.3 V ±10 mA 2.5 dBm 9 dBm θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 12. Thermal Resistance Package Type 144-Ball CSP_BGA Airflow Velocity (m/sec) 0 1.0 2.5 θJA1, 2 32.3 29.6 27.8 θJC1, 3 9.6 θJB1, 4 20.2 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-STD 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 1 2 (TJMAX − TA)/θJA 110°C ESD CAUTION −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. REFLOW PROFILE The AD9361 reflow profile is in accordance with the JEDEC JESD20 criteria for Pb-free devices. The maximum reflow temperature is 260°C. Rev. D | Page 15 of 36 ΨJT1, 2 0.27 0.43 0.57 Unit °C/W °C/W °C/W AD9361 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 A RX2A_N RX2A_P NC VSSA TX_MON2 VSSA TX2A_N TX2A_P TX2B_N TX2B_P VDDA1P1_ TX_VCO TX_EXT_ LO_IN B VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO VDDA1P3_ TX_LO VDDA1P3_ TX_VCO_ LDO TX_VCO_ LDO_OUT VSSA AUXDAC2 TEST/ ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA CTRL_IN3 CTRL_IN2 P0_D9/ TX_D4_P P0_D7/ TX_D3_P P0_D5/ TX_D2_P P0_D3/ TX_D1_P P0_D1/ TX_D0_P VSSD P0_D11/ TX_D5_P P0_D8/ TX_D4_N P0_D6/ TX_D3_N P0_D4/ TX_D2_N P0_D2/ TX_D1_N P0_D0/ TX_D0_N VSSD P0_D10/ TX_D5_N VSSD FB_CLK_P VSSD VDDD1P3_ DIG RX_ FRAME_N RX_ FRAME_P TX_ FRAME_P FB_CLK_N DATA_ CLK_P VSSD TX_ FRAME_N VSSD DATA_ CLK_N VDD_ INTERFACE C RX2C_P VSSA D RX2C_N VDDA1P3_ RX_RF VDDA1P3_ CTRL_OUT0 RX_TX E RX2B_P VDDA1P3_ RX_LO VDDA1P3_ TX_LO_ CTRL_OUT1 CTRL_OUT2 CTRL_OUT3 BUFFER F RX2B_N VDDA1P3_ RX_VCO_ LDO VSSA G RX_EXT_ LO_IN RX_VCO_ LDO_OUT VDDA1P1_ RX_VCO CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 CTRL_OUT7 EN_AGC ENABLE RX1B_P VSSA VSSA TXNRX SYNC_IN VSSA VSSD J RX1B_N VSSA VDDA1P3_ RX_SYNTH SPI_DI SPI_CLK CLK_OUT P1_D10/ RX_D5_N P1_D9/ RX_D4_P P1_D7/ RX_D3_P P1_D5/ RX_D2_P P1_D3/ RX_D1_P P1_D1/ RX_D0_P K RX1C_P VSSA VDDA1P3_ TX_SYNTH VDDA1P3_ BB RESETB SPI_ENB P1_D8/ RX_D4_N P1_D6/ RX_D3_N P1_D4/ RX_D2_N P1_D2/ RX_D1_N P1_D0/ RX_D0_N VSSD L RX1C_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA M RX1A_P RX1A_N NC VSSA TX_MON1 VSSA TX1A_P TX1A_N TX1B_P TX1B_N XTALP XTALN ANALOG I/O DIGITAL I/O NO CONNECT 10453-002 H P1_D11/ RX_D5_P DC POWER GROUND Figure 2. Pin Configuration, Top View Table 13. Pin Function Descriptions Pin No. A1, A2 Type 1 I Mnemonic RX2A_N, RX2A_P Description Receive Channel 2 Differential Input A. Alternatively, each pin can be used as a single-ended input or combined to make a differential pair. Tie unused pins to ground. No Connect. Do not connect to these pins. Analog Ground. Tie these pins directly to the VSSD digital ground on the printed circuit board (one ground plane). A3, M3 A4, A6, B1, B2, B12, C2, C7 to C12, F3, H2, H3, H6, J2, K2, L2, L3, L7 to L12, M4, M6 A5 A7, A8 A9, A10 NC I NC VSSA I O O TX_MON2 TX2A_N, TX2A_P TX2B_N, TX2B_P Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground. Transmit Channel 2 Differential Output A. Tie unused pins to 1.3 V. Transmit Channel 2 Differential Output B. Tie unused pins to 1.3 V. A11 A12 B3 B4 to B7 B8 I I O O I VDDA1P1_TX_VCO TX_EXT_LO_IN AUXDAC1 GPO_3 to GPO_0 VDD_GPO B9 B10 B11 I I O VDDA1P3_TX_LO VDDA1P3_TX_VCO_LDO TX_VCO_LDO_OUT C1, D1 I RX2C_P, RX2C_N Transmit VCO Supply Input. Connect to B11. External Transmit LO Input. If this pin is unused, tie it to ground. Auxiliary DAC 1 Output. 3.3 V Capable General-Purpose Outputs. 2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. When the VDD_GPO supply is not used, this supply must be set to 1.3 V. Transmit LO 1.3 V Supply Input. Transmit VCO LDO 1.3 V Supply Input. Connect to B9. Transmit VCO LDO Output. Connect to A11 and a 1 µF bypass capacitor in series with a 1 Ω resistor to ground. Receive Channel 2 Differential Input C. Each pin can be used as a single-ended input or combined to make a differential pair. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground. Rev. D | Page 16 of 36 Data Sheet AD9361 Pin No. C3 C4 C5, C6, D5, D6 D2 D3 D4, E4 to E6, F4 to F6, G4 Type 1 O I I I I O D7 I/O Mnemonic AUXDAC2 TEST/ENABLE CTRL_IN0 to CTRL_IN3 VDDA1P3_RX_RF VDDA1P3_RX_TX CTRL_OUT0, CTRL_OUT1 to CTRL_OUT3, CTRL_OUT6 to CTRL_OUT4, CTRL_OUT7 P0_D9/TX_D4_P D8 I/O P0_D7/TX_D3_P D9 I/O P0_D5/TX_D2_P D10 I/O P0_D3/TX_D1_P D11 I/O P0_D1/TX_D0_P D12, F7, F9, F11, G12, H7, H10, K12 E1, F1 I VSSD I RX2B_P, RX2B_N E2 E3 E7 I I I/O VDDA1P3_RX_LO VDDA1P3_TX_LO_BUFFER P0_D11/TX_D5_P E8 I/O P0_D8/TX_D4_N E9 I/O P0_D6/TX_D3_N E10 I/O P0_D4/TX_D2_N E11 I/O P0_D2/TX_D1_N E12 I/O P0_D0/TX_D0_N Description Auxiliary DAC 2 Output. Test Input. Ground this pin for normal operation. Control Inputs. Used for manual RX gain and TX attenuation control. Receiver 1.3 V Supply Input. Connect to D3. 1.3 V Supply Input. Control Outputs. These pins are multipurpose outputs that have programmable functionality. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D4_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D3_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D2_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D1_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D0_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Ground. Tie these pins directly to the VSSA analog ground on the printed circuit board (one ground plane). Receive Channel 2 Differential Input B. Each pin can be used as a single-ended input or combined to make a differential pair. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground. Receive LO 1.3 V Supply Input. 1.3 V Supply Input. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D11, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D5_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D4_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D3_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D2_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D1_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D0_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Rev. D | Page 17 of 36 AD9361 Data Sheet Pin No. F2 F8 Type 1 I I/O Mnemonic VDDA1P3_RX_VCO_LDO P0_D10/TX_D5_N F10, G10 I FB_CLK_P, FB_CLK_N F12 G1 G2 I I O VDDD1P3_DIG RX_EXT_LO_IN RX_VCO_LDO_OUT G3 G5 G6 G7, G8 I I I O VDDA1P1_RX_VCO EN_AGC ENABLE RX_FRAME_N, RX_FRAME_P G9, H9 I TX_FRAME_P, TX_FRAME_N G11, H11 O DATA_CLK_P, DATA_CLK_N H1, J1 I RX1B_P, RX1B_N H4 I TXNRX H5 I SYNC_IN H8 I/O P1_D11/RX_D5_P H12 J3 J4 J5 J6 I I I I O VDD_INTERFACE VDDA1P3_RX_SYNTH SPI_DI SPI_CLK CLK_OUT J7 I/O P1_D10/RX_D5_N J8 I/O P1_D9/RX_D4_P J9 I/O P1_D7/RX_D3_P J10 I/O P1_D5/RX_D2_P Description Receive VCO LDO 1.3 V Supply Input. Connect to E2. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D10, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D5_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination. Feedback Clock. These pins receive the FB_CLK signal that clocks in TX data. In CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground. 1.3 V Digital Supply Input. External Receive LO Input. If this pin is unused, tie it to ground. Receive VCO LDO Output. Connect this pin directly to G3 and a 1 µF bypass capacitor in series with a 1 Ω resistor to ground. Receive VCO Supply Input. Connect this pin directly to G2 only. Manual Control Input for Automatic Gain Control (AGC). Control Input. This pin moves the device through various operational states. Receive Digital Data Framing Output Signal. These pins transmit the RX_FRAME signal that indicates whether the RX output data is valid. In CMOS mode, use RX_FRAME_P as the output and leave RX_FRAME_N unconnected. Transmit Digital Data Framing Input Signal. These pins receive the TX_FRAME signal that indicates when TX data is valid. In CMOS mode, use TX_FRAME_P as the input and tie TX_FRAME_N to ground. Receive Data Clock Output. These pins transmit the DATA_CLK signal that is used by the BBP to clock RX data. In CMOS mode, use DATA_CLK_P as the output and leave DATA_CLK_N unconnected. Receive Channel 1 Differential Input B. Alternatively, each pin can be used as a single-ended input. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground. Enable State Machine Control Signal. This pin controls the data port bus direction. Logic low selects the RX direction, and logic high selects the TX direction. Input to Synchronize Digital Clocks Between Multiple AD9361 Devices. If this pin is unused, tied it to ground. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D11, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D5_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. 1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode). 1.3 V Supply Input. SPI Serial Data Input. SPI Clock Input. Output Clock. This pin can be configured to output either a buffered version of the external input clock, the DCXO, or a divided-down version of the internal ADC_CLK. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D10, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D5_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D4_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D3_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D2_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Rev. D | Page 18 of 36 Data Sheet AD9361 Pin No. J11 Type 1 I/O Mnemonic P1_D3/RX_D1_P J12 I/O P1_D1/RX_D0_P K1, L1 I RX1C_P, RX1C_N K3 K4 K5 K6 K7 I I I I I/O VDDA1P3_TX_SYNTH VDDA1P3_BB RESETB SPI_ENB P1_D8/RX_D4_N K8 I/O P1_D6/RX_D3_N K9 I/O P1_D4/RX_D2_N K10 I/O P1_D2/RX_D1_N K11 I/O P1_D0/RX_D0_N L4 I RBIAS L5 L6 M1, M2 I O I AUXADC SPI_DO RX1A_P, RX1A_N M5 M7, M8 M9, M10 M11, M12 I O O I TX_MON1 TX1A_P, TX1A_N TX1B_P, TX1B_N XTALP, XTALN 1 Description Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D1_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D0_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Receive Channel 1 Differential Input C. Alternatively, each pin can be used as a single-ended input. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground. 1.3 V Supply Input. 1.3 V Supply Input. Asynchronous Reset. Logic low resets the device. SPI Enable Input. Set this pin to logic low to enable the SPI bus. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D4_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D3_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D2_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D1_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D0_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination. Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor to ground. Auxiliary ADC Input. If this pin is unused, tie it to ground. SPI Serial Data Output in 4-Wire Mode, or High-Z in 3-Wire Mode. Receive Channel 1 Differential Input A. Alternatively, each pin can be used as a single-ended input. Tie unused pins to ground. Transmit Channel 1 Power Monitor Input. When this pin is unused, tie it to ground. Transmit Channel 1 Differential Output A. Tie unused pins to 1.3 V. Transmit Channel 1 Differential Output B. Tie unused pins to 1.3 V. Reference Frequency Crystal Connections. When a crystal is used, connect it between these two pins. When an external clock source is used, connect it to XTALN and leave XTALP unconnected. I is input, O is output, I/O is input/output, or NC is not connected. Rev. D | Page 19 of 36 AD9361 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 0 4.0 –40°C +25°C +85°C RX EVM (dB) –15 2.5 2.0 1.5 –25 –35 0.5 –40 750 800 850 900 RF FREQUENCY (MHz) –45 –75 5 –60 –65 –55 –50 –45 –40 –35 –30 –25 RX INPUT POWER (dBm) Figure 6. RX EVM vs. RX Input Power, 64 QAM LTE 10 MHz Mode, 19.2 MHz REF_CLK 0 –40°C +25°C +85°C 4 –70 10453-006 –30 Figure 3. RX Noise Figure vs. RF Frequency –5 –40°C +25°C +85°C –10 3 –15 2 RX EVM (dB) 1 0 –20 –25 –30 –1 –35 –2 –80 –70 –60 –50 –40 –30 –20 –10 RX INPUT POWER (dBm) 0 –5 1 –10 RX EVM (dB) 2 0 –20 –2 –25 –70 –60 –50 –40 –30 –20 –10 RX INPUT POWER (dBm) Figure 5. RSSI Error vs. RX Input Power, Edge Modulation (Referenced to −50 dBm Input Power at 800 MHz) –30 –72 10453-005 –80 –60 –50 –30 –40 –20 –10 –40°C +25°C +85°C –15 –1 –90 –70 RX INPUT POWER (dBm) –40°C +25°C +85°C –3 –110 –100 –80 Figure 7. RX EVM vs. RX Input Power, GSM Mode, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer) Figure 4. RSSI Error vs. RX Input Power, LTE 10 MHz Modulation (Referenced to −50 dBm Input Power at 800 MHz) 3 –45 –90 10453-004 –90 10453-007 –40 –3 –100 –68 –64 –60 –56 –52 –48 –44 –40 INTERFERER POWER LEVEL (dBm) –36 –32 10453-008 RSSI ERROR (dB) –20 1.0 0 700 RSSI ERROR (dB) –40°C +25°C +85°C –10 3.0 10453-003 RX NOISE FIGURE (dB) 3.5 –5 Figure 8. RX EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = −82 dBm, 5 MHz OFDM Blocker at 7.5 MHz Offset Rev. D | Page 20 of 36 Data Sheet 0 AD9361 20 –40°C +25°C +85°C 15 10 –4 IIP3 (dBm) RX EVM (dB) 5 –8 0 –5 –40°C +25°C +85°C –10 –12 –15 –54 –52 –50 –48 –46 –44 –42 –40 –38 –25 10453-009 –16 –56 –36 INTERFERER POWER LEVEL (dBm) 20 14 52 44 RX GAIN INDEX 60 68 76 100 90 –40°C +25°C +85°C 80 10 70 IIP2 (dBm) RX NOISE FIGURE (dB) 36 Figure 12. Third-Order Input Intercept Point (IIP3) vs. RX Gain Index, f1 = 1.45 MHz, f2 = 2.89 MHz, GSM Mode Figure 9. RX EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = −90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset 12 28 10453-012 –20 8 6 –40°C +25°C +85°C 60 50 40 30 4 20 2 –39 –35 –31 –27 –23 INTERFERER POWER LEVEL (dBm) 0 –100 RX LO LEAKAGE (dBm) 52 60 68 76 –40°C +25°C +85°C 74 72 70 –110 –115 –120 –125 750 800 RX LO FREQUENCY (MHz) 850 900 10453-011 68 Figure 11. RX Gain vs. RX LO Frequency, Gain Index = 76 (Maximum Setting) Rev. D | Page 21 of 36 –130 700 750 800 850 900 RX LO FREQUENCY (MHz) Figure 14. RX Local Oscillator (LO) Leakage vs. RX LO Frequency 10453-014 RX GAIN (dB) 44 –105 76 66 700 36 Figure 13. Second-Order Input Intercept Point (IIP2) vs. RX Gain Index, f1 = 2.00 MHz, f2 = 2.01 MHz, GSM Mode –40°C +25°C +85°C 78 28 RX GAIN INDEX Figure 10. RX Noise Figure vs. Interferer Power Level, Edge Signal of Interest with PIN = −90 dBm, CW Blocker at 3 MHz Offset, Gain Index = 64 80 20 10453-013 –43 10453-010 0 –47 10 AD9361 Data Sheet –20 –40 –60 –80 –100 2000 6000 4000 10000 8000 12000 FREQUENCY (MHz) Figure 15. RX Emission at LNA Input, DC to 12 GHz, fLO_RX = 800 MHz, LTE 10 MHz, fLO_TX = 860 MHz 10 5 0 –5 15 FREQUENCY OFFSET (MHz) Figure 18. TX Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, LTE 10 MHz Downlink (Digital Attenuation Variations Shown) Figure 16. TX Output Power vs. TX LO Frequency, Attenuation Setting = 0 dB, Single Tone Output –80 1.6 1.4 1.2 1.0 0.8 0.6 –100 FREQUENCY OFFSET (MHz) 10453-019 TX LO FREQUENCY (MHz) –60 0.4 900 –40 0 850 –20 0.2 800 ATT 0dB ATT 3dB ATT 6dB 0 –0.2 750 10453-016 6.5 Figure 19. TX Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 3 MHz Range 20 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 10 20 30 40 50 ATTENUATION SETTING (dB) Figure 17. TX Power Control Linearity Error vs. Attenuation Setting ATT 0dB ATT 3dB ATT 6dB –20 –40 –60 –80 –100 –120 –6 10453-017 –0.4 0 –4 –2 0 2 FREQUENCY OFFSET (MHz) 4 6 10453-020 –40°C +25°C +85°C TRANSMITTER OUTPUT POWER (dBm/30kHz) STEP LINEARITY ERROR (dB) –10 –0.4 7.0 0 –90 –0.6 7.5 –0.5 –80 –0.8 8.0 0.4 –70 –1.0 8.5 0.5 –60 –100 –15 TRANSMITTER OUTPUT POWER (dBm/30kHz) TX OUTPUT POWER (dBm) 9.0 6.0 700 –50 20 –40°C +25°C +85°C 9.5 –40 –1.2 10.0 –30 –1.4 0 –20 –1.6 –120 ATT 0dB ATT 3dB ATT 6dB –10 10453-018 TRANSMITTER OUTPUT POWER (dBm/100kHz) 0 10453-015 POWER AT LNA INPUT (dBm/750kHz) 0 Figure 20. TX Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 12 MHz Range Rev. D | Page 22 of 36 Data Sheet 0.30 –40°C +25°C +85°C INTEGRATED PHASE NOISE (°rms) –25 –35 –40 –50 0 5 10 15 20 25 30 35 40 TX ATTENUATION SETTING (dB) Figure 21. TX EVM vs. TX Attenuation Setting, fLO_TX = 800 MHz, LTE 10 MHz, 64 QAM Modulation, 19.2 MHz REF_CLK 0.10 0.05 –35 TX CARRIER AMPLITUDE (dBc) –40°C +25°C +85°C –30 –35 –40 –45 800 850 900 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 10 20 30 40 50 –70 700 10453-022 0 0.4 0.3 0.2 0 700 750 800 FREQUENCY (MHz) 850 900 10453-023 0.1 Figure 23. Integrated TX LO Phase Noise vs. Frequency, 19.2 MHz REF_CLK 850 900 Figure 25. TX Carrier Rejection vs. Frequency TX SECOND-ORDER HARMONIC DISTORTION (dBc) –40°C +25°C +85°C 800 FREQUENCY (MHz) Figure 22. TX EVM vs. TX Attenuation Setting, fLO_TX = 800 MHz, GSM Modulation, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer) 0.5 750 10453-025 –65 TX ATTENUATION SETTING (dB) INTEGRATED PHASE NOISE (°RMS) 750 Figure 24. Integrated TX LO Phase Noise vs. Frequency, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer) –30 –25 TX EVM (dB) 0.15 FREQUENCY (MHz) –20 –50 0.20 0 700 10453-021 –45 –40°C +25°C +85°C –50 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –55 –60 –65 –70 –75 –80 700 750 800 FREQUENCY (MHz) 850 900 10453-026 TX EVM (dB) –30 0.25 10453-024 –20 AD9361 Figure 26. TX Second-Order Harmonic Distortion (HD2) vs. Frequency Rev. D | Page 23 of 36 Data Sheet –20 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –25 170 ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C 165 TX SNR (dB/Hz) –30 –35 –40 –45 145 750 800 850 900 30 15 10 12 16 20 TX ATTENUATION SETTING (dB) 10453-028 5 8 Figure 28. TX Third-Order Output Intercept Point (OIP3) vs. TX Attenuation Setting 170 –40°C +25°C +85°C 160 155 150 3 6 9 TX ATTENUATION SETTING (dB) 12 15 10453-029 145 0 12 16 20 –35 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 –70 700 750 800 850 900 FREQUENCY (MHz) Figure 31. TX Single Sideband (SSB) Rejection vs. Frequency, 1.5375 MHz Offset 165 140 8 TX ATTENUATION SETTING (dB) TX SINGLE SIDEBAND AMPLITUDE (dBc) 20 4 4 –30 –40°C +25°C +85°C 0 0 Figure 30. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, GSM Signal of Interest with Noise Measured at 20 MHz Offset 25 0 140 Figure 29. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, LTE 10 MHz Signal of Interest with Noise Measured at 90 MHz Offset Rev. D | Page 24 of 36 10453-031 –60 700 10453-030 –55 Figure 27. TX Third-Order Harmonic Distortion (HD3) vs. Frequency TX OIP3 (dBm) –40°C +25°C +85°C 155 150 FREQUENCY (MHz) TX SNR (dB/Hz) 160 –50 10453-027 TX THIRD-ORDER HARMONIC DISTORTION (dBc) AD9361 Data Sheet AD9361 2.4 GHz FREQUENCY BAND 0 4.0 –40°C +25°C +85°C –5 3.0 –10 2.5 RX EVM (dB) RX NOISE FIGURE (dB) 3.5 2.0 1.5 –15 –20 1.0 1900 2000 2100 2200 2300 2400 2500 2600 2700 RF FREQUENCY (MHz) Figure 32. RX Noise Figure vs. RF Frequency 5 4 –30 –72 10453-032 0 1800 –40°C +25°C +85°C –68 –64 –60 –56 –52 –48 –44 –40 –36 –32 –28 INTERFERER POWER LEVEL (dBm) 10453-035 –25 0.5 Figure 35. RX EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest with PIN = −75 dBm, LTE 20 MHz Blocker at 20 MHz Offset 0 –40°C +25°C +85°C –40°C +25°C +85°C –5 –10 2 RX EVM (dB) RSSI ERROR (dB) 3 1 0 –15 –20 –1 –25 –90 –80 –70 –60 –50 –40 –30 –20 –10 RX INPUT POWER (dBm) Figure 33. RSSI Error vs. RX Input Power, Referenced to −50 dBm Input Power at 2.4 GHz 0 –5 –30 –60 10453-033 –3 –100 –55 –50 –45 –40 –35 –30 –25 –20 INTERFERER POWER LEVEL (dBm) 10453-036 –2 Figure 36. RX EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest with PIN = −75 dBm, LTE 20 MHz Blocker at 40 MHz Offset 80 –40°C +25°C +85°C 78 –40°C +25°C +85°C –10 76 RX GAIN (dB) –20 –25 74 72 –30 70 –35 –45 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25 INPUT POWER (dBm) Figure 34. RX EVM vs. Input Power, 64 QAM LTE 20 MHz Mode, 40 MHz REF_CLK 66 1800 1900 2000 2100 2200 2300 2400 RX LO FREQUENCY (MHz) 2500 2600 2700 10453-037 68 –40 10453-034 RX EVM (dB) –15 Figure 37. RX Gain vs. RX LO Frequency, Gain Index = 76 (Maximum Setting) Rev. D | Page 25 of 36 AD9361 15 0 –40°C +25°C +85°C POWER AT LNA INPUT (dBm/750kHz) 20 Data Sheet 10 IIP3 (dBm) 5 0 –5 –10 –15 –20 –40 –60 –80 –100 28 36 44 52 60 76 68 RX GAIN INDEX –120 10453-038 –25 20 6000 4000 8000 10000 12000 Figure 41. RX Emission at LNA Input, DC to 12 GHz, fLO_RX = 2.4 GHz, LTE 20 MHz, fLO_TX = 2.46 GHz 10.0 –40°C +25°C +85°C –40°C +25°C +85°C 9.5 TX OUTPUT POWER (dBm) 70 60 IIP2 (dBm) 2000 FREQUENCY (MHz) Figure 38. Third-Order Input Intercept Point (IIP3) vs. RX Gain Index, f1 = 30 MHz, f2 = 61 MHz 80 0 10453-041 –20 50 40 9.0 8.5 8.0 7.5 7.0 30 36 28 44 60 52 68 76 RX GAIN INDEX Figure 39. Second-Order Input Intercept Point (IIP2) vs. RX Gain Index, f1 = 60 MHz, f2 = 61 MHz –100 6.0 1800 10453-039 20 20 STEP LINEARITY ERROR (dB) –105 2300 2400 2500 2600 2700 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –125 –130 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 RX LO FREQUENCY (MHz) –0.5 0 10 20 30 ATTENUATION SETTING (dB) 40 50 10453-043 –0.4 10453-040 RX LO LEAKAGE (dBm) 2200 –40°C +25°C +85°C 0.4 –120 2100 Figure 42. TX Output Power vs. TX LO Frequency, Attenuation Setting = 0 dB, Single Tone Output 0.5 –115 2000 TX LO FREQUENCY (MHz) –40°C +25°C +85°C –110 1900 10453-042 6.5 Figure 43. TX Power Control Linearity Error vs. Attenuation Setting Figure 40. RX Local Oscillator (LO) Leakage vs. RX LO Frequency Rev. D | Page 26 of 36 Data Sheet –30 ATT 0dB ATT 3dB ATT6dB –35 TX CARRIER AMPLITUDE (dBc) –20 –40 –60 –80 –100 –40 –45 –50 –55 –60 –10 –5 0 5 10 15 20 25 –70 1800 –25 TX EVM (dB) –30 –35 –40 0 5 10 15 20 25 30 35 40 ATTENUATION SETTING (dB) 10453-045 –45 0.5 –40°C +25°C +85°C 0.4 0.3 0.2 0 1800 1900 2000 2100 2200 2300 2400 FREQUENCY (MHz) 2500 2600 2700 2300 2400 2500 2600 2700 –50 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –55 –60 –65 –70 –75 –80 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 Figure 48. TX Second-Order Harmonic Distortion (HD2) vs. Frequency 10453-046 0.1 2200 FREQUENCY (MHz) TX THIRD-ORDER HARMONIC DISTORTION (dBc) Figure 45. TX EVM vs. Transmitter Attenuation Setting, 40 MHz REF_CLK, LTE 20 MHz, 64 QAM Modulation 2100 Figure 47. TX Carrier Rejection vs. Frequency TX SECOND-ORDER HARMONIC DISTORTION (dBc) –40°C +25°C +85°C 2000 FREQUENCY (MHz) Figure 44. TX Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 2.3 GHz, LTE 20 MHz Downlink (Digital Attenuation Variations Shown) –20 1900 10453-047 –15 10453-048 –20 FREQUENCY OFFSET (MHz) INTEGRATED PHASE NOISE (°rms) ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C Figure 46. Integrated TX LO Phase Noise vs. Frequency, 40 MHz REF_CLK Rev. D | Page 27 of 36 –20 –25 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C –30 –35 –40 –45 –50 –55 –60 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) Figure 49. TX Third-Order Harmonic Distortion (HD3) vs. Frequency 10453-049 –120 –25 –50 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –65 10453-044 TRANSMITTER OUTPUT POWER (dBm/100kHz) 0 AD9361 AD9361 –30 TX SINGLE SIDEBAND AMPLITUDE (dBc) –40°C +25°C +85°C TX OIP3 (dBm) 25 20 15 10 0 0 4 8 12 16 20 TX ATTENUATION SETTING (dB) 10453-050 5 Figure 50. TX Third-Order Output Intercept Point (OIP3) vs. TX Attenuation Setting 160 156 TX SNR (dB/Hz) 154 152 150 148 146 144 0 3 6 9 TX ATTENUATION SETTING (dB) 12 15 10453-051 142 140 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 –70 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) Figure 52. TX Single Sideband (SSB) Rejection vs. Frequency, 3.075 MHz Offset –40°C +25°C +85°C 158 –35 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C Figure 51. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, LTE 20 MHz Signal of Interest with Noise Measured at 90 MHz Offset Rev. D | Page 28 of 36 10453-052 30 Data Sheet Data Sheet AD9361 6 5 5 0 4 –5 RX EVM (dB) 3 –40°C +25°C +85°C 2 –10 –40°C +25°C +85°C –15 –20 1 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 RF FREQUENCY (GHz) –25 –72 10453-053 0 5.0 Figure 53. RX Noise Figure vs. RF Frequency –67 –62 –57 –52 –47 –42 –37 –32 INTERFERER POWER LEVEL (dBm) 10453-056 RX NOISE FIGURE (dB) 5.5 GHz FREQUENCY BAND Figure 56. RX EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest with PIN = −74 dBm, WiMAX 40 MHz Blocker at 40 MHz Offset 5 5 4 0 2 –40°C +25°C +85°C –5 RX EVM (dB) RSSI ERROR (dB) 3 1 0 –10 –40°C +25°C +85°C –15 –1 –20 –80 –70 –60 –50 –40 –30 –20 –10 RX INPUT POWER (dBm) –25 –60 10453-054 –3 –90 –55 –50 –45 –40 –35 –30 –25 INTERFERER POWER LEVEL (dBm) Figure 54. RSSI Error vs. RX Input Power, Referenced to −50 dBm Input Power at 5.8 GHz 10453-057 –2 Figure 57. RX EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest with PIN = −74 dBm, WiMAX 40 MHz Blocker at 80 MHz Offset 0 70 –5 –20 –25 66 64 –30 –40°C +25°C +85°C 62 –35 –68 –62 –56 –50 –44 –38 RX INPUT POWER (dBm) –32 –26 –20 60 5.0 10453-055 –40 –74 Figure 55. RX EVM vs. RX Input Power, 64 QAM WiMAX 40 MHz Mode, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer) 5.1 5.2 5.3 5.4 5.5 5.6 FREQUENCY (GHz) 5.7 5.8 5.9 6.0 10453-058 –15 RX GAIN (dB) RX EVM (dB) 68 –40°C +25°C +85°C –10 Figure 58. RX Gain vs. Frequency, Gain Index = 76 (Maximum Setting) Rev. D | Page 29 of 36 AD9361 Data Sheet 20 0 5 –40°C +25°C +85°C 0 –5 –10 –20 6 16 26 36 46 56 66 76 RX GAIN INDEX –80 –100 15 30 25 20 FREQUENCY (GHz) 10 70 9 TX OUTPUT POWER (dBm) 80 –40°C +25°C +85°C 50 10 5 Figure 62. RX Emission at LNA Input, DC to 26 GHz, fLO_RX = 5.8 GHz, WiMAX 40 MHz 60 40 30 –40°C +25°C +85°C 8 7 6 5 20 28 36 44 52 60 68 76 RX GAIN INDEX 4 5.0 10453-060 20 Figure 60. Second-Order Input Intercept Point (IIP2) vs. RX Gain Index, f1 = 70 MHz, f2 = 71 MHz 0.4 –94 0.3 STEP LINEARITY ERROR (dB) –92 –40°C +25°C +85°C –100 –102 –104 5.5 5.6 5.7 5.8 5.9 FREQUENCY (GHz) 6.0 10453-061 5.4 5.8 5.9 6.0 0.0 –0.2 –0.4 5.3 5.7 –0.1 –108 5.2 5.6 0.1 –0.3 5.1 5.5. 5.4 0.2 –106 –110 5.0 5.3 Figure 63. TX Output Power vs. Frequency, Attenuation Setting = 0 dB, Single Tone 0.5 –98 5.2 FREQUENCY (GHz) –90 –96 5.1 10453-063 IIP2 (dBm) –60 0 Figure 59. Third-Order Input Intercept Point (IIP3) vs. RX Gain Index, f1 = 50 MHz, f2 = 101 MHz RX LO LEAKAGE (dBm) –40 –120 10453-059 –15 –20 Figure 61. RX Local Oscillator (LO) Leakage vs. Frequency –40°C +25°C +85°C –0.5 0 10 20 30 40 50 60 70 80 90 ATTENUATION SETTING (dB) Figure 64. TX Power Control Linearity Error vs. Attenuation Setting Rev. D | Page 30 of 36 10453-064 IIP3 (dBm) 10 10453-062 POWER AT LNA INPUT (dBm/150kHz) 15 Data Sheet AD9361 0 –10 –10 –20 TX CARRIER AMPLITUDE (dBc) ATT 0dB ATT 3dB ATT 6dB –30 –40 –50 –60 –70 –20 –30 –40 –50 –20 –10 0 10 20 30 40 50 –70 5.0 –34 –36 –40°C +25°C +85°C 2 4 6 8 10 TX ATTENUATION SETTING (dB) 10453-066 TX EVM (dB) –32 0 Figure 66. TX EVM vs. TX Attenuation Setting, WiMAX 40 MHz, 64 QAM Modulation, fLO_TX = 5.495 GHz, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer) 0.6 0.5 0.4 –40°C +25°C +85°C 0.2 5.3 5.4 5.5 5.6 FREQUENCY (GHz) 5.7 5.8 5.9 6.0 5.6 5.7 5.8 5.9 6.0 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –55 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –60 –65 –70 –75 –80 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 FREQUENCY (GHz) 10453-067 0.1 5.2 5.5 –50 5.0 TX THIRD-ORDER HARMONIC DISTORTION (dBc) INTEGRATED PHASE NOISE (°RMS) 0.7 5.1 5.4 Figure 69. TX Second-Order Harmonic Distortion (HD2) vs. Frequency 0.8 0.3 5.3 Figure 68. TX Carrier Rejection vs. Frequency TX SECOND-ORDER HARMONIC DISTORTION (dBc) –30 –40 5.2 FREQUENCY (GHz) Figure 65. TX Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 5.8 GHz, WiMAX 40 MHz Downlink (Digital Attenuation Variations Shown) –38 5.1 10453-068 –30 10453-069 –40 FREQUENCY OFFSET (MHz) 0 5.0 ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C Figure 67. Integrated TX LO Phase Noise vs. Frequency, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer) Rev. D | Page 31 of 36 –10 –15 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –20 –25 –30 –35 –40 –45 –50 5.0 5.1 5.2 5.3 5.4 5.5 5.6 FREQUENCY (GHz) 5.7 5.8 5.9 6.0 10453-070 –90 –50 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –60 –80 10453-065 TRANSMITTER OUTPUT POWER (dBm/1MHz) 0 Figure 70. TX Third-Order Harmonic Distortion (HD3) vs. Frequency AD9361 Data Sheet 20 TX OIP3 (dBm) 16 12 –40°C +25°C +85°C 8 4 –4 0 4 8 12 16 20 TX ATTENUATION SETTING (dB) 149 TX SNR (dB/Hz) 148 147 146 –40°C +25°C +85°C 144 142 6 9 TX ATTENUATION SETTING (dB) 12 15 10453-072 143 3 –45 –50 –55 –60 –65 5.1 5.2 5.3 5.4 5.5 5.6 FREQUENCY (GHz) 150 0 ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C 5.7 5.8 5.9 6.0 Figure 73. TX Single Sideband (SSB) Rejection vs. Frequency, 7 MHz Offset Figure 71. TX Third-Order Output Intercept Point (OIP3) vs. TX Attenuation Setting, fLO_TX = 5.8 GHz 145 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C –40 –70 5.0 10453-071 0 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –35 10453-073 TX SINGLE SIDEBAND AMPLITUDE (dBc) –30 Figure 72. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, WiMAX 40 MHz Signal of Interest with Noise Measured at 90 MHz Offset, fLO_TX = 5.745 GHz Rev. D | Page 32 of 36 Data Sheet AD9361 THEORY OF OPERATION GENERAL The AD9361 is a highly integrated radio frequency (RF) transceiver capable of being configured for a wide range of applications. The device integrates all RF, mixed signal, and digital blocks necessary to provide all transceiver functions in a single device. Programmability allows this broadband transceiver to be adapted for use with multiple communication standards, including frequency division duplex (FDD) and time division duplex (TDD) systems. This programmability also allows the device to be interfaced to various baseband processors (BBPs) using a single 12-bit parallel data port, dual 12-bit parallel data ports, or a 12-bit low voltage differential signaling (LVDS) interface. The AD9361 also provides self-calibration and automatic gain control (AGC) systems to maintain a high performance level under varying temperatures and input signal conditions. In addition, the device includes several test modes that allow system designers to insert test tones and create internal loopback modes that can be used by designers to debug their designs during prototyping and optimize their radio configuration for a specific application. RECEIVER The receiver section contains all blocks necessary to receive RF signals and convert them to digital data that is usable by a BBP. There are two independently controlled channels that can receive signals from different sources, allowing the device to be used in multiple input, multiple output (MIMO) systems while sharing a common frequency synthesizer. Each channel has three inputs that can be multiplexed to the signal chain, making the AD9361 suitable for use in diversity systems with multiple antenna inputs. The receiver is a direct conversion system that contains a low noise amplifier (LNA), followed by matched in-phase (I) and quadrature (Q) amplifiers, mixers, and band shaping filters that down convert received signals to baseband for digitization. External LNAs can also be interfaced to the device, allowing designers the flexibility to customize the receiver front end for their specific application. Gain control is achieved by following a preprogrammed gain index map that distributes gain among the blocks for optimal performance at each level. This can be achieved by enabling the internal AGC in either fast or slow mode or by using manual gain control, allowing the BBP to make the gain adjustments as needed. Additionally, each channel contains independent RSSI measurement capability, dc offset tracking, and all circuitry necessary for self-calibration. The receivers include 12-bit, sigma-delta (Σ-Δ) ADCs and adjustable sample rates that produce data streams from the received signals. The digitized signals can be conditioned further by a series of decimation filters and a fully programmable 128-tap FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing decimation factors to produce the desired output data rate. TRANSMITTER The transmitter section consists of two identical and independently controlled channels that provide all digital processing, mixed signal, and RF blocks necessary to implement a direct conversion system while sharing a common frequency synthesizer. The digital data received from the BBP passes through a fully programmable 128-tap FIR filter with interpolation options. The FIR output is sent to a series of interpolation filters that provide additional filtering and data rate interpolation prior to reaching the DAC. Each 12-bit DAC has an adjustable sampling rate. Both the I and Q channels are fed to the RF block for upconversion. When converted to baseband analog signals, the I and Q signals are filtered to remove sampling artifacts and fed to the upconversion mixers. At this point, the I and Q signals are recombined and modulated on the carrier frequency for transmission to the output stage. The combined signal also passes through analog filters that provide additional band shaping, and then the signal is transmitted to the output amplifier. Each transmit channel provides a wide attenuation adjustment range with fine granularity to help designers optimize signal-to-noise ratio (SNR). Self-calibration circuitry is built into each transmit channel to provide automatic real-time adjustment. The transmitter block also provides a TX monitor block for each channel. This block monitors the transmitter output and routes it back through an unused receiver channel to the BBP for signal monitoring. The TX monitor blocks are available only in TDD mode operation while the receiver is idle. CLOCK INPUT OPTIONS The AD9361 operates using a reference clock that can be provided by two different sources. The first option is to use a dedicated crystal with a frequency between 19 MHz and 50 MHz connected between the XTALP and XTALN pins. The second option is to connect an external oscillator or clock distribution device (such as the AD9548) to the XTALN pin (with the XTALP pin remaining unconnected). If an external oscillator is used, the frequency can vary between 10 MHz and 80 MHz. This reference clock is used to supply the synthesizer blocks that generate all data clocks, sample clocks, and local oscillators inside the device. Errors in the crystal frequency can be removed by using the digitally programmable digitally controlled crystal oscillator (DCXO) function to adjust the on-chip variable capacitor. This capacitor can tune the crystal frequency variance out of the system, resulting in a more accurate reference clock from which all other frequency signals are generated. This function can also be used with on-chip temperature sensing to provide oscillator frequency temperature compensation during normal operation. Rev. D | Page 33 of 36 AD9361 Data Sheet SYNTHESIZERS RX_FRAME Signal RF PLLs The device generates an RX_FRAME output signal whenever the receiver outputs valid data. This signal has two modes: level mode (RX_FRAME stays high as long as the data is valid) and pulse mode (RX_FRAME pulses with a 50% duty cycle). Similarly, the BBP must provide a TX_FRAME signal that indicates the beginning of a valid data transmission with a rising edge. Similar to the RX_FRAME, the TX_FRAME signal can remain high throughout the burst or it can be pulsed with a 50% duty cycle. The AD9361 contains two identical synthesizers to generate the required LO signals for the RF signal paths:—one for the receiver and one for the transmitter. Phase-locked loop (PLL) synthesizers are fractional-N designs incorporating completely integrated voltage controlled oscillators (VCOs) and loop filters. In TDD operation, the synthesizers turn on and off as appropriate for the RX and TX frames. In FDD mode, the TX PLL and the RX PLL can be activated simultaneously. These PLLs require no external components. BB PLL The AD9361 also contains a baseband PLL synthesizer that is used to generate all baseband related clock signals. These include the ADC and DAC sampling clocks, the DATA_CLK signal (see the Digital Data Interface section), and all data framing signals. This PLL is programmed from 700 MHz to 1400 MHz based on the data rate and sample rate requirements of the system. DIGITAL DATA INTERFACE The AD9361 data interface uses parallel data ports (P0 and P1) to transfer data between the device and the BBP. The data ports can be configured in either single-ended CMOS format or differential LVDS format. Both formats can be configured in multiple arrangements to match system requirements for data ordering and data port connections. These arrangements include single port data bus, dual port data bus, single data rate, double data rate, and various combinations of data ordering to transmit data from different channels across the bus at appropriate times. Bus transfers are controlled using simple hardware handshake signaling. The two ports can be operated in either bidirectional (TDD) mode or in full duplex (FDD) mode where half the bits are used for transmitting data and half are used for receiving data. The interface can also be configured to use only one of the data ports for applications that do not require high data rates and prefer to use fewer interface pins. DATA_CLK Signal RX data supplies the DATA_CLK signal that the BBP can use when receiving the data. The DATA_CLK can be set to a rate that provides single data rate (SDR) timing where data is sampled on each rising clock edge, or it can be set to provide double data rate (DDR) timing where data is captured on both rising and falling edges. This timing applies to operation using either a single port or both ports. FB_CLK Signal For transmit data, the interface uses the FB_CLK signal as the timing reference. FB_CLK allows source synchronous timing with rising edge capture for burst control signals and either rising edge (SDR mode) or both edge capture (DDR mode) for transmit signal bursts. The FB_CLK signal must have the same frequency and duty cycle as DATA_CLK. ENABLE STATE MACHINE The AD9361 transceiver includes an enable state machine (ENSM) that allows real-time control over the current state of the device. The device can be placed in several different states during normal operation, including • • • • • • Wait—power save, synthesizers disabled Sleep—wait with all clocks/BB PLL disabled TX—TX signal chain enabled RX—RX signal chain enabled FDD—TX and RX signal chains enabled Alert—synthesizers enabled The ENSM has two possible control methods: SPI control and pin control. SPI Control Mode In SPI control mode, the ENSM is controlled asynchronously by writing SPI registers to advance the current state to the next state. SPI control is considered asynchronous to the DATA_CLK because the SPI_CLK can be derived from a different clock reference and can still function properly. The SPI control ENSM method is recommended when real-time control of the synthesizers is not necessary. SPI control can be used for realtime control as long as the BBIC has the ability to perform timed SPI writes accurately. Pin Control Mode In pin control mode, the enable function of the ENABLE pin and the TXNRX pin allow real-time control of the current state. The ENSM allows TDD or FDD operation depending on the configuration of the corresponding SPI register. The ENABLE and TXNRX pin control method is recommended if the BBIC has extra control outputs that can be controlled in real time, allowing a simple 2-wire interface to control the state of the device. To advance the current state of the ENSM to the next state, the enable function of the ENABLE pin can be driven by either a pulse (edge detected internally) or a level. When a pulse is used, it must have a minimum pulse width of one FB_CLK cycle. In level mode, the ENABLE and TXNRX pins are also edge detected by the AD9361 and must meet the same minimum pulse width requirement of one FB_CLK cycle. Rev. D | Page 34 of 36 Data Sheet AD9361 In FDD mode, the ENABLE and TXNRX pins can be remapped to serve as real-time RX and TX data transfer control signals. In this mode, the ENABLE pin enables or disables the receive signal path, and the TXNRX pin enables or disables the transmit signal path. In this mode, the ENSM is removed from the system for control of all data flow by these pins. SPI INTERFACE The AD9361 uses a serial peripheral interface (SPI) to communicate with the BBP. This interface can be configured as a 4-wire interface with dedicated receive and transmit ports, or it can be configured as a 3-wire interface with a bidirectional data communication port. This bus allows the BBP to set all device control parameters using a simple address data serial bus protocol. AUXILIARY CONVERTERS AUXADC The AD9361 contains an auxiliary ADC that can be used to monitor system functions such as temperature or power output. The converter is 12 bits wide and has an input range of 0 V to 1.25 V. When enabled, the ADC is free running. SPI reads provide the last value latched at the ADC output. A multiplexer in front of the ADC allows the user to select between the AUXADC input pin and a built-in temperature sensor. AUXDAC1 and AUXDAC2 The AD9361 contains two identical auxiliary DACs that can provide power amplifier (PA) bias or other system functionality. The auxiliary DACs are 10 bits wide, have an output voltage range of 0.5 V to VDD_GPO − 0.3 V, a current drive of 10 mA, and can be directly controlled by the internal enable state machine. Write commands follow a 24-bit format. The first six bits are used to set the bus direction and number of bytes to transfer. The next 10 bits set the address where data is to be written. The final eight bits are the data to be transferred to the specified register address (MSB to LSB). The AD9361 also supports an LSB-first format that allows the commands to be written in LSB to MSB format. In this mode, the register addresses are incremented for multibyte writes. The AD9361 must be powered by the following three supplies: the analog supply (VDDD1P3_DIG/VDDAx = 1.3 V), the interface supply (VDD_INTERFACE = 1.8 V), and the GPO supply (VDD_GPO = 3.3 V). Read commands follow a similar format with the exception that the first 16 bits are transferred on the SPI_DI pin and the final eight bits are read from the AD9361, either on the SPI_DO pin in 4-wire mode or on the SPI_DI pin in 3-wire mode. For applications requiring optimal noise performance, it is recommended that the 1.3 V analog supply be split and sourced from low noise, low dropout (LDO) regulators. Figure 74 shows the recommended method. POWERING THE AD9361 3.3V CONTROL PINS ADP2164 Control Inputs (CTRL_IN[3:0]) 1.8V ADP1755 1.3V_A ADP1755 1.3V_B Figure 74. Low Noise Power Solution for the AD9361 For applications where board space is at a premium, and optimal noise performance is not an absolute requirement, the 1.3 V analog rail can be provided directly from a switcher, and a more integrated power management unit (PMU) approach can be adopted. Figure 75 shows this approach. The AD9361 provides four edge detected control input pins. In manual gain mode, the BBP can use these pins to change the gain table index in real time. In transmit mode, the BBP can use two of the pins to change the transmit gain in real time. GPO PINS (GPO_3 TO GPO_0) The AD9361 provides four, 3.3 V capable general-purpose logic output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins can be used to control other peripheral devices such as regulators and switches via the AD9361 SPI bus, or they can function as slaves for the internal AD9361 state machine. Rev. D | Page 35 of 36 ADP5040 1.2A BUCK ADP1755 1.3V LDO VDDD1P3_DIG/VDDAx AD9361 300mA LDO 1.8V 300mA LDO 3.3V VDD_INTERFACE VDD_GPO Figure 75. Space-Optimized Power Solution for the AD9361 10453-075 The AD9361 provides eight simultaneous real-time output signals for use as interrupts to the BBP. These outputs can be configured to output a number of internal settings and measurements that the BBP can use when monitoring transceiver performance in different situations. The control output pointer register selects what information is output to these pins, and the control output enable register determines which signals are activated for monitoring by the BBP. Signals used for manual gain mode, calibration flags, state machine states, and the ADC output are among the outputs that can be monitored on these pins. 10453-074 Control Outputs (CTRL_OUT[7:0]) AD9361 Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS A1 BALL CORNER 10.10 10.00 SQ 9.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 8.80 SQ E F G H 0.80 J K L M 0.60 REF TOP VIEW BOTTOM VIEW DETAIL A 1.70 MAX DETAIL A 1.00 MIN 0.32 MIN 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1. 11-18-2011-A SEATING PLANE Figure 76. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9361BBCZ AD9361BBCZ-REEL 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Z = RoHS Compliant Part. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10453-0-11/13(D) Rev. D | Page 36 of 36 Package Option BC-144-7 BC-144-7