AD AD9864

IF Digitizing Subsystem
AD9864*
PRODUCT OVERVIEW
FEATURES
The AD9864 is a general-purpose IF subsystem that digitizes a
low level 10 MHz to 300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the
AD9864 consists of a low noise amplifier (LNA), a mixer, a
band-pass Σ-∆ analog-to-digital converter (ADC), and a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit gives the AD9864 12 dB of
continuous gain adjustment. Auxiliary blocks include both
clock and LO synthesizers.
10 MHz to 300 MHz input frequency
6.8 kHz to 270 kHz output signal bandwidth
7.5 dB SSB NF
–7.0 dBm IIP3
AGC free range up to –34 dBm
12 dB continuous AGC range
16 dB front end attenuator
Baseband I/Q 16-bit (or 24-bit) serial digital output
LO and sampling clock synthesizers
Programmable decimation factor, output format,
AGC, and sythesizer settings
370 Ω input impedance
2.7 V to 3.6 V supply voltage
Low current consumption: 17 mA
48-lead LFCSP package
The high dynamic range of the AD9864 and inherent antialiasing provided by the band-pass Σ-∆ converter allow the device to
cope with blocking signals up to 95 dB stronger than the desired
signal. This attribute often reduces the cost of a radio by reducing IF filtering requirements. Also, it enables multimode radios
of varying channel bandwidths, allowing the IF filter to be
specified for the largest channel bandwidth.
APPLICATIONS
The SPI® port programs numerous parameters of the AD9864,
allowing the device to be optimized for any given application.
Programmable parameters include synthesizer divide ratios,
AGC attenuation and attack/decay time, received signal
strength level, decimation factor, output data format, 16 dB
attenuator, and the selected bias currents.
Multimode narrow-band radio products
Analog/digital UHF/VHF FDMA receivers
TETRA, APCO25, GSM/EDGE
Portable and mobile radio products
SATCOM terminals
The AD9864 is available in a 48-lead LFCSP package and
operates from a single 2.7 V to 3.6 V supply. The total power
consumption is typically 56 mW and a power-down mode is
provided via serial interfacing.
*Protected by U.S. Patent No. 5,969,657; other patents pending.
FUNCTIONAL BLOCK DIAGRAM
MXOP MXON IF2P IF2N
GCP GCN
DAC
AD9864
AGC
–16dB
IFIN
∑-∆ ADC
LNA
DECIMATION
FILTER
FORMATTING/SSI
DOUTA
DOUTB
FS
CLKOUT
FREF
CONTROL LOGIC
IOUTL
VOLTAGE
REFERENCE
CLK SYN
LOP LON
LO VCO AND
LOOP FILTER
IOUTC
CLKP
CLKN
VREFP VCM VREFN
SPI
PC
PD
PE
SYNCB
04319-0-001
LO
SYN
LOOP FILTER
Figure 1. AD9864 Block Diagram
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9864
TABLE OF CONTENTS
General Description ......................................................................... 3
IF LNA/Mixer ............................................................................. 26
AD9864 Specifications..................................................................... 4
Band-Pass ∑-∆ ADC .................................................................. 27
Digital Specifications........................................................................ 6
Decimation Filter ....................................................................... 29
Absolute Maximum Ratings............................................................ 7
Variable Gain Amplifier Operation With Automatic Gain
Control......................................................................................... 30
Thermal Resistance ...................................................................... 7
Pin Configuration and Functional Descriptions.......................... 8
Definition of Specifications/Test Methods ............................... 9
Typical Performance Characteristics ........................................... 10
Serial Peripheral Interface (SPI) ............................................... 15
Theory of Operation ...................................................................... 17
Serial Port Interface (SPI).......................................................... 17
Synchronous Serial Interface (SSI)........................................... 18
Syncronization Using SYNCB .................................................. 22
Interfacing to DSPs..................................................................... 22
Power Control............................................................................. 23
LO Synthesizer ............................................................................ 23
Variable Gain Control................................................................ 31
Automatic Gain Control (AGC)............................................... 32
System Noise Figure (NF) Versus VGA (or AGC) Control .. 34
Applications Considerations..................................................... 35
Spurious Responses.................................................................... 37
External Passive Component Requirements .......................... 37
Applications ................................................................................ 38
Layout Example, Evaluation Board, and Software ................. 42
Outline Dimensions ....................................................................... 43
ESD Caution................................................................................ 43
Ordering Guide .......................................................................... 43
Fast Acquire Mode...................................................................... 24
Clock Synthesizer ....................................................................... 24
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD9864
GENERAL DESCRIPTION
The AD9864 is a general-purpose narrow-band IF subsystem that
digitizes a low level 10 MHz to 300 MHz IF input with a signal
bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of
the AD9864 consists of an LNA, a mixer, a band-pass Σ-∆ ADC,
and a decimation filter with programmable decimation factor.
The input LNA is a fixed gain block with an input impedance of
approximately 370 Ω||1.4 pF. The LNA input is single-ended
and self-biasing, allowing the input IF to be ac-coupled. The
LNA can be disabled through the serial interface, providing a
fixed 16 dB attenuation to the input signal.
The LNA drives the input port of a Gilbert-type active mixer.
The mixer LO port is driven by the on-chip LO buffer, which
can be driven externally, single-ended or differential. The LO
buffer inputs are self-biasing and allow the LO input to be
ac-coupled. The open-collector outputs of the mixer drive an
external resonant tank consisting of a differential LC network
tuned to the IF of the band-pass Σ-∆ ADC.
The external differential LC tank forms the resonator for the
first stage of the band-pass Σ-∆ ADC. The tank LC values must
be selected for a center frequency of fCLK/8, where fCLK is the
sample rate of the ADC. The fCLK/8 frequency is the IF digitized
by the band-pass Σ-∆ ADC. On-chip calibration allows standard tolerance inductor and capacitor values. The calibration is
typically performed once at power-up.
The ADC contains a sixth order multibit band-pass Σ-∆ modulator that achieves very high instantaneous dynamic range over
a narrow frequency band centered at fCLK/8. The modulator
output is quadrature mixed to baseband and filtered by three
cascaded linear phase FIR filters to remove out-of-band noise.
The first FIR filter is a fixed decimate by 12 using a fourth order
comb filter. The second FIR filter also uses a fourth order comb
filter with programmable decimation from 1 to 16. The third
FIR stage is programmable for decimation of either 4 or 5. The
cascaded decimation factor is programmable from 48 to 960.
The decimation filter data is output via the synchronous serial
interface (SSI) of the chip.
Additional functionality built into the AD9864 includes LO and
clock synthesizers, programmable AGC, and a flexible synchronous serial interface for output data.
The LO synthesizer is a programmable PLL consisting of a low
noise phase frequency detector (PFD), a variable output current
charge pump (CP), a 14-bit reference divider, A and B counters,
and a dual modulus prescaler. The user only needs to add an
appropriate loop filter and VCO for complete operation.
The clock synthesizer is equivalent to the LO synthesizer with
the following differences:
• It does not include the prescaler or A counter.
• It includes a negative resistance core used for VCO
generation.
The AD9864 contains both a variable gain amplifier (VGA) and a
digital VGA (DVGA). Both of these can operate manually or
automatically. In manual mode, the gain for each is programmed
through the SPI. In automatic gain control mode, the gains are
adjusted automatically to ensure the ADC does not clip and that
the rms output level of the ADC is equal to a programmable reference level.
The VGA has 12 dB of attenuation range and is implemented by
adjusting the ADC full-scale reference level. The DVGA gain is
implemented by scaling the output of the decimation filter. The
DVGA is most useful in extending the dynamic range in narrow-band applications requiring 16-bit I and Q data format.
The SSI provides a programmable frame structure, allowing
24-bit or 16-bit I and Q data and flexibility by including
attenuation and RSSI data if required.
Rev. 0 | Page 3 of 44
AD9864
AD9864 SPECIFICATIONS
Table 1. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS,
fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
SYSTEM DYNAMIC PERFORMANCE1
SSB Noise Figure @ Minimum VGA Attenuation2, 3
@ Maximum VGA Attenuation2,3
Dynamic Range with AGC Enabled2,3
IF Input Clip Point @ Maximum VGA Attenuation3
@ Minimum VGA Attenuation3
Input Third Order Intercept (IIP3)
Gain Variation over Temperature
LNA + MIXER
Maximum RF and LO Frequency Range
LNA Input Impedance
Mixer LO Input Resistance
LO SYNTHESIZER
LO Input Frequency
LO Input Amplitude
FREF Frequency (for Sinusoidal Input Only)
FREF Input Amplitude
FREF Slew Rate
Minimum Charge Pump Current @ 5 V4
Maximum Charge Pump Current @ 5 V4
Charge Pump Output Compliance5
Synthesizer Resolution
CLOCK SYNTHESIZER
CLK Input Frequency
CLK Input Amplitude
Minimum Charge Pump Output Current4
Maximum Charge Pump Output Current4
Charge Pump Output Compliance5
Synthesizer Resolution
Σ-∆ ADC
Resolution
Clock Frequency (fCLK)
Center Frequency
Pass-Band Gain Variation
Alias Attenuation
GAIN CONTROL
Programmable Gain Step
AGC Gain Range
GCP Output Resistance
Temperature
Test Level
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
Full
25°C
25°C
IV
V
V
300
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
VI
VI
VI
IV
7.75
0.3
8
0.3
7.5
0.4
6.25
VDDP – 0.4
Full
Full
Full
Full
Full
Full
IV
IV
VI
VI
VI
VI
13
0.3
26
VDDC
Full
Full
Full
Full
Full
IV
IV
V
IV
IV
Full
Full
Full
V
V
IV
1
Min
91
–20
–32
–12
Typ
Max
Unit
7.5
13
95
–19
–31
–7.0
0.7
9.5
dB
dB
dB
dBm
dBm
dBm
dB
500
370||1.4
1
Rev. 0 | Page 4 of 44
MHz
Ω||pF
kΩ
300
2.0
25
3
0.67
5.3
0.67
5.3
0.4
2.2
VDDQ – 0.4
16
13
24
26
fCLK/8
1.0
80
50
16
12
72.5
This includes 0.9 dB loss of matching network.
AGC with DVGA enabled.
3
Measured in 10 kHz bandwidth.
4
Programmable in 0.67 mA steps.
5
Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
2
2
95
MHz
V p-p
MHz
V p-p
V/µs
mA
mA
V
kHz
MHz
V p-p
mA
mA
V
kHz
Bits
MHz
MHz
dB
dB
dB
dB
kΩ
AD9864
Parameter
OVERALL
Analog Supply Voltage (VDDA, VDDF, VDDI)
Digital Supply Voltage (VDDD, VDDC, VDDL)
Interface Supply Voltage (VDDH)1
Charge Pump Supply Voltage (VDDP, VDDQ)
Total Current
Operation Mode2
Standby
OPERATING TEMPERATURE RANGE
1
2
Temperature
Test Level
Min
Typ
Max
Unit
Full
Full
Full
Full
VI
VI
VI
VI
2.7
2.7
1.8
2.7
3.0
3.0
3.6
3.6
3.6
5.5
V
V
V
V
Full
Full
VI
VI
+85
mA
mA
°C
17
0.01
–40
VDDH must be less than VDDD + 0.5 V.
Clock VCO off and additional 0.7 mA with VGA @ maximum attenuation.
Rev. 0 | Page 5 of 44
5.0
AD9864
DIGITAL SPECIFICATIONS
Table 2. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS,
fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
DECIMATOR
Decimation Factor1
Pass-Band Width
Pass-Band Gain Variation
Alias Attenuation
SPI-READ OPERATION (See Figure 30)
PC Clock Frequency
PC Clock Period (tCLK)
PC Clock High (tHI)
PC Clock Low (tLOW)
PC to PD Setup Time (tDS)
PC to PD Hold Time (tDH)
PE to PC Setup Time (tS)
PC to PE Hold Time (tH)
SPI-WRITE OPERATION2 (See Figure 29)
PC Clock Frequency
PC Clock Period (tCLK)
PC Clock High (tHI)
PC Clock Low (tLOW)
PC to PD Setup Time (tDS)
PC to PD Hold Time (tDH)
PC to PD (or DOUTB) Data Valid Time (tDV)
PE to PD Output Valid to Hi-Z (tEZ)
SSI2 (See Figure 32)
CLKOUT Frequency
CLKOUT Period (tCLK)
CLKOUT Duty Cycle (tHI, tLOW)
CLKOUT to FS Valid Time (tV)
CLKOUT to DOUT Data Valid Time (tDV)
CMOS LOGIC INPUTS3
Logic 1 Voltage (VIH)
Logic 0 Voltage (VIL)
Logic 1 Current (IIH)
Logic 0 Current (IIL)
Input Capacitance
CMOS LOGIC OUTPUTS2, 3, 4
Logic 1 Voltage (VOH)
Logic 0 Voltage (VOL)
Temperature
Test Level
Min
Full
Full
Full
Full
IV
V
IV
IV
48
88
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
100
45
45
2
2
5
5
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
100
45
45
2
2
3
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
0.867
38.4
33
–1
–1
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
VDDH – 0.2
Full
Full
IV
IV
1
Programmable in steps of 48 or 60.
CMOS output mode with CLOAD = 10 pF and Drive Strength = 7.
3
Absolute maximum and minimum input/output levels are VDDH + 0.3 V and –0.3 V.
4
IOL = 1 mA; specification is also dependent on drive strength setting.
2
Rev. 0 | Page 6 of 44
Typ
Max
Unit
960
50%
1.2
10
MHz
ns
ns
ns
ns
ns
ns
ns
10
MHz
ns
ns
ns
ns
ns
ns
ns
26
1153
67
+1
+1
MHz
ns
ns
ns
ns
8
50
fCLKOUT
dB
dBm
0.5
10
10
3
VDDH – 0.2
0.2
V
V
µA
µA
pF
V
V
AD9864
ABSOLUTE MAXIMUM RATINGS
Table 3. AD9864 Absolute Maximum Ratings
Parameter
VDDF, VDDA, VDDC,
VDDD, VDDH, VDDL, VDDI
VDDF, VDDA, VDDC,
VDDD, VDDH, VDDL, VDDI
VDDP, VDDQ
GNDF, GNDA, GNDC, GNDD,
GNDH, GNDL, GNDI, GNDQ, GNDP, GNDS
MXOP, MXON, LOP,
LON, IFIN, CXIF, CXVL, CXVM
PC, PD, PE, CLKOUT,
DOUTA, DOUTB, FS, SYNCB
IF2N, IF2P, GCP, GCN
VFEFP, VREGN, RREF
IOUTC
IOUTL
CLKP, CLKN
FREF
Junction Temperature
Storage Temperature
Lead Temperature
With Respect to
GNDF, GNDA, GNDC, GNDD,
GNDH, GNDL, GNDI, GNDS
VDDR, VDDA, VDDC,
VDDD, VDDH, VDDL, VDDI
GNDP, GNDQ
GNDF, GNDA, GNDC, GNDD,
GNDH, GNDL, GNDI, GNDQ, GNDP, GNDS
GNDH
Min
–0.3
Max
+4.0
Unit
V
–4.0
+4.0
V
–0.3
–0.3
+6.0
+0.3
V
V
–0.3
VDDI + 0.3
V
GNDH
–0.3
VDDH + 0.3
V
GNDF
GNDA
GNDQ
GNDP
GNDC
GNDL
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
VDDF + 0.3
VDDA + 0.3
VDDQ + 0.3
VDDP + 0.3
VDDC + 0.3
VDDL + 0.3
150
+150
300
V
V
V
V
V
V
°C
°C
°C
–65
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, i.e., θJA is specified for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
48-Lead LFCSP
θJA
29.5
Rev. 0 | Page 7 of 44
Unit
°C/W
AD9864
GNDP
IOUTL
VDDP
VDDL
CXVM
LON
LOP
CXVL
GNDI
CXIF
IFIN
VDDI
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
MXOP 1
36 GNDL
PIN 1
IDENTIFIER
MXON 2
35 FREF
GNDF 3
34 GNDS
IF2N 4
33 SYNCB
IF2P 5
32 GNDH
AD9864
VDDF 6
31 FS
TOP VIEW
(Not to Scale)
GCP 7
30 DOUTB
GCN 8
29 DOUTA
VDDA 9
28 CLKOUT
GNDA 10
27 VDDH
VREFP 11
26 VDDD
VREFN 12
25 PE
04319-0-002
PD
PC
GNDD
GNDS
CLKN
CLKP
GNDC
VDDC
GNDQ
IOUTC
RREF
VDDQ
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. 48-Lead LFCSP, Backside Paddle Contact Is Connected to Ground
Table 5. Pin Function Descriptions—48-Lead Lead Frame Chip Scale Package (LFCSP)
Pin No.
1
2
3
4
5
6
7
Mnemonic
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
8
9
10
11
12
13
GCN
VDDA
GNDA
VREFP
VREFN
RREF
14
15
16
VDDQ
IOUTC
GNDQ
17
18
19
VDDC
GNDC
CLKP
20
CLKN
21
22
23
24
25
26
GNDS
GNDD
PC
PD
PE
VDDD
Description
Mixer Output, Positive
Mixer Output, Negative
Ground for Front End of ADC
Second IF Input (to ADC), Negative
Second IF Input (to ADC), Positive
Positive Supply for Front End of ADC
Filter Capacitor for ADC Full-Scale
Control
Full-Scale Control Ground
Positive Supply for ADC Back End
Ground for ADC Back End
Voltage Reference, Positive
Voltage Reference, Negative
Reference Resistor: Requires 100 kΩ to
GNDA
Positive Supply for Clock Synthesizer
Clock Synth Charge Pump Out Current
Ground for Clock Synthesizer Charge
Pump
Positive Supply for Clock Synthesizer
Ground for Clock Synthesizer
Sampling Clock Input/Clock VCO Tank,
Positive
Sampling Clock Input/Clock VCO Tank,
Negative
Substrate Ground
Ground for Digital Functions
Clock Input for SPI Port
Data I/O for SPI Port
Enable Input for SPI Port
Positive Supply for Internal Digital
Pin No.
27
28
29
30
Mnemonic
VDDH
CLKOUT
DOUTA
DOUTB
31
32
33
FS
GNDH
SYNCB
34
35
GNDS
FREF
36
37
GNDL
GNDP
38
IOUTL
39
VDDP
40
41
VDDL
CXVM
42
LON
43
LOP
44
CXVL
45
46
GNDI
CXIF
47
48
IFIN
VDDI
Rev. 0 | Page 8 of 44
Description
Positive Supply for Digital Interface
Clock Output for SSI Port
Data Output for SSI Port
Data Output for SSI Port (Inverted) or
SPI Port
Frame Sync for SSI Port
Ground for Digital Interface
Resets SSI and DecimatorCounters;
Active Low
Substrate Ground
Reference Frequency Input for Both
Synthesizers
Ground for LO Synthesizer
Ground for LO Synthesizer Charge
Pump
LO Synthesizer Charge Pump Out
Current
Positive Supply for LO Synthesizer
Charge Pump
Postive Supply for LO Synthesizer
External Filter Capacitor; DC Output of
LNA
LO Input to Mixer and LO Synthesizer,
Negative
LO Input to Mixer and LO Synthesizer,
Positive
External Bypass Capacitor for LNA
Power Supply
Ground for Mixer and LNA
External Capacitor for Mixer V-I
Converter Bias
First IF Input (to LNA)
Positive Supply for LNA and Mixer
AD9864
DEFINITION OF SPECIFICATIONS/TEST METHODS
Single Sideband Noise Figure (SSB NF)
Dynamic Range (DR)
Noise figure (NF) is defined as the degradation in SNR performance (in dB) of an IF input signal after it passes through a
component or system. It can be expressed with the equation
Dynamic range is the measure of a small target input signal
(PTARGET) in the presence of a large unwanted interferer signal
(PINTER). Typically, the large signal will cause some unwanted
characteristic of the component or system to degrade, thus making it unable to detect the smaller target signal correctly. In the
case of the AD9864, it is often a degradation in noise figure at
increased VGA attenuation settings that limits its dynamic range.
Noise Figure = 10 × log (SNR IN / SNROUT )
The term SSB is applicable for heterodyne systems containing a
mixer. It indicates that the desired signal spectrum resides on
only one side of the LO frequency (i.e., single sideband); thus a
“noiseless” mixer has a noise figure of 3 dB.
The SSB noise figure of the AD9864 is determined by the equation
SSB NF = PIN – [10 × log ( BW )] – (−174 dBm/Hz ) – SNR
where PIN is the input power of an unmodulated carrier, BW is
the noise measurement bandwidth, –174 dBm/Hz is the thermal noise floor at 293K, and SNR is the measured signal-tonoise ratio in dB of the AD9864.
Note that PIN is set to –85 dBm to minimize any degradation in
measured SNR due to phase noise from the RF and LO signal
generators. The IF frequency, CLK frequency, and decimation
factors are selected to minimize any spurious components
falling within the measurement bandwidth. Note also that a
bandwidth of 10 kHz is used for the data sheet specification. All
references to noise figures within this data sheet imply single
sideband noise figure.
Input Third Order Intercept (IIP3)
IIP3 is a figure of merit used to determine a component’s or
system’s susceptibility to intermodulation distortion (IMD)
from its third order nonlinearities. Two unmodulated carriers
at a specified frequency relationship (f1 and f2) are injected into
a nonlinear system exhibiting third order nonlinearities producing IMD components at 2f1 – f2 and 2f2 – f1. IIP3 graphically represents the extrapolated intersection of the carrier’s
input power with the third order IMD component when plotted in dB. The difference in power (D in dBc) between the two
carriers and the resulting third order IMD components can be
determined from the equation
The test method for the AD9864 is as follows. The small target
signal (an unmodulated carrier) is input at the center of the IF
frequency, and its power level (PTARGET) is adjusted to achieve an
SNRTARGET of 6 dB. The power of the signal is then increased by
3 dB prior to injecting the interferer signal. The offset frequency
of the interferer signal is selected so that aliases produced by the
decimation filter’s response as well as phase noise from the LO
(due to reciprocal mixing) do not fall back within the measurement bandwidth. For this reason, an offset of 110 kHz was
selected. The interferer signal (also an unmodulated carrier) is
then injected into the input and its power level is increased to the
point (PINTER) where the target signal SNR is reduced to 6 dB. The
dynamic range is determined with the equation
DR = PINTER – PTARGET + SNRTARGET
Note that the AD9864’s AGC is enabled for this test.
IF Input Clip Point
The IF input clip point is defined as the input power that
results in a digital output level 2 dB below full-scale. Unlike
other linear components that typically exhibit a soft compression (characterized by its 1 dB compression point), an ADC
exhibits a hard compression once its input signal exceeds its
rated maximum input signal range. In the case of the AD9864,
which contains a Σ-∆ ADC, hard compression should be
avoided because it causes severe SNR degradation.
D = 2 × (IIP 3 – PIN )
Rev. 0 | Page 9 of 44
AD9864
TYPICAL PERFORMANCE CHARACTERISTICS
0
9.5
9.0
–2
+85°C
–4
IIP3 (dBm)
NF (dB)
8.5
8.0
+25°C
7.5
+85°C
–6
+25°C
–8
7.0
–40°C
–40°C
3.0
3.3
3.6
VDDx (V)
–12
2.7
04319-0-003
6.0
2.7
3.0
Figure 3. SSB Noise Figure vs. Supply
–17.5
97
–18.0
–40°C
95
+85°C
93
+85°C
–19.0
+25°C
–19.5
–40°C
–20.0
3.0
3.3
3.6
VDDx (V)
04319-0-005
92
2.7
–18.5
–20.5
2.7
3.0
3.3
3.6
VDDx (V)
Figure 4. Dynamic Range vs. Supply
04319-0-006
DR (dB)
INPUT CLIP POINT (dBm)
+25°C
94
3.6
Figure 6. IIP3 vs. Supply
98
96
3.3
VDDx (V)
04319-0-004
–10
6.5
Figure 7. Maximum VGA Attenuation Clip Point vs. Supply
0.1
–29.5
0
GAIN VARIATION (dB)
–0.1
–30.5
+85°C
–31.0
+25°C
–0.2
–0.3
–0.4
–0.5
–0.6
–31.5
–0.7
–32.0
2.7
3.0
3.3
VDDx (V)
3.6
–0.8
–20
–17
–14
–11
–8
–5
LO DRIVE (dBm)
Figure 8. Normalized Gain Variation vs. LO Drive (VDDx = 3.0 V)
Figure 5. Minimum VGA Attenuation Clip Point vs. Supply
Rev. 0 | Page 10 of 44
04319-0-008
–40°C
04319-0-007
INPUT CLIP POINT (dBm)
–30.0
AD9864
–12
–10
–15
–30
8.2
NF
–40
8.0
7.8
–50
IMD
–60
7.4
–18
–21
–27
–30
–70
–15
–5
–10
0
5
–33
–80
LO DRIVE (dBm)
–36
–36 –33 –30 –27 –24 –21 –18 –15 –12
Figure 9. Noise Figure and IMD vs. LO Drive (VDDx = 3.0 V)
–55
ADC DOES NOT GO INTO
HARD COMPRESSION
–2
–21
2.7V
–73
3.0V
–24
–79
IMD (dBm)
3.0V
–85
–30
3.3V
–91
2.7V
–33
–97
–10
–36
3.6V
–28
–26
–24
–22
–20
–18
–16
–14
IFIN (dBm)
04319-0-011
–12
–103
–39
–109
–42
–115
–51
–48
–45
–42
–39
–36
–33
–45
–30
IFIN (dBm)
Figure 13. IMD vs. IFIN
Figure 10. Gain Compression vs. IFIN
10.0
10.0
9.5
16-BIT
I/Q DATA
NOISE FIGURE (dB)
16-BIT
I/Q DATA WITH
DVGA ENABLED
9.0
8.5
8.0
16-BIT
DATA
9.0
16-BIT DATA
WITH DVGA ENABLED
8.5
8.0
24-BIT
I/Q DATA
24-BIT
DATA
100
CHANNEL BANDWIDTH (kHz)
1000
7.5
10
04319-0-013
7.5
10
–27
04319-0-012
dBFS
–18
–67
–6
9.5
–0
PIN
3.3V
–8
–3
–15
–61
3.6V
–4
–6
Figure 12. Gain Compression vs. IFIN with 16 dB LNA Attenuator Enabled
0
–14
–30
–9
IFIN (dBm)
Figure 11. Noise Figure vs. BW (Minimum Attenuation, fCLK = 13 MSPS)
100
CHANNEL BANDWIDTH (kHz)
1000
04319-0-014
7.0
–20
04319-0-009
7.2
–24
PIN (dBFS)
7.6
NOISE FIGURE (dB)
NOISE FIGURE (dBc)
–20
8.4
04319-0-010
8.6
dBm
8.8
0
IMD WITH IFIN = –36 dBm (dBc)
9.0
Figure 14. Noise Figure vs. BW (Minimum Attenuation, fCLK = 18 MSPS)
Rev. 0 | Page 11 of 44
AD9864
10.0
11.5
16-BIT DATA
WITH DVGA ENABLED
11.0
10.5
24-BIT
DATA
16-BIT
DATA
9.0
NOISE FIGURE (dB)
NOISE FIGURE (dB)
9.5
8.5
BW = 27.08kHz
(K = 0, M = 3)
10.0
BW = 12.04kHz
(K = 0, M = 8)
9.5
9.0
BW = 6.78kHz
(K = 0, M = 15)
8.5
8.0
8.0
100
1000
CHANNEL BANDWIDTH (kHz)
7.0
04319-0-015
7.5
10
14
13
BW = 75kHz
(K = 0, M = 1)
12
BW = 50kHz
(K = 0, M = 2)
NOISE FIGURE (dB)
11
BW = 15kHz
(K = 0, M = 9)
10
9
BW = 135.42kHz
(K = 1, M = 1)
BW = 90.28kHz
(K = 1, M = 2)
12
11
10
BW = 27.08kHz
(K = 1, M = 9)
9
8
3
6
9
12
VGA ATTENUATION (dB)
7
12
9
Figure 19. Noise Figure vs. VGA Attenuation (fCLK = 26 MSPS)
–5
–40
6
3
VGA ATTENUATION (dB)
Figure 16. Noise Figure vs. VGA Attenuation (fCLK = 18 MSPS)
–30
0
04319-0-018
0
04319-0-017
8
–5
–30
–40
–10
–50
–10
–50
–15
PIN
–15
PIN
–60
–25
–90
–30
–100
–20
–70
–80
–25
–90
–30
PIN (dBFS)
–80
IMD (dBm)
–20
–70
POUT (dBFS)
–60
–100
–35
–110
–40
–42
–39
–36
–33
–30
–27
IFIN (dB)
–24
–45
–40
–120
04319-0-019
–120
–35
–110
–130
–45
Figure 17. IMD vs. IFIN (fCLK = 13 MSPS)
–42
–39
–36
–33
–30
–27
IFIN (dBm)
Figure 20. IMD vs. IFIN (fCLK = 18 MSPS)
Rev. 0 | Page 12 of 44
–24
–45
04319-0-020
NOISE FIGURE (dB)
13
IMD (dB)
12
9
Figure 18. Noise Figure vs. VGA Attenuation (fCLK = 13 MSPS)
14
–130
–45
6
3
VGA ATTENUATION (dB)
Figure 15. Noise Figure vs. BW (Minimum Attenuation, fCLK = 26 MSPS)
7
0
04319-0-016
7.5
AD9864
–40
–5
13
–10
12
–50
PIN
16-BIT WITH DVGA
–15
–80
–25
–90
–30
PIN (dBFS)
–20
–70
–100
–120
–130
–45
–42
–39
–36
–33
–30
–27
–24
11
10
9
24-BIT
–35
8
–40
7
–45
04319-0-021
–110
IFIN (dBm)
6
50
0
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 21. IMD vs. IFIN (fCLK = 26 MSPS)
Figure 24. Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 18 MSPS, BW = 10 kHz)
0
13
16-BIT WITH DVGA
12
11
10
9
–4
IIP3 (dBm)
NOISE FIGURE (dB)
–2
24-BIT
–6
8
–8
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
–10
50
0
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 22. Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 26 MSPS, BW = 10 kHz)
04319-0-025
0
Figure 25. Input IIP3 vs. Frequency (fCLK = 18 MSPS)
20.0
0
128
18.5
112
AGC
NOISE FIGURE (dBc)
–2
–4
–6
17.0
96
15.5
80
14.0
64
12.5
48
NOISE FIGURE
11.0
32
MEAN AGC ATTN VALUE
6
04319-0-023
7
–8
–10
0
50
100
150
200
250
300
350
400
450
FREQUENCY (MHz)
500
8.0
–55
16
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
INTERFERER LEVEL (dBm)
Figure 26. Noise Figure vs. Interferer Level (16-Bit Data,
BW = 12.5 kHz, AGCR = 1, fINTERFERER = fIF + 110 kHz)
Figure 23. Input IIP3 vs. Frequency (fCLK = 26 MSPS)
Rev. 0 | Page 13 of 44
0
04319-0-026
9.5
04319-0-023
IIP3 (dBm)
IMD (dBc)
NOISE FIGURE (dB)
–60
04319-0-022
–30
AD9864
16
256
16
224
15
14
192
14
13
160
15
128
96
10
64
9
32
8
–50
–45
–40
–35
–30
–25
–20
–15
0
–10
INTERFERER LEVEL (dBm)
13
12
64
11
NOISE FIGURE
32
10
MEAN AGC ATTN VALUE
11
96
9
Figure 27. Noise Figure vs. Interferer Level (16-Bit Data with DVGA,
BW = 12.5 kHz, AGCR = 1, fINTERFERER = fIF + 110 kHz)
8
–65
–55
–45
–35
–25
–15
–5
INTERFERER LEVEL (dBm)
Figure 28. Noise Figure vs. Interferer Level (24-Bit Data,
BW = 12.5 kHz, AGCR = 1, fINTERFERER = fIF + 110 kHz)
Rev. 0 | Page 14 of 44
0
04319-0-028
128
NOISE FIGURE
NOISE FIGURE (dBc)
12
MEAN AGC ATTN VALUE
AGC ATTN
04319-0-027
NOISE FIGURE (dBc)
AGC ATTN
AD9864
SERIAL PERIPHERAL INTERFACE (SPI)
The SPI is a bidirectional serial port. It is used to load the configuration information into the registers listed below as well as to read back
their contents. Table 6 provides a list of the registers that can be programmed through the SPI port. Addresses and default values are given
in hexadecimal form.
Table 6. SPI Address Map
Bit
Address (Hex)
Breakdown
POWER CONTROL REGISTERS
0x00
(7:0)
Width
Default
Value
Name
Description
8
0xFF
STBY
0x01
(3:2)
2
0x00
CKOB
(1:0)
(7:0)
2
8
0x00
0x00
ADCB
TEST
Standby control bits (REF, LO, CKO, CK, GC, LNAMX, unused, and
ADC). Default is power-up condition of standby.
CK oscillator bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.40 mA,
3 = 0.65 mA).
Do not use.
Factory test mode. Do not use.
(7)
(6:0)
(7:0)
(7:4)
1
7
8
4
0
0x00
0x00
0x00
ATTEN
AGCG (14:8)
AGCG (7:0)
AGCA
(3:0)
(7)
(6:4)
(3)
(2:0)
4
1
3
1
3
0x00
0
0x00
0
0x00
AGCD
AGCV
AGCO
AGCF
AGCR
3
1
4
0
0x04
Unused
K
M
6
8
0x00
0x38
LOR (13:8)
LOR (7:0)
0x02
AGC
0x03
0x04
0x05
0x06
DECIMATION FACTOR
0x07
(7:5)
(4)
(3:0)
LO SYNTHESIZER
0x08
(5:0)
0x09
(7:0)
0x0A
(7:5)
(4:0)
3
5
0x05
0x00
LOA
LOB (12:8)
0x0B
0x0C
(7:0)
(6)
(5)
8
1
1
0x1D
0
0
LOB (7:0)
LOF
LOINV
(4:2)
3
0x00
LOI
(1:0)
2
0x03
LOTM
0x0D
(5:0)
0x0E
(7:0)
CLOCK SYNTHESIZER
0x10
(5:0)
0x11
(7:0)
6
8
0x00
0x04
LOFA (13:8)
LOFA (7:0)
6
8
0x00
0x38
CKR (13:8)
CKR (7:0)
0x12
5
0x00
CKN (12:8)
(4:0)
Apply 16 dB attenuation in the front end.
AGC attenuation setting (7 MSBs of a 15-bit unsigned word).
AGC attenuation setting (8 LSBs of a 15-bit unsigned word).
AGC attack bandwidth setting. Default yields 50 Hz loop
bandwidth.
AGC decay time setting. Default is decay time = attack time.
Enable digital VGA to increase AGC range by 12 dB.
AGC overload update setting. Default is slowest update.
Fast AGC (minimizes resistance seen between GCP and GCN).
AGC enable/reference level (disabled, 3 dB, 6 dB, 9 dB, 12 dB,
15 dB below clip).
Decimation factor = 60 × (M + 1), if K = 0; 48 × (M + 1), if K = 1.
Default is decimate-by-300.
Reference frequency divider (6 MSBs of a 14-bit word).
Reference frequency divisor (8 LSBs of a 14-bit word).
Default (56) yields 300 kHz from fREF = 16.8 MHz.
A Counter (prescaler control counter).
B Counter MSB (5 MSB of a 13-bit word).
Default LOA and LOB values yield 300 kHz from 73.35 MHz to
2.25 MHz.
B Counter LSB (8 LSB of a 13-bit word).
Enable fast acquire.
Invert charge pump (0 = source current to increase VCO
frequency).
Charge pump current in normal operation.
IPUMP = (LOI +1) × 0.625 mA.
Manual control of LO charge pump (0 = Off, 1 = Up, 2 = Down,
and 3 = Normal).
LO fast acquire time unit (6 MSBs of a 14-bit word).
LO fast acquire time unit (8 LSBs of a 14-bit word).
Reference frequency divisor (6 MSBs of a 14-bit word).
Reference frequency divisor (8 LSBs of a 14-bit word).
Default yields 300 kHz from fREF = 16.8 MHz; Minimum = 3,
Maximum = 16383.
Synthesized frequency divisor (5 MSBs of a 13-bit word).
Rev. 0 | Page 15 of 44
AD9864
Bit
Breakdown
(7:0)
Width
8
Default
Value
0x3C
Name
CKN (7:0)
(6)
(5)
1
1
0
0
CKF
CKINV
(4:2)
3
0x00
CKI
(1:0)
2
0x03
CKTM
0x15
0x16
SSI CONTROL
0x18
(5:0)
(7:0)
6
8
0x00
0x04
CKFA (13:8)
CKFA (7:0)
(7:0)
8
0x12
SSICRA
0x19
(7:0)
8
0x07
SSICRB
0x1A
ADC TUNING
0x1C
(3:0)
4
0x01
SSIORD
(1)
(0)
(3:0)
(5:0)
(7:0)
1
1
3
6
8
0
0
0x00
0x00
0x00
TUNE_LC
TUNE_RC
CAPL1 (2:0)
CAPL0 (5:0)
CAPR
Perform tuning on LC portion of the ADC (cleared when done).
Perform tuning on RC portion of the ADC (cleared when done).
Coarse capacitance setting of LC tank (LSB is 25 pF, differential).
Fine capacitance setting of LC tank (LSB is 0.4 pF, differential).
Capacitance setting for RC resonator (64 LSB of fixed
capacitance).
TEST
TEST
SPIREN
TEST
TEST
TRI
TEST
TEST
ID
Factory test mode. Do not use.
Factory test mode. Do not use.
Enable read from SPI port.
Factory test mode. Do not use.
Factory test mode. Do not use.
Three-state DOUTB.
Factory test mode. Do not use.
Factory Test mode. Do not use.
Revision ID (read-only); A write of 0x99 to this register is
equivalent to a power-on reset.
Address (Hex)
0x13
0x14
0x1D
0x1E
0x1F
TEST REGISTERS AND SPI PORT READ ENABLE
0x37–0x39
(7:0)
8
0x00
0x3A
(7:4)
4
0x00
(3)
1
0
(2:0)
3
0x00
0x3B
(7:4)
4
0x00
(3)
1
0
(2:0)
3
0x00
0x3C–0x3E
(7:0)
8
0x00
0x3F
(7:0)
8
Subject
to
Change
Description
Synthesized frequency divisor (8 LSBs of a 13-bit word).
Default yields 300 kHz from 18 MHz; Minimum = 3,
Maximum = 8191.
Enable fast acquire.
Invert charge pump (0 = source current to increase VCO
frequency).
Charge pump current in normal operation.
IPUMP = (CKI + 1) × 0.625 mA.
Manual control of CLK charge pump (0 = Off, 1 = Up, 2 = Down,
and 3 = Normal).
CK fast acquire time unit (6 LSBs of a 14-bit word).
CK fast acquire time unit (8 LSBs of a 14-bit word).
SSI Control Register A. See Table 8. Default is FS and CLKOUT
three-stated.
SSI Control Register B. See Table 8 (16-Bit Data, maximum drive
strength).
Output rate divisor. fCLKOUT = fCLK/SSIORD.
Rev. 0 | Page 16 of 44
AD9864
THEORY OF OPERATION
SERIAL PORT INTERFACE (SPI)
The serial port of the AD9864 has 3-wire or 4-wire SPI capability, allowing read/write access to all registers that configure the
device’s internal parameters. The default 3-wire serial communication port consists of a clock (PC), peripheral enable (PE),
and bidirectional data (PD) signal. The inputs to PC, PE, and
PD contain a Schmitt trigger with a nominal hysteresis of 0.4 V
centered about the digital interface supply, i.e., VDDH/2.
A 4-wire SPI interface can be enabled by setting the MSB of the
SSICRB register (Reg. 0x19, Bit 7) and setting Reg. 0x3A to 00,
resulting in the output data appearing on the DOUTB pin.
Note that since the default power-up state sets DOUTB low,
bus contention is possible for systems sharing the SPI output
line. To avoid any bus contention, the DOUTB pin can be
three-stated by setting the fourth control bit in the three-state
bit (Reg. 0x3B, Bit 3). This bit can then be toggled to gain access
to the shared SPI output line. An 8-bit instruction header must
accompany each read and write SPI operation. Only the write
operation supports an auto-increment mode, which allows the
entire chip to be configured in a single write operation. The
instruction header is shown in Table 7. It includes a read/notwrite indicator bit, six address bits, and a Don’t Care bit. The
data bits immediately follow the instruction header for both
read and write operations. Note that the address and data are
always given MSB first.
eight clock cycles. PE stays low during the operation and goes
high at the end of the transfer. If PE rises before the eight clock
cycles have passed, the operation is aborted. If PE stays low for
an additional eight clock cycles, the destination address is
incremented and another eight bits of data are shifted in.
Again, should PE rise early, the current byte is ignored. By
using this implicit addressing mode, the chip can be configured
with a single write operation. Registers identified as being subject to frequent updates, namely those associated with power
control and AGC operation, have been assigned adjacent
addresses to minimize the time required to update them. Note
that multibyte registers are big endian (the most significant
byte has the lower address) and are updated when a write to the
least significant byte occurs.
Figure 30 illustrates the timing for a read operation to the SPI
port. Although the AD9864 does not require read access for
proper operation, it is often useful in the product development
phase or for system authentication. Note that the read-back
enable bit (Register 0x3A, Bit 3) must be set for a read operation with a 3-wire SPI interface. After the peripheral enable
(PE) signal goes low, data (PD) pertaining to the instruction
header is read on the rising edges of the clock (PC). A read
operation occurs if the read/not-write indicator is set high.
After the address bits of the instruction header are read, the
eight data bits pertaining to the specified register are shifted out
of the data pin (PD) on the falling edges of the next eight clock
cycles. If the 4-wire SPI interface is enabled, the eight data bits
will also appear on the DOUTB pin with the same timing relationship as those appearing at PD. After the last data bit is
shifted out, the user should return PE high, causing PD to
become three-stated and return to its normal status as an input
pin. Since the auto-increment mode is not supported for read
operations, an instruction header is required for each register
read operation and PE must return high before initiating the
next read operation.
Table 7. Instruction Header Information
I6
A5
I5
A4
I4
A3
I3
A2
I2
A1
LSB
I0
X
I1
A0
Figure 29 illustrates the timing requirements for a write operation to the SPI port. After the peripheral enable (PE) signal goes
low, data (PD) pertaining to the instruction header is read on
the rising edges of the clock (PC). To initiate a write operation,
the read/not-write bit is set low. After the instruction header is
read, the eight data bits pertaining to the specified register are
shifted into the data pin (PD) on the rising edges of the next
tS
tCLK
tH
PE
tHI
tLOW
PC
tDS
PD
tDH
R/W
A5
A4
A0
DON'T
CARE
D7
Figure 29. SPI Write Operation Timing
Rev. 0 | Page 17 of 44
D6
D1
D0
04319-0-029
MSB
I7
R/W
AD9864
tS
PE
tCLK
tHI
tLOW
PC
PD
DOUTB
DON'T
T
CARE
tDV
tDH
R/W
A5
DON'T
CARE
DON'T
CARE
tEZ
A0
DON'T
CARE
D7
D6
D1
D0
DON'T
CARE
DON'T
CARE
D7
D6
D1
D0
A1
DON'T
CARE
04319-0-030
tDS
Figure 30. SPI Read Operation Timing
The AD9864 provides a high degree of programmability of its
SSI output data format, control signals, and timing parameters
to accommodate various digital interfaces. In a 3-wire digital
interface, the AD9864 provides a frame sync signal (FS), a clock
output (CLKOUT), and a serial data stream (DOUTA) signal to
the host device. In a 2-wire interface, the frame sync information is embedded into the data stream, thus only CLKOUT and
DOUTA output signals are provided to the host device. The SSI
control registers are SSICRA, SSICRB, and SSIORD. Table 8
shows the different bit fields associated with these registers.
The primary output of the AD9864 is the converted I and Q
demodulated signal available from the SSI port as a serial bit
stream contained within a frame. The output frame rate is equal
to the modulator clock frequency (fCLK) divided by the digital
filter’s decimation factor that is programmed in the Decimator
Register (0x07). The bit stream consists of an I word followed
by a Q word, where each word is either 24 bits or 16 bits long
and is given MSB first in twos complement form. Two optional
bytes may also be included within the SSI frame following the
Q word. One byte contains the AGC attenuation and the other
byte contains both a count of modulator reset events and an
estimate of the received signal amplitude (relative to full scale
of the AD9864’s ADC). Figure 31 illustrates the structure of the
SSI data frames in a number of SSI modes.
The two optional bytes are output if the EAGC bit of SSICRA is
set. The first byte contains the 8-bit attenuation setting (0 = no
attenuation, 255 = 24 dB of attenuation), while the second byte
contains a 2-bit reset field and 6-bit received signal strength
field. The reset field contains the number of modulator reset
events since the last report, saturating at 3. The received signal
strength (RSSI) field is a linear estimate of the signal strength at
the output of the first decimation stage; 60 corresponds to a
full-scale signal.
The two optional bytes follow the I and Q data as a 16-bit word
provided that the AAGC bit of SSICRA is not set. If the AAGC
bit is set, the two bytes follow the I and Q data in an alternating
fashion. In this alternate AGC data mode, the LSB of the byte
containing the AGC attenuation is a 0, while the LSB of the
byte containing reset and RSSI information is always a 1.
In a 2-wire interface, the embedded frame sync bit (EFS) within
the SSICRA register is set to 1. In this mode, the framing
information is embedded in the data stream, with each eight
bits of data surrounded by a start bit (low) and a stop bit (high),
and each frame ends with at least 10 high bits. FS remains
either low or three-stated (default), depending on the state of
the SFST bit. Other control bits can be used to invert the frame
sync (SFSI), to delay the frame sync pulse by one clock period
(SLFS), to invert the clock (SCKI), or to three-state the clock
(SCKT). Note that if EFS is set, SLFS is a Don’t Care.
24-BIT I AND Q, EAGC = 0, AAGC = X:48 DATA BITS
I(23:0)
Q(23:0)
24-BIT I AND Q, EAGC = 1, AAGC = 0:64 DATA BITS
I(23:0)
ATTN(7:0)
Q(23:0)
SSI(5:0)
RESET COUNT
16-BIT I AND Q, EAGC = 0, AAGC = X:32 DATA BITS
I(15:0)
Q(15:0)
16-BIT I AND Q, EAGC = 0, AAGC = 0:32 DATA BITS
I(15:0)
Q(15:0)
ATTN(7:0)
SSI(5:0)
16-BIT I AND Q, EAGC = 1, AAGC = 1:40 DATA BITS
I(15:0)
Q(15:0)
ATTN(7:1) 0
I(15:0)
Q(15:0)
SSI(5:1) 1
RESET COUNT
04319-0-031
SYNCHRONOUS SERIAL INTERFACE (SSI)
Figure 31. SSI Frame Structure
The SSIORD register controls the output bit rate (fCLKOUT) of the
serial bit stream. fCLKOUT can be set equal to the modulator clock
frequency (fCLK) or an integer fraction of it. It is equal to fCLK
divided by the contents of the SSIORD register. Note that fCLKOUT
should be chosen such that it does not introduce harmful spurs
within the pass band of the target signal. Users must verify that
the output bit rate is sufficient to accommodate the required
number of bits per frame for a selected word size and decimation
factor. Idle (high) bits are used to fill out each frame.
Rev. 0 | Page 18 of 44
AD9864
Table 8. SSI Control Registers
4
SCKI
SCKT
SLFS
SFSI
DIV_0
Output Bit Rate Divisor fCLKOUT = fCLK/SSIORD.
DIV_1
1
SSIORD (ADDR = 0x1A)
DIV
SFST
Enable 4-Wire SPI Interface for SPI Read Operation via DOUTB.
I/Q Data-Word Width (0 = 16 Bit, 1 Bit–24 Bit). Automatically 16-Bit when the AGCV = 1).
FS, CLKOUT, and DOUT Drive Strength.
DIV_2
0
0
7
DIV_3
1
1
3
DS_0
SSICRB (ADDR = 0x19)
4_SPI
DW
DS
Alternate AGC Data Bytes.
Embed AGC Data.
Embed Frame Sync.
Three-State Frame Sync.
Invert Frame Sync.
Late Frame Sync (1 = Late, 0 = Early).
Three-state CLKOUT.
Invert CLKOUT.
DS_1
0
0
0
1
0
0
1
0
DW
1
1
1
1
1
1
1
1
4_SPI
AAGC
EAGC
EFS
SFST
SFSI
SLFS
SCKT
SCKI
DS_2
SSICRA (ADDR = 0x18)
Description
EFS
Default
EAGC
Width
AAGC
Name
Rev. 0 | Page 19 of 44
AD9864
CLKOUT
FS
DOUT
I15
I0
Q15
Q14
Q0
SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0
CLKOUT
FS
DOUT
I15
I0
Q15
Q14
Q0
SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0
CLKOUT
FS
DOUT
I15
I0
Q15
Q14
Q0
ATTN7
ATTEN6
RSSI0
SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC
CLKOUT
FS
IDLE (HIGH) BITS
HI-Z
START
START
STOP
BIT
I7
I0
STOP
BIT
BIT
BIT
SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0
SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 0, EAGC = 0; AS ABOVE, BUT FS IS LOW
I15
I8
Figure 32. SSI Timing for Several SSICRA Settings with 16-Bit I/Q Data
Rev. 0 | Page 20 of 44
Q15
04319-0-032
DOUT
AD9864
tCLK
tHI tLOW
Table 9. Number of Bits per Frame for Different SSICR Settings
AAGC
NA
NA
0
1
0
1
NA
NA
0
1
0
1
*The number of bits per frame with embedded frame sync (EFS = 1); assume
at least 10 idle bits are desired.
The maximum SSIORD setting can be determined by the
equation
[
tV
FS
tDV
DOUT
I15
I14
04319-0-033
EFS
0
1
0
0
1
1
0
1
0
0
1
1
Figure 33. SSI Timing Parameters for SSI Timing*
*Timing parameters also apply to inverted CLKOUT or FS modes, with tDV
relative to the falling edge of the CLK and/or FS.
The AD9864 also provides the means for controlling the
switching characteristics of the digital output signals via the DS
(drive strength) field of the SSICRB. This feature is useful in
limiting switching transients and noise from the digital output
that may ultimately couple back into the analog signal path,
potentially degrading the AD9864’s sensitivity performance.
Figure 34 and Figure 35 show how the NF can vary as a function of the SSI setting for an IF frequency of 109.65 MHz. The
following two observations can be made from these figures:
1. The NF becomes more sensitive to the SSI output drive
strength level at higher signal bandwidth settings.
]
SSIORD ≤ TRUNC (Decimation Factor )/(No. of Bits per Frame) (1)
where TRUNC is the truncated integer value.
Table 9 lists the number of bits within a frame for 16-bit and 24bit output data formats for all of the different SSICR settings. The
decimation factor is determined by the contents of Register 0x07.
An example helps illustrate how the maximum SSIORD setting
is determined. Suppose a user selects a decimation factor of 600
(Register 0x07, K = 0, M = 9) and prefers a 3-wire interface with
a dedicated frame sync (EFS = 0) containing 24-bit data
(DW = 1) with nonalternating embedded AGC data included
(EAGC = 1, AAGC = 0). Referring to Table 9, each frame will
consist of 64 data bits. Using Equation 1, the maximum
SSIORD setting is 9 (= TRUNC(600/64)). Thus, the user can
select any SSIORD setting between 1 and 9.
2. The NF is dependent on the number of bits within an SSI
frame that become more sensitive to the SSI output drive
strength level as the number of bits is increased. As a result,
one should select the lowest possible SSI drive strength setting that still meets the SSI timing requirements.
10.0
9.8
9.6
16-BIT I/O DATA
9.4
9.2
9.0
24-BIT I/O DATA
8.8
8.6
8.4
8.2
Figure 32 illustrates the output timing of the SSI port for several
SSI control register settings with 16-bit I/Q data, while Figure 33
shows the associated timing parameters. Note that the same
timing relationship holds for 24-bit I/Q data, with the exception that I and Q word lengths now become 24 bits. In the
default mode of operation, data is shifted out on rising edges of
CLKOUT after a pulse equal to a clock period is output from
the frame sync (FS) pin. As described above, the output data
consists of a 16-bit or 24-bit I sample followed by a 16-bit or
24-bit Q sample, plus two optional bytes containing AGC and
status information.
Rev. 0 | Page 21 of 44
16-BIT I/0 DATA
w/ DVGA ENABLED
8.0
1
2
4
3
5
6
SSI OUTPUT DRIVE STRENGTH SETTING
Figure 34. NF vs. SSI Output Drive Strength
(VDDx = 3.0 V, FCLK = 18 MSPS, BW = 10 kHz)
7
04319-0-034
1 (24 Bit)
EAGC
0
0
1
1
1
1
0
0
1
1
1
1
CLKOUT
NOISE FIGURE (dB)
DW
0 (16 Bit)
Number
of Bits
per
Frame
32
49*
48
40
69*
59*
48
69*
64
56
89*
79*
AD9864
14
13
24-BIT I/O DATA
NOISE FIGURE (dB)
12
16-BIT I/O DATA
w/DVGA ENABLED
11
10
16-BIT I/O DATA
9
7
1
2
4
3
5
6
SSI OUTPUT DRIVE STRENGTH SETTING
7
04319-0-035
8
Figure 36 shows the timing relationship between SYNCB and
the SSI port’s CLKOUT and FS signals. SYNCB is an asynchronous active-low signal that must remain low for at least half an
input clock period, i.e., 1/(2 × fCLK). CLKOUT remains high
while FS remains low upon SYNCB going low. CLKOUT will
become active within one to two output clock periods upon
SYNCB returning high. FS will reappear several output cycles
later, depending on the digital filter’s decimation factor and the
SSIORD setting. Note that for any decimation factor and
SSIORD setting, this delay is fixed and repeatable. To verify
proper synchronization, the FS signals of the multiple AD9864
devices should be monitored.
SYNCB
Figure 35. NF vs. SSI Output Drive Strength
(VDDx = 3.0 V, FCLK = 18 MSPS, BW = 75 kHz)
FS
Table 10. Typical Rise/Fall Times (±25%) with a 10 pF
Capacitive Load for Each DS Setting
Typ (ns)
13.5
7.2
50
3.7
3.2
2.8
2.3
2.0
Figure 36. SYNCB Timing
INTERFACING TO DSPs
The AD9864 connects directly to an Analog Devices programmable digital signal processor (DSP). Figure 37 illustrates an
example with the Blackfin® series of ADSP-2153x processors.
The Blackfin DSP series of 16-bit products is optimized for
telecommunications applications with its dynamic power management feature, making it well suited for portable radio products. The code compatible family members share the fundamental core attributes of high performance, low power consumption, and the ease-of-use advantages of a microcontroller
instruction set.
AD9864
SPI
SCK
SEL
MOSI
ISO
SSI
CLKOUT
FS
DOUTAD
RSCLK
RFS
R
SYNCRONIZATION USING SYNCB
Many applications require the ability to synchronize one or
more AD9864s in a way that causes the output data to be precisely aligned to an external asynchronous signal. For example,
receiver applications employing diversity often require synchronization of multiple AD9864s’ digital outputs. Satellite
communication applications using TDMA methods may
require synchronization between payload bursts to compensate
for reference frequency drift and Doppler effects.
SYNCB can be used for this purpose. It is an active-low signal
that clears the clock counters in both the decimation filter and
the SSI port. The counters in the clock synthesizers are not reset
because it is presumed that the CLK signals of multiple chips
would be connected. SYNCB also resets the modulator, resulting in a large-scale impulse that must propagate through the
AD9864’s digital filter and SSI data formatting circuitry before
recovering valid output data. As a result, data samples unaffected by this SYNCB induced impulse can be recovered 12
output data samples after SYNCB goes high (independent of
the decimation factor).
ADSP-2153x
PC
PE
PD
DOUTBM
SPI-PORT
SERIAL
PORT
04319-0-037
Table 10 lists the typical output rise/fall times as a function of DS
for a 10 pF load. Rise/fall times for other capacitor loads can be
determined by multiplying the typical values presented by a scaling factor equal to the desired capacitive load divided by 10 pF.
DS
0
1
2
3
4
5
6
7
04319-0-036
CLKOUT
Figure 37. Example of AD9864 and ADSP-2153x Interface
As shown in Figure 37, AD9864’s synchronous serial interface
(SSI) links the receive data stream to the DSP’s serial port
(SPORT). For AD9864 setup and register programming, the
device connects directly to ADSP-2153x’s SPI port. Dedicated
select lines (SEL) allow the ADSP-2153x to program and read
back registers of multiple devices using only one SPI port. The
DSP driver code pertaining to this interface is available on the
AD9864 Web page.
Rev. 0 | Page 22 of 44
AD9864
To allow power consumption to be minimized, the AD9864
possesses numerous SPI programmable power-down and bias
control bits. The AD9864 powers up with all of its functional
blocks placed into a standby state, i.e., STBY register default is
0xFF. Each major block may then be powered up by writing a 0
to the appropriate bit of the STBY register. This scheme provides the greatest flexibility for configuring the IC to a specific
application as well as for tailoring the IC’s power-down and
wake-up characteristics. Table 11 summarizes the function of
each of the STBY bits. Note that when all the blocks are in
standby, the master reference circuit is also put into standby,
and thus the current is reduced further by 0.4 mA.
input. A complete PLL can be implemented if the synthesizer is used
with an external loop filter and voltage controlled oscillator (VCO).
The A, B, and R counters can be programmed via the following
registers: LOA, LOB, and LOR. The charge pump output
current is programmable via the LOI register from 0.625 mA to
5.0 mA using the equation
IPUMP = (LOI + 1) × 0.625 mA
(2)
An on-chip fast acquire function (enabled by the LOF bit)
automatically increases the output current for faster settling
during channel changes. The synthesizer may also be disabled
using the LO standby bit located in the STBY register.
TO EXTERNAL
LOOP
FILTER
Table 11. Standby Control Bits
STBY Bit
7: REF
6: LO
5: CKO
4: CK
3: GC
2: LNAMX
1: Unused
0: ADC
Effect
Voltage reference OFF;
all biasing shut down.
LO synthesizer OFF,
IOUTL three-state.
Clock oscillator OFF.
Clock synthesizer OFF,
IOUTC three-state. Clock
buffer OFF if ADC is OFF.
Gain control DAC OFF.
GCP and GCN threestate.
LNA and Mizer OFF.
CXVM, CXVL, and CXIF
three-state.
ADC OFF; Clock buffer
OFF if CLK synthesizer
OFF; VCM three-state;
clock to the digital filter
halted; digital outputs
static.
Current
Reduction
(mA)1
0.6
1.2
Wake-Up
Time (ms)
fREF
REF
BUFFER
fREF
÷R
LOR
<0.1 (CREF
= 4.7 nF)
Note 2
PHASE/
FREQUENCY
DETECTOR
fLO
FAST
ACQUIRE
LOA, LOB
A. B
COUNTERS
1.1
1.3
CHARGE
PUMP
÷8/9
Note 2
Note 2
LO
BUFFER
fLO
FROM
VCO
04319-0-038
POWER CONTROL
Figure 38. LO Synthesizer
0.2
Depends
on CGC
8.2
<2.2
9.2
<0.1
NOTES
1
When all blocks are in standby, the master reference circuit is also put into
standby, and thus the current is further reduced by 0.4 mA.
2
Wake-up time is dependent on programming and/or external components.
The LO (and CLK) synthesizer works in the following manner.
The externally supplied reference frequency, fREF, is buffered
and divided by the value held in the R counter. The internal fREF
is then compared to a divided version of the VCO frequency,
fLO. The phase/frequency detector provides UP and DOWN
pulses whose widths vary, depending upon the difference in
phase and frequency of the detector’s input signals. The
UP/DOWN pulses control the charge pump, making current
available to charge the external low-pass loop filter when there
is a discrepancy between the inputs of the PFD. The output of
the low-pass filter feeds an external VCO whose output frequency, fLO, is driven such that its divided down version, fLO,
matches that of fREF, thus closing the feedback loop.
The synthesized frequency is related to the reference frequency
and the LO register contents as follows:
f LO = (8 × LOB + LOA ) / LOR × f REF
LO SYNTHESIZER
The LO synthesizer shown in Figure 38 is a fully programmable
phase-locked loop (PLL) capable of 6.25 kHz resolution at
input frequencies up to 300 MHz and reference clocks of up to
25 MHz. It consists of a low noise digital phase-frequency
detector (PFD), a variable output current charge pump (CP), a
14-bit reference divider, programmable A and B counters, and
a dual-modulus 8/9 prescaler.
The A (3-bit) and B (13-bit) counters, in conjunction with the
dual 8/9 modulus prescaler, implement an N divider with N = 8
× B + A. In addition, the 14-bit reference counter (R Counter)
allows selectable input reference frequencies, fREF, at the PFD
(3)
Note that the minimum allowable value in the LOB register is 3
and its value must always be greater than that loaded into LOA.
An example may help illustrate how the values of LOA, LOB, and
LOR can be selected. Consider an application employing a 13
MHz crystal oscillator, i.e., fREF = 13 MHz, with the requirement
that fREF = 100 kHz and fLO = 143 MHz, i.e., high side injection
with fIF = 140.75 MHz and fCLK = 18 MSPS. LOR is selected to be
130 such that fREF = 100 kHz. The N-divider factor is 1430, which
can be realized by selecting LOB = 178 and LOA = 6.
Rev. 0 | Page 23 of 44
AD9864
The stability, phase noise, spur performance, and transient
response of the AD9864’s LO (and CLK) synthesizers are
determined by the external loop filter, the VCO, the N-divide
factor, and the reference frequency, fREF. A good overview of the
theory and practical implementation of PLL synthesizers (featured as a three-part series in Analog Dialogue) can be found
on the Analog Devices website. Also, a free software copy of the
Analog Devices’ ADIsimPLL, a PLL synthesizer simulation
tool, is available at www.analog.com. Note that the ADF4112
model can be used as a close approximation to the AD9864’s
LO synthesizer when using this software tool.
LOP
84kΩ
LO
BUFFER
~VDDL/2
LON
TO MIXER
LO PORT
500Ω
FREF
500Ω
NOTES
1. ESD DIODE STRUCTURES OMITTED FOR CLARITY.
2. FREF STBY SWITCHES SHOWN WITH LO SYNTHESIZER ON.
04319-0-039
1.75V
BIAS
Figure 39. Equivalent Input of LO and REF Buffers
Figure 39 shows the equivalent input structures of the synthesizers’ LO and REF buffers (excluding the ESD structures). The
LO input is fed to the LO synthesizer’s buffer as well as the LO
port of the AD9864’s mixer. Both inputs are self-biasing and
thus tolerate ac-coupled inputs. The LO input can be driven
with a single-ended or differential signal. Single-ended dccoupled inputs should ensure sufficient signal swing above and
below the common-mode bias of the LO and REF buffers (i.e.,
1.75 V and VDDL/2). Note that the fREF input is slew rate
dependent and must be driven with input signals exceeding
7.5 V/µs to ensure proper synthesizer operation. If this condition cannot be met, an external logic gate can be inserted prior
to the fREF input to square up the signal, thus allowing an fREF
input frequency approaching dc.
is 3I0, and so forth, up to eight times the minimum output current. If the nominal charge pump current is more than the
minimum value, i.e., LOI > 0, the preceding rule is only applied
if it results in an increase in the instantaneous charge pump
current. If the charge pump current is set to its lowest value
(LOI = 0) and the fast acquire circuit is enabled, the instantaneous charge pump current will never fall below 2I0 when the
pulsewidth is less than T. Thus, the charge pump current when
fast acquire is enabled is given by
I PUMP–FA = I 0 × [1 = Max (1, LOI , Pulsewidth / T )]
(4)
The recommended setting for LOFA is LOR/16. Choosing a
larger value for LOFA will increase T. Thus, for a given phase
difference between the LO input and the fREF input, the instantaneous charge pump current will be less than that available for
a LOFA value of LOR/16. Similarly, a smaller value for LOFA
will decrease T, making more current available for the same
phase difference. In other words, a smaller value of LOFA will
enable the synthesizer to settle faster in response to a frequency
hop than will a large LOFA value. Care must be taken to choose
a value for LOFA that is large enough (values greater than 4
recommended) to prevent the loop from oscillating back and
forth in response to a frequency hop.
Table 12. SPI Registers Associated with LO Synthesizer
Address
(Hex)
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Bit Break–
down
(7:0)
(5:0)
(7:0)
(7:5)
(4:0)
(7:0)
(6)
(5)
(4:2)
(1:0)
(3:0)
(7:0)
Width
1
6
8
3
5
8
1
1
3
2
4
8
Default
Value
0xFF
0x00
0x38
0x5
0x00
0xiD
0
0
0
0
0x0
0x04
Name
STBY
LOR (13:8)
LOR (7:0)
LOA
LOB (12:8)
LOB(7:0)
LOF
LOINV
LOI
LOTM
LOFA(13:8)
LOFA(7:0)
FAST ACQUIRE MODE
The fast acquire circuit attempts to boost the output current
when the phase difference between the divided-down LO, i.e.,
fLO, and the divided-down reference frequency, i.e., fREF, exceeds
the threshold determined by the LOFA register. The LOFA
register specifies a divisor for the fREF signal that determines the
period (T) of this divided-down clock. This period defines the
time interval used in the fast acquire algorithm to control the
charge pump current.
CLOCK SYNTHESIZER
•
It does not include an 8/9 prescaler nor an A counter.
Assume for the moment that the nominal charge pump current
is at its lowest setting, i.e., LOI = 0, and denote this minimum
current by I0. When the output pulse from the phase comparator exceeds T, the output current for the next pulse is 2I0. When
the pulse is wider than 2T, the output current for the next pulse
•
It includes a negative-resistance core that, when used in
conjunction with an external LC tank and varactor, serves
as the VCO.
The clock synthesizer is a fully programmable integer-N PLL
capable of 2.2 kHz resolution at clock input frequencies up to
18 MHz and reference frequencies up to 25 MHz. It is similar
to the LO synthesizer described in Figure 38 with the following
exceptions:
Rev. 0 | Page 24 of 44
AD9864
The 14-bit reference counter and 13-bit N-divider counter can be
programmed via registers CKR and CKN. The clock frequency,
fCLK, is related to the reference frequency by the equation
f CLK = (CKN / CKR × f REF )
(5)
The charge pump current is programmable via the CKI register
from 0.625 mA to 5.0 mA using the equation
I PUMP = (CKI + 1) × 0.625 mA
(6)
The fast acquire subcircuit of the charge pump is controlled by
the CKFA register in the same manner the LO synthesizer is
controlled by the LOFA register. An on-chip lock detect function (enabled by the CKF bit) automatically increases the output current for faster settling during channel changes. The synthesizer may also be disabled using the CK standby bit located
in the STBY register.
VDDC = 3.0V
LOOP
FILTER
RD
RF
RBIAS
COSC
CLK source or VCO is used, the clock oscillator must be
disabled via the CKO standby bit.
The phase noise performance of the clock synthesizer is
dependent on several factors, including the CLK oscillator IBIAS
setting, charge pump setting, loop filter component values, and
internal fREF setting. Figure 41 and Figure 42 show how the
measured phase noise attributed to the clock synthesizer varies
(relative to an external fCLK) as a function of the IBIAS setting and
charge pump setting for a –31 dBm IFIN signal at 73.35 MHz
with an external LO signal at 71.1 MHz. Figure 41 shows that
the optimum phase noise is achieved with the highest IBIAS
(CKO) setting, while Figure 42 shows that the higher charge
pump values provide the optimum performance for the given
loop filter configuration. The AD9864 clock synthesizer and
oscillator were set up to provide an fCLK of 18 MHz from an
external fREF of 16.8 MHz. The following external component
values were selected for the synthesizer: RF = 390 Ω, RD = 2 kΩ,
CZ = 0.68 µF, CP = 0.1 µF, COSC = 91 pF, LOSC = 1.2 µH, and CVAR
= Toshiba 1SV228 Varactor.
LOSC
0
–10
0.1µF
CP
CVAR
–20
CZ
–30
–40
CLKP
–50
CLKN
VCM = VDDC – RBIAS × IBIAS > 1.6V
fOSC > 1/{2π × (LOSC × (CVARACTOR||COSC))1/2}
–60
–70
–80
CKO = 2
–90
–100
2
IBIAS = 0.15mA, 0.25mA,
0.40mA, OR 0.65mA
–110
04319-0-040
CLK OSC. BIAS
CK0 = 0
CKO = 3
CKO = 1
EXT CLK
–120
–130
–140
–25
Figure 40. External Loop Filter, Varactor, and LC Tank
Are Required to Realize a Complete Clock Synthesizer
–20
–15
–10
–5
0
5
10
15
20
25
FREQUENCY OFFSET (kHz)
The bias, IBIAS, of the negative-resistance core has four programmable settings. Lower equivalent Q of the LC tank circuit
may require a higher bias setting of the negative-resistance core
to ensure proper oscillation. RBIAS should be selected so the
common-mode voltage at CLKP and CLKN is approximately
1.6 V. The synthesizer may be disabled via the CK standby bit
to allow the user to employ an external synthesizer and/or VCO
in place of those resident on the IC. Note that if an external
Figure 41. CLK Phase Noise vs. IBIAS Setting (CKO) (IF = 73.35 MHz,
IF = 71.1 MHz, IFIN = –31 dBm, fCLK = 18 MHz, fREF = 16.8 MHz)
(CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60 with fREF = 300 kHz)
0
–10
–20
–30
–40
–50
dBc/Hz
The AD9864 clock synthesizer circuitry includes a negative
resistance core so that only an external LC tank circuit with a
varactor is needed to realize a voltage controlled clock oscillator
(VCO). Figure 40 shows the external components required to
complete the clock synthesizer along with the equivalent input
circuitry of the CLK input. The resonant frequency of the VCO
is approximately determined by LOSC and the series equivalent
capacitance of COSC and CVAR. As a result, LOSC, COSC, and CVAR
should be selected to provide a sufficient tuning range to ensure
proper locking of the clock synthesizer.
04319-0-041
AD9864
20
dBc/Hz
IOUTC
19
–60
–70
–80
CP = 0
–90
CP = 2
–100
–110
CP = 4
CP = 6
EXT CLK
–120
–130
–140
–25
–20
–15
–10
5
0
5
10
FREQUENCY OFFSET (kHz)
15
20
25
04319-0-042
15
Figure 42. CLK Phase Noise vs. IBIAS Setting (CKO) (IF = 73.35 MHz,
IF = 71.1 MHz, IFIN = –31 dBm, fCLK = 18 MHz, fREF = 16.8 MHz) (CLK SYN
Settings: CKO Bias = 3, CKR = 56, and CKN = 60 with fREF = 300 kHz
Rev. 0 | Page 25 of 44
AD9864
600
Table 13. SPI Registers Associated with CLK Synthesizer
Default
Value
0xFF
0
00
0x38
0x00
0x3C
0
0
0
0
0x0
0x04
Name
STBY
CKOB
CKR (13:8)
CKR (7:0)
CKN (12:8)
CKN (7:0)
CKF
CKINV
CKI
CKTM
CKFA (13:8)
CKFA (7:0)
550
300
0
50
100
250
150
200
FREQUENCY (MHz)
300
350
Figure 44. The Shunt Input Resistance vs.
the Frequency of the AD9864’s IF1 Input
L
C
MXOP
CAPACITANCE (pF)
1.5
1.0
0.5
0
0
50
100
200
150
250
FREQUENCY (MHz)
300
350
The mixer’s differential LO port is driven by the LO buffer
stage shown in Figure 43, which can be driven single-ended or
differential. Since it is self-biasing, the LO signal level can be
ac-coupled and range from 0.3 V p-p to 1.0 V p-p with negligible effect on performance. The mixer’s open-collector outputs,
MXOP and MXON, drive an external resonant tank consisting
of a differential LC network tuned to the IF of the band-pass
Σ-∆ ADC, i.e., fIF2_ADC = fCLK/8. The two inductors provide a dc
bias path for the mixer core via a series resistor of 50 Ω, which
is included to dampen the common-mode response. The
mixer’s output must be ac-coupled to the input of the bandpass Σ-∆ ADC, IF2P, and IF2N via two 100 pF capacitors to
ensure proper tuning of the LC center frequency.
50Ω
L
2.0
Figure 45. The Shunt Capacitance vs. the Frequency of the AD9864’s IF1 Input
2.7V TO 3.6V
MXON
CXVL
LO INPUT =
0.3V p-p TO
1.0V p-p
RGAIN
MULTI-TANH
V–I STAGE
CXIF
CXVM
IFIN
DC SERVO
LOOP
Figure 43. Simplified Schematic of AD9864’s LNA/Mixer
04319-0-043
RF
400
2.5
The AD9864 contains a single-ended LNA followed by a Gilbert-type active mixer, shown in Figure 43 with the required
external components. The LNA uses negative shunt feedback to
set its input impedance at the IFIN pin, thus making it dependent on the input frequency. It can be modeled as approximately
370 Ω||1.4 pF (±20%) below 100 MHz. Figure 44 and Figure 45
show the equivalent input impedance versus frequency characteristics of the AD9864. The increase in shunt resistance versus
frequency can be attributed to the reduction in bandwidth, thus
the amount of negative feedback of the LNA. Note that the
input signal into IFIN should be ac-coupled via a 10 nF capacitor since the LNA input is self-biasing.
RBIAS
450
350
IF LNA/MIXER
VDDI
500
04319-0-045
0x15
0x16
Width
8
2
6
8
5
8
1
1
3
1
4
8
04319-0-044
Bit
Breakdown
(7:0)
(3:2)
(5:0)
(7:0)
(4:0)
(7:0)
(6)
(5)
(4:2)
(1:0)
(3:0)
(7:0)
RESISTANCE (Ω)
Address
(Hex)
0x00
0x01
0x10
0x11
0x12
0x13
0x14
The external differential LC tank forms the resonant element for
the first resonator of the band-pass Σ-∆ modulator, and so must
be tuned to the fCLK/8 center frequency of the modulator. The
inductors should be chosen such that their impedance at fCLK/8 is
about 140, i.e., L = 180/fCLK. An accuracy of 20% is considered to
be adequate. For example, at fCLK = 18 MHz, L = 10 µH is a good
choice. Once the inductors have been selected, the required tank
capacitance may be calculated using the relation
Rev. 0 | Page 26 of 44
AD9864
]
EXTERNAL
LC
A 16 dB step attenuator is also included within the LNA/mixer
circuitry to prevent large signals (i.e., > –18 dBm) from overdriving the Σ-∆ modulator. In such instances, the Σ-∆ modulator will become unstable, thus severely desensitizing the
receiver. The 16 dB step attenuator can be invoked by setting
the ATTEN bit (Register 0x03, Bit 7), causing the mixer gain to
be reduced by 16 dB. The 16 dB step attenuator could be used
in applications in which a potential target or blocker signal
could exceed the IF input clip point. Although the LNA will be
driven into compression, it may still be possible to recover the
desired signal if it is FM. Refer to Table 14 to see the gain compression characteristics of the LNA and mixer with the 16 dB
attenuator enabled.
IF2P
fCLK = 13 MSPS TO 26 MSPS
RC
RESONATOR
IF2N
MXOP
SC
RESONATOR
NINELEVEL
FLASH
MXON
MIXER
OUTPUT
TO DIGITAL
FILTER
ESL
DAC1
04319-0-047
For example, at fCLK = 18 MHz and L = 10 µH, a capacitance of
250 pF is needed. However, in order to accommodate an inductor tolerance of ±10%, the tank capacitance must be adjustable
from 227 pF to 278 pF. Selecting an external capacitor of 180 pF
ensures that even with a 10% tolerance and stray capacitances
as high as 30 pF, the total capacitance will be less than the
minimum value needed by the tank. Extra capacitance is supplied by the AD9864’s on-chip programmable capacitor array.
Since the programming range of the capacitor array is at least
160 pF, the AD9864 has plenty of range to make up for the tolerances of low cost external components. Note that if fCLK is
increased by a factor of 1.44 MHz to 26 MHz so that fCLK/8
becomes 3.25 MHz, reducing L and C by approximately the
same factor (i.e., L = 6.9 µH and C = 120 pF) still satisfies the
requirements stated above.
GAIN
CONTROL
Figure 46. Equivalent Circuit of Sixth Order Band-Pass Σ-∆ Modulator
Figure 47 shows the measured power spectral density measured at
the output of the undecimated band-pass Σ-∆ modulator. Note
that the wide dynamic range achieved at the center frequency,
fCLK/8, is achieved once the LC and RC resonators of the Σ-∆
modulator have been successfully tuned. The out-of-band noise is
removed by the decimation filters following quadrature mixer.
0
–2dBFS OUTPUT
–10
fCLK = 18MHz
NBW = 3.3kHz
–20
–30
dBFS/NBW
[
f CLK / 8 = 1/ 2 × π × (2L × C )
–40
–50
–60
–70
–80
Address
(Hex)
0x00
0x03
Bit
Breakdown
(7:0)
(7)
Width
8
1
Default
Value
0xFF
0
–100
Name
STBY
ATTEN
BAND-PASS ∑-∆ ADC
The ADC of the AD9864 is shown in Figure 46. The ADC contains a sixth order multibit band-pass Σ-∆ modulator that
achieves very high instantaneous dynamic range over a narrow
frequency band. The loop filter of the band-pass Σ-∆ modulator
consists of two continuous-time resonators followed by a discrete
time resonator, with each resonator stage contributing a pair of
complex poles. The first resonator is an external LC tank, while
the second is an on-chip active RC filter. The output of the LC
resonator is ac-coupled to the second resonator input via 100 pF
capacitors. The center frequencies of these two continuous-time
resonators must be tuned to fCLK/8 for the ADC to function properly. The center frequency of the discrete-time resonator automatically scales with fCLK, thus no tuning is required.
0
1
2
3
4
5
FREQUENCY (MHz)
6
7
8
9
04319-0-048
–90
Table 14. SPI Registers Associated with LNA/Mixer
Figure 47. Measured Undecimated Spectral Output of Σ-∆
Modulator ADC with fCLK = 18 MSPS and Noise Bandwidth of 3.3 kHz
The signal transfer function of the AD9864 possesses inherent
anti-alias filtering by virtue of the continuous-time portions of
the loop filter in the band-pass Σ-∆ modulator. Figure 48 illustrates this property by plotting the nominal signal transfer
function of the ADC for frequencies up to 2fCLK. The notches
that naturally occur for all frequencies that alias to the fCLK/8
pass band are clearly visible. Even at the widest bandwidth setting, the notches are deep enough to provide greater than 80 dB
of alias protection. Thus, the wideband IF filtering requirements preceding the AD9864 will be determined mostly by the
mixer’s image band, which is offset from the desired IF input
frequency by fCLK/4 (i.e., 2 × fCLK/8) rather than any aliasing
associated with the ADC.
Rev. 0 | Page 27 of 44
AD9864
0
When tuning the LC tank, the sampling clock frequency must
be stable and the LNA/mixer, LO synthesizer, and ADC must
all be placed in standby. Large LO and IF signals present at the
inputs of the AD9864 can corrupt the calibration. These signals
should be minimized or disabled during the calibration
sequence. Tuning is triggered when the ADC is taken out of
standby if the TUNE_LC bit of Register 0x1C has been set. This
bit will clear when the tuning operation is complete (less than
6 ms). The tuning codes can be read from the 3-bit CAPL1
(0x1D) and the 6-bit CAPL0 (0x1E) registers.
–10
–20
dB
–30
NOTCH AT ALL ALIAS FREQUENCIES
–40
–50
–60
–80
0
0.5
1.0
1.5
2.0
NORMALIZED FREQUENCY (RELATIVE TO fOUT)
04319-0-049
–70
Figure 48. Signal Transfer Function of the Band-Pass Σ-∆
Modulator from 0 fCLK to 2fCLK
Figure 49 shows the nominal signal transfer function magnitude for frequencies near the fCLK/8 pass band. The width of the
pass band determines the transfer function droop, but even at
the lowest oversampling ratio (48) where the pass band edges
are at ±fCLK/192 (±0.005 fCLK), the gain variation is less than
0.5 dB. Note that the amount of attenuation offered by the signal transfer function near fCLK/8 should also be considered when
determining the narrow-band IF filtering requirements preceding the AD9864.
0
dB
–5
Table 15. Tuning Sequence
Address (Hex)
0x00
Value
0x45
0x1C
0x03
0x00
0x44
Comments
LO synthesizer, LNA/mixer, and
ADC are placed in standby.*
Set TUNE_LC and TUNE_RC. Wait
for CLK to stabilize if CLK
synthesizer used.
Take the ADC out of standby. Wait
for 0x1C to clear (<6 ms).
LNA/mixer can now be taken out
of standby
*If external CLK VCO or source used, the CLK oscillator must also be disabled.
Large IF or LO signals can corrupt the calibration; these signals should be
disabled during the calibration sequence.
–10
–15
Table 16. SPI Registers Associated with Band-Pass Σ-∆ ADC
–0.05
0
0.05
NORMALIZED FREQUENCY (RELATIVE TO fCLK)
0.10
04319-0-050
–20
–0.10
In a similar manner, tuning of the RC resonator is activated if
the TUNE_RC bit of Register 0x1C is set when the ADC is
taken out of standby. This bit will clear when tuning is complete. The tuning code can be read from the CAPR (0x1F)
register. Setting both the TUNE_LC and TUNE_RC bits tunes
the LC tank and the active RC resonator in succession. During
tuning, the ADC is not operational and neither data nor a clock
is available from the SSI port. Table 15 lists the recommended
sequence of the SPI commands for tuning the ADC, and
Table 16 lists all of the SPI registers associated with band-pass
Σ-∆ ADC.
Address
(Hex)
0x00
0x1C
Figure 49. Magnitude of the ADC’s Signal Transfer Function near fCLK/8
Tuning of the Σ-∆ modulator’s two continuous-time resonators
is essential in realizing the ADC’s full dynamic range and must
be performed upon system startup. To facilitate tuning of the
LC tank, a capacitor array is internally connected to the MXOP
and MXON pins. The capacitance of this array is programmable
from 0 pF to 200 pF ± 20% and can be programmed either
automatically or manually via the SPI port. The capacitors of
the active RC resonator are similarly programmable. Note that
the AD9864 can be placed in and out of its standby mode without retuning since the tuning codes are stored in the SPI Registers.
0x1D
0x1E
0x1F
Value
(7:0)
(1)
(0)
(2:0)
(5:0)
(7:0)
Width
8
1
1
3
6
8
Default
Value
0xFF
0
0
0
0x00
0x00
Name
STBY
TUNE_LC
TUNE_RC
CAPL1 (2:0)
CAPL1 (5:0)
CAPR
Once the AD9864 has been tuned, the noise figure degradation
attributed solely to the temperature drift of the LC and RC
resonators is minimal. Since the drift of the RC resonator is
actually negligible compared to that of the LC resonator, the
external L and C components’ temperature drift characteristics
tend to dominate. Figure 50 shows the degradation in noise
figure as the product of the LC value is allowed to vary from
–12.5% to +12.5%. Note that the noise figure remains relatively
Rev. 0 | Page 28 of 44
AD9864
constant over a ±3.5% range (i.e., ±35,000 ppm), suggesting
that most applications will not be required to retune over the
operating temperature range.
Note that signals falling around frequency offsets that are odd
integer multiples of fOUT/2 (i.e., 10 kHz, 30 kHz, and 50 kHz)
will fall back into the transition band of the digital filter.
12
0
±5.0kHz PASS BAND
FOLD–40 ING
POINT
dB
NF (dB)
–20
BW = 75kHz
11
10
–88dB
–60
–88dB
–101dB
BW = 30kHz
–103dB
–80
9
BW = 10kHz
–5
0
5
10
15
LC ERROR (%)
–120
120
0
The decimation filter shown in Figure 51 consists of an fCLK/8
complex mixer and a cascade of three linear phase FIR filters:
DEC1, DEC2, and DEC3. DEC1 downsamples by a factor of 12
using a fourth order comb filter. DEC2 also uses a fourth order
comb filter, but its decimation factor is set by the M field of
Register 0x07. DEC3 is either a decimate-by-5 FIR filter or a
decimate-by-4 FIR filter, depending on the value of the K bit
within Register 0x07. Thus, the composite decimation factor
can be set to either 60 × M or 48 × M for K equal to 0 or 1,
respectively.
The output data rate (fOUT) is equal to the modulator clock frequency (fCLK) divided by the digital filter’s decimation factor.
Due to the transition region associated with the decimation
filter’s frequency response, the decimation factor must be
selected such that fOUT is equal to or greater than twice the signal bandwidth. This ensures low amplitude ripple in the pass
band along with the ability to provide further applicationspecific digital filtering prior to demodulation.
DEC1
SIN
SINC4
FILTER
DEC2
12
SINC4
FILTER
M+1
DEC3
FIR
FILTER
40
50
60
FREQUENCY (kHz)
70
80
90
100
0
–20
–60
Figure 52 shows the response of the decimation filter at a decimation factor of 900 (K = 0, M = 14) and a sampling clock frequency of 18 MHz. In this example, the output data rate (fOUT)
is 20 kSPS, with a usable complex signal bandwidth of 10 kHz
centered around dc. As this figure shows, the first and second
alias bands (occurring at even integer multiples of fOUT/2) have
the least attenuation but provide at least 88 dB of attenuation.
–94dB
–115dB
–100
I
Figure 51. Decimation Filter Architecture
–98dB
–80
–120
COMPLEX
4 DATA TO
OR SSI PORT
5 Q
±135.466kHz PASS BAND
–40
K
04319-0-052
DATA
FROM Σ-∆
MODULATOR
30
Figure 53 shows the response of the decimation filter with a
decimation factor of 48 and a sampling clock rate of 26 MHz.
The alias attenuation is at least 94 dB and occurs for frequencies at the edges of the fourth alias band. The difference
between the alias attenuation characteristics of Figure 52 and
those of Figure 53 is due to the fact that the third decimation
stage decimates by a factor of 5 for Figure 52 compared with a
factor of 4 for Figure 53.
dB
DECIMATION FILTER
M
20
Figure 52. Decimation Filter Frequency Response for
fOUT = 20 kSPS (fCLK = 18 MHz, OSR = 900)
Figure 50. Typical Noise Figure Degradation from L and C
Component Drift (fCLK = 18 MSPS, fIF = 73.3501 MHz)
COS
10
0
0.5
1.0
1.5
FREQUENCY
EQUENCY (MHz)
2.0
2.5
04319-0-054
–10
04319-0-051
8
–15
04319-0-053
–100
Figure 53. Decimation Filter Frequency Response for
fOUT = 541.666 kSPS (fCLK = 26 MHz, OSR = 48)
Figure 54 and Figure 55 show expanded views of the pass band
for the two possible configurations of the third decimation filter. When decimating by 60n (K = 0), the pass-band gain variation is 1.2 dB; when decimating by 48n (K = 1), the pass-band
gain variation is 0.9 dB. Normalization of full scale at band
center is accurate to within 0.14 dB across all decimation
modes. Figure 56 and Figure 57 show the folded frequency
response of the decimator for K = 0 and K = 1, respectively.
Rev. 0 | Page 29 of 44
AD9864
3
0
2
–20
PASS-BAND GAIN FREQUENCY = 1.2dB
–40
0
dB
dB
1
–60
–1
–80
–2
–100
0
0.125
NORMALIZED FREQUENCY (RELATIVE TO fOUT)
0.250
–120
Figure 54. Pass-Band Frequency Response of the Decimator for K = 0
3
PASS-BAND GAIN VARIATION = 0.9dB
dB
1
0
–1
0
0.125
NORMALIZED FREQUENCY (RELATIVE TO fOUT)
0.250
04319-0-056
–2
Figure 55. Pass-Band Frequency Response of the Decimator for K = 1
0
0.50
Figure 57. Folded Decimator Frequency Response for K = 1
–40
–60
MIN ALIAS ATTN = 87.7dB
–80
0
0.25
NORMALIZED FREQUENCY (RELATIVE TO fOUT)
0.50
Figure 56. Folded Decimator Frequency Response for K = 0
04319-0-057
–100
–120
The AD9864 contains both a variable gain amplifier (VGA) and a
digital VGA (DVGA) along with all of the necessary signal estimation
and control circuitry required to implement automatic gain control
(AGC), as shown in Figure 58. The AGC control circuitry provides a
high degree of programmability, allowing users to optimize the AGC
response as well as the AD9864’s dynamic range for a given application. The VGA is programmable over a 12 dB range and implemented
within the ADC by adjusting its full-scale reference level. Increasing the
ADC’s full scale is equivalent to attenuating the signal. An additional
12 dB of digital gain range is achieved by scaling the output of the
decimation filter in the DVGA. Note that a slight increase in the supply
current (i.e., 0.67 mA) is drawn from VDDI and VDDF as the VGA
changes from 0 dB to 12 dB attenuation.
The purpose of the VGA is to extend the usable dynamic range of the
AD9864 by allowing the ADC to digitize a desired signal over a large
input power range as well as recover a low level signal in the presence
of larger unfiltered interferers without saturating or clipping the ADC.
The DVGA is most useful in extending the dynamic range in narrowband applications requiring a 16-bit I and Q data format. In these
applications, quantization noise resulting from internal truncation to
16 bits as well as external 16-bit fixed point post processing can
degrade the AD9864’s effective noise figure by 1 dB or more.
–20
dB
0.25
NORMALIZED FREQUENCY (RELATIVE TO fOUT)
VARIABLE GAIN AMPLIFIER OPERATION WITH
AUTOMATIC GAIN CONTROL
2
–3
0
04319-0-058
–3
04319-0-055
MIN ALIAS ATTN = 97.2dB
The DVGA is enabled by writing a 1 to the AGCV field. The VGA
(and the DVGA) can operate in either a user controlled variable gain
mode or automatic gain control (AGC) mode. It is worth noting that
the VGA imparts negligible phase error upon the desired signal as its
gain is varied over a 12 dB range. This is due to the bandwidth of the
VGA being far greater than the down converted desired signal (centered about fCLK/8) and remaining relatively independent of gain
setting. As a result, phase modulated signals should experience minimal phase error as the AGC varies the VGA gain while tracking an
interferer or the desired signal under fading conditions. Note that the
envelope of the signal will still be affected by the AGC settings.
Rev. 0 | Page 30 of 44
AD9864
Σ-∆ ADC
FS
I/Q DATA
TO SSI
DEC2
AND
DEC3
DEC1
C1
÷12
DVGA
AGCR
REF LEVEL
I + Q
SELECT
LARGER
+
K
1
(1 – Z–1)
I + Q
AGCA/AGCD
SCALING
VGA
DAC
AGCV
CV
SETTING
RSSI DATA
TO SSI
04319-0-059
GCP
CDAC
Figure 58. Functional Block Diagram of VGA and AGC
VARIABLE GAIN CONTROL
The variable gain control is enabled by setting the AGCR field
of Register 0x06 to 0. In this mode, the gain of the VGA (and
the DVGA) can be adjusted by writing to the 16-bit AGCG
register. The maximum update rate of the AGCG register via
the SPI port is fCLK/240. The MSB of this register is the bit that
enables 16 dB of attenuation in the mixer. This feature allows
the AD9864 to cope with large level signals beyond the VGA’s
range (i.e., > –18 dBm at LNA input) to prevent overloading of
the ADC.
The lower 15 bits specify the attenuation in the remainder of
the signal path. If the DVGA is enabled, the attenuation range
is from –12 dB to +12 dB since the DVGA provides 12 dB of
digital gain. In this case, all 15 bits are significant. However,
with the DVGA disabled, the attenuation range extends from
0 dB to 12 dB and only the lower 14 bits are useful. Figure 59
shows the relationship between the amount of attenuation and
the AGC register setting for both cases.
12
VGA
RANGE
6
DVGA AND
VGA ENABLED
0
DVGA
RANGE
–6
–12
0000
1FFF
3FFF
5FFF
7FFF
AGCG SETTING (HEX)
A linear estimate of the received signal strength is performed at
the output of the first decimation stage (DEC1) and output of
the DVGA (if enabled), as discussed in the AGC section. This
data is available as a 6-bit RSSI field within an SSI frame with
60 corresponding to a full-scale signal for a given AGC attenuation setting. The RSSI field is updated at fCLK/60 and can be used
with the 8-bit attenuation field (or AGCG attenuation setting)
to determine the absolute signal strength.
The accuracy of the mean RSSI reading (relative to the IF input
power) depends on the input signal’s frequency offset relative
to the IF frequency since both DEC1 filter’s response as well as
the ADC’s signal transfer function attenuate the mixer’s
downconverted signal level centered at fCLK/8. As a result, the
estimated signal strength of input signals falling within proximity to the IF is reported accurately, while those signals at
increasingly higher frequency offsets incur larger measurement
errors. Figure 60 shows the normalized error of the RSSI reading as a function of the frequency offset from the IF frequency.
Note that the significance of this error becomes apparent when
determining the maximum input interferer (or blocker) levels
with the AGC enabled.
04319-0-060
AGC ATTENUATION (dB)
ONLY
VGA ENABLED
ing at the gain control pin (GCP). For applications implementing automatic gain control, the DAC’s output resistance can be
reduced by a factor of 9 to decrease the attack time of the AGC
response for faster signal acquisition. An external capacitor,
CDAC, from GCP to analog ground is required to smooth the
DAC’s output each time it updates as well as to filter wideband
noise. Note that CDAC, in combination with the DAC’s programmable output resistance, sets the –3 dB bandwidth and
time constant associated with this RC network.
Figure 59. AGC Gain Range Characteristics vs. AGCG Register
Setting with and without DVGA Enabled
Referring to Figure 58, the gain of the VGA is set by an 8-bit
control DAC that provides a control signal to the VGA appearRev. 0 | Page 31 of 44
AD9864
0
Signal estimation after the first decimation stage allows the
AGC to cope with out-of-band interferers and in-band signals
that could otherwise overload the ADC. Signal estimation after
the DVGA allows the AGC to minimize the effects of the 16-bit
truncation noise.
MEASURED RSSI ERROR (dB)
–3
–6
When the estimated signal level falls within the range of the
AGC, the AGC loop adjusts the VGA (or DVGA) attenuation
setting so that the estimated signal level is equal to the programmed level specified in the AGCR field. The absolute signal
strength can be determined from the contents of the ATTN and
RSSI field that is available in the SSI data frame when properly
configured. Within this AGC tracking range, the 6-bit value in
the RSSI field remains constant while the 8-bit ATTN field varies according to the VGA/DVGA setting. Note that the ATTN
value is based on the 8 MSB contained in the AGCG field of
Registers 0x03 and 0x04.
–9
–12
–18
0
0.01
0.02
0.03
0.04
NORMALIZED FREQUENCY OFFSET ((fIN–fIF) fCLK)
0.05
04319-0-061
–15
Figure 60. Normalized RSSI Error vs. Normalized IF Frequency Offset
AUTOMATIC GAIN CONTROL (AGC)
The gain of the VGA (and DVGA) is automatically adjusted
when the AGC is enabled via the AGCR field of Register 0x06.
In this mode, the gain of the VGA is continuously updated at
fCLK/60 in an attempt to ensure that the maximum analog signal
level into the ADC does not exceed the ADC clip level and that
the rms output level of the ADC is equal to a programmable
reference level. With the DVGA enabled, the AGC control loop
also attempts to minimize the effects of 16-bit truncation noise
prior to the SSI output by continuously adjusting the DVGA’s
gain to ensure maximum digital gain while not exceeding the
programmable reference level.
This programmable level can be set at 3 dB, 6 dB, 9 dB, 12 dB,
and 15 dB below the ADC saturation (clip) level by writing
values from 1 to 5 to the 3-bit AGCR field. Note that the ADC
clip level is defined to be 2 dB below its full scale (i.e., –18 dBm
at the LNA input for a matched input and maximum attenuation). If AGCR is 0, automatic gain control is disabled. Since
clipping of the ADC input will degrade the SNR performance,
the reference level should also take into consideration the peakto-rms characteristics of the target (or interferer) signals.
The 4-bit code in the AGCA field sets the raw bandwidth of the
AGC loop. With AGCA = 0, the AGC loop bandwidth is at its
minimum of 50 Hz, assuming fCLK = 18 MHz. Each increment
of AGCA increases the loop bandwidth by a factor of √2; thus
the maximum bandwidth is 9 kHz. A general expression for the
attack bandwidth is
Referring again to Figure 58, the majority of the AGC loop
operates in the discrete time domain. The sample rate of the
loop is fCLK/60; therefore, registers associated with the AGC
algorithm are updated at this rate. The number of overload and
ADC reset occurrences within the final I/Q update rate of the
AD9864, as well as the AGC value (8 MSB), can be read from
the SSI data upon proper configuration.
BWA = 50 × ( f CLK /18 MHz )× 2 ( AGCA / 2 ) Hz
(8)
and the corresponding attack time is
(
)
t ATTACK = 2.2 / 100 × π × 2 ( AGCA / 2 ) = 35 / BWA
The AGC performs digital signal estimation at the output of the
first decimation stage (DEC1) as well as the DVGA output that
follows the last decimation stage (DEC3). The rms power of the
I and Q signal is estimated by the equation
Xest [n] = Abs(I [n]) + Abs(Q[n])
A description of the AGC control algorithm and the user
adjustable parameters follows. First, consider the case in which
the in-band target signal is bigger than all out-of-band interferers and the DVGA is disabled. With the DVGA disabled, a
control loop based only on the target signal power measured
after DEC1 is used to control the VGA gain, and the target
signal will be tracked to the programmed reference level. If the
signal is too large, the attenuation is increased with a proportionality constant determined by the AGCA setting. Large
AGCA values result in large gain changes, thus rapid tracking
of changes in signal strength. If the target signal is too small
relative to the reference level, the attenuation is reduced; but
now the proportionality constant is determined by both the
AGCA and AGCD settings. The AGCD value is effectively
subtracted from AGCA, so a large AGCD results in smaller
gain changes and thus slower tracking of fading signals.
(7)
assuming that the loop dynamics are essentially those of a
single-pole system.
The 4-bit code in the AGCD field sets the ratio of the attack
time to the decay time in the amplitude estimation circuitry.
When AGCD is zero, this ratio is one. Incrementing AGCD
multiplies the decay time constant by 21/2, allowing a 180:1
Rev. 0 | Page 32 of 44
(9)
AD9864
128
range in the decay time relative to the attack time. The decay
time may be computed from
Figure 61 shows the AGC response to a 30 Hz pulse-modulated
IF burst for different AGCA and AGCD settings. The 3-bit
value in the AGCO field determines the amount of attenuation
added in response to a reset event in the ADC. Each increment
in AGCO doubles the weighting factor. At the highest AGCO
setting, the attenuation will change from 0 dB to 12 dB in
approximately 10 µs, while at the lowest setting the attenuation
will change from 0 dB to 12 dB in approximately 1.2 ms. Both
times assume fCLK = 18 MHz. Figure 62 shows the AGC attack
time response for different AGCO settings.
AGCA = 0
96
AGCD = 8
80
48
AGCD = 0
16
VGA ATTENUATION SETTING
0
AGCA = 4
96
80
AGCO = 7
80
64
AGCO = 4
48
32
AGCD = 0
16
0
0
0.1
0.2
0.3
0.4
0.5
0.6
TIME (ms)
0.7
0.8
0.9
1.0
Figure 62. AGC Response for Different AGCO Settings with fCLK = 18 MSPS,
fCLKOUT = 300 kSPS, Decimate by 60 and AGCA = AGCD = 0
Lastly, the AGCF bit reduces the DAC source resistance by at
least a factor of 10. This facilitates fast acquisition by lowering
the RC time constant that is formed with the external capacitors connected from the GCP pin to ground (GCN pin). For an
overshoot-free step response in the AGC loop, the capacitor
connected from the GCP pin to the GCN ground pin should be
chosen so that the RC time constant is less than one quarter of
the raw loop. Specifically
64
32
96
04319-0-063
(10)
VGA ATTENUATION SETTING
t DECAY = t ATTACK × 2 ( AGCD / 2 )
112
AGCD = 8
64
RC < 1/(8πBW )
48
(11)
AGCD = 0
32
16
0
AGCA = 8
96
80
AGCD = 8
64
48
32
0
0
10
20
30
TIME (ms)
40
50
04319-0-062
AGCD = 0
16
Figure 61. AGC Response for Different AGCA and AGCD Settings with
fCLK = 18 MSPS, fCLKOUT = 20 kSPS, Decimate by 900, and AGCO = 0
where R is the resistance between the GCP pin and ground
(72.5 kΩ ±30% if AGCF = 0, < 8 kΩ if AGCF = 1) and BW is
the raw loop bandwidth. Note that with C chosen at this upper
limit, the loop bandwidth increases by approximately 30%.
Now consider the case described above but with the DVGA
enabled to minimize the effects of 16-bit truncation. With the
DVGA enabled, a control loop based on the larger of the two
estimated signal levels, i.e., output of DEC1 and DVGA, is used
to control the DVGA gain. The DVGA multiplies the output of
the decimation filter by a factor of 1 to 4, i.e., 0 dB to 12 dB.
When signals are small, the DVGA gain is 4 and the 16-bit output is extracted from the 24-bit data produced by the decimation filter by dropping 2 MSB and taking the next 16 bits. As
signals get larger, the DVGA gain decreases to the point where
the DVGA gain is 1 and the 16-bit output data is simply the
16 MSB of the internal 24-bit data. As signals get even larger,
attenuation is accomplished by the normal method of increasing the ADC’s full scale.
The extra 12 dB of gain range provided by the DVGA reduces
the input-referred truncation noise by 12 dB and makes the
data more tolerant of LSB corruption within the DSP. The price
paid for this extension to the gain range is that the start of AGC
action is 12 dB lower and that the AGC loop will be unstable if
its bandwidth is set too wide. The latter difficulty results from
the large delay of the decimation filters, DEC2 and DEC3, when
one implements a large decimation factor. As a result, given an
Rev. 0 | Page 33 of 44
AD9864
DECIMATION FACTOR
M
60
0
120
1
300
4
540
8
900
E
AGCA
4 5 6
7
8
9
10 11 12 13 14 15
–3
–6
–9
–12
–15
0
0.01
0.02
0.04
0.03
0.05
NORMALIZED FREQUENCY OFFSET = (fIN–fIF)/fCLK
04319-0-064
Table 17. AGCA Limits if the DVGA Is Enabled
0
RELATIVE TO CLIP POINT (dBFS)
option, the use of 24-bit data is preferable to using the DVGA.
Table 17 indicates which AGCA values are reasonable for
various decimation factors. The white cells indicate that the
(decimation factor/AGCA) combination works well; the light gray
cells indicate ringing and an increase in the AGC settling time; and
the dark gray cells indicate that the combination results in instability
or near instability in the AGC loop. Setting AGCF = 1 improves the
time-domain behavior at the expense of increased spectral spreading.
Figure 63. Maximum Interferer (or Blocker) Input Level
vs. Normalized IF Frequency Offset
Table 18. SPI Registers Associated with AGC
Finally, consider the case of a strong out-of-band interferer
(i.e., –18 dBm to –32 dBm for matched IF input) that is larger
than the target signal and large enough to be tracked by the
control loop based on the output of the DEC1. The ability of
the control loop to track this interferer and set the VGA
attenuation to prevent clipping of the ADC is limited by the
accuracy of the digital signal estimation occurring at the output
of DEC1. The accuracy of the digital signal estimation is a
function of the frequency offset of the out-of-band interferer
relative to the IF frequency as shown in Figure 60. Interferers at
increasingly higher frequency offsets incur larger measurement
errors, potentially causing the control loop to inadvertently
reduce the amount of VGA attenuation that may result in clipping of the ADC. Figure 63 shows the maximum measured
interferer signal level versus the normalized IF offset frequency
(relative to fCLK) tolerated by the AD9864 relative to its maximum target input signal level (0 dBFS = –18 dBm). Note that
the increase in allowable interferer level occurring beyond
0.04 × fCLK results from the inherent signal attenuation provided
by the ADC’s signal transfer function.
Address
(Hex)
0x03
0x04
0x05
0x06
Bit
Breakdown
(7)
(6:0)
(7:0)
(7:4)
(3:0)
(7)
(6:4)
(3)
(2:0)
Width
1
7
8
4
4
1
3
1
3
Default
Value
0
0x00
0x00
0
0x00
0
0
0
0
Name
ATTEN
AGCG (14:8)
AGCG (7:0)
AGCA
AGCO
AGCV
AGCO
AGCF
AGCR
SYSTEM NOISE FIGURE (NF) VERSUS VGA (OR
AGC) CONTROL
The AD9864’s system noise figure is a function of the ACG
attenuation and output signal bandwidth. Figure 64 plots the
nominal system NF as a function of the AGC attenuation for
both narrow-band (20 kHz) and wideband (150 kHz) modes
with fCLK = 18 MHz. Also shown on the plot is the SNR that
would be observed at the output for a –2 dBFS input. The high
dynamic range of the ADC within the AD9864 ensures that the
system NF increases gradually as the AGC attenuation is
increased. In narrow-band (BW = 20 kHz) mode, the system
noise figure increases by less than 3 dB over a 12 dB AGC
range, while in wideband (BW = 150 kHz) mode, the degradation is about 5 dB. As a result, the highest instantaneous
dynamic range for the AD9864 occurs with 12 dB of AGC
attenuation, since the AD9864 can accommodate an additional
12 dB peak signal level with only a moderate increase in its
noise floor.
As Figure 64 shows, the AD9864 can achieve an SNR in excess
of 100 dB in narrow-band applications. To realize the full
performance of the AD9864 in such applications, it is recommended that the I/Q data be represented with 24 bits. If 16-bit
Rev. 0 | Page 34 of 44
AD9864
data is used, the effective system NF will increase because of the
quantization noise present in the 16-bit data after truncation.
SNR = 90.1dBFS
14
13
NOISE FIGURE (dB)
Frequency Planning
The LO frequency (and/or ADC clock frequency) must be chosen
carefully to prevent known internally generated spurs from mixing
down along with the desired signal, thus degrading the SNR performance. The major sources of spurs in the AD9864 are the ADC
clock and digital circuitry operating at 1/3 of fCLK. Thus, the clock
frequency (fCLK) is the most important variable in determining
which LO (and therefore IF) frequencies are viable.
15
BW = 50kHz
12
APPLICATIONS CONSIDERATIONS
BW = 150kHz
11
SNR = 103.2dB
SNR = 82.9dBFS
10
8
SNR = 95.1dBFS
0
3
6
9
12
VGA ATTENUATION (dB)
04319-0-065
BW = 10kHz
9
Figure 64. Nominal System Noise Figure and Peak SNR vs. AGCG Setting (fIF =
73.35 MHz, fCLK = 18 MSPS, and 24-bit I/Q Data)
Figure 65 plots the nominal system NF with 16-bit output data
as a function of AGC in both narrow-band and wideband
mode. In wideband mode, the NF curve is virtually unchanged
relative to the 24-bit output data because the output SNR before
truncation is always less than the 96 dB SNR that 16-bit data
can support. However, in narrow-band mode, where the output
SNR approaches or exceeds the SNR that can be supported with
16-bit data, the degradation in system NF is more severe. Furthermore, if the signal processing within the DSP adds noise at
the level of an LSB, the system noise figure can be degraded
even more than Figure 65 shows. For example, this could occur
in a fixed 16-bit DSP whose code is not optimized to process
the AD9864’s 16-bit data with minimal quantization effects. To
limit the quantization effects within the AD9864, the 24-bit
data undergoes noise shaping just prior to 16-bit truncation,
thus reducing the in-band quantization noise by 5 dB (with 2×
oversampling). This explains why 98.8 dBFS SNR performance
is still achievable with 16-bit data in a 10 kHz BW.
17
NOISE FIGURE (dB)
Figure 66 plots the measured in-band noise power as a function
of the LO frequency for fCLK = 18 MHz and an output signal
bandwidth of 150 kHz when no signal is present. Any LO
frequency resulting in large spurs should be avoided. As this
figure shows, large spurs result when the LO is fCLK/8 = 2.25
MHz away from a harmonic of 18 MHz , i.e., n fCLK ± fCLK/8.
Also problematic are LO frequencies whose odd order harmonics, i.e., m fLO, mix with harmonics of fCLK to fCLK/8. This spur
mechanism is a result of the mixer being internally driven
by a squared-up version of the LO input consisting of the LO
frequency and its odd order harmonics. These spur frequencies
can be calculated from the relation
m × f LO = (n ± 1/ 8 ) × f CLK
(12)
where m = 1, 3, 5... and n = 1, 2, 3...
A second source of spurs is a large block of digital circuitry that
is clocked at fCLK/3. Problematic LO frequencies associated with
this spur source are given by
SNR = 98.8dBFS
16
15
Many applications have frequency plans that take advantage of
industry-standard IF frequencies due to the large selection of
low cost crystal or SAW filters. If the selected IF frequency and
ADC clock rate result in a problematic spurious component, an
alternative ADC clock rate should be selected by slightly modifying the decimation factor and CLK synthesizer settings (if
used) such that the output sample rate remains the same. Also,
applications requiring a certain degree of tuning range should
take into consideration the location and magnitude of these
spurs when determining the tuning range as well as optimum
IF and ADC clock frequency.
BW = 10kHz
f LO = f CLK / 3 + n × f CLK ± f CLK / 8
14
13
(13)
where n = 1, 2, 3...
BW = 150kHz
12
SNR = 89.9dBFS
11
SNR = 94.1dBFS
10
SNR = 83dBFS
8
0
3
6
VGA ATTENUATION (dB)
9
12
Figure 65. Nominal System Noise Figure and Peak SNR vs. AGCG
Setting (fIF = 73.35 MHz, fCLK = 18 MSPS, and 16-bit I/Q Data)
04319-0-066
BW = 50kHz
9
Figure 67 shows that omitting the LO frequencies given by
Equation 12 for m = 1, 3, and 5 and by Equation 13 accounts
for most of the spurs. Some of the remaining low level spurs
can be attributed to coupling from the SSI digital output. As a
result, users are also advised to optimize the output bit rate
(fCLKOUT via the SSIORD register) and the digital output driver
strength to achieve the lowest spurious and noise figure performance for a particular LO frequency and fCLK setting. This is
especially the case for particularly narrow-band channels in
Rev. 0 | Page 35 of 44
AD9864
which low level spurs can degrade the AD9864’s sensitivity
performance.
bandwidth of the AD9864. As evidence of this property,
Figure 68 shows that the in-band noise is quite constant for LO
frequencies ranging from 70 MHz to 71 MHz.
Despite the many spurs, sweet spots in the LO frequency are
generally wide enough to accommodate the maximum signal
–60
–70
–80
–90
50
0
100
150
200
250
300
LO FREQUENCY (MHz)
04319-0-067
IN-BAND POWER (dBFS)
–50
Figure 66. Total In-Band Noise + Spur Power with No Signal Applied as a Function of the LO Frequency (fCLK = 18 MHz and Output Signal Bandwidth = 150 kHz)
–60
–70
–80
–90
0
50
100
150
200
250
LO FREQUENCY (MHz)
Figure 67. Same as Figure 66 Excluding LO Frequencies Known to Produce Large In-Band Spurs
Rev. 0 | Page 36 of 44
300
04319-0-068
IN-BAND POWER (dBFS)
–50
AD9864
giving a selectivity of 90 dB for this spurious response. The
largest spurious response at approximately –70 dBFS occurs
with input frequencies of 70.35 MHz and 71.85 MHz. These
spurs result from third order nonlinearity in the signal path
(i.e., abs [3 × fLO – 3 × fIF_INPUT] = fCLK /8).
–60
–80
Figure 70 shows an example circuit using the AD9864 and
Table 19 shows the nominal dc bias voltages seen at the different pins. The purpose is to show the various external passive
components required by the AD9864, along with nominal dc
voltages for troubleshooting purposes.
100pF
–60
2.2nF
1nF
GNDS 34
4 IF2N
5 IF2P
SYNCB 33
GNDH 32
AD9864
6 VDDF
7 GCP
FS 31
DOUTB 30
80
90
100
PC
GNDD
GNDS
CLKN
CLKP
GNDC
VDDC
PE 25
13 14 15 16 17 18 19 20 21 22 23 24
100kΩ
Figure 69. Response of AD9864 to a –20 dBm IF Input when fLO = 71.1 MHz
SPURIOUS RESPONSES
VDDD 26
10nF
10nF
04319-0-071
70
IF FREQUENCY (MHz)
11 VREFP
12 VREFN
100pF
04319-0-070
60
10 GNDA
GNDQ
10nF
CLKOUT 28
VDDH 27
IOUTC
–100
DOUTA 29
9 VDDA
VDDQ
100pF
GNDP
IOUTL
VDDL
VDDP
CXVM
LOP
LON
GNDI
CXVL
IFIN
GNDL 36
FREF 35
3 GNDF
8 GCN
–80
–120
50
1 MXOP
2 MXON
PD
100
pF
100nF
10nF
DESIRED
RESPONSES
48 47 46 45 44 43 42 41 40 39 38 37
RREF
dBFS
–40
180pF
VDDI
D = fCLK/4 = 4.5MHz
–20
10µH
LC TANK
0
100nF
50Ω
Figure 68. Expanded View from 70 MHz to 71 MHz
CXIF
71.0
70.5
LO FREQUENCY (MHz)
10µH
–90
70.0
10nF
EXTERNAL PASSIVE COMPONENT REQUIREMENTS
10nF
–70
04319-0-069
IN-BAND POWER (dBFS)
–50
Figure 70. Example Circuit Showing Recommended Component Values
The spectral purity of the LO (including its phase noise) is an
important consideration since LO spurs can mix with undesired signals present at the AD9864’s IFIN input to produce an
in-band response. To demonstrate the low LO spur level introduced within the AD9864, Figure 69 plots the demodulated
output power as a function of the input IF frequency for an LO
frequency of 71.1 MHz and a clock frequency of 18 MHz.
The two large –10 dBFS spikes near the center of the plot are
the desired responses at fLO, ± fIF2_ADC, where fIF2_ADC = fCLK/8, i.e.,
at 68.85 MHz and 73.35 MHz. LO spurs at fLO ± fSPUR would
result in spurious responses at offsets of ± fSPUR around the
desired responses. Close-in spurs of this kind are not visible on
the plot, but small spurious responses at fLO ± fIF2_ADC ± fCLK, i.e.,
at 50.85 MHz, 55.35 MHz, 86.85 MHz, and 91.35 MHz, are
visible at the –90 dBFS level. This data indicates that the
AD9864 does an excellent job of preserving the purity of the LO
signal.
Figure 69 can also be used to gauge how well the AD9864
rejects undesired signals. For example, the half-IF response (at
69.975 MHz and 72.225 MHz) is approximately –100 dBFS,
Table 19. Nominal DC Bias Voltages
Pin Number
1
2
4
5
11
12
13
19
20
35
41
42
43
44
46
47
Rev. 0 | Page 37 of 44
Mnemonic
MXOP
MXON
IF2N
IF2P
VREFP
VREFN
RREF
CLKP
CLKN
FREF
CXVM
LON
LOP
CXVL
CXIF
IFIN
Nominal DC Bias (V)
VDDI – 0.2
VDDI – 0.2
1.3 – 1.7
1.3 – 1.7
VDDA/2 + 0.250
VDDA/2 – 0.250
1.2
VDDC – 1.3
VDDC – 1.3
VDDC/2
1.6 – 2.0
1.65 – 1.9
1.65 – 1.9
VDDI – 0.05
1.6 – 2.0
0.9 – 1.1
AD9864
The LO, CLK, and IFIN signals are coupled to their respective
inputs using 10 nF capacitors. The output of the mixer is coupled to the input of the ADC using 100 pF. An external 100 kΩ
resistor from the RREF pin to GND sets up the AD9864’s
internal bias currents. VREFP and VREFN provide a differential reference voltage to the AD9864’s Σ-∆ ADC and must be
decoupled by a 0.01 µF differential capacitor along with two
100 pF capacitors to GND. The remaining capacitors are used
to decouple other sensitive internal nodes to GND.
clock. For example, if fCLK = 26 MHz, the two inductors should
be = 6.9 µH and the capacitor should be about 120 pF. A tolerance of 10% is sufficient for these components since tuning of
the LC tank is performed upon system startup.
APPLICATIONS
SuperHeterodyne Receiver Example
The AD9864 is well suited for analog and/or digital narrow-band
radio systems based on a superheterodyne receiver architecture. The
superheterodyne architecture is noted for achieving exceptional
dynamic range and selectivity by using two or more downconversion
stages to provide amplification of the target signal while filtering the
undesired signals. The AD9864 greatly simplifies the design of these
radio systems by integrating the complete IF strip (excluding the LO
VCO) while providing an I/Q digital output (along with other system parameters) for the demodulation of both analog and digital
modulated signals. The AD9864’s exceptional dynamic range often
simplifies the IF filtering requirements and eliminates the need for an
external AGC.
Although power supply decoupling capacitors are not shown, it
is recommended that a 0.1 µF surface-mount capacitor be
placed as close as possible to each power supply pin for maximum effectiveness. Also not shown is the input impedance
matching network used to match the AD9864’s IF input to the
external IF filter. Lastly, the loop filter components associated
with the LO and CLK synthesizers are not shown.
LC component values for fCLK = 18 MHz are given Figure 70.
For other clock frequencies, the two inductors and the capacitor of the LC tank should be scaled in inverse proportion to the
VDDA
TUNER
AD9864
DAC AGC
–16dB
DOUTA
IFIN
LNA
GCN
GCP
II-2P
II-2N
VXOP
IF CRYSTAL OR
SAW FILTER
Σ-∆ ADC
LNA
DECIMATION
FILTER
FORMATTING/SSI
DOUTB
FS
TO
DSP
CLKOUT
CONTROL LOGIC
VCO
SAMPLE CLOCK
SYNTHESIZER
LO
SYNTH.
LOOP
FILTER
VCO
SYNCB
PE
PD
PC
RREF
VREFN
VREFP
CLKN
CLKP
IOUTC
REFIN
VOLTAGE
REFERENCE
SPI
LON
ADF42xx
PLL SYN
LOP
LOOP
FILTER
VDDC
CRYSTAL
OSCILLATOR
FROM DSP
Figure 71. Typical Dual Conversion Superheterodyne Application Using the AD9864
Rev. 0 | Page 38 of 44
04319-0-072
PRESELECT
FILTER
IOUTC
RF
INPUT
VXON
IF2 = fCLK/8
AD9864
Figure 71 shows a typical dual conversion superheterodyne
receiver using the AD9864. An RF tuner is used to select and
downconvert the target signal to a suitable first IF for the
AD9864. A preselect filter may precede the tuner to limit the
RF input to the band of interest. The output of the tuner drives
an IF filter that provides partial suppression of adjacent channels and interferers that could otherwise limit the receiver’s
dynamic range. The conversion gain of the tuner should be set
such that the peak IF input signal level into the AD9864 is no
greater than –18 dBm to prevent clipping. The AD9864 downconverts the first IF signal to a second IF that is exactly 1/8 of
the Σ-∆ ADC’s clock rate, i.e., fCLK/8, to simplify the digital
quadrature demodulation process.
This second IF signal is then digitized by the Σ-∆ ADC,
demodulated into its quadrature I and Q components, filtered
via matching decimation filters, and reformatted to enable a
synchronous serial interface to a DSP. In this example, the
AD9864’s LO and CLK synthesizers are both enabled, requiring
some additional passive components (for the synthesizer’s loop
filters and CLK oscillator) and a VCO for the LO synthesizer.
Note that not all of the required decoupling capacitors are
shown. Refer to the previous section and Figure 70 for more
information on required external passive components.
The selection of the first IF frequency is often based on the
availability of low cost standard crystal or SAW filters as well as
system frequency planning considerations. In general, crystal
filters are often used for narrow-band radios having channel
bandwidths below 50 kHz with IFs below 120 MHz, while SAW
filters are more suited for channel bandwidths greater than
50 kHz with IFs greater than 70 MHz. The ultimate stop-band
rejection required by the IF filter will depend on how much
suppression is required at the AD9864’s image band resulting
from downconversion to the second IF. This image band is
offset from the first IF by twice the second IF frequency
(i.e., ± fCLK/4, depending on high- or low-side injection).
The selectivity and bandwidth of the IF filter will depend on
both the magnitude and frequency offset(s) of the adjacent
channel blocker(s) that could overdrive the AD9864’s input or
generate in-band intermodulation components. Further suppression is performed within the AD9864 by its inherent bandpass response and digital decimation filters. Note that some
applications will require additional application-specific filtering
performed in the DSP that follows the AD9864 to remove the
adjacent channel and/or implement a matched filter for optimum signal detection.
between the AD9864’s rated operating range of 13 MHz to
26 MHz and no significant spurious products related to fCLK fall
within the desired pass band, resulting in a reduction in sensitivity performance. If a spurious component is found to limit
the sensitivity performance, the decimation factor can often be
modified slightly to find a spurious free pass band. Selecting a
higher fCLK is typically more desirable given a choice, since the
first IF’s filtering requirements often depend on the transition
region between the IF frequency and the image band (i.e.,
± fCLK/4). Lastly, the output SSI clock rate, fCLKOUT, and digital
driver strength should be set to their lowest possible settings to
minimize the potential harmful effects of digital induced noise
while preserving a reliable data link to the DSP. Note that the
SSICRA, SSICRB, and SSIORD registers, i.e., 0x18, 0x19, and
0x1A, provide a large degree of flexibility for optimization of
the SSI interface.
Syncronization of Multiple AD9864S
Some applications, such as receiver diversity and beam steering,
may require two or more AD9864s operating in parallel while
maintaining synchronization. Figure 71 shows an example of
how multiple AD9864s can be cascaded, with one device serving as the master and the other devices serving as the slaves. In
this example, all of the devices have the same SPI register configuration since they share the same SPI interface to the DSP.
Since the state of each of the AD9864’s internal counters is
unknown upon initialization, synchronization of the devices is
required via a SYNCB pulse (see Figure 36) to synchronize their
digital filters and ensure precise time alignment of the data
streams.
Although all of the devices’ synthesizers are enabled, the LO
and CLK signals for the slave(s) are derived from the masters’
synthesizers and are referenced to an external crystal oscillator.
All of the necessary external components(i.e., loop filters,
varactor, LC, and VCO) required to ensure proper closed-loop
operation of these synthesizers are included.
Note that although the VCO output of the LO synthesizer is
ac-coupled to the slave’s LO input(s), all of the CLK inputs of
the devices must be dc-coupled if the AD9864’s CLK oscillators
are enabled. This is because of the dc current required by the
CLK oscillators in each device. In essence, these negative
impedance cores are operating in parallel, increasing the
effective Q of the LC resonator circuit. RBIAS should be sized
such that the sum of the oscillators’ dc bias currents maintains
a common-mode voltage of around 1.6 V.
The output data rate of the AD9864, fOUT, should be chosen to
be at least twice the bandwidth or symbol rate of the desired
signal to ensure that the decimation filters provide a flat passband response as well as to allow for postprocessing by a DSP.
Once fOUT is determined, the decimation factor of the digital
filters should be set such that the input clock rate, fCLK, falls
Rev. 0 | Page 39 of 44
AD9864
VDDC
0.1µF
RBIAS
operating in parallel. The RF front end consists of a duplexer
and preselect filter to pass the GSM RF band of interest. A high
performance LNA isolates the duplexer from the preselect filter
while providing sufficient gain to minimize system NF. An RF
mixer is used to downconvert the entire GSM band to a suitable
IF, where much of the channel selectivity is accomplished. The
170.6 MHz IF is chosen to avoid any self-induced spurs from
the AD9864. The IF stage consists of two SAW filters isolated
by a 15 dB gain stage.
LOOP
FILTER
COSC
RD
LOSC
CVAR
RF
CP
CZ
15
IOUTC
FREF 35
19 CLKP
FROM
CRYSTAL
OSCILLATION
The cascaded SAW filter response must provide sufficient
blocker rejection in order for the receiver to meet its sensitivity
requirements under worst-case blocker conditions. A composite response having 27 dB, 60 dB, and 100 dB rejection at
frequency offsets of ±0.8 MHz, ±1.6 MHz, and ±6.5 MHz, respectively, provides enough blocker suppression to ensure that
the AD9864 with the lower clip point will not be overdriven by
any blocker. This configuration results in the best possible receiver sensitivity under all blocking conditions.
20 CLKN
47 IFIN
FS 31
DOUTA 29
TO DSP
CLKOUT 28
43 LOP
PE 25
42 LON
PD 24
AD9864
MASTER
IOUTL
FROM
DSP
PC 23
SYNCB 33
38
VCO
LOOP
FILTER
15
IOUTC
PE 25
47 IFIN
PD 24
PC 23
43 LOP
SYNCB 33
42 LON
AD9864
SLAVE
TO OTHER
AD9864s
19 CLKP
FS 31
DOUTA 29
TO OTHER
AD9864s
CLKOUT 28
TO
DSP
FREF 35
04319-0-073
20 CLKN
Figure 72. Example of Synchronizing Multiple AD9864s
Split Path Rx Architecture
A split path Rx architecture may be attractive for those applications whose instantaneous dynamic range requirements exceed
the capability of a single AD9864 device. To cope with these
higher dynamic range requirements, two AD9864s can be operated in parallel with their respective clip points offset by a fixed
amount. Adding a fixed amount of attenuation in front of the
AD9864 and/or programming the attenuation setting of its internal VGA can adjust the input-referred clip point. To save
power and simplify hardware, the LO and CLK circuits of the
device can also be shared. Connecting the SYNCB pins of the two
devices and pulsing this line low synchronizes the two devices.
An example of this concept for possible use in a GSM base station is shown in Figure 73. The signal chain consists of a high
linearity RF front end and IF stage followed by two AD9864s
The output of the last SAW filters drives the two AD9864s via a
direct signal path and an attenuated signal path. The direct path
corresponds to the AD9864 having the lowest clip point and
provides the highest receiver sensitivity with a system noise
figure of 4.7 dB. The VGA of this device is set for maximum
attenuation, so its clip point is approximately –17 dBm. Since
conversion gain from the antenna to the AD9864 is 19 dB, the
digital output of this path will nominally be selected unless the
target signal’s power exceeds –36 dBm at the antenna. The
attenuated path corresponds to the AD9864 having the highest
input-referred clip point, and its digital output point of this
path is set to 7 dBm by inserting a 30 dB attenuator and setting
the AD9864’s VGA to the middle of its 12 dB range. This
setting results in a ±6 dB adjustment of the clip point, allowing
the clip point difference to be calibrated to exactly 24 dB, so
that a simple 5-bit shift would make up the gain difference. The
attenuated path can handle signal levels up to –12 dB at the
antenna before being overdriven. Since the SAW filters provide
sufficient blocker suppression, the digital data from this path
need only be selected when the target signal exceeds –36 dBm.
Although the sensitivity of the receiver with the attenuated path
is 20 dB lower than the direct path, the strong target signal
ensures a sufficiently high carrier-to-noise ratio.
Since GSM is based on a TDMA scheme, digital data (or path)
selection can occur on a slot-by-slot basis. The AD9864 would
be configured to provide Serial I and Q data at a frame rate of
541.67 kSPS, as well as additional information including a 2-bit
reset field and a 6-bit RSSI field. These two fields contain the
information needed to decide whether the direct or attenuated
path should be used for the current time slot.
Rev. 0 | Page 40 of 44
AD9864
VDDC
LOOP
FILTER
RBIAS
0.1µF
COSC
RD
LOSC
CVAR
CP
RF
CZ
ATTENUATED PATH WITH
CLIP POINT = 7.0dBm
15
19 CLKP
13MHz
IO
FREF 35
20 CLKN
FS 31
47 IFIN
DOUTA 29
CLKOUT 28
36dB
PAD
43 LOP
42 LON
AD9864
MASTER
PE 25
PD 24
PC 23
SYNCB 33
IOUTL
38
VCO
LOOP
FILTER
DUPLEXER PRESELECT
IF SAW 1I
F SAW 2
15
IO
IF
AMP
LNA
PE 25
47 IFIN
PD 24
MIXER
PC 23
43 LOP
GAIN = –2dB
NF = 2dB
GAIN = 22dB
NF = 1dB
GAIN = –3dB
NF = 3dB
GAIN = 5dB GAIN = 15dB GAIN = –9dB
NF = –9dB
NF = 12dB NF = 2dB
DSP
OR
ASIC
SYNCB 33
42 LON
AD9864
SLAVE
DIRECT PATH WITH
CLIP POINT = –17dBm
20 CLKN
DOUTA 29
CLKOUT 28
FREF 35
04319-0-074
FS 31
19 CLKP
Figure 73. Example of Split Path Rx Architecture to Increase Receiver Dynamic Range Capabilities
Hung Mixer Mode
The AD9864 can operate in hung mixer mode by tying one of
the LO’s self-biasing inputs to ground, i.e., GNDI, or the
positive supply (VDDI). In this mode, the AD9864 acts as a
narrow-band, band-pass Σ-∆ ADC, since its mixer passes the
IFIN signal without any frequency translation. The IFIN signal
must be centered about the resonant frequency of the Σ-∆ ADC
(i.e., fCLK/8) and the clock rate, fCLK, and decimation factors must
be selected to accommodate the bandwidth of the desired input
signal. Note that the LO synthesizer can be disabled because it
is no longer required.
Since the mixer does not have any losses associated with the mixing operation, the conversion gain through the LNA and mixer is
higher resulting in a nominal input clip point of –24 dBm. The
SNR performance is dependent on the VGA attenuation setting,
I/Q data resolution, and output bandwidth as shown in Figure 74.
Applications requiring the highest instantaneous dynamic range
should set the VGA for maximum attenuation. Also, several extra
decibels in SNR performance can be gained at lower signal bandwidths by using 24-bit I/Q data.
Rev. 0 | Page 41 of 44
AD9864
105
The evaluation board is designed to interface to a PC via a
National Instruments NI 6533 digital IO card. An XILINX FPGA
formats the data between the AD9864 and digital I/O card.
fCLK = 18MSPS
100
IF
LO
INPUT INPUT
MAX ATTEN WITH
16-BIT I/Q DATA
AD9864
90
MIXER
INPUT
MIN ATTEN WITH
16-BIT I/Q DATA
DUT
0
20
40
60
80
100
120
140
BW (kHz)
160
04319-0-075
80
XILINX
SPARTON
FPGA
Figure 74. Hung Mixer SNR vs. BW and VGA
POWER SUPPLY
DISTRIBUTION
LAYOUT EXAMPLE, EVALUATION BOARD, AND
SOFTWARE
CLK
INPUT
FREF
INPUT
CRYSTAL
OSCILLATOR
(OPTIONAL)
85
MIN ATTEN WITH
24-BIT I/Q DATA
VCO
MODULE
INTERFACE
IDT
FIFO
EPROM
04319-0-076
95
NIDAQ 68-PIN
CONNECTOR
SNR (dB)
MAX ATTEN WITH
24-BIT I/Q DATA
Figure 75. Evaluation Board Platform
The evaluation board and its accompanying software provide a
simple way to evaluate the AD9864. The block diagram in
Figure 75 shows the major blocks of the evaluation board,
which is designed to be flexible, allowing configuration for
different applications.
The power supply distribution block provides filtered, adjustable voltages to the various supply pins of the AD9864. In the
IF input signal path, component pads are available to implement
different IF impedance matching networks. The LO and CLK
signals can be externally applied or internally derived from a
user-supplied VCO module interface daughter board. The reference for the on-chip LO and CLK synthesizers can be applied via
the external fREF input or an on-board crystal oscillator.
Software developed using National Instruments’ LabVIEW™
(and provided as Microsoft® Windows® executable programs) is
supplied for the configuration of the SPI port registers and
evaluation of the AD9864 output data. These programs have a
convenient graphical user interface that allows for easy access
to the various SPI port configuration registers and frequency
analysis of the output data.
For more information on the AD9864 evaluation board, including an example layout, please refer to the EVAL-AD9874EB
Data Sheet
(www.analog.com/Analog_Root/static/pdf/techSupport/AD987
4EB_0.pdf).
Rev. 0 | Page 42 of 44
AD9864
OUTLINE DIMENSIONS
7.00
BSC SQ
0.60 MAX
0.60 MAX
37
36
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
0.20
REF
12° MAX
48
PIN 1
INDICATOR
1
5.25
5.10 SQ
4.95
BOTTOM
VIEW
0.50
0.40
0.30
1.00
0.90
0.80
0.30
0.23
0.18
25
24
12
13
0.25 MIN
5.50
REF
1.00 MAX
0.65 NOM
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 76. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)—Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ORDERING GUIDE
AD9864 Products
AD9864BCPZ*
AD9864BCPZRL*
AD9864-EB
Temperature Package
–40°C to +85°C
–40°C to +85°C
Package Description
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Evaluation Board
*This is a lead free product.
Rev. 0 | Page 43 of 44
Package Outline
CP-48
CP-48
AD9864
NOTES
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies.
C04319-0-8/03(0)
Rev. 0 | Page 44 of 44