EXAR XRT4000

XRT4000
Universal Multiprotocol
Serial Interface
November 1998-2
FEATURES
•
•
•
•
•
•
•
Software-configurable multiprotocol serial
interface supporting:
V.35, V.36, EIA-530 (A), RS232
(V.28), X.21, RS449
One chip fully integrated solution (Internal
termination)
Contains 8 receivers and 8 transmitters for full
DTE and DCE support
Glitch filters on the control signals (Optional)
+5V, +12V, -6V power supplies required
Full support of loopbacks, data & clock inversion,
and echoed clock in DTE and DCE modes
Full support of most popular types of HDLC
controllers (single, double, and triple clocks
supported)
•
•
•
•
•
Internal oscillator for standalone DTE loopback
testing
Control signals can be registered and nonregistered
Control signals can be tri-stated for bus-based
designs
“Fail Safe” operation supported
ESD Protection Over + 2kV Range
APPLICATIONS
•
•
•
Data Service Units (DSU)
Routers
Access Multiplexers
GENERAL DESCRIPTION
The XRT4000 is a fully integrated multiprotocol serial
interface. It is a universal device because it supports
all of the popular serial physical interfaces such as
V.35, V.36, EIA-530 (A), RS232 (V.28), X.21 and
RS449. Furthermore it can easily be interfaced with
most common types of HDLC controllers. This
device contains 8 receivers and 8 transmitters. It is
a complete solution containing all of the required
source and load terminations in one 100 pin TQFP
package.
operation and power down mode. It fully supports
echoed clock as well as clock and data inversion. An
elaborate set of loopbacks are supported in DTE and
DCE modes of operation. This eliminates the need
for external circuitry for loopback implementation.
The control signals such as RI, RL, DCD, DTR, DSR
are protected against glitches by internal filters.
These filters can be disabled.
XRT4000 has an
internal oscillator which is used to create a clock
signal needed to conduct standalone diagnostics of
DTE equipment.
XRT4000 can be configured to operate in one of the
seven interfaces in either DTE and DCE modes of
ORDER INFORMATION
Part No.
Package
XRT4000CV
100 Pin TQFP
Operating
Temperature Range
0°C to +70°C
Rev. 1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 95538 ♦ (510) 668-7000 ♦ FAX (510) 668-7017
XRT4000
Figure 1. XRT4000 Functional Block Diagram
Rev. 1.00
-2-
XRT4000
Figure 2. XRT4000 RTMOD1 Block
Figure 3. XRT4000 RTMOD2 Block
Rev. 1.00
-3-
XRT4000
Figure 4. XRT4000 RTMOD3 Block
Figure 5. XRT4000 Control Block
Note: Signals without pin numbers having names identical to those with pin numbers are CMOS level-shifted
versions of TTL-compatible input signals.
Rev. 1.00
-4-
XRT4000
VDD
CM_TX1
TX1B
TX1A
TX2A
TX2B
80
TX2D
CM_TX2
VDD
TX3D
CM_TR3
VSS
TR3A
TR3B
RX3D
GND
90
GND
VDD
VSS
RX2D
RX2B
RX2A
RX1A
VDD
RX1B
RX1D
PIN CONFIGURATION
TX1D
GND
GND
M0
VSS
M1
VDD
M2
VDD
70
EN_FLTR
EN_TERM
GND
VSS
LATCH*
DTINV*
VSS
CKINV*
VSS
10
EN_OSC*
GND
2CK/3CK*
100-Pin
TQFP
XRT4000
CLKFS
TX4D
VDD
TX4B
REG_CLK
VR
VPP
NC
TX4A
NC
60
TX5A
NC
TX5B
NC
GND
TX5D
VPP
20
VDD
TX8D
E_232H*
VSS
LP*
VDD
-5-
N/C
GND
RX4D
SLEW_CNTL
RX4B
RX4A
RX5A
RX5B
EC*
RX5D
RX67D
DCE/DTE*
TR6B
TR6A
TR7
TX76D
VSS
RX8I
GND
RX8D
VDD
VDD
VSS
REG
N/C
EN_OUT*
Rev. 1.00
50
GND
40
N/C
VSS
30
TX8O
XRT4000
PIN DESCRIPTION
Pin
#
1
2
3
4
5
6
Symbol
DTE
Mode
DCE
Mode
Type
VDD
GND
M0
M1
M2
EN_FLTR
I
I
I
I
7
EN_TERM
I
8
LATCH*
I
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VSS
VSS
GND
CLKFS
TX4D
VDD
TX4B
TX4A
TX5A
TX5B
GND
TX5D
TX8D
LP*
23
24
25
26
27
TX8O
VSS
VDD
EN_OUT*
REG
28
29
30
31
32
33
34
VSS
VDD
VDD
RX8D
GND
RX8I
VSS
D_RTS
D_CTS
O
I
RTSB
RTSA
DTRA
DTRB
CTSB
CTSA
DSRA
DSRB
O
O
O
O
D_DTR
D_RL
D_DSR
D_RI
I
I
I
RLA
RIA
O
I
I
D_RI
D_RL
O
RIA
RLA
I
Function
Digital VDD for Receiver 1 - Connect to +5V
Digital GND for Receiver 1
Mode Control - Mode Select Input 0; Internal 20KΩ pull-up
Mode Control - Mode Select Input 1; Internal 20KΩ pull-up
Mode Control - Mode Select Input 2; Internal 20KΩ pull-up
Enable Glitch Filter on Receiver 4, 5, 6, 7, 8 inputs.
Internal 20KΩ pull-down
Enable input termination for Receiver 1, 2, 3 in V.11 Mode.
Internal 20KΩ pull-down
Mode Control Input Latch Enable - Logic 0: Changes on
M0, 1, 2, EN_FLTR, and EN_TERM pins cause mode
changes (input latches in transparent state).
Logic 1: Changes on these input pins do not cause mode
changes (input latches in latched state). Internal 20KΩ pulldown
Digital VSS for Transmitter 4, 5, 6. Connect to -6V
Analog VSS for bias generation Connect to -6V
Digital GND for Transmitter 7, 8
Internal Clock Generated - 500kHz
Transmitter 4 - Digital Data Input from equipment
Digital VDD for Transmitter 4, 5, 6; Connect to +5V
Transmitter 4 - Positive Data Differential Output to line
Transmitter 4 - Negative Data Differential Output to line
Transmitter 5 - Negative Data Differential Output to line
Transmitter 5 - Positive Data Differential Output to line
Digital GND for Transmitter 4, 5, 6
Transmitter 5 - Digital Data Input from equipment
Transmitter 8 - Digital Data Input from equipment
Loopback Enable - Active low; Logic 0: Loopback
enabled.
Logic 1: Loopback disabled. Internal 20KΩ pull-up
Transmitter 8 - Single Ended Data Output to line
Digital VSS for Transmitter 7, 8; Connect to -6V
Digital VDD for Transmitter 7, 8; Connect to +5V
Output Enable for Receiver 5, 8; Internal 20KΩ pull-down
Register Control - Logic 1: TX5D, TX8D signal values will
be latched on the positive edge of REG_CLK, Logic 0: The
Register flip-flop is bypassed therefore REG_CLK has no
effect on these signals. Internal 20KΩ pull-down
Analog VSS for Receiver 4, 5, 6; Connect to -6V
Analog VDD for Receiver 4, 5, 6; Connect to +5V
Analog VDD for Receiver 7, 8; Connect to +5V
Receiver 8 - Digital Data Output to equipment
Analog GND for Receiver 7, 8
Receiver 8 - Single Ended Data Input from line
Analog VSS for Receiver 7, 8; Connect to -6V
Note: An asterisk (*) following a pin symbol indicates that the pin is active low.
Names begining with D_ are digital signals.
Names ending with B and A are the positive and negative polarities of differential signals respectively.
Rev. 1.00
-6-
XRT4000
PIN DESCRIPTION (CONT’D)
Pin
#
35
Symbol
DCE
Mode
LLA
Type
TR7
DTE
Mode
LLA
36
37
TX76D
TR6A
D_LL
DCDA
D_DCD
DCDA
I
I/O
38
TR6B
DCDB
DCDB
I/O
39
DCE/DTE*
LOW
HIGH
I
40
41
42
RX67D
RX5D
EC*
D_DCD
D_DSR
D_LL
D_DTR
O
O
I
43
44
45
46
47
RX5B
RX5A
RX4A
RX4B
SLEW_
CNTL
DSRB
DSRA
CTSA
CTSB
DTRB
DTRA
RTSA
RTSB
I
I
I
I
O
48
49
50
51
52
53
54
55
RX4D
GND
NC
NC
GND
NC
VSS
E_232H*
D_CTS
D_RTS
O
56
57
58
59
60
61
62
63
VDD
VPP
NC
NC
NC
NC
VPP
VR
I/O
Function
DTE Mode - Transmitter 7 - Single Ended Data Output to line
DCE Mode - Receiver 7 - Single Ended Data Input from line
Digital Input - Refer to Mode Control Table
DTE Mode - Receiver 6 - Negative Data Differential Input
from line
DCE Mode - Transmitter 6 - Negative Data Differential
Output to line
DTE Mode - Receiver 6 - Positive Data Differential Input from
line
DCE Mode - Transmitter 6 - Positive Data Differential Output
to line
DCE/DTE Select - Selects operating mode. Logic 0: DTE
Mode. Logic 1: DCE Mode. Internal 20KΩ pull-up
Digital Output - Refer to Mode Control Table
Receiver 5 - Digital Data Output to equipment
Enable Clock Mode - Active Low, Logic 0: Echoed Mode.
Logic 1: Normal Mode. Internal 20KΩ pull-up
Receiver 5 - Positive Data Differential Input from line
Receiver 5 - Negative Data Differential Input from line
Receiver 4 - Negative Data Differential Input from line
Receiver 4 - Positive Data Differential Input from line
Analog Output - Resistor connected between this pin and
Ground controls transmitter output pulse rise and fall time in
V.10 or V.28 mode as specified in Figures 15 and 16
respectively.
Receiver 4 - Digital Data Output to equipment
Digital GND for Receiver 4, 5, 6
Analog GND for bias generator.
I
O
Analog Substrate - Connect to -6V
High Speed RS-232 Enable - Logic 0: Enables high speed
RS-232 mode (drives 3KΩ in parallel with 1000pF at 256KHz).
Internal 20KΩ pull-up
Analog VDD for bias generation circuit; Connect to +5V
VPP - Connect to +12V supply
VPP - Connect to +12V supply
VR - Internally generated +2.2V Reference (Sources 20µA
maximum)
Note: An asterisk (*) following a pin symbol indicates that the pin is active low.
Names begining with D_ are digital signals.
Names ending with B and A are the positive and negative polarities of differential signals respectively
Rev. 1.00
-7-
XRT4000
Pin
#
64
65
Symbol
DTE
Mode
DCE
Mode
Type
REG_CLK
2CK/3CK*
I
I
66
EN_OSC*
I
67
CKINV*
I
68
DTINV*
I
69
VSS
70
71
GND
VDD
72
73
74
75
76
77
78
79
80
81
82
83
84
VDD
VSS
GND
TX1D
CM_TX1
TX1B
TX1A
TX2A
TX2B
CM_TX2
TX2D
VDD
TX3D
85
86
VSS
CM_TR3
87
TR3A
D_TXD
D_RXD
TXDB
TXDA
SCTEA
SCTEB
RXDB
RXDA
RXCA
RXCB
D_SCTE
D_RXC
I
O
O
O
O
O
O
I
D_X
D_TXC
I
O
TXCA
TXCA
I/O
Function
Clock - For Transmitter 5, 8 input register. Internal 20KΩ pull-up
2 or 3 Clock Select - Internal 20KΩ pull-up
Logic Don’t Care: 1 Clock When Mode = X.21 (M2, M1, M0= 011)
Logic 0: 3 Clocks When Mode ≠ X.21 (M2, M1, M0 ≠ 011)
Logic 1: 2 Clocks When Mode ≠ X.21 (M2, M1, M0 ≠ 011)
Test Oscillator Enable - Active Low; Logic 0: Oscillator Enabled.
Logic 1: Oscillator Disabled. Internal 20KΩ pull-up
Invert Clock - Active Low; Logic 0: Clock Inverted.
Logic 1: Clock not Inverted. Internal 20KΩ pull-up
Invert Data - Active Low; Logic 0: Data Inverted.
Logic 1: Data not Inverted. Internal 20KΩ pull-up
Digital VSS for Transmitter 1, 2, 3 Output Drivers;
Connect to -6V
Digital GND for Transmitter 1, 2, 3 Output Drivers
Digital VDD for Transmitter 1, 2, 3 Output Drivers;
Connect to +5V
Analog VDD for Transmitter 1, 2; Connect to +5V
Analog VSS for Transmitter 1, 2; Connect to -6V
Analog GND for Transmitter 1, 2 “T” termination
Transmitter 1- Digital Data Input from equipment
AC GND - Transmitter 1 Output Termination center tap in V.35 mode
Transmitter 1 - Positive Data Differential Output to line
Transmitter 1 - Negative Data Differential Output to line
Transmitter 2 - Negative Data Differential Output to line
Transmitter 2 - Positive Data Differential Output to line
AC GND - Transmitter 2 Output Termination center tap in V.35 mode
Transmitter 2 - Digital Data Input from equipment
Digital VDD for Receiver and Transmitter 1, 2, 3; Connect to +5V
DTE Mode - Input not used
DCE Mode - Transmitter 3 - Digital Data Input from equipment
Digital VSS for Receiver and Transmitter 1, 2, 3; Connect to -6V
DTE Mode - AC GND - Transmitter 3 Output Termination center tap
in V.35 mode
DCE Mode - AC GND - Receiver 3 Input Termination center tap in
V.35 mode
DTE Mode - Receiver 3 - Negative Data Differential Input from line.
DCE Mode - Transmitter 3 - Negative Data Differential Output to
line.
Note: An asterisk (*) following a pin symbol indicates that the pin is active low.
Names begining with D_ are digital signals.
Names ending with B and A are the positive and negative polarities of differential signals respectively
Rev. 1.00
-8-
XRT4000
Pin
#
88
Symbol
DCE
Mode
TXCB
Type
TR3B
DTE
Mode
TXCB
89
90
GND
RX3D
D_TXC
D_X
O
91
92
93
94
95
96
97
98
99
100
VDD
GND
RX2D
VSS
RX2B
RX2A
RX1A
RX1B
VDD
RX1D
D_RXC
D_SCTE
O
RXCB
RXCA
RXDA
RXDB
SCTEB
SCTEA
TXDA
TXDB
I
I
I
I
D_RXD
D_TXD
O
I/O
Function
DCE Mode - Transmitter 3 - Positive Data Differential
Output to line
DTE Mode - Receiver 3 - Positive Data Differential Input
from line
Analog GND for Receiver 1, 2, 3
DTE Mode - Receiver 3- Digital Data Output to equipment
DCE Mode - Not used
Digital VDD for Receiver 2, 3; Connect to +5V
Digital GND for Receiver 2, 3
Receiver 2 - Digital Data Output to equipment
Analog VSS for Receiver 1, 2, 3; Connect to -6V
Receiver 2 - Positive Data Differential Input from line
Receiver 2 - Negative Data Differential Input from line
Receiver 2 - Negative Data Differential Input from line
Receiver 2 - Positive Data Differential Input from line
Analog VDD for Receiver 1, 2, 3; Connect to +5V
Receiver 1 - Digital Data Output to equipment
Note: An asterisk (*) following a pin symbol indicates that the pin is active low.
Names begining with D_ are digital signals.
Names ending with B and A are the positive and negative polarities of differential signals respectively.
`
Rev. 1.00
-9-
XRT4000
ELECTRICAL CHARCTERISTICS
Test Conditions: VDD = 5V, VSS = -6V, VPP = 12V (all ± 5%), TA = 25°C
Sybol
Parameter
Supply Currents
IDD
VDD
Supply
Current
(DCE
Mode,
All Digital
Pins=GND
or VDD)
ISS
IPP
VSS
Supply
Current
(DCE
Mode,
All Digital
Pins=GND
or VDD)
VPP
Supply
Current
(DCE
Mode,
All Digital
Pins =
GND
or VDD)
Min
Typ
Max
Unitd
Interface
20
mA
M0
0
M1
0
M2
0
V.10, No Load
90
mA
0
0
0
V.10, Full Load
20
mA
1
0
0
EIA-530A, No Load
160
55
55
mA
mA
mA
1
0
0
0
0
0
0
1
1
16
16
2
30
mA
mA
mA
mA
0
0
1
0
1
1
1
0
1
1
1
0
EIA-530A, Full Load
V.35, No Load on V.28 Drivers
V.35, Full Load on V.28
Drivers
RS232, No Load
RS232, Full Load
Power Down Mode
V.10, No Load
90
mA
0
0
0
V.10, Full Load
30
mA
1
0
0
EIA-530A, No Load
50
45
55
mA
mA
mA
1
0
0
0
0
0
0
1
1
16
30
2
10
mA
mA
mA
mA
0
0
1
0
1
1
1
0
1
1
1
0
EIA-530A, Full Load
V.35, No Load on V.28 Drivers
V.35, Full Load on V.28
Drivers
RS232, No Load
RS232, Full Load
Power Down Mode
V.10, No Load
10
mA
0
0
0
V.10, Full Load
10
mA
1
0
0
EIA-530A, No Load
10
10
20
mA
mA
mA
1
0
0
0
0
0
0
1
1
10
25
10
mA
mA
mA
0
0
1
1
1
1
1
1
1
EIA-530A, Full Load
V.35, No Load on V.28 Drivers
V.35, Full Load on V.28
Drivers
RS232, No Load
RS232, Full Load
Power Down Mode
Note 1: Absolute Maximum Ratings are those beyond which the safety of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device are negative. All voltages are
referenced to device ground unless otherwise specified.
Rev. 1.00
- 10 -
XRT4000
ELECTRICAL CHARCTERISTICS (CONT’D)
Test Conditions: VDD = 5V, VSS = -6V, VPP = 12V (all ± 5%), TA = 25°C
Symbol
Parameter
Logic Inputs and Outputs
VIH
Logic Input High
Voltage
VIL
Logic Input Low
Voltage
IIN
Logic Input
Current
VOH
Output High
Voltage
VOL
Output Low
Voltage
IOSR
Output ShortCircuit Current
IOZR
Three-State
Output Current
V.11 Driver
VOD
Differential Output
Voltage
Change in
∆VOD
Magnitude of
Differential Output
Voltage
VOC
Common Mode
Output Voltage
Change in
∆VOC
Magnitude of
Common Mode
Output Voltage
ISS
Short-Circuit
Current
IOZ
Output Leakage
Current
tr, tf
Rise or Fall Time
TPLH
Input to Output
TPHL
Input to Output
Inp. to Out.
∆t
Difference, |TPLH
- TPHL|
TSKEW
Output to Output
Skew
Min
Typ
Max
2
3
0.8
V
±250
µA
With 20kΩ internal pull-up/down resistor
V
IO = -4mA
0.8
V
IO = 4mA
60
mA
0V ≤ VO ≤ VDD
±1
µA
M0 = Ml = M2 = VDD 0V ≤ VO ≤ VDD
5
V
4.5
-60
0.2
V
Open Circuit
RL = 50Ω (Figure 6)
RL = 50Ω (Figure 6)
3.0
V
RL = 50Ω (Figure 6)
V
RL = 50Ω (Figure 6)
±2
0.2
4
50
50
0
Conditions
V
0.3
0
Units
±150
mA
VO = GND
±0.01
±100
µA
13
70
70
5
25
110
110
15
ns
ns
ns
ns
-0.25V ≤ VO ≤ 0.25V, Power Off or
Driver Disabled
(Figures 7, 11)
(Figures 7, 11)
(Figures 7, 11)
(Figures 7, 11)
ns
(Figures 7, 11)
5
Note 1: Absolute Maximum Ratings are those beyond which the safety of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device are negative. All voltages are
referenced to device ground unless otherwise specified.
Rev. 1.00
- 11 -
XRT4000
ELECTRICAL CHARCTERISTICS (CONT’D)
Test Conditions: VDD = 5V, VSS = -6V, VPP = 12V (all ± 5%), TA = 25°C
Symbol
Parameter
V.11 Receiver
VTH
Input Threshold
Voltage
∆VTH
IIN
RIN
tr, tf
TPLH
TPHL
∆t
V.35 Driver
VOD
IOH
IOL
IOZ
tr, tf
TPLH
TPHL
∆t
Input Hysteresis
Input Current (A,
B)
Input Impedance
Rise or Fall Time
Input to Output
Input to Output
Inp. to Out.
Difference, |TPLH
- TPHL|
Differential Output
Voltage
Transmitter
Output High
Current
Transmitter
Output Low
Current
Transmiter Output
Leakage Current
Rise or Fall Time
Input to Output
Input to Output
Inp. to Out.
Difference, |TPLH
- TPHL|
TSKEW
Output to Output
Skew
V.35 Receiver
VTH
Differential Input
Threshold Volt.
Input Hysteresis
∆VTH
IIN
Input Current
(A,B)
RIN
Input Impedance
(A, B)
tr, tf
Rise or Fall Time
TPLH
Input to Output
TPHL
Input to Output
Input to Output
∆t
Difference, ITPLH
- TPHLI
Min
Typ
-0.2
Max
Units
Conditions
-7V ≤ VCM ≤ 7V
0.2
35
±1
60
±1.5
mV
mA
-7V ≤ VCM ≤ 7V
-10V ≤ VA,B ≤ 10V
11
50
50
0
10
20
80
80
5
120
120
15
kΩ
ns
ns
ns
ns
-10V ≤ VA,B ≤ 10V
(Figures 7, 12)
(Figures 7, 12)
(Figures 7, 12)
(Figures 7, 12)
±0.44
±0.55
±0.66
V
-12
-11
-10
mA
VA, B = 0V
10
11
12
mA
VA, B = 0V
±0.01
±100
µA
-0.25 ≤ VA,B ≤ 0.25V
5
55
55
5
85
85
15
ns
ns
ns
ns
(Figures 8, 11)
(Figures 8, 11)
(Figures 8, 11)
(Figures 8, 11)
ns
(Figures 8, 11)
0.2
V
-2V = (VA + VB)/2 = 2V (Figure 8)
60
mV
mA
-2V = (VA + VB)/2 = 2V (Figure 8)
-10V = VA, B = 10V
9
25
25
0
5
-0.2
35
±60
175
20
80
100
5
120
120
15
With Load, (Figure 12)
Ω
-10V = VA, B = 10V
ns
ns
ns
ns
(Figures 8, 12)
(Figures 8, 12)
(Figures 8, 12)
(Figures 8, 12)
Note 1: Absolute Maximum Ratings are those beyond which the safety of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device are negative. All voltages are
referenced to device ground unless otherwise specified.
Rev. 1.00
- 12 -
XRT4000
ELECTRICAL CHARCTERISTICS (CONT’D)
Test Conditions: VDD = 5V, VSS = -6V, VPP = 12V (all ± 5%), TA = 25°C
Symbol
V.10 Driver
VO
ISS
Parameter
Output Voltage
tr, tf
Short-Circuit
Current
Input Leakage
Current
Rise or Fall Time
TPLH
TPHL
IOZ
Min
±4.0
±3.6
SR
TPLH
TPHL
Units
±100
Open Circuit, RL = 3.9k
RL = 450Ω (Figure 9)
VO = GND
±100
µA
-0.25 ≤ VO ≤ 0.25V, Power Off or
Driver Disabled
(Figures 9, 13), RL = 450Ω, CL = 100pF
RSLEW_CNTL = 10k
(Figures 9, 13), RL = 450Ω, CL = 100pF
RSLEW_CNTL = 10k
(Figures 9, 13), RL = 450Ω, CL = 100pF
RSLEW_CNTL = 10k
Input to output
5
µs
Input to output
5
µs
0
-0.2
9
Short-Circuit
Current
Input Leakage
Current
Slew Rate
Input to output
Input to output
Conditions
V
V
mA
µs
V.28 Receiver
VTHL
Input Low
Threshold Voltage
VTLH
Input High
Threshold Voltage
AVTH
Receiver Input
Hysteresis
RIN
Receiver Input
Impedance
tr, tf
Rise or Fall Time
TPLH
Input to Output
TPHL
Input to Output
Rev. 1.00
±6.0
±0.1
0.2
V
35
60
mV
±1
±1.5
mA
-10 ≤ VA ≤ 10V
10
11
kΩ
-10 ≤ VA ≤ 10V
ns
ns
ns
(Figures 10, 14)
(Figures 10, 14)
(Figures 10, 14)
±6
V
±100
mA
Open Circuit
RL = 3k (Figure 9)
VO = GND
±0.01
±100
µA
2
2
30.0
4
4
V/µs
µs
µs
1.4
0.8
V
20
100
100
±5
IOZ
Max
5
V.10 Receiver
VTH
Receiver Input
Threshold Voltage
AVTH
Receiver Input
Hysteresis
IIN
Receiver Input
Current
RIN
Receiver Input
Impedance
tr, tf
Rise or Fall Time
TPLH
Input to Output
TPHL
Input to Output
V.28 Driver
VO
Output Voltage
ISS
Typ
±5.5
4.0
-0.25 ≤ VCM ≤ 0.25V, Power Off or
Driver Disabled
(Figures 9, 13), RL = 3k, CL = 2500pF
(Figures 9, 13), RL = 3k, CL = 2500pF
(Figures 9, 13), RL = 3k, CL = 2500pF
2.0
1.4
V
0.1
0.4
1.0
V
3
5
7
kΩ
-15 ≤ VA ≤ 15V
ns
ns
ns
(Figures 10, 14)
(Figures 10, 14)
(Figures 10, 14)
20
120
180
- 13 -
XRT4000
The following tests circuits and timing diagrams are referenced in the preceding Electrical Characteristics
Tables.
Figure 6. RS422 Driver Test Circuit
Figure 7. RS422 Driver/Receiver AC Test Circuit
Figure 8. V.35 Driver/Receiver AC Test Circuit (TX1/RX1, TX2/RX2 Only)
Figure 9. V.10/V.28 Driver Test Circuit
Figure 10. V.10/V.28 Receiver Test Circuit
Rev. 1.00
- 14 -
XRT4000
Figure 11. V.11, V.35 Driver Propagation Delays
V1 = 0V for V.35, 2.5V for V.11
Figure 12. V.11, V.35 Receiver Propagation Delays
Figure 13. V.10, V.28 Driver Propagation Delays
V1 = 1.8V for V.28, 0.1V for V.10
V2 = 1.0V for V.28. -0.1V for V.10
Figure 14. V.10, V.28 Receiver Propagation Delays
Rev. 1.00
- 15 -
XRT4000
SYSTEM DESCRIPTION
It is important to describe the difference
between an electrical specification and a
physical interface specification. An electrical
specification defines the electrical characteristics
of a transmitter or receiver. These include
voltage, current, impedance levels, rise/fall
times and other similar parameters. Popular
electrical interfaces are V.10, V.11, V.35 and
V.28. A serial physical interface specification,
however, describes an interface in its entirety.
This description includes the names and
functions of all involved signals, the electrical
parameters of each of the signals, and the
connector type. Popular serial interface types
include V.35, RS232 (V.28), RS449, EIA-530(A),
X.21, and V.36. The XRT4000 contains a
sufficient number of receivers, transmitters and
transceivers to transport all of the signals
required for a physical serial interface. It has
control circuitry that can configure each driver
and receiver to the appropriate electrical levels
required by the specification for the selected
serial interface.
RTMOD1 Block
Figure 1 is a top level block diagram that shows
how the eight receivers and eight transmitters
present in the XRT4000 are grouped in three
modules named RTMOD1, RTMOD2, and
RTMOD3. A forth module labeled CONTROL
programs these receivers and transmitters with
the appropriate electrical levels for operation
with most popular standard serial interfaces
such as V.35, RS232, RS449, EIA-530(A), X.21,
and V.36. These interfaces are fully compliant
with
international
NET1
and
NET2
specifications.
RTMOD2 Block
Figures 2, 3, 4, and 5 are a set of functional
block diagrams that give more detailed
information about the four modules shown in the
top-level diagram. The eight receivers and
transmitters are grouped in three different
categories according to the type of signals
transmitted or received. The categories are
denoted as RTMOD1 (Figure 2), RTMOD2
(Figure 3), RTMOD3 (Figure 4), and CONTROL
(Figure 5).
Rev. 1.00
- 16 -
RTMOD1 is intended for the high speed data
and clock signals of a selected interface. This
block contains receivers RX1 and RX2,
transmitters TX1 and TX2, and bi-directional
transceiver TR3 which is composed of TX3 and
RX3. All of these devices may be programmed
with the electrical levels required for V.35, V.11,
V.10, or V.28 operating modes. In V.35 mode,
each transmitter has a common mode pin that is
connected to the center of the internal
termination. This pin should be bypassed to
ground with an external capacitor in order to
provide the best possible driver output stage
balance. In a system application, the TX1-RX1
pair and TX2-RX2 pair handle the TXD-RXD and
TXC-RXC
high-speed
interface
signals
respectively. Transceiver TR3 is dedicated to
the SCTE signal for both DCE and DTE modes
of operation. It functions as a receiver for the
DTE mode and as a transmitter during the DCE
mode.
RTMOD2 contains receivers RX4 and RX5,
transmitters TX4 and TX5, and transceiver TR6
which is composed of TX6 and RX6. These
devices may be programmed with the electrical
levels required for V.11, V.10, or V.28 operating
modes. The RX4-TX4 pair are dedicated for
RTS and CTS signals while RX5-TX5 are
intended for DTR and DSR signals. Transceiver
TR3 handles the DCD signal which requires a
transmitter in the DCE and a receiver in-theDTE mode.
RTMOD3 Block
RTMOD3 contains transceiver TR7, which is
composed of TX7 and RX7, receiver RX8 and
transmitter TX8. These devices, which may be
programmed with the electrical levels required
for V.10, or V.28 operating modes, are intended
for the LL, RL and RI signals.
XRT4000
CONTROL Block
Power Requirements
The CONTROL block contains the configuration
and bias generation circuitry required by
RTMOD1, RTMOD2, and RTMOD3. It includes
TTL to CMOS level shifters for the control signal
inputs which have either an internal 20 kΩ pullup or pull-down resistor as shown in Figure 5
and as described in the pin description. This
block also includes a reference voltage source,
bias voltage and current generators, and a slew
rate control circuit that is used in the V.10 and
V.28 modes.
The physical interface
configuration is done by three control pins called
M0, M1 and M2. The logic levels present on
these three inputs are internally latched during a
positive transition of the LATCH* signal. The
functions of the eight possible combinations of
M0, M1 and M2 are described in Tables 1 and 2.
Table 3, which contains the maximum and
minimum peak supply currents for each of the 3
supply voltages, provides the information
necessary for determining a system power
budget.
Notice that maximum current is
required in the V.11 mode when TX1, TX2, and
TX3 are terminated with 100Ω. Minimum current
consumption occurs when none of the
transmitters are terminated and the device is not
in the V.35 mode.
Rev. 1.00
- 17 -
Receiver and Transmitter Specifications
Tables 4 and 5, which are for the XRT4000
receiver and transmitter sections respectively,
summarize the electrical requirements for V.35,
V.11, V.10, and RS232 interfaces. These tables
provide virtually all of the electrical information
necessary to describe these 4 interfaces in a
concise form.
XRT4000
CONTROL
DRIVER/RECEIVER PAIR AND CORRESPONDING SIGNAL NAME - DTE MODE
INPUTS
M2 M1
TX1
M0
RX1
TX2
RX2 TX3 RX3
TXD RXD SCTE RXC
TX4
RX4
TX5
DTR DSR
-
TXC
RTS
CTS
RX5
INTERFACE
TX6
RX6
TX7
RX7
TX8 RX8 STANDARD
-
DCD
LL
TM
RL
RI
0
0
0
10
10
10
10
Off
10
10
10
10
10
Off
10
10
Off
10
10 V.10
0
0
1
11
11
11
11
Off
11
11
11
10
10
Off
11
10
Off
10
10 EIA-530-A
0
1
0
11
11
11
11
Off
11
11
11
11
11
Off
11
10
Off
10
10 EIA-530, RS449, V.36
0
1
1
11
11
11
11
Off
11
11
11
11
11
Off
Off
Off
Off
Off
Off X.21
28 V.35
1
0
0
35
35
35
35
Off
35
28
28
28
28
Off
28
28
Off
28
1
0
1
11
11
11
11
Off
11
11
11
11
11
Off
11
10
Off
10
10 RESERVED
1
1
0
28
28
28
28
Off
28
28
28
28
28
Off
28
28
Off
28
28 RS232
1
1
1
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off POWER DOWN
Table 1. DTE Mode - Control Programming for Driver and Receiver Mode Selection
CONTROL
DRIVER/RECEIVER PAIR AND CORRESPONDING SIGNAL NAME - DCE MODE
INPUTS
TX1 RX1
TX2
RX2
TX3 RX3 TX4
M2 M1 M0 RXD TXD RXC SCTE TXC
-
RX4
TX5
RX5
TX6
CTS RTS
RX6 TX7
INTERFACE
RX7 TX8
RX8
STANDARD
DSR
DTR
DCD
-
TM
LL
RI
RL
0
0
0
10
10
10
10
10
Off
10
10
10
10
10
Off
Off
10
10
10
V.10
0
0
1
11
11
11
11
11
Off
11
11
10
10
11
Off
Off
10
10
10
EIA-530-A
0
1
0
11
11
11
11
11
Off
11
11
11
11
11
Off
Off
10
10
10
EIA-530, RS449, V.36
0
1
1
11
11
11
11
11
Off
11
11
11
11
OFF
Off
Off
Off
Off
Off
X.21
1
0
0
35
35
35
35
35
Off
28
28
28
28
28
Off
Off
28
28
28
V.35
1
0
1
11
11
11
11
11
Off
11
11
11
11
11
Off
Off
10
10
10
RESERVED
1
1
0
28
28
28
28
28
Off
28
28
28
28
28
Off
Off
28
28
28
RS232
1
1
1
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
POWER DOWN
Table 2. DCE Mode - Control Programming for Driver and Receiver Mode Selection
Note: For the above tables:
Rev. 1.00
Table
Representation
35
11
10
28
- 18 -
Corresponding
Electrical Level
V.35
V.11
V.10
V.28/RS232
Type
Signal
Differential
Differential
Single Ended
Single Ended
XRT4000
Supply
Maximum Current
TX1-TX3 Drivers Terminated
with 100Ω in V.11 Mode
160 mA
120 mA
40 mA
VDD (+5V)
VSS (-6V)
VPP (+12V)
Minimum Current
None of the Drivers Terminated
(Non-V.35 Mode)
15 mA
20 mA
10 mA
Table 3. Maximum and Minimum Peak Supply Currents
V.35
V.11
V.10
RS232
Single-Ended or Differential
Max Signal Level
DIFF
± 660 mV
DIFF
±6V
Single-Ended
±6V
Single-Ended
± 15 V
Min Signal Level
± 440 mV
± 300 mV
± 300 mV
±3V
Common-Mode Voltage
±2V
±7V
Note 1
N/A
Max Signal Peak Operation
± 2.66 V
± 10 V
± 10 V
± 15 V
Max Signal Peak no Damage
N/A
± 12 V
± 12 V
± 25 V
Rin Differential
100 Ω±10%
Note 2
N/A
N/A
Rin Common-Mode
150 Ω±15%
N/A
N/A
N/A
DC Rin Each Input to Ground
> 8K Ω
> 8K Ω
> 8K Ω
3K Ω < DC Rin < 7 K Ω
Clock Frequency
20 MHz
20MHz
120KHz
256KHz
Table 4. Receiver Specifications
Note 1: ± 7 V on Receivers 1-6, not applicable for Receivers 7-8
Note 2: 100 to 150 Ohms terminated.
Rev. 1.00
- 19 -
XRT4000
V.35
V.11
V.10
RS232
Single-Ended or Differential
Max Signal Level
DIFF
± 660 mV
RL= 100Ω
DIFF
|V0| < 6 V
RL=3900Ω
Single-Ended
4 < |V0| < 6 V
RL=3900Ω
Min Signal Level
± 440 mV
RL= 100Ω
|VT| > 0.9 V0
RL= 450Ω
N/A
2V < |VT|
>0.5 V0
RL=100Ω
|Vos| < 3V
Rout Differential
100Ω ± 10%
100Ω
N/A
N/A
Rout Common-Mode
150Ω ± 15%
N/A
N/A
N/A
Rout Power Off
N/A
N/A
N/A
> 300Ω
Output Slew Rate/Tr,Tf
20 ns
20 ns
1ms
< 30 V/µs
20 MHz
20 MHz
120 KHz
256 KHz
Offset Voltage
Clock Frequency
N/A
Single-Ended
±6V
3000Ω < RL <
7000Ω
±5V
3000Ω < RL <
7000Ω
N/A
Table 5. Transmitter Specification
V.10\V.28 Output Pulse Rise and Fall Time
SLEW_CNTL (pin 47) is an analog output that
controls transmitter pulse rise and fall time for
the V.10 and V.28 modes.
Connecting a
resistor, RSLEW, having a value between 0 and
200 kΩ from this pin to ground controls the
rise/fall times for V.10 and the slew rate for V.28
as shown in Figures 15 and 16 respectively.
High-Speed RS232 Mode
When E_232H* (pin 55) is set to logic 0 in
RS232 mode, the transmitters are put is a
special high-speed RS232 mode that can drive
loads of 3000Ω in parallel with 1000pF at
speeds up to 256 KHz.
Power Down Mode
All transmitters and receivers may be powered
down by either setting the pins for control bits
M0, M1 and M2 to logic 1 or by leaving them
open.
Internal Cable Terminations
XRT4000 has fully integrated receiver and
transmitter cable terminations for high speed
signals (RXD, TXD, RXC, TXC, SCTE).
Rev. 1.00
- 20 -
Therefore, no external resistors and/or switches
are necessary to implement the proper line
termination. The schematic diagrams given in
Figures 17 and 18 show the effective receiver
and transmitter terminations respectively for
each mode of operation. When a specific
electrical interface is selected by M0, M1 and
M2, the termination required for that interface is
also automatically chosen. The XRT4000
eliminates double termination problems and
makes point to multipoint operation possible in
the V.11 mode by providing the option for
disabling the internal input termination on high
speed receivers.
Glitch Filters
Occasional
extraneous
glitches
on
control/handshake signal inputs such as CTS,
RTS, DTR and DSR can have damaging effects
on the integrity of a connection. The XRT4000
is equipped with lowpass filters on the input of
each of the receivers for the control and
handshake signals.
These filters eliminate
glitches which are narrower than 10µs. The
user may disable these filters by setting
EN_FLTR to logic 0.
XRT4000
Clock Inversion
Transmit Clock signal, TXC, has an inversion
option for both DTE and DCE modes of
operation. The user can invert the polarity of the
TXC by setting CKINV* to logic 0. In the DTE
mode, the incoming TXC signal from the line will
be inverted before it is routed to the system. In
DCE mode, the incoming TXC signal from the
system will be inverted before it is sent over the
line toward the remote DTE. This feature allows
a phase correction when there is a long cable
delay between the DTE and DCE. This
correction may be necessary in order to obtain
the desired clock-to-data phase relationship.
Similarly, the outputs of the receivers (RX5 and
RX8) can be disabled by setting the EN_OUT*
input high. This allows these drivers to be
connected directly to a microcontroller bus since
they can be enabled during read cycles and
disabled in other times.
Data Inversion
XRT4000 contains internal logic to place the
interface in a loopback mode for test purposes.
The loopback feature is supported in both DTE
and DCE modes of operation and it can be
invoked by setting the LP* input at logic 0.
Possible loopback implementations are depicted
in the scenarios located at the end of this
document.
Similar to TXC, there is a provision in the
XRT4000 to invert the TXD and RXD signals.
Once the Setting the DTINV* input to logic 0
enables an inverter at the output of RX1 and
input of TX1.
Registered Mode of Operation
The XRT4000 has integrated registers allowing
users the option of clocking the values of
DSR/DTR and RL/RI signals. This can be done
if the registered mode of operation is selected
(REG=1). In this case, the values of these
signals will be latched on the positive edge of
the REG_CLK signal. In the normal mode (REG
= 0), the registers on the path of the DSR/DTR
and RL/RI are bypassed and REG_CLK will
have no effect.
Rev. 1.00
- 21 -
This feature eliminates the need for external
registers when a microcontroller is used to
control (reading and writing) DSR/DTR and
RL/RI signals.
Loopbacks
XRT4000
V.10 Rise Time (us)
3
1 10
100
10
1
10
100
3
1 10
R (K Ohms)
Figure 15. V.10 Rise Time as a Function of RSLEW
V.28 Slew Rate (V/us)
10
1
0.1
0.01
10
100
3
1 10
R (K Ohms)
Figure 16. V.28 Slew Rate Over ± 3 V Output Range
with 3 kΩ in Parallel with 2500 pF Load as a Function of RSLEW
Rev. 1.00
- 22 -
XRT4000
Echoed Clock
The XRT4000 can interface with serial
controllers which have two or three clock pins.
Furthermore, it can handle interfaces (e.g. X.21)
which have only one clock.
Information
contained in the Pin Description for the EC* and
2CK/3CK* pins shows how the user can select
the number of available clocks by applying the
appropriate logic levels to these inputs.
Self-contained DTE Loopback Testing
Equipment having a DTE interface obtains
timing information from another interface (DCE).
RXC and TXC are clocks which are sourced by
the DCE. A DTE device uses them to clock
data in/out of the interface. The SCTE clock is
generated by DTE using TXC or RXC which are
originated in the DCE.
In summary, a DTE
equipment is a timing slave.
Occasionally it is beneficial to conduct testing of
a DTE interface without connecting it to its DCE
counterpart. Lack of a synchronization source
will make the standalone testing of DTE
equipment not possible. The XRT4000 has an
on-board oscillator which can be used as a
timing source while the DCE connection is
missing. This feature allows users to conduct
loopback testing on isolated equipment with a
DTE interface.
Rev. 1.00
- 23 -
This mode is invoked if EN_OSC* is set to logic
0. This connects an internally generated clock
signal (32 kHz - 64 kHz) to the RX2D/RX3D
output. A standalone system test may be
performed by combining this feature with the
appropriate loopback mode.
Operational Scenarios
Visualizing features such as clock/data
inversion, echoed clock, and loopbacks, in DTE
and DCE modes makes configuring the
XRT4000 a non-trivial task. A series of 48
system level application diagrams located at the
end of the data sheet called “Scenarios” assist
users in understanding the benefits of these
different features. The internal XRT4000
connections required for a particular scenario
are made through MUX1 and MUX2 that are
shown on the block diagrams given in Figures 2
and 3 respectively. Table 6 contains the signal
routing information versus control input logic
level for MUX1 and Table 7 contains similar
information for MUX2.
XRT4000
the V.11 specification, it is necessary to prevent
reflections that would corrupt signals on highspeed clock and data lines. The differential
receiver input resistance without the optional
termination is 20 kΩ nominal.
APPLICATIONS INFORMATION
Traditional interfaces either require different
transmitters and receivers for each electrical
standard, or use complicated termination
switching methods to change modes of
operation. Mechanical switching schemes,
which are expensive and inconvenient, include
relays, and custom cables with the terminations
located in the connectors. Electrical switching
circuits using FETs are difficult to implement
because the FET must remain off when the
signal voltage exceeds the supply voltage and
when the interface power is off.
V.28 (RS232) Interface
The XRT4000 uses innovative, patented circuit
design techniques to solve the termination
switching problem. This device includes internal
circuitry that may be controlled by software to
provide the correct terminations for V.10
(RS423), V.11 (RS422), V.28 (RS232), and V.35
electrical interfaces. The schematic diagrams
given in Figures 17 and 18 conceptually show
the switching options for the high-speed receiver
input and transmitter output terminations
respectively. Additionally, Tables 4 and 5
provide a summary of receiver and transmitter
specifications respectively for the different
electrical modes of operation.
V.10 (RS423) Interface
Figure 19 shows a typical V.10 (RS423)
interface. This configuration uses an
unbalanced cable to connect the transmitter
TXA output to the receiver RXA input. The “B”
outputs and inputs that are present on the
differential transmitters and receivers contained
in the XRT4000 are not used. The system
ground provides the signal return path. The
receiver input resistance is 10 kΩ nominal and
no other cable termination is normally used for
the V.10 mode.
V.35 Interface
Figure 21 shows a typical V.35 interface. This
configuration uses a balanced cable to connect
the transmitter TXA and TXB outputs to the
receiver RXA and RXB inputs respectively. The
XRT4000 internal terminations meets the
following V.35 requirements. The receiver
differential input resistance is 100 Ω ± 10 Ω and
the shorted-terminal resistance (RXA and RXB
connected together) to ground is 150 Ω ± 15 Ω.
The transmitter differential output resistance is
100 Ω ± 10 Ω and the shorted-terminal
resistance (TXA and TXB connected together)
to ground is 150 Ω ± 15.
The junction of the 3 resistors (CMTX) on the
transmit termination is brought out to pins 76
and 81 for TX1 and TX2 respectively. Figure 21
shows how capacitor C having a value of 100 to
1000 pF bypasses this point to ground to reduce
common mode noise. This capacitor shorts
current caused by differential driver rise and fall
time or propagation delay miss-match directly to
ground. If it was not present, the flow of this
current through the 125 Ω resistor to ground
would cause common mode voltage spikes at
the TXA and TXB outputs.
V.11 (RS422) Interface
Figure 11 shows a typical V.11 (RS422)
interface. This configuration uses a balanced
cable to connect the transmitter TXA and TXB
outputs to the receiver RXA and RXB inputs
respectively. The XRT4000 includes provisions
for adding a 125 Ω terminating resistor for the
V.11 mode. Although this resistor is optional in
Rev. 1.00
Figure 19 shows a typical V.28 (RS232)
interface. This configuration uses an
unbalanced cable to connect the transmitter
TXA output to the receiver RXA input. The “B”
outputs and inputs that are present on the
differential transmitters and receivers contained
in the XRT4000 are not used. The system
ground provides the signal return path. The
receiver “B” input is internally connected to a 1.4
V reference source to provide a 1.4 V threshold.
The receiver input resistance is 5 kΩ nominal
and no other cable termination is normally used
for the V.28 mode.
- 24 -
XRT4000
RXxA
R9
4K
RXxB
R1
20
R2
20
S3
R3
85
R8
10K
S2
S1
R4
30
R4
30
R10
4K
To
Receiver
R11
6K
R12
6K
S4
R6
125
Mode
Switches
S2
S3
S1
V.35
V.11 Terminated
V.11 Unterminated
V.10
V.28
Closed
Open
Open
Open
Open
Closed
Open
Open
Open
Open
Open
Closed
Open
Open
Open
Figure 17. Receiver Termination
TXxB
TXxA
S2
S1
R1
50
R2
50
R3
125
Mode
Rev. 1.00
Switches
S1
S2
V.35
Closed
Closed
V.11/V.10/V.28
Open
Open
- 25 -
S4
Open
Open
Open
Open
Open
XRT4000
Figure 18. Transmitter Termination
Figure 19. Typical V.10 or V.28 Interface (R1 = 10 KΩ in V.10 and 5 KΩ in V.28)
Figure 20. Typical V.11 Interface (Termination Resistor, R1, is Optional.)
Figure 21. Typical V.35 Interface
Note: All Resistors shown above are internal to the XRT4000.
Rev. 1.00
- 26 -
XRT4000
Scenario Number
Logic Level Applied to
Control Input Name/Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal Source for
Output Name/Pin Number
DCE/
DTE*
EC*
2CK/
3CK*
LP*
CK
INV*
DT
INV*
EN
_OSC*
RX1D
TX1B-TX1A
RX2D
39
42
65
22
67
68
66
100
77,78
93
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
INVERT
UNCHANGED
UNCHANGED
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
NOTE 1
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
RX1B-RX1A
NOTE 1
INVERT
UNCHANGED
UNCHANGED
RX2B-RX2A
RX2B-RX2A
TX2D
TX2D
RX2B-RX2A
RX2B-RX2A
TX2D
TX2D
RX2B-RX2A
TX3D
TX2D
TX2D
RX2B-RX2A
TX3D
TX2D
TX2D
RX2B-RX2A
TX2D
TX2D
TX2D
RX2B-RX2A
(TX2D)*
TX2D
TX2D
RX2B-RX2A
RX2B-RX2A
TR3B-TR3A
TX3D
RX2B-RX2A
RX2B-RX2A
(TR3B-TR3A)*
TX3D
RX2B-RX2A
TX3D
TR3B-TR3A
TX3D
RX2B-RX2A
TX3D
(TR3B-TR3A)*
TX3D
RX2B-RX2A
TX3D
RX2B-RX2A
TX3D
RX2B-RX2A
(TX3D)*
RX2B-RX2A
TX3D
UNCHANGED
UNCHANGED
32-64 kHz
Table 6. MUX1 Connection Table
Table entries are inputs to MUX1.
Column headings are outputs.
Signal names ending with A or B are analog inputs or outputs.
Rev. 1.00
- 27 -
TX2B-TX2A
RX3D
TR3B-TR3A
80,79
90
88,87
TX2D
TX2D
RX2B-RX2A
RX2B-RX2A
TX2D
TX2D
RX2B-RX2A
RX2B-RX2A
X
TX2D
X
TX3D
X
TX2D
X
TX3D
X
TX2D
X
RX2B-RX2A
X
TX2D
X
TX2D
TR3B-TR3A
TX3D
RX2B-RX2A
RX2B-RX2A
(TR3B-TR3A)*
TX3D
RX2B-RX2A
RX2B-RX2A
X
TX3D
X
TX3D
X
TX3D
X
TX3D
X
TX3D
X
TX3D
X
TX3D
X
TX3D
UNCHANGED
UNCHANGED
UNCHANGED
TR3B-TR3A
X
TR3B-TR3A
X
(TR3B-TR3A)*
X
(TR3B-TR3A)*
X
TR3B-TR3A
X
TR3B-TR3A
X
(TR3B-TR3A)*
X
(TR3B-TR3A)*
X
RX2B-RX2A
X
TR3B-TR3A
X
(RX2B-RX2A)*
X
(RX2B-RX2A)*
X
TR3B-TR3A
X
TR3B-TR3A
X
(TR3B-TR3A)*
X
(TR3B-TR3A)*
X
TR3B-TR3A
X
TR3B-TR3A
X
(TR3B-TR3A)*
X
(TR3B-TR3A)*
X
RX2B-RX2A
X
RX2B-RX2A
X
(RX2B-RX2A)*
X
RX2B-RX2A
X
UNCHANGED
32-64 kHz
32-64 kHz
X
TX3D
X
TX3D
X
(TX3D)*
X
(TX3D)*
X
TX3D
X
TX3D
X
(TX3D)*
X
(TX3D)*
X
X
X
X
X
X
X
X
X
TX3D
X
TX3D
X
(TX3D)*
X
(TX3D)*
X
TX3D
X
TX3D
X
(TX3D)*
X
(TX3D)*
X
X
X
X
X
X
X
X
UNCHANGED
UNCHANGED
UNCHANGED
XRT4000
Signal names ending with D are digital inputs or outputs.
* Indicates signal complement.
Note 1: Refer to Figure 22 located on the next page for signal definition.
X is don’t care.
Figure 22. Signal Definition for Scenario Number 48
Scenario
Number
Control Input/
Pin Number
Signal Source for
Output Name/Pin Number
DCE/
DTE*
LP*
RX4D
TX4B-TX4A
RX5D
TX5B-TX5A
RX67D
TR6B-TR6A
TR7
39
22
48
15,16
41
18,17
40
38,37
35
1
0
0
TX4D
RX4B-RX4A
TX5D
TR6B-TR6A
TX5D
X
TX76D
2
0
1
RX4B-RX4A
TX4D
RX5B-RX5A
TX5D
TR6B-TR6A
X
TX76D
3
1
0
TX4D
RX4B-RX4A
TX76D
RX5B-RX5A
TR7
RX5B-RX5A
X
4
1
1
RX4B-RX4A
TX4D
RX5B-RX5A
TX5D
TR7
TX76D
X
Table 7. MUX2 Connection Table
Table entries are inputs to MUX2. Column headings are outputs.
Signal names ending with A or B are analog inputs or outputs. Signal names ending with D are digital
inputs or outputs.
Rev. 1.00
- 28 -
XRT4000
Operating Modes for the XRT4000 Device
The XRT4000 Multiprotocol Serial Interface
device can be configured to operate in a
wide variety of modes or “scenarios”. This
document illustrates some of these
“scenarios” and provides the reader with the
following information associated with each of
these scenarios.
• Which pins (on the “DCE Mode” XRT4000
and “DTE Mode” XRT4000 devices) are
used to propagate various data or clock
signals.
• Which signals are to be used when
operating the XRT4000 devices in the
“differential” or “single-ended” modes.
• How does one configure the “DCE Mode”
and “DTE Mode” XRT4000 device to
operate in these scenarios.
Rev. 1.00
Notes:
1. The “line” signals are drawn with both a
“solid” line and a “dashed” line. Both lines
are used to transmit and receive “differential”
mode signals. However, the “solid” line
indentifies the signal that should be used,
when operating the Transmitter in the
“Single-Ended” mode.
2. Each scenarios includes a table that indicates
how to configure the XRT4000 device into
each of these modes, by specifying the
appropriate logic states for EC*, 2CK/3CK*,
LP*, CKINV*, DTINV*, and EN_OSC*.
3. In all, 48 scenarios have been defined for the
XRT4000 device. Currently, this document
only lists a subset of these scenarios.
Further versions of the XRT4000 data sheet
will include this information for all 48
scenarios.
- 29 -
XRT4000
Scenarios 1 & 2
TXD
SCTE
78
75
TX1
79
82
TX2
90
RX3
93
RX2
HDLC (L)
100
SCTE
95
TXC
93
RX2
87
RXD
RXC
84
TX3
88
TXC
79
RXC
82
95
RX1
100
RX1
96
88
97
RXD
98
80
96
RXC
97
77
87
TXC
TXD
TX2
80
RXD
SCTE
78
TX1
77
98
75
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenarios 1 & 2)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
0
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 30 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
0
1
1
1
1
XRT4000
Scenario 3
78
75
TXD
TX1
TX2
90
RX3
RXC
RX2
HDLC (L)
100
RX1
100
RX1
RXD
96
95
TXC
93
RX2
87
RXC
RXC
84
TX3
88
TXC
79
82
95
97
RXD
SCTE
88
96
93
98
80
87
TXC
97
77
79
82
SCTE
TXD
TX2
80
SCTE
78
RXD
TX1
77
98
75
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 3)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
0
0
1
1
1
Pin Number
39
42
65
22
67
68
66
- 31 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
0
1
1
1
1
XRT4000
Scenario 4
78
75
TXD
SCTE
TX1
TX2
90
RX3
93
RX2
HDLC (L)
100
RX1
RXD
96
93
RX2
RXC
87
84
TX3
88
RXC
TXC
79
82
95
97
RXD
TXC
100
RX1
95
88
96
RXC
SCTE
80
87
TXC
97
98
77
79
82
TXD
RXD
98
SCTE
TX2
80
78
75
TX1
77
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 4)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
0
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 32 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
0
0
1
1
1
XRT4000
Scenario 5
78
75
TXD
TX1
TX2
90
RX3
93
RX2
HDLC (L)
100
RX1
100
RX1
RXD
96
95
TXC
93
RX2
RXC
87
RXC
84
TX3
88
TXC
79
95
97
RXD
SCTE
88
96
RXC
98
80
87
TXC
97
77
79
82
SCTE
TXD
RXD
82
TX2
80
SCTE
78
TX1
77
98
T4000 (DTE)
75
T4000 (DCE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 5)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
0
1
0
1
1
Pin Number
39
42
65
22
67
68
66
- 33 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
0
1
1
1
1
XRT4000
Scenario 6
78
75
TXD
TX1
79
TX2
90
RX3
93
RX2
HDLC (L)
100
RX1
100
RX1
RXD
96
95
TXC
93
RX2
RXC
87
RXC
84
TX3
88
TXC
79
82
95
97
RXD
SCTE
88
96
RXC
98
80
87
TXC
97
77
82
SCTE
TXD
TX2
80
SCTE
78
RXD
TX1
77
98
75
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenarios 1 & 2)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
0
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 34 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
0
1
0
1
1
XRT4000
Scenario 7
78
TXD
75
TXD
TX1
82
TX2
SCTE
77
98
79
SCTE 96
80
95
87
TXC
90
93
HDLC (L)
RXC
RX2
100
RX1
RXD
87
RXC
TXC
79
82
TX2
SCTE
78
TX1
75
T4000 (DCE)
T4000 (DTE)
RXD
84
TX3
77
98
93
RX2
80
95
100
RX1
88
88
97
RXD
TXC
RX3
96
RXC
97
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenarios 7)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
0
0
0
1
1
Pin Number
39
42
65
22
67
68
66
- 35 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
0
1
1
1
1
XRT4000
Scenario 8
78
TXD
75
TX1
82
TX2
90
RX3
93
RX2
HDLC (L)
100
RX1
RXC
93
RX2
84
TX3
TXC
79
82
98
RXC
87
TX2
80
RXD
RXD
96
88
95
97
RXD
TXC
100
RX1
95
88
96
RXC
SCTE
80
87
TXC
97
98
77
79
SCTE
TXD
SCTE
78
75
TX1
77
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 8)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
0
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 36 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
0
0
0
1
1
XRT4000
Scenarios 9 & 10
78
TXD
SCTE
75
TX1
82
TX2
90
RX3
98
79
96
80
95
93
RX2
HDLC (L)
100
RX1
100
RX1
93
RX2
87
RXC
RXD
RXC
84
TX3
88
TXC
79
82
95
97
RXD
TXC
88
96
RXC
97
77
87
TXC
TXD
TX2
80
RXD
SCTE
78
TX1
77
98
75
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenarios 9 & 10)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
1
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 37 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
1
1
1
1
1
XRT4000
Scenario 12
78
75
TXD
TX1
82
SCTE
TX2
90
RX3
98
79
96
80
95
93
RX2
HDLC (L)
100
RX1
100
RX1
93
RX2
RXD
RXC
87
84
TX3
88
RXC
TXC
79
82
95
97
RXD
TXC
88
96
RXC
97
77
87
TXC
TXD
TX2
80
RXD
98
SCTE
78
75
TX1
77
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 12)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
0
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 38 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
1
0
1
1
1
XRT4000
Scenario 13
78
TXD
SCTE
75
TX1
82
TX2
90
RX3
98
79
96
80
95
93
RX2
HDLC (L)
100
RX1
100
RX1
93
RX2
RXD
RXC
87
RXC
84
TX3
88
TXC
79
95
97
RXD
TXC
88
96
RXC
97
77
87
TXC
TXD
RXD
82
TX2
80
SCTE
78
TX1
77
98
75
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 13)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
1
1
0
1
1
Pin Number
39
42
65
22
67
68
66
- 39 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
1
0
1
1
1
XRT4000
Scenario 14
78
TXD
SCTE
75
TX1
82
TX2
90
RX3
98
79
96
80
95
93
RX2
HDLC (L)
100
RX1
100
RX1
93
RX2
87
RXC
RXD
RXC
84
TX3
88
TXC
79
95
97
RXD
TXC
88
96
RXC
97
77
87
TXC
TXD
RXD
82
TX2
80
SCTE
78
TX1
77
98
75
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 14)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
1
1
0
1
1
Pin Number
39
42
65
22
67
68
66
- 40 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
1
1
0
1
1
XRT4000
Scenario 16
78
75
TXD
SCTE
TX1
82
TX2
90
RX3
98
79
96
80
95
93
RX2
HDLC (L)
100
RX1
RXC
100
RX1
93
RX2
84
TX3
82
98
RXC
TXC
79
TX2
80
RXD
RXD
87
88
95
97
RXD
TXC
88
96
RXC
97
77
87
TXC
TXD
SCTE
78
75
TX1
77
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 16)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
1
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 41 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
1
0
0
1
1
XRT4000
Scenario 17 & 18
78
75
TXD
TX1
82
SCTE
TXC
TX2
90
RX3
93
RX2
98
79
96
80
95
87
87
88
88
HDLC (L)
100
RX1
RXC
100
RX1
93
RX2
RXD
RXC
84
TX3
TXC
79
82
95
97
RXD
97
77
96
RXC
TXD
TX2
80
RXD
SCTE
78
TX1
77
98
75
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 17 & 18)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
X
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 42 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
X
1
1
1
1
XRT4000
Scenario 20
78
75
TXD
TX1
82
SCTE
TXC
TX2
90
RX3
93
RX2
98
79
96
80
95
87
87
88
88
HDLC (L)
100
RX1
100
RX1
93
RX2
RXD
RXC
84
RXC
TX3
TXC
79
82
95
97
RXD
97
77
96
RXC
TXD
TX2
80
RXD
98
SCTE
78
75
TX1
77
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 20)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
X
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 43 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
X
0
1
1
1
XRT4000
Scenario 21
78
TXD
SCTE
TXC
75
TX1
82
TX2
90
RX3
93
RX2
98
79
96
80
95
87
87
88
88
HDLC (L)
100
RX1
RXC
100
RX1
93
RX2
84
TX3
RXD
RXC
TXC
79
95
97
RXD
97
77
96
RXC
TXD
RXD
82
TX2
80
SCTE
78
TX1
77
98
75
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 21)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
X
1
0
1
1
Pin Number
39
42
65
22
67
68
66
- 44 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
X
1
1
1
1
XRT4000
Scenario 22
78
TXD
SCTE
TXC
75
TX1
98
79
96
80
95
82
TX2
90
RX3
87
87
88
88
93
RX2
HDLC (L)
100
RX1
100
RX1
93
RX2
RXC
TXC
82
TX2
80
RXD
RXD
84
TX3
79
RXC
95
97
RXD
97
77
96
RXC
TXD
SCTE
78
75
TX1
77
98
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 22)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
X
1
1
1
1
Pin Number
39
42
65
22
67
68
66
- 45 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
X
1
0
1
1
XRT4000
Scenario 23
78
TXD
75
TXD
TX1
82
TX2
SCTE
TXC
90
77
98
79
96
80
95
87
87
88
88
RX3
96
RXC
93
HDLC (L)
RXC
RX2
100
RX1
RXD
100
RX1
RXD
93
RX2
RXC
84
TX3
TXC
79
82
TX2
80
95
97
RXD
97
SCTE
78
75
TX1
77
98
T4000 (DCE)
T4000 (DTE)
TXD
HDLC (R)
Options
DTE
DCE
Normal
Echo Mode
3 Clocks
2 Clocks
1 Clock (X.21)
No Loopback
Loopback
No Invert
Invert
Input Pin Settings (Scenario 23)
Pin Number
39
42
65
22
67
68
66
Rev. 1.00
T4000 (DTE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
0
1
X
0
0
1
1
Pin Number
39
42
65
22
67
68
66
- 46 -
T4000 (DCE)
Name
DCE/DTE*
EC*
2CK/3CK*
LP*
CKINV*
DTINV*
EN_OSC*
State
1
1
X
1
1
1
1