Realtek RTD2023L RTD2023L Flat Panel Display Controller Version 0.13 Last updated: 2005/3/30 Realtek RTD2023L Revision History 0.13 3/30/2005 Initial release 2 Realtek RTD2023L 1. Features z General z z z z z z Support DDCCI Zoom scaling up and down No external memory required. Require only one crystal to generate all timing. Programmable 3.3V/5V detection reset output. 3 channels 8 bits PWM output, and wide range selectable PWM frequency. Host Interface z Support MCU serial bus interface. z Support MCU dual edge data latch. Embedded OSD z Embedded 12K SRAM dynamically stores OSD Analog RGB Input Interface z z z z z Integrated 8-bit triple-channel 165MHz ADC/PLL Embedded programmable Schmitt trigger of HSYNC Support Sync On Green (SOG) and various kinds of composite sync modes On-chip high-performance hybrid PLLs High resolution true 64 phase ADC PLL z z z z z z z z Auto Detection /Auto Calibration z z z Input format detection Compatibility with standard VESA mode and support user-defined mode Smart engine for Phase/Image position/Color calibration z z z Fully programmable zoom ratios Independent horizontal/vertical scaling Advanced zoom algorithm provides high image quality Sharpness/Smooth filter enhancement Support non-linear scaling from 4:3 to 16:9 or 16:9 to 4:3 BJT control Color Processor z z z z z z z True 10 bits color processing engine sRGB compliance Advanced Dithering logic for 18-bit panel color depth enhancement Content adaptive edge enhancement. Dynamic overshoot-smear canceling engine Brightness and contrast control Programmable 10-bit gamma support Output Interface z z z z command and fonts Support multi-color RAM font, 1, 2 and 4-bit per pixel 16 color palette with 24bit true color selection Maximum 8 window with alpha-blending/ gradient/dynamic fade-in/fade-out, bordering/ shadow/3D window type Every window can place anywhere on the screen Rotary 90,180,270 degree Independent row shadowing/bordering Programmable blinking effects for each character OSD-made internal pattern generator for factory mode Support 12x18~4x18 proportional font Power & Technology z 1.8V and 3.3V power supplier z 0.18um CMOS process, 48-pin LQFP package z Embedded 3.3V to 1.8V voltage regulator (P type) Scaling z z z Fixed Last Line output for perfect panel capability Fully programmable display timing generator Flexible data pair swapping for easier system design. Dual/Single LVDS output interface Spread-Spectrum DPLL to reduce EMI 3 Realtek RTD2023L 2. Pin-Out Diagram Analog Input with LVDS (when CR8D[7] = 0 ) Analog Input with LVDS (when CR8D[7] = 1 ) 4 Realtek RTD2023L APLL_GND APLL_VDD PLL TEST1/PWM0 1 2 3 RTD2023L & RTD2323/RTD2523B pin-to-pin Illustration 5 Realtek RTD2023L 3. Pin Description (I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground) INPUT PORT Name I/O I 4 AHS I 5 AI AI AI AI AI AI AI AG AP 6 7 8 9 10 11 12 13 14 I/O Pin No Description XO XI AO AI 1 2 PLL_GND PLL_VDD AG AP 3 48 Crystal OSC output Reference clock input from external crystal or from single-ended CMOS/TTL OSC Ground for display digital PLL Power for digital PLL (3.3V) I/O Pin No Description I/O O O 43/15 44/16 45/17 PLL Name SDIO[3] SCSB SCLK ADC vertical sync input Adjustable Schmidt trigger Power from PIN 48 ADC horizontal sync input Power from PIN 48 Negative BLUE analog input Positive BLUE analog input Negative GREEN analog input Positive GREEN analog input Sync on Green Negative RED analog input Positive RED analog input ADC Ground ADC Power (1.8V) Tolerance Note 5V 5V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Tolerance Note 3.3V Host interface Name Description AVS BB+ GG+ SOG RR+ ADC_GND ADC_VDD Pin No Serial control I/F data in (Open drain) Serial control I/F chip select (Open drain) Serial control I/F clock (Open drain) Tolerance Note 5V 5V 5V Pad/Digital Power & Ground Name I/O Pin No Pad 1.8V Power Pad 1.8V Ground P G 19/42 20/41 Description Tolerance Note Description Tolerance Note PVCC ( 1.8V) PGND DDC Channel & PWM Name I/O No PWM0 DDCSCL/PWM1 DDCSDA/PWM2 O I/O I/O 15/45 16/44 17/43 I/O No BJT_B O 18 RESET_OUT O 46 33VRST_REF I 47 Open drain Open drain Open drain 5V 5V 5V MISC Name Description Embedded regulator P type BJT control pin out Reset out Open drain Reference 3.3V for Reset Out 6 Tolerance 3.3V 5V Note Realtek RTD2023L LVDS Display Interface Name I/O No TXE3+ / TXE0TXE3- / TXE0+ TXEC+ / TXE1TXEC- / TXE1+ TXE2+ / TXE2TXE2- / TXE2+ TXE1+ / TXECTXE1- / TXEC+ TXE0+ / TXE3TXE0- / TXE3+ TXO3+ / TXO0TXO3- / TXO0+ TXOC+ / TXO1TXOC- / TXO1+ TXO2+ / TXO2TXO2- / TXO2+ TXO1+ / TXOCTXO1- / TXOC+ TXO0+ / TXO3TXO0- / TXO3+ O O O O O O O O O O O O O O O O O O O O 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Description (CR8D[7] = 0 ) / (CR8D[7] = 1 ) 7 Tolerance 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V Note Realtek RTD2023L 4.Architecture Y RSDS/LVDS/TTL PANEL PANEL VCC Pb Pr R G B R G B RTD2323 DVI RESET OUT MCU 5 to 3.3 Regulator Video Decoder CVBS 5V Power Source RST RST XI MCU COUT RTD2023L MCU 8 RTD2023L Realtek RTD2023L 5. Mechanical Specification 48 Pin LQFP L L1 SYMBOL MILLIMETER MIN. TYPICAL A MAX. MIN. TYPICAL 1.60 A1 0.05 A2 1.35 c 0.09 1.40 TITLE: LQFP-48 (7.0x7.0x1.6mm) INCH PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm MAX 0.063 0.15 0.002 1.45 0.053 0.20 0.004 0.006 0.055 0.057 LEADFRAME MATERIAL APPROVE 0.008 DOC. NO. D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 DATE E 9.00 BSC 0.354 BSC REALTEK SEMICONDUCTOR CORP. E1 7.00BSC 0.276 BSC E2 5.50 0.217 b 0.17 e 0.20 0.27 0.007 0.50 BSC 0.008 CHECK 0.011 0.0196 BSC TH 0o 3.5o 7o 0o 3.5o 7o L 0.45 0.60 0.75 0.018 0.0236 0.030 L1 1.00 0.0393 9 VERSION 02 DWG NO PKGC-065