TPD7S019 www.ti.com SLLSE33 – MAY 2010 7-CHANNEL INTEGRATED ESD SOLUTION FOR VGA PORT WITH INTEGRATED LEVEL SHIFTER AND MATCHING IMPEDANCE Check for Samples: TPD7S019 FEATURES 1 • • • • • 7-Channel ESD Protection Includes ESD Protection, Level-Shifting, Buffering and Sync Impedance Matching Exceeds IEC61000-4-2 (Level 4) ESD Protection to Requirements on the External Pins – ±15-kV Human-Body Model (HBM) – ±8-kV IEC 61000-4-2 Contact Discharge Very Low Loading Capacitance from ESD Protection Diodes on VIDEO Lines (2.5 pF) 5-V Drivers for HSYNC and VSYNC Lines Integrated Impedance Matching Resistors on Sync Lines: – TPD7S019-65: 65-Ω Termination – TPD7S019-15: 15-Ω Termination – TPD7S019-55: 55-Ω Termination • • Bi-Directional Level Shifting N-Channel FETs Provided for DDC_CLK and DDC_DATA Channels Flow-Through Single-In-Line Pin Mapping Ensures no Additional Board Layout Burden while Placing the ESD Protection Chip Near the Connector APPLICATIONS • VGA and DVI-I Ports in: – Desktop and Notebook PCs – Graphics Cards – Set Top Boxes – TV RSV PACKAGE (TOP VIEW) DBQ PACKAGE (TOP VIEW) ORDERING INFORMATION TA PACKAGE µQFN – RSV –40°C to 85°C (1) (2) SSOP/QSOP – DBQ (1) (2) Tape and reel Tape and reel ORDERABLE PART NUMBER TOP-SIDE MARKING TPD7S019-15RSVR PREVIEW TPD7S019-15DBQR PQ19-15 TPD7S019-55DBQR PREVIEW TPD7S019-65DBQR PREVIEW Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPD7S019 SLLSE33 – MAY 2010 TERMINATION AT SYNC www.ti.com PITCH LENGTH (TYP) WIDTH (TYP) HEIGHT (MAX) 15-Ω 55-Ω TPD7S019-15DBQR 0.635 mm 4.9 mm 6.0 mm 1.75 mm 0.4 mm 2.6 mm 1.8 mm 0.55 mm 65-Ω 15-Ω ORDERABLE PART NO. TPD7S019-55DBQR TPD7S019-65DBQR TPD7S019-15RSVR DESCRIPTION/ORDERING INFORMATION The TPD7S019 is an integrated 7-channel ESD solution for the VGA or DVI-I port connector. This device integrates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. Three individual supply lines control the power rails of the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage video controller ICs in mixed supply-voltage environments. Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the video controller IC (SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC_SYNC, which is typically 5 V. Additionally, each driver has a series termination resistor (RT) connected to the SYNC_OUT pin, eliminating the external termination resistors typically required for the HSYNC and VSYNC lines of the video cable. At the SYNC output the TPD7S019 offers 65-Ω, 55-Ω, or 15-Ω series termination resistor option to match different transmisison line impedances. Two N-channel MOSFETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. The gate terminals for the MOSFETs (VCC_DDC) should be connected to the supply rail (typically 3.3 V) that supplies power to the transceivers of the DDC controller. The TPD7S019 confirms the IEC61000-4-2 (Level 4) system level ESD protection and ±15KV HBM ESD protection. This device is offered in space-saving 16-pin DBQ and 16-pin RSV packages. The TPD7S019 is characterized for operation over ambient air temperature of –40°C to 85°C. CIRCUIT DIAGRAM 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD7S019 TPD7S019 www.ti.com SLLSE33 – MAY 2010 TERMINAL FUNCTIONS TERMINAL NAME NO. TYPE DBQ RSV 8 6 Power DDC_IN1 DDC_IN2 10 11 8 9 I DDC_OUT1 DDC_OUT2 9 12 7 10 O BYP DESCRIPTION Bypass pin. Using a 0.2 µF bypass capacitor will increase the ESD robustness of the system. DDC signal input. Connects to the VGA controller side of one of the sync lines. DDC signal output. Connects to the video connector side of one of the sync lines. GND 6 4 – SYNC_IN1 SYNC_IN2 13 15 11 13 I SYNC_OUT1 SYNC_OUT2 14 16 12 14 O VCC_DDC 7 5 Power Isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates 1 15 Power Isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associated ESD protection circuits VCC_VIDEO 2 16 Power Supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits VIDEO1 VIDEO2 VIDEO3 3 4 5 1 2 3 ESD VCC_SYNC Ground Sync signal buffer input. Connects to the VGA controller side of one of the sync lines. Sync signal buffer output. Connects to the video connector side of one of the sync lines High-speed ESD clamp input ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX –0.5 6.0 V VIDEOx pins –0.5 VCC_VIDEO V SYNC pins –0.5 VCC_SYNC V Input voltage DDC_INx pins –0.5 6.0 V Output voltage DDC_INx pins –0.5 6.0 V –55 125 °C kV VCC_VIDEO, VCC_DDC, VCC_SYNC Supply voltage VIO(VIDEO) IO voltage VI(SYNC) Input voltage VI(DDC) VO(DDC) Tstg Storage temperature (1) IEC 61000-4-2 Contact Discharge VIDEO, DDC_OUT, SYNC_OUT pins ±8 HBM ESD VIDEO, DDC_OUT, SYNC_OUT pins ±15 VCC, DDC_IN, SYNC_IN, BYP Pins ±2 UNIT kV Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT 0 5.5 V VCC_VIDEO, VCC_DDC, VCC_SYNC Supply voltage VIO(VIDEO) IO voltage VIDEOx pins 0 VCC_VIDEO V VI(SYNC) Input voltage SYNC pins 0 VCC_SYNC V VI(DDC) Input voltage DDC_INx pins 0 5.5 V VO(DDC) Output voltage DDC_INx Pins 0 5.5 V TA Operating temperature –40 85 °C Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD7S019 3 TPD7S019 SLLSE33 – MAY 2010 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT ICC_VIDEO VCC_VIDEO supply current VCC_VIDEO = 5 V, VIDEO inputs at VCC_VIDEO or GND 1 10 ICC_DDC VCC_DDC supply current VCC_DDC = 5 V 1 10 ICC_SYNC VCC_SYNC supply current VCC_SYNC = 5 V, SYNC inputs at GND or VCC_SYNC, SYNC outputs unloaded 1 50 µA µA µA SYNC inputs at 3 V; SYNC outputs unloaded 2.0 mA IIO_VIDEO VIDEO input/output pins VIO_VIDEO = 3 V 0.01 1.0 µA IOFF DDC pin powerdown leakage current VCC_DDC ≤ 0.4 V, VDDC_OUT = 5 V 0.01 1.0 µA VD Diode forward voltage for lower clamp of VIDEO, DDC, SYNC output pins ID = 8 mA, lower clamp diode –0.8 –0.95 RDYN_VIDEO Dynamic resistance (VIDEO pins) I=1A VIH High-level SYNC logic input voltage VCC_SYNC = 5 V VIL Low-level SYNC logic input voltage VCC_SYNC = 5 V VOH High-level SYNC logic output voltage IOH = 0 mA, VCC_SYNC = 5 V VOH-15 High-level SYNC logic output voltage IOH = 24 mA, VCC_SYNC = 5 V VOL Low-level SYNC logic output voltage IOH = 0 mA, VCC_SYNC = 5 V 0.15 VOL-15 Low-level SYNC logic output voltage TPD7S019-15 IOH = 24 mA, VCC_SYNC = 5 V 0.8 RT SYNC driver output resistance TPD7S019-15 VCC_SYNC = 5 V, SYNC inputs at GND or 3 V TPD7S019-15 –0.6 V Ω 1.0 2.0 V 0.6 4.85 V V 2 V V V 15 TPD7S019-55 55 TPD7S019-65 65 2.5 Ω CIO_VIDEO IO capacitance of VIDEO pins VIO = 2.5 V 4 pF tPLH SYNC driver L => H propagation delay CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns 12 ns tPHL SYNC driver H => L propagation delay CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns 12 ns tR, tF SYNC driver output rise & fall times CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns VBR VIDEO ESD diode break-down voltage IIO = 1 mA 4 9 ns V Typical Characteristics Figure 1. TPD7S019-xx TLP VID1 to GND, Barth, Trf = 10 ns 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD7S019 TPD7S019 www.ti.com SLLSE33 – MAY 2010 Typical Characteristics (continued) Figure 2. TPD7S019-xx IEC Clamping Waveforms Positive Contact Figure 3. TPD7S019-xx IEC Clamping Waveforms Negative Contact Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD7S019 5 TPD7S019 SLLSE33 – MAY 2010 www.ti.com Typical Characteristics (continued) Figure 4. Leakage Current Trough VIDEO Pins VCC_VIDEO = 5 V Figure 5. IOFF (DDC_OUTx) VCC_DDC = 0 V 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD7S019 TPD7S019 www.ti.com SLLSE33 – MAY 2010 APPLICATION INFORMATION Figure 6. Typical Application Schematics with TPD7S019 RP: Pullup resistor for the DDC data and clock lines. Typically system designer selects 47 kΩ pullup values RT: Line termination resistor for the RGB lines. RT is selected to match the transmission line. For a single-ended transmission line, RT can be anywhere from 50 Ω to 75 Ω depending on board trace impedance. Some systems may require additional filters at the SYNC and RGB lines. The TPD7S019 should be placed as close to the VGA port as possible. The ESD protection channels VIDEO1, VIDEO2, VIDEO3 are identical circuits, they can be used interchangeably between the R, G, B signals. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD7S019 7 TPD7S019 SLLSE33 – MAY 2010 www.ti.com Figure 7. Simplified Layout with TPD7S019 (Only IO Lines are Shown) 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD7S019 PACKAGE OPTION ADDENDUM www.ti.com 21-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPD7S019-15DBQR ACTIVE SSOP/QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples TPD7S019-55DBQR PREVIEW SSOP/QSOP DBQ 16 2500 TBD Call TI Call TI Samples Not Available TPD7S019-65DBQR PREVIEW SSOP/QSOP DBQ 16 2500 TBD Call TI Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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