SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178B – MARCH 1984 – REVISED MAY 1997 D Inputs Are TTL-Voltage Compatible Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs SN54HCT646 . . . JT OR W PACKAGE SN74HCT646 . . . DW OR NT PACKAGE (TOP VIEW) CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND description Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be stored in one register and /or B data can be stored in the other register. 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8 DIR SAB CLKAB NC VCC CLKBA SBA SN54HCT646 . . . FK PACKAGE (TOP VIEW) A1 A2 A3 NC A4 A5 A6 5 4 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 3 19 12 13 14 15 16 17 18 A7 A8 GND NC B8 The ’HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental busmanagement functions that can be performed with the ’HCT646. 1 OE B1 B2 NC B3 B4 B5 B7 B6 D D D D D NC – No internal connection When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. The SN54HCT646 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74HCT646 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 21 OE L 3 DIR L 1 23 CLKAB CLKBA X X 2 SAB X BUS B BUS A BUS A BUS B SCLS178B – MARCH 1984 – REVISED MAY 1997 22 SBA L 21 OE L 3 DIR H 3 DIR X X X 1 23 CLKAB CLKBA X ↑ X ↑ ↑ ↑ 2 SAB X X X 22 SBA X X X 21 OE L L 22 SBA X BUS B 3 DIR L H STORAGE FROM A, B, OR A AND B 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H TRANSFER STORED DATA TO A AND/OR B Pin numbers shown are for the DW, JT, NT, and W packages. Figure 1. Bus-Management Functions 2 2 SAB L BUS A BUS A 21 OE X X H 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 22 SBA H X SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178B – MARCH 1984 – REVISED MAY 1997 FUNCTION TABLE INPUTS DATA I/O OPERATION OR FUNCTION OE DIR CLKAB CLKBA SAB SBA A1– A8 B1– B8 X X ↑ X X X Input Unspecified† X X X ↑ X X Unspecified† Input Store A, B unspecified† Store B, A unspecified† H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus † The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. logic symbol‡ OE DIR CLKBA SBA CLKAB SAB A1 21 3 23 22 1 2 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 ≥1 4 1 7 1 A3 A4 A5 A6 A7 A8 20 B1 5 1 6D A2 4D 5 ≥1 2 7 5 19 6 18 7 17 8 16 9 15 10 14 11 13 B2 B3 B4 B5 B6 B7 B8 ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, NT, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178B – MARCH 1984 – REVISED MAY 1997 logic diagram (positive logic) OE DIR CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DW, JT, NT, and W packages. absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178B – MARCH 1984 – REVISED MAY 1997 recommended operating conditions SN54HCT646 SN74HCT646 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0 0.8 0 0.8 V Input voltage 0 0 Output voltage 0 0 VCC VCC V VO tt VCC VCC 0 500 0 500 ns TA Operating free-air temperature –55 125 –40 85 °C High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 Input transition (rise and fall) time 2 V V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = –20 µA IOH = –6 mA 45V 4.5 VOL VI = VIH or VIL IOL = 20 µA IOL = 6 mA 45V 4.5 II IOZ Control inputs A or B ICC ∆ICC† Ci MIN TA = 25°C TYP MAX SN54HCT646 MIN MAX SN74HCT646 MIN 4.4 4.499 4.4 4.4 3.98 4.3 3.7 3.84 MAX UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 ±1000 ±1000 nA V VI = VCC or 0 VO = VCC or 0 5.5 V ±0.1 ±100 5.5 V ±0.01 ±0.5 ±10 ±5 µA VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC 5.5 V 8 160 80 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF 5.5 V 4.5 V to 5.5 V Control inputs † This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock l k Clock frequency tw Pulse duration, duration CLKBA or CLKAB high or low tsu Set p time, Setup time A before CLKAB↑ or B before CLKBA↑ th time A after CLKAB↑ or B after CLKBA↑ Hold time, TA = 25°C MIN MAX SN54HCT646 SN74HCT646 MIN MAX MIN MAX 4.5 V 0 31 0 22 0 27 5.5 V 0 36 0 24 0 29 4.5 V 16 23 19 5.5 V 14 21 17 4.5 V 20 30 25 5.5 V 18 27 23 4.5 V 5 5 5 5.5 V 5 5 5 UNIT MHz ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178B – MARCH 1984 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLKBA or CLKAB tpd d A or B A or B B or A SBA or SAB† A or B ten OE A or B tdis di OE A or B ten DIR A or B tdis di DIR A or B tt Any VCC MIN TA = 25°C TYP MAX SN54HCT646 MIN MAX SN74HCT646 MIN 4.5 V 31 54 22 27 5.5 V 36 64 24 29 MAX UNIT MHz 4.5 V 18 36 54 45 5.5 V 16 32 49 41 4.5 V 14 27 41 34 5.5 V 12 24 37 31 4.5 V 20 38 57 48 5.5 V 17 34 51 43 4.5 V 25 49 74 61 5.5 V 22 44 67 55 4.5 V 25 49 74 61 5.5 V 22 44 67 55 4.5 V 25 49 74 61 5.5 V 22 44 67 55 4.5 V 25 49 74 61 5.5 V 22 44 67 55 4.5 V 9 12 18 15 5.5 V 7 11 16 14 ns ns ns ns ns ns † These parameters are measured with the internal output state of the storage register opposite that of the bus input. switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd d FROM (INPUT) TO (OUTPUT) CLKBA or CLKAB A or B A or B B or A SBA or SAB† A or B OE A or B DIR A or B ten tt Any VCC MIN TA = 25°C TYP MAX SN54HCT646 MIN MAX SN74HCT646 MIN MAX 4.5 V 24 53 80 66 5.5 V 22 47 52 60 4.5 V 22 44 67 55 5.5 V 20 39 60 50 4.5 V 26 55 83 69 5.5 V 24 49 74 62 4.5 V 33 66 100 87 5.5 V 22 59 90 74 4.5 V 33 66 100 87 5.5 V 22 59 90 74 4.5 V 17 42 63 53 5.5 V 14 38 57 48 UNIT ns ns ns † These parameters are measured with the internal output state of the storage register opposite that of the bus input. operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 50 UNIT pF SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178B – MARCH 1984 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION VCC S1 Test Point From Output Under Test PARAMETER ten RL tdis CL (see Note A) S2 tPZH RL 1 kΩ tPZL tPHZ 1 kΩ CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF tPLZ 50 pF or 150 pF –– tpd or tt LOAD CIRCUIT 3V High-Level Pulse 1.3 V 3V Reference Input 1.3 V 0V 1.3 V tsu 0V tw Data Input 1.3 V 0.3 V 3V Low-Level Pulse 1.3 V 1.3 V Output Control (Low-Level Enabling) 3V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% tPHL 90% 90% tr Out-ofPhase Output tPHL 90% VOH 1.3 V 10% V OL tf 1.3 V 10% tf 3V 1.3 V 0.3 V 0 V tf 3V 1.3 V 1.3 V 0V tPZL Output Waveform 1 (See Note B) tPLZ ≈ VCC 1.3 V 10% VOL tPZH tPLH 1.3 V 10% 2.7 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 2.7 V tr 0V Input th 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES Output Waveform 2 (See Note B) 1.3 V 90% VOH ≈0V tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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