SN74LVC646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS302A – JANUARY 1993 – REVISED JULY 1995 D D D D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages DB, DW, OR PW PACKAGE (TOP VIEW) CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8 This octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation. The SN74LVC646 consists of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVC646. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in one register and B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVC646 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS DATA I/Os OPERATION OR FUNCTION OE DIR CLKAB CLKBA SAB SBA A1 – A8 B1 – B8 X X ↑ X X X Input Unspecified† X X X ↑ X X Unspecified† Input Store A, B unspecified† Store B, A unspecified† H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus † The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVC646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS 21 OE L 3 DIR L 1 23 CLKAB CLKBA X X 2 SAB X BUS B BUS A BUS A BUS B SCAS302A – JANUARY 1993 – REVISED JULY 1995 22 SBA L 21 OE L 3 DIR H 3 DIR X X X 1 23 CLKAB CLKBA X ↑ X ↑ ↑ ↑ 2 SAB X X X 22 SBA X X X 21 OE L L 22 SBA X BUS B 3 DIR L H STORAGE FROM A, B, OR A AND B 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions 2 2 SAB L BUS A BUS A 21 OE X X H 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 22 SBA H X SN74LVC646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS302A – JANUARY 1993 – REVISED JULY 1995 logic symbol† 21 OE DIR CLKBA SBA CLKAB SAB A1 3 23 22 1 2 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 ≥1 4 1 5 6D 7 1 A2 A3 A4 A5 A6 A7 A8 4D 5 20 B1 1 ≥1 2 7 5 19 6 18 7 17 8 16 9 15 10 14 11 13 B2 B3 B4 B5 B6 B7 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVC646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS302A – JANUARY 1993 – REVISED JULY 1995 logic diagram (positive logic) OE DIR CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 1D C1 To Seven Other Channels 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B1 SN74LVC646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS302A – JANUARY 1993 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage VI Input voltage VO Output voltage MIN MAX 2.7 3.6 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2 Control inputs 0 5.5 Data inputs 0 VCC VCC IOH High level output current High-level IOL Low level output current Low-level VCC = 2.7 V VCC = 3 V ∆t /∆v Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 0.8 0 VCC = 2.7 V VCC = 3 V UNIT – 12 12 – 24 24 V V V mA mA 0 10 ns / V – 40 85 °C 5 SN74LVC646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS302A – JANUARY 1993 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC† MIN to MAX TEST CONDITIONS IOH = – 100 µA IOH = – 24 mA IOL = 100 µA TYP‡ MAX VCC – 0.2 2.2 2.7 V IOH = – 12 mA VOH MIN 3V 2.4 3V 2 UNIT V MIN to MAX 0.2 VOL IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 II IOZ§ VI = 5.5 V or GND VO = VCC or GND 3.6 V ±5 µA 3.6 V ± 10 µA ICC nICC VI = VCC or GND, One input at VCC – 0.6 V, 3.6 V 20 µA 3 V to 3.6 V 500 µA IO = 0 Other inputs at VCC or GND V Ci Control inputs VI = VCC or GND 3.3 V 4.6 pF Cio A or B ports VO = VCC or GND 3.3 V 7.2 pF † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are measured at VCC = 3.3 V, TA = 25°C. § For I/O ports, the parameter IOZ includes the input leakage current. timing characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN UNIT MAX tw tsu Pulse duration 5 5 ns Setup time, data before CLK↑ 5 5 ns th Hold time, data after CLK↑ 1 1 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER 6 VCC = 2.7 V TO (OUTPUT) A or B B or A 1.5 8 9.2 fmax tpd VCC = 3.3 V ± 0.3 V FROM (INPUT) MIN MAX 100 MIN UNIT MAX 80 MHz ns CLK A or B 1.5 9 11 SBA or SAB A or B 1.5 9 11 ten tdis OE A or B 1.5 8.5 9.5 ns OE A or B 1.5 8.5 9.5 ns ten tdis DIR A or B 1.5 9 10 ns DIR A or B 1.5 9 10 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS302A – JANUARY 1993 – REVISED JULY 1995 operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance per transceiver pF CL = 50 pF, Outputs disabled TYP 38 f = 10 MHz 4.2 UNIT pF PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 0V tPLH 1.5 V tPLH VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 6 V (see Note B) VOH VOL tPHL 1.5 V tPZL tPHL 1.5 V Output 2.7 V Output Control 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74LVC646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS302A – JANUARY 1993 – REVISED JULY 1995 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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