TI CD74HCT646M96

CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
D
D
D
D
D
D
D
D
D
D
CD54HC646 . . . F PACKAGE
CD74HCT646 . . . M PACKAGE
(TOP VIEW)
2-V to 6-V VCC Operation (CD54HC646)
4.5-V to 5.5-V VCC Operation (CD74HCT646)
Wide Operating Temperature Range of
–55°C to 125°C
Balanced Propagation Delays and
Transition Times
Standard Outputs Drive Up To 15 LS-TTL
Loads
Significant Power Reduction Compared to
LS-TTL Logic ICs
Inputs Are TTL-Voltage Compatible
(CD74HCT646)
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
description/ordering information
The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops,
and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal
registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate
clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can
be performed with these devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be
stored in one register and /or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one
of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
–55°C
55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
SOIC – M
Tape and reel
CD74HCT646M96
HCT646M
CDIP – F
Tube
CD54HC646F3A
CD54HC646F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
FUNCTION TABLE
INPUTS
DATA I/O
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1– A8
B1– B8
X
X
↑
X
X
X
Input
Unspecified†
OPERATION OR FUNCTION
X
X
X
↑
X
X
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
† The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
21
OE
L
3
DIR
L
1
23
CLKAB CLKBA
X
X
2
SAB
X
BUS B
BUS A
BUS A
BUS B
SCHS278B – APRIL 2003 – REVISED APRIL 2003
22
SBA
L
21
OE
L
3
DIR
H
3
DIR
X
X
X
1
23
CLKAB CLKBA
X
↑
X
↑
↑
↑
2
SAB
X
X
X
2
SAB
L
22
SBA
X
BUS B
BUS A
BUS A
21
OE
X
X
H
23
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
1
CLKAB
X
22
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
21
OE
L
L
3
DIR
L
H
1
CLKAB
X
H or L
23
CLKBA
H or L
X
2
SAB
X
H
22
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
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• DALLAS, TEXAS 75265
3
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
logic diagram (positive logic)
21
OE
3
DIR
2
To Channels
2–8
SAB
22
SBA
1
CLKAB
CLKBA
23
CLK
D
VCC
P
4
A1
N
VCC
GND
P
20
B1
N
GND
Q
C
C
D
VCC
C
P
P
N
N
24
12
C
P N
C
C
P N
C
C
GND
F/F
4
One of Eight Identical Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2) M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions for CD54HC646 (see Note 3)
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
Low-level input voltage
VI
VO
Input voltage
tt
MIN
MAX
2
6
V
3.15
4.2
0.5
1.35
V
1.8
0
0
VCC = 2 V
VCC = 4.5 V
Input transition (rise and fall) time
V
1.5
VCC = 4.5 V
VCC = 6 V
Output voltage
UNIT
VCC
VCC
V
V
1000
500
ns
VCC = 6 V
400
TA
Operating free-air temperature
–55
125
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions for CD74HCT646 (see Note 3)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
VO
tt
Output voltage
High-level input voltage
MIN
MAX
4.5
5.5
2
Input voltage
Input transition (rise and fall) time
UNIT
V
V
0.8
V
VCC
VCC
V
500
ns
V
TA
Operating free-air temperature
–55
125
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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• DALLAS, TEXAS 75265
5
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
electrical characteristics for CD54HC646 over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –20 µA
VOH
VI = VIH or VIL
IOH = –6 mA
IOH = –7.8 mA
VOL
VI = VCC or 0
VO = VCC or 0
ICC
Ci
VI = VCC or 0,
TA = –55°C
TO 125°C
TA = –40°C
TO 85°C
MIN
MIN
MIN
MAX
MAX
2V
1.9
1.9
1.9
4.5 V
4.4
4.4
4.4
6V
5.9
5.9
5.9
4.5 V
3.98
3.7
3.84
6V
5.48
5.2
UNIT
MAX
V
5.34
2V
0.1
0.1
0.1
IOL = 20 µA
4.5 V
0.1
0.1
0.1
6V
0.1
0.1
0.1
IOL = 6 mA
IOL = 7.8 mA
4.5 V
0.26
0.4
0.33
6V
0.26
0.4
0.33
6V
±0.1
±1
±1
µA
6V
±0.5
±10
±5
µA
VI = VIH or VIL
II
IOZ
TA = 25°C
IO = 0
6V
Co
V
8
160
80
µA
10
10
10
pF
20
20
20
pF
electrical characteristics for CD74HCT646 over recommended operating free-air temperature
range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
VOH
VI = VIH or VIL
IOH = –20 µA
IOH = –6 mA
45V
4.5
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 6 mA
45V
4.5
II
IOZ
VI = VCC to GND
VO = VCC or 0
5.5 V
5.5 V
ICC
VI = VCC or 0,
IO = 0
One input at VCC – 2.1 V,
Other inputs at 0 or VCC
5.5 V
∆ICC†
TYP
MIN
MIN
MAX
4.4
4.4
4.4
3.7
3.84
4.5 V to 5.5 V
100
Co
† Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
POST OFFICE BOX 655303
TA = –40°C
TO 85°C
3.98
Ci
6
MAX
TA = –55°C
TO 125°C
• DALLAS, TEXAS 75265
UNIT
MAX
V
0.1
0.1
0.1
0.26
0.4
0.33
±0.1
±1
±1
µA
±0.5
±10
±5
µA
8
160
80
µA
360
490
450
µA
10
10
10
pF
20
20
20
pF
V
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
HCT INPUT LOADING TABLE
INPUT
UNIT LOAD†
OE
1.3
DIR
0.75
CLKAB or CLKBA
0.6
SAB or SBA
0.45
A or B
0.3
† Unit Load is ∆ICC limit specified in
electrical characteristics table (e.g.,
360 µA max at 25°C).
timing requirements for CD54HC646 over recommended operating free-air temperature range
(unless otherwise noted) (see Figure 2)
VCC
fclock
Clock frequency
TA = 25°C
TA = –55°C
TO 125°C
TA = –40°C
TO 85°C
MIN
MIN
MIN
MAX
tsu
th
Pulse duration, CLKBA or CLKAB high or low
Setup time, A before CLKAB↑
↑ or B before CLKBA↑
↑
Hold time, A after CLKAB↑
↑ or B after CLKBA↑
↑
UNIT
MAX
2V
6
4
5
4.5 V
30
20
25
6V
tw
MAX
35
23
MHz
29
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
60
90
75
4.5 V
12
18
15
6V
10
15
13
2V
35
55
45
4.5 V
7
11
9
6V
6
9
8
ns
ns
ns
timing requirements for CD74HCT646 over recommended operating free-air temperature range,
VCC = 4.5 V (unless otherwise noted) (see Figure 3)
TA = 25°C
TA = –55°C
TO 125°C
TA = –40°C
TO 85°C
MIN
MIN
MIN
MAX
25
MAX
fclock
tw
Clock frequency
Pulse duration, CLKBA or CLKAB high or low
25
38
31
ns
tsu
Setup time, A before CLKAB↑ or B before CLKBA↑
12
18
15
ns
th
Hold time, A after CLKAB↑ or B after CLKBA↑
5
5
5
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
UNIT
MAX
20
MHz
7
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
switching characteristics for CD54HC646 over recommended operating free-air temperature range
(unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
CL = 50 pF
fmax
CLKBA or
CLKAB
A or B
A or B
B or A
A or B
OE
A or B
tt
OE
A or B
Any
MIN
MIN
MAX
2V
6
4
5
4.5 V
30
20
25
6V
35
23
29
220
330
275
44
66
55
6V
37
56
47
2V
135
205
170
4.5 V
27
41
34
6V
23
35
29
2V
170
255
215
4.5 V
34
51
43
6V
29
43
37
2V
175
265
220
4.5 V
35
53
44
6V
30
45
37
2V
175
265
220
4.5 V
35
53
44
6V
30
45
37
CL = 50 pF
CL = 50 pF
CL = 50 pF
60
5V
18
5V
5V
14
5V
ns
14
CL = 15 pF
5V
2V
60
90
75
CL = 50 pF
4.5 V
12
18
15
POST OFFICE BOX 655303
ns
12
ns
14
6V
10
15
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
8
MHz
2V
CL = 50 pF
UNIT
MAX
4.5 V
CL = 15 pF
tdis
di
MAX
CL = 50 pF
CL = 15 pF
ten
TYP
TA = –40°C
TO 85°C
5V
CL = 15 pF
SBA or
SAB†
MIN
TA = –55°C
TO 125°C
CL = 15 pF
CL = 15 pF
tpd
d
TA = 25°C
VCC
• DALLAS, TEXAS 75265
13
ns
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
switching characteristics for CD74HCT646 over recommended operating free-air temperature
range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
d
CLKBA or
CLKAB
A or B
A or B
B or A
SBA or
SAB†
A or B
ten
OE
A or B
tdis
di
OE
A or B
LOAD
CAPACITANCE
VCC
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
TA = 25°C
MIN
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
TYP
MAX
25
TA = –55°C
TO 125°C
TA = –40°C
TO 85°C
MIN
MIN
MAX
17
UNIT
MAX
20
MHz
45
44
66
55
37
56
46
46
69
58
45
68
56
35
53
44
18
15
ns
19
19
14
tt
CL = 50 pF
4.5 V
12
18
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
15
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TYP
Power dissipation capacitance
52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
pF
9
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION – CD54HC646
VCC
Test
Point
From Output
Under Test
PARAMETER
S1
ten
RL = 1 kΩ
tdis
CL
(see Note A)
S2
S1
S2
tPZH
Open
Closed
tPZL
Closed
Open
tPHZ
Open
Closed
tPLZ
Closed
Open
Open
Open
tpd or tt
tw
LOAD CIRCUIT
VCC
Input
50% VCC
50% VCC
0V
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
VCC
Reference
Input
VCC
50% VCC
50% VCC
0V
0V
tsu
trec
Data
50%
Input 10%
VCC
50% VCC
CLK
90%
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC
50% VCC
tPLH
tPHL
50%
10%
90%
90%
tr
tPHL
Out-of-Phase
Output
90%
tf
tf
VCC
VOH
50% VCC
10%
VOL
tf
50%
10%
90%
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
Output
Waveform 1
(see Note B)
50% VCC
Output
Waveform 2
(see Note B)
10%
VOL
tPHZ
tPZH
VOH
VOL
VCC
Output
Control
tPLH
50% VCC
10%
VCC
50% VCC
10% 0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
0V
In-Phase
Output
90%
tr
0V
Input
th
50% VCC
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION – CD74HCT646
VCC
Test
Point
From Output
Under Test
PARAMETER
S1
ten
1 kΩ
tdis
CL
(see Note A)
S2
S1
S2
tPZH
Open
Closed
tPZL
Closed
Open
tPHZ
Open
Closed
tPLZ
Closed
Open
Open
Open
tpd or tt
tw
LOAD CIRCUIT
3V
1.3 V
Input
1.3 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
3V
Reference
Input
3V
1.3 V
1.3 V
0V
0V
tsu
trec
Data
1.3 V
Input 0.3
V
3V
1.3 V
CLK
th
2.7 V
3V
2.7 V
1.3 V
0.3 V 0 V
tf
tr
0V
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3V
Input
1.3 V
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
90%
tPHL
90%
1.3 V
1.3 V
0V
tPHL
90%
tr
Out-of-Phase
Output
3V
Output
Control
VOH
1.3 V
10%
tf
VOL
1.3 V
10%
tf
1.3 V
10%
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
1.3 V
Output
Waveform 2
(see Note B)
10%
VOL
tPHZ
tPZH
VOH
VOL
≈VCC
Output
Waveform 1
(see Note B)
tPLH
90%
tPLZ
tPZL
1.3 V
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
5962-8688501JA
ACTIVE
CDIP
J
24
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8688501JA
CD54HC646F3A
CD54HC646F3A
ACTIVE
CDIP
J
24
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8688501JA
CD54HC646F3A
CD74HCT646M96
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT646M
CD74HCT646M96E4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT646M
CD74HCT646M96G4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT646M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC646 :
• Catalog: CD74HC646
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CD74HCT646M96
Package Package Pins
Type Drawing
SOIC
DW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.7
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HCT646M96
SOIC
DW
24
2000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
B
13
24
C
1
12
0.065 (1,65)
0.045 (1,14)
Lens Protrusion (Lens Optional)
0.010 (0.25) MAX
0.175 (4,45)
0.140 (3,56)
0.090 (2,29)
0.060 (1,53)
A
Seating Plane
0.018 (0,46) MIN
24
PINS **
DIM
”A”
”B”
”C”
NARR
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
28
WIDE
NARR
40
32
WIDE
NARR
WIDE
NARR
WIDE
MAX
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
MIN
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
MAX
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
MIN
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
MAX
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
MIN
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
4040084/C 10/97
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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