bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 SYNCHRONOUS SWITCHMODE, LI-ION AND LI-POL CHARGE MANAGEMENT IC WITH INTEGRATED POWERFETS (bqSWITCHERE) FEATURES D Ideal For High-Efficient Charger Designs For D D D D D D D D D D D D D D Single-, Two- or Three-Cell Li-Ion and Li-Pol Battery Packs Integrated Synchronous Fixed-Frequency PWM Controller Operating at 1.1 MHz with 0 to 100% Duty Cycle Integrated PowerFETs For Up To 2-A Charge Rate High-Accuracy Voltage and Current Regulation Available In Both Stand-Alone (Built-In Charge Management and Control) and System-Controlled (Under System Command) Versions Status Outputs For LED or Host Processor Interface Indicates Charge-In-Progress, Charge Completion, Fault, and AC-Adapter Present Conditions 20-V Maximum Voltage Rating on IN and OUT Pins High-Side Current Sensing Optional Battery Temperature Monitoring Automatic Sleep Mode for Low Power Consumption System-Controlled Version Can Be Used In NiMH and NiCd Applications Uses Ceramic Capacitors Reverse Leakage Protection Prevents Battery Drainage Thermal Shutdown and Protection Built-In Battery Detection DESCRIPTION The bqSWITCHER™ series are highly integrated Li-ion and Li-polymer switch-mode charge management devices targeted at a wide range of portable applications. The bqSWITCHER™ series offers integrated synchronous PWM controller and power FETs, high-accuracy current and voltage regulation, charge preconditioning, charge status, and charge termination, in a small, thermally enhanced QFN package. The system-controlled version provides additional inputs for full charge management under system control. The bqSWITCHER charges the battery in three phases: conditioning, constant current, and constant voltage. Charge is terminated based on user-selectable minimum current level. A programmable charge timer provides a safety backup for charge termination. The bqSWITCHER automatically re-starts the charge cycle if the battery voltage falls below an internal threshold. The bqSWITCHER automatically enters sleep mode when VCC supply is removed. APPLICATIONS D Handheld Products D Portable Media Players D Industrial and Medical Equipment D Portable Equipment Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. bqSWITCHER™ and PowerPAD™ are trademarks of Texas Instruments. Copyright © 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PowerPAD should act as the star ground between PGND and VSS. See Layout section for more details. TYPICAL SINGLE CELL Li-ION STAND-ALONE CHARGER LOUT 10 µH bq24100RHL VIN 3 IN OUT 1 4 IN OUT 20 6 VCC PGND 17 2 STAT1 PGND 18 19 STAT2 SNS 15 PG BAT 14 10 µF 5 7 CTTC COUT 10 µF PACK+ 16 CE PACK− R(ISET1) 0.1 µF R(ISET2) ISET2 9 10 VSS + VTSB ISET1 8 TTC R(SNS) RT1 TS 12 TEMP PWR PAD VTSB 11 RT2 VIN VIN D1 Adapter Present BATTERY PACK VIN D3 Charge D2 Done UDG−04033 ORDERING INFORMATION TJ CHARGE REGULATION VOLTAGE (V) INTENDED APPLICATION PART NUMBER(1)(2) 4.2 Stand-alone bq24100RHLR CIA −40°C 40 C to 125°C 125 C 1 or 2 cells selectable (CELLS pin 4.2 or 8.4 V) Stand-alone bq24103RHLR CID Externally programmable (2.1 to 15.5 V) Stand-alone bq24105RHLR CIF (1) (2) 2 MARKINGS 4.2 (Blinking status pins) Stand-alone bq24108RHLR CIU 1 or 2 cells selectable (CELLS pin 4.2 or 8.4 V) System-controlled bq24113RHLR CIJ Externally programmable (2.1 to 15.5 V) System-controlled bq24115RHLR CIL The RHL package is available taped and reeled only. Quantities are 3,000 devices per reel. This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for use in specified lead-free soldering processes. www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 PACKAGE DISSIPATION RATINGS (1) PACKAGE θJA TA < 40°C POWER RATING DERATING FACTOR ABOVE TA = 40°C RHL(1) 46.87 °C/W 1.81 W 0.021 W/°C This data is based on using the JEDEC High-K board, and the exposed die pad is connected to a copper pad on the board. This is connected to the ground plane by a 2x3 via matrix. ABSOLUTE MAXIMUM RATINGS(1) UNIT Supply voltage range, (with respect to VSS) Input voltage range, (with respect to VSS and PGND) IN, VCC 20 STAT1, STAT2, PG, CE, CELLS, SNS, BAT −0.3 to 20 OUT −0.7 to 20 CMODE, TS, TTC 7 VTSB 3.6 ISET1, ISET2 3.3 Voltage difference between SNS and BAT inputs (VSNS − VBAT) ±1 Output sink STAT1, STAT2, PG Output current (average) OUT 10 mA 2.2 A Operating free−air temperature range, TA −40 to 85 Junction temperature range, TJ −40 to 125 Storage temperature, Tstg −65 to 150 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) V °C 300 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN † ‡ NOM MAX UNIT Supply voltage, VCC and IN (Tie together) 4.35† 16.0‡ V Operating junction temperature range, TJ −40 125 °C The IC continues to operate below Vmin, to 3.5 V, but the specifications are not tested nor guaranteed. The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the IN or OUT pins. A tight layout minimizes switching noise. www.ti.com 3 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT INPUT CURRENTS IVCC(VCC) I(SLP) VCC supply current Battery discharge sleep current, (SNS, BAT, OUT, FB pins) VCC > VCC(min), PWM switching VCC > VCC(min), PWM NOT switching VCC > VCC(min), CE = HIGH 10 5 315 0°C ≤ TJ ≤ 65°C, VI(BAT) = 4.2 V VCC < V(SLP) or VCC > V(SLP) but not in charge 3.5 0°C ≤ TJ ≤ 65°C, VI(BAT) = 8.4 V VCC < V(SLP) or VCC > V(SLP) but not in charge 5.5 0°C ≤ TJ ≤ 65°C, VI(BAT) = 12.6 V VCC < V(SLP) or VCC > V(SLP) but not in charge 7.7 mA µA µA VOLTAGE REGULATION VOREG VIBAT Output voltage, voltage bq24103/13 CELLS = Low, in voltage regulation 4.2 CELLS = High, in voltage regulation 8.4 Output voltage, bq24100/08 Operating in voltage regulation 4.2 Feedback regulation REF for bq24105/15 only (W/FB) IIBAT = 25 nA typical into pin 2.1 Voltage regulation accuracy TA = 25°C V V −0.5% 0.5% −1% 1% 150 2000 −10% 10% CURRENT REGULATION − FAST CHARGE IOCHARGE Output current range of converter VLOWV ≤ VI(BAT) < VOREG, V(VCC) − VI(BAT) > V(DO−MAX) mA 100 mV ≤ VIREG ≤ 200 mV, 1V 1000, RSET1 Programmed Where 5 kΩ ≤ RSET1 ≤ 10kΩ, Select RSET1 to program VIREG, VIREG(measured) = IOCHARGE + RSNS V VIREG Voltage regulated across RSNS− Accuracy IREG + (−10% to +10% excludes errors due to RSET1 and RSNS tolerances) V(ISET1) Output current set voltage V(LOWV) ≤ VI(BAT) ≤ VO(REG) V(VCC) ≥ VI(BAT) × V(DO−MAX), 1 K(ISET1) Output current set factor VLOWV ≤ VI(BAT) < VO(REG) V(VCC) ≥ VI(BAT) + V(DO−MAX), 1000 V V/A PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION VLOWV Precharge to fast-charge transition voltage threshold, BAT, bq24100/03/05/08 ICs only t Deglitch time for precharge to fast charge transition IOPRECHG V(ISET2) K(ISET2) Precharge current set factor 4 68 71.4 75 %VO(REG) Rising voltage; tRISE, tFALL = 100 ns, 2-mV overdrive 20 30 40 ms Precharge range VI(BAT) < VLOWV, t < tPRECHG 15 200 mA Precharge set voltage, ISET2 VI(BAT) < VLOWV, t < tPRECHG www.ti.com 100 mV 1000 V/A bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 100 mV ≤ VIREG-PRE ≤ 100 mV, V VIREG-PRE Voltage regulated across RSNS− Accuracy IREG*PRE + 0.1V RSET2 1000, (PGM) Where 1.2 kΩ ≤ RSET2 ≤ 10kΩ, Select RSET1 to program VIREG−PRE, VIREG−PRE (Measured) = IOPRE−CHG × RSNS −20% 20% 15 200 (−20% to +20% excludes errors due to RSET1 and RSNS tolerances) CHARGE TERMINATION (CURRENT TAPER) DETECTION ITERM Charge current termination detection range VI(BAT) > VRCH VTERM Charge termination detection set voltage, ISET2 VI(BAT) > VRCH K(ISET2) Termination current set factor tdg-TERM Charger termination accuracy VI(BAT) > VRCH Deglitch time for charge termination Both rising and falling, tRISE, tFALL = 100 ns 100 mV 1000 V/A −20% 2-mV overdrive mA 20% 20 30 40 ms TEMPERATURE COMPARATOR AND VTSB BIAS REGULATOR VLTF Cold temperature threshold, TS 72.8 73.5 74.2 VHTF Hot temperature threshold, TS 33.7 34.4 35.1 VTCO Cutoff temperature threshold, TS 28.7 29.3 29.9 0.5 1.0 1.5 20 30 40 LTF hysteresis tdg-TS Deglitch time for temperature fault, TS Both rising and falling, tRISE, tFALL = 100 ns 2-mV overdrive VO(VTSB) TS bias output voltage VCC > VIN(min), I(VTSB) = 10 mA 0.1 µF ≤ CO(VTSB) ≤ 1 µF, VO(VTSB) TS bias voltage regulation accuracy VCC > IN(min), I(VTSB) = 10 mA 0.1 µF ≤ CO(VTSB) ≤ 1 µF, 3.15 −10% % VO( O(VTSB) S ) ms V 10% BATTERY RECHARGE THRESHOLD VRCH Recharge threshold voltage Below VOREG 75 100 125 mV/cell tdg-RCH Deglitch time VI(BAT) < decreasing below threshold, tFALL = 100 ns 10-mV overdrive 20 30 40 ms STAT1, STAT2, AND PG OUTPUTS VOL(STATx) Low-level output saturation voltage, STATx IO = 5 mA 0.5 VOL(PG) Low-level output saturation voltage, PG IO = 10 mA 0.1 V CE CMODE, CELLS INPUTS VIL Low-level input voltage IIL = 5 µA 0.0 0.4 VIH High-level input voltage IIH = 20 µA 1.3 VCC www.ti.com V 5 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX 1440 1800 UNIT TTC INPUT tPRECHG Precharge timer tCHARGE Programmable charge timer range t(CHG) = C(TTC) × K(TTC) Charge timer accuracy 0.01 µF ≤ C(TTC) ≤ 0.18 µF KTTC Timer multiplier CTTC Charge time capacitor range VTTC_EN TTC enable threshold voltage 2160 s 25 572 minutes −10% 10% 2.6 0.01 V(TTC) rising min/nF 0.22 200 µF mV SLEEP COMPARATOR VCC ≤ 2.3 V ≤ VI(OUT) ≤ VOREG, for 1 or 2 cells VSLP−ENT Sleep mode entry threshold Sleep-mode VI(OUT) = 12.6 V, RIN = 1 kΩ (1) bq24105/15 VSLP−EXIT Sleep-mode exit hysteresis, 2.3 V ≤ VI(OUT) ≤ VOREG VIBAT +5 mV +75mV VCC ≤ VCC ≤ VIBAT VIBAT −4 mV +73mV 40 160 VCC decreasing below threshold, tFALL = 100 ns, 10-mV overdrive, PMOS turns off tdg-SLP Deglitch time for sleep mode VCC decreasing below threshold, tFALL = 100 ns, 10-mV overdrive, STATx pins turn off VCC ≤ VIBAT 5 V mV µs 20 30 40 3.50 ms UVLO VUVLO−ON IC active threshold voltage VCC rising 3.15 3.30 IC active hysteresis VCC falling 120 150 Internal P P-channel channel MOSFET on-resistance 7 V ≤ VCC ≤ VCC(max) 400 4.5 V ≤ VCC ≤ 7 V 500 7 V ≤ VCC ≤ VCC(max) 130 V mV PWM Internal N N-channel channel MOSFET on-resistance fOSC 4.5 V ≤ VCC ≤ 7 V 150 Oscillator frequency 1.1 Frequency accuracy mΩ −9% MHz 9% DMAX Maximum duty cycle DMIN Minimum duty cycle 100% tTOD Switching delay time (turn on) 20 ns tsyncmin Minimum synchronous FET on time 60 ns 0% Synchronous FET minimum current-off threshold (2) 6 50 www.ti.com 400 mA bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BATTERY DETECTION IDETECT Battery detection current during time-out fault VI(BAT) < VOREG − VRCH IDISCHRG1 Discharge current tDISCHRG1 Discharge time IWAKE tWAKE 2 mA VSHORT < VI(BAT) < VOREG − VRCH 400 µA VSHORT < VI(BAT) < VOREG − VRCH 1 s Wake current VSHORT < VI(BAT) < VOREG − VRCH 2 mA Wake time VSHORT < VI(BAT) < VOREG − VRCH 0.5 s IDISCHRG2 Termination discharge current Begins after termination detected, VI(BAT) ≤ VOREG 400 µA tDISCHRG2 Termination time 262 ms OUTPUT CAPACITOR COUT Required output ceramic capacitor range from SNS to PGND, between inductor and RSNS CSNS Required SNS capacitor (ceramic) at SNS pin 4.7 10 47 0.1 µF µF PROTECTION Threshold over VOREG to turn-off P-channel MOSFET, STAT1, and STAT2 during charge or termination states VOVP OVP threshold voltage ILIMIT Cycle-by-cycle current limit VSHORT Short-circuit voltage threshold, BAT VI(BAT) falling ISHORT Short-circuit current VI(BAT) ≤ VSHORT TSHTDWN Thermal trip 110 117 121 %VO(REG) 2.6 3.6 4.5 A 1.95 2.00 2.05 V/cell 35 165 Thermal hysteresis mA °C For bq24105 and bq24115 only. RIN is connected between IN and PGND pins and needed to ensure sleep entry. N-channel always turns on for ~60 ns and then turns off if current is too low. 19 20 1 2 18 3 17 4 16 5 15 6 14 7 8 13 12 11 10 9 STAT1 IN IN PG VCC TTC ISET1 ISET2 VSS STAS2 PGND PGND CE SNS BAT NC TS OUT RHL PACKAGE (BOTTOM VIEW) OUT (2) 10 VTSB (1) 65 www.ti.com 7 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 TERMINAL FUNCTIONS TERMINAL Description bq24103 bq24105 bq24113 bq24115 BAT 14 14 14 14 14 I Battery voltage sense input. Bypass it with a capacitor to PGND if there are long inductive leads to battery. CE 16 16 16 16 16 I Charger enable input. This active low input, if set high, suspends charge and places the device in the low-power sleep mode. Do not pull up this input to VTSB. I Available on parts with fixed output voltage. Ground or float for single cell operation (4.2 V). For two cells operation (8.4 V) pull up this pin with a resistor to VCC. 7 I Charge mode selection: low for precharge as set by ISET2 pin and high (pull up to VTSB or <7 V) for fast charge as set by ISET1. 13 I Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider powered from the battery terminals to this node to adjust the output battery voltage regulation. Charger input voltage. CELLS 13 13 CMODE 7 FB IN 13 3, 4 3, 4 3, 4 3, 4 3, 4 I ISET1 8 8 8 8 8 I/O Charger current set point 1 (fast charge). Use a resistor to ground to set this value. ISET2 9 9 9 9 9 I/O Charge current set point 2 (precharge and termination), set by a resistor connected to ground. A low-level CMODE signal selects the ISET2 charge rate, but if the battery voltage reaches the regulation set point, bqSWITCHER changes to voltage regulation regardless of CMODE input. N/C 13 19 19 1 1 1 1 1 20 20 20 20 20 − O O 5 5 5 5 5 O 17,18 17,18 17,18 17,18 17, 18 SNS 15 15 15 15 15 I Charge current-sense input. Battery current is sensed via the voltage drop developed on this pin by an external sense resistor in series with the battery pack. A 0.1-µF capacitor to PGND is required. STAT1 2 2 2 2 2 O Charge status 1 (open-drain output). When the transistor turns on indicates charge in process. When it is off and with the condition of STAT2 indicates various charger conditions (See Table 1) STAT2 19 19 19 O Charge status 2 (open-drain output). When the transistor turns on indicates charge is done. When it is off and with the condition of STAT1 indicates various charger conditions (See Table 1) TS 12 12 12 I Temperature sense input. This input monitors its voltage against an internal threshold to determine if charging is allowed. Use an NTC thermistor and a voltage divider powered from VTSB to develop this voltage. (See Figure 7) TTC 7 7 7 I Timer and termination control. Connect a capacitor from this node to GND to set the bqSWITCHER timer. When this input is low the timer and termination detection are disabled. I Analog device input OUT PG PGND 12 12 VCC 6 6 6 6 6 VSS 10 10 10 10 10 VTSB 11 11 11 11 11 Exposed Thermal Pad 8 I/O bq24100 bq24108 NAME Pad Pad Pad Pad Pad No connection. This pin must be left floating in the application. Charge current output inductor connection. connection Power good status output (open drain). The transistor turns on when a valid VCC is detected. It is turned off in the sleep mode. PG can be used to drive a LED or communicate with a host processor. Power ground input Analog ground input O TS internal bias regulator voltage. Connect capacitor (with a value between a 0.1-µF and 1-µF) between this output and VSS. − There is an internal electrical connection between the exposed thermal pad and VSS. The exposed thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. The power pad can be used as a star ground connection between VSS and PGND. A common ground plane may be used. VSS pin must be connected to ground at all times. www.ti.com www.ti.com VCC Term & Timer Disable VCC VTSB VCC VSS TTC STAT2 STAT1 CE PG VTSB VCC IN IN 0.5V 1V CE CHARGE 50 mV BAT WAKE TERM OVP Charge (STATE MACHINE) TIMER FF CHAIN PRE−CHG TIMEOUT TIMER CLK *Patent Pending #36889 TG CONTROL LOGIC DSABL_TERM PRE−CHARGE 0.75V bq2410x VCC DISCHARGE 0.25V SLEEP V(3.6A) Icntrl Sense FET VCC−6V Poff VCC PG 2.1V VCC−6V bqSWITCHER VCC VTSB Voltage Reference Vuvlo UVLO/POR POR CHARGE SLEEP + − VIN Protection PMOS FET is OFF when not charging or in SLEEP to prevent discharge of battery when IN < BAT SLEEP SYNCH PkILim VSHORT BAT_PRS_ disch LowV Term_Det Vrch UVLO/ POR SUSPEND TIMEOUT MOD SYNCH OVP FAST CHG TIMEOUT RESET PkILim 6V VCC−6V VCC BG VSHORT LowV 30ms Dgltch BAT_PRS_dischg Vovp Q R Q S I 2.1V BAT VCC + − SNS+ 1V TS SPIN SUSPEND FASTCHG Disable BAT 20uA VCC Ibat Reg + − + − 2.1V + − TCO HTF LTF 30ms dgltch PRE−CHG Disable 0.1V FASTCHG Disable TEMP SUSPEND 0.1V SNS + 1k − TERM SLEEP SUSPEND 1V Vbat Reg + − 20uA VCC VCC RAMP (Vpp=VCC/10) VCC RAMP OSC VCC/10 * COMPENSATION Discharge Charge Wake Vrch 30ms Dgltch Vreg BAT CLAMP Synch Gate Drive TG − + V(150 mA) Isynch PkILim or OVP TIMEOUT FAULT SUSPEND TERM UVLO/POR MOD OVP BG Sense FET BAT 1C 2C FB SPIN 1k VTSB Term_Det + − Co 10 m F 10 m H Lo Rsns TS ISET2 ISET1 VTSB RSET2 RSET1 FB CELLS (bq24103/13) FB (bq24105/15) N/C (bq24100) VTSB BAT SNS PGND PGND OUT OUT to FB FB SPIN ONLY Temp Pack− + Pack+ bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 FUNCTIONAL BLOCK DIAGRAM 9 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS EFFICIENCY vs OUTPUT CHARGE CURRENT 100 EFFICIENCY vs OUTPUT CHARGE CURRENT 100 90 90 80 80 70 70 η − Efficiency − % η − Efficiency − % VIN = 9 V VIN = 4.5 V 60 VIN = 16 V 50 40 30 20 50 40 30 20 V(BAT) = 4.2 V 1 Cell TA = 25°C 10 0 VIN = 16 V 60 0 0.5 1 1.5 V(BAT) = 8.4 V 2 Cell TA = 25°C 10 2 0 0 IO(CHARGE) = Output Charge Current − A 0.5 1 1.5 IO(CHARGE) = Output Charge Current − A Figure 1 Figure 2 bq24113RHL VIN 10 µF 3 IN OUT 1 4 IN OUT 20 6 VCC PGND 17 2 STAT1 PGND 18 5 PG SNS 15 7 CMODE BAT 14 16 CE ISET1 8 10 VSS ISET2 9 13 CELLS LOUT 10 µH R(SNS) COUT 10 µF PACK+ + R(ISET1) R(ISET2) TS 12 0.1 µF PACK− RT1 TEMP VTSB 11 RT2 To System BATTERY PACK UDG−04035 Figure 3. Typical Application Circuit (System-Controlled Version) 10 2 www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 APPLICATION INFORMATION POR Check for Battery Presence Battery Detect? No Indicate BATTERY ABSENT Yes Suspend Charge TS Pin in LTF to HTF Range? No Indicate CHARGE SUSPEND Yes VBAT <VLOWV Yes Regulate IPRECHG Reset and Start T30min timer Indicate Charge− In−Progress No Reset and Start FSTCHG timer TS pin in LTF to TCO range? Regulate Current or Voltage Yes Indicate Charge− In−Progress TS Pin in LTF to TCO Range? No Yes Indicate CHARGE SUSPEND Yes Indicate CHARGE SUSPEND No TS pin in LTF to HTF range? VBAT <VLOWV Suspend Charge No Suspend Charge No Yes T30min Expired? No No TS pin in LTF to HTF range? FSTCHG Timer Expired? No Yes Yes Yes VBAT <VLOWV Yes No − Fault Condition − Enable IDETECT No ITERM detection? Indicate Fault No Yes Battery Replaced? (Vbat < Vrch?) − Turn Off Charge − Enable IDISCHG for tDISCHG2 Indicate Charge− In−Progress *NOTE: If the TTC pin is pulled low, the safety timer and termination are disabled; the charger continues to regulate, and the STAT pins indicate charge in progress. If the TTC pin is pulled high (VTSB), only the safety timer is disabled (termination is normal). Yes Charge Complete VBAT < VRCH? No Indicate DONE * Battery Removed Yes Indicate BATTERY ABSENT Figure 4. Stand-Alone Version Operational Flow Chart www.ti.com 11 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 POR SLEEP MODE No Vcc > V I(BAT) Checked at All Times No Indicate SLEEP MODE Yes /CE=Low Yes CMODE=Low Regulate IO(PRECHG) Yes Indicate Charge− In−Progress No Yes /CE=High No Regulate Current or Voltage Indicate Charge− In−Progress Yes Yes CMODE=High or VIBAT in VREG Yes No No CMODE=Low No /CE=High Yes Turn Off Charge Indicate DONE Yes No /CE=Low Yes Figure 5. System-Controlled Operational Flow Chart 12 www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 FUNCTIONAL DESCRIPTION FOR STANDALONE VERSION (bq2410x) The bqSWITCHER™ supports a precision Li-ion or Li-polymer charging system for single-, two- or three-cell applications. See Figure 4 and Figure 5 for operational flow charts and Figure 6 for a typical charge profile. Precharge Phase Voltage Regulation and Charge Termination Phase Current Regulation Phase Regulation Voltage Regulation Current Charge Voltage VLOW VSHORT Charge Current Precharge and Termination ISHORT UDG−04037 Programmable Safety Timer Precharge Timer Figure 6. Typical Charging Profile Temperature Qualification The bqSWITCHER continuously monitors battery temperature by measuring the voltage between the TS pin and VSS pin. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this voltage. The bqSWITCHER compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the battery temperature must be within the V(LTF)-to-V(HTF) thresholds. If battery temperature is outside of this range, the bqSWITCHER suspends charge and waits until the battery temperature is within the V(LTF)-to-V(HTF) range. During the charge cycle (both precharge and fast charge), the battery temperature must be within the V(LTF)-to-V(TCO) thresholds. If battery temperature is outside of this range, the bqSWITCHER suspends charge and waits until the battery temperature is within the V(LTF)-to-V(HTF) range. The bqSWITCHER suspends charge by turning off the PWM and holding the timer value (i.e., timers are not reset during a suspend condition). Note that the bias for the external resistor divider is provided from the VTSB output. Applying a constant voltage between the V(LTF)-to-V(HTF) thresholds to the TS pin disables the temperature-sensing feature. www.ti.com 13 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 VCC Charge Suspend V(LTF) Charge Suspend Temperature Range to Initiate Charge V(HTF) V(TCO) Temperature Range During Charge Cycle Charge Suspend Charge Suspend VSS Figure 7. TS Pin Thresholds Battery Preconditioning (Precharge) On power up, if the battery voltage is below the VLOWV threshold, the bqSWITCHER applies a precharge current, IPRECHG, to the battery. This feature revives deeply discharged cells. The bqSWITCHER activates a safety timer, tPRECHG, during the conditioning phase. If the VLOWV threshold is not reached within the timer period, the bqSWITCHER turns off the charger and enunciates FAULT on the STATx pins. In the case of a FAULT condition, the bqSWITCHER reduces the current to IDETECT. IDETECT is used to detect a battery replacement condition. Fault condition is cleared by POR or battery replacement. The magnitude of the precharge current, IO(PRECHG), is determined by the value of programming resistor, R(ISET2), connected to the ISET2 pin. I O(PRECHG) + K (ISET2) ǒR(ISET2) V (ISET2) R (SNS) Ǔ (1) where D D D D RSNS is the external current-sense resistor V(ISET2) is the output voltage of the ISET2 pin K(ISET2) is the V/A gain factor V(ISET2) and K(ISET2) are specified in the Electrical Characteristics table. Battery Charge Current The battery charge current, IO(CHARGE), is established by setting the external sense resistor, R(SNS), and the resistor, R(ISET1), connected to the ISET1 pin. In order to set the current, first choose R(SNS) based on the regulation threshold VIREG across this resistor. Let VIREG = 100 mV to start and calculate the RSNS value needed. R (SNS) + 14 V IREG I OCHARGE (2) www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 If this value is not a standard sense resistor value, choose the next larger value. Using the selected standard value, solve for VIREG. V IREG + R (SNS) I OCHARGE (3) The value of R(ISET1) is then calculated based on the following equation: R SET1 + K ISET1 I OCHARGE V ISET1 + 1000 V V IREG R SNS (4) where D D D D D VIREG is the voltage regulated across RSNS IOCHARGE is the battery charge current RSNS is the external current sense resistor V(ISET1) is the output voltage of the ISET1 pin K(ISET1) is the V/A gain factor (see electrical characteristics table) The following provide a more detailed design procedure and example for this parameter: 1. Select the charge current. Example: • IOCHARGE = 2 A • IOPRECHG = 200 mA 2. Select the sense resistor value. Ensure that the power rating of the sense resistor is not exceeded Example: • Let VIREG = 100 mV (S/B from 100−200 mV) V IREG + 100 mV + 50 mW 2A • Solve for R SNS + • • Check availability for RSNS. Use value that is equal (next larger value if not available). Check for power dissipation P (SNS) + R (SNS) • I OCHARGE ǒI OCHARGEǓ 2 + 0.05 W 2 (2 A) + 0.2 W (5) Select 0805 or 1206 size rated at 0.25 W www.ti.com 15 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 3. Determine R(ISET1). • V(ISET1) = 1 V • K(ISET1) = 1000 V/A R (ISET1) + K (ISET1) R (SNS) V (ISET1) I OCHARGE + 1000 VńA 1 V + 10 kW 0.05 W 2 A (6) + 1000 VńA 0.1 V + 10 kW 0.05 W 0.2 A (7) 4. Determine R(ISET2) • V(ISET2) = 0.1 V • K(ISET2) = 1000V/A R (ISET2) + K (ISET2) R (SNS) V (ISET2) I OPRECHG RSENSE SNS BAT V(ISET1) = 1 V ISET1 R(ISET1) I(ISET1) V(ISET2) = 0.1 V ISET2 VSS R(ISET2) I(ISET2) UDG−04036 Figure 8. Program Charge Current with R(ISET1) and R(ISET2) Battery Voltage Regulation The voltage regulation feedback occurs through the BAT pin. This input is tied directly to the positive side of the battery pack. The bqSWITCHER monitors the battery-pack voltage between the BAT and VSS pins. The bqSWITCHER is offered in two fixed-voltage versions: 4.2 V and 8.4 V as selected by the CELLS input. A low or floating input on the CELLS selects single-cell mode (4.2 V) while a high-input selects two-cell mode. For device options that include adjustable output voltage, the voltage regulation feedback is through the FB pin. A resistor divider is used from the battery output voltage to GND. BAT pin remains connected directly to the battery output voltage for current sensing with respect to SNS. 16 www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 Charge Termination And Recharge The bqSWITCHER monitors the charging current during the voltage regulation phase. Once the termination threshold, ITERM, is detected, the bqSWITCHER terminates charge. The termination current level is selected by the value of programming resistor, R(ISET2), connected to the ISET2 pin. I TERM + K (ISET2) ǒR(ISET2) V TERM Ǔ R (SNS) (8) where D R(SNS) is the external current-sense resistor D VTERM is the output of the ISET2 pin D K(ISET2) is the A/V gain factor D VTERM and K(ISET2) are specified in the Electrical Characteristics table As a safety backup, the bqSWITCHER also provides a programmable charge timer. The charge time is programmed by the value of a capacitor connected between the TTC pin and GND by the following formula: t CHARGE + C (TTC) K (TTC) (9) where D C(TTC) is the capacitor connected to the TTC pin D K(TTC) is the multiplier A new charge cycle is initiated when one of the following conditions are detected: D The battery voltage falls below the VRCH threshold D Power-on reset (POR), if battery voltage is below the VRCH threshold D CE toggle D TTC pin, described as follows. In order to disable the charge termination and safety timer, the user can pull the TTC input below the VTTC_EN threshold. Going above this threshold enables the termination and safety timer features and also reset the timer. Tying TTC high to VTSB disables the safety timer only. Sleep Mode The bqSWITCHER enters the low-power sleep mode if the VCC pin is removed from the circuit. This feature prevents draining the battery during the absence of VCC. Charge Status Outputs The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the following table. These status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates that the open-drain transistor is turned off. Table 1. Status Pins Summary STAT1 STAT2 Charge-in-progress Charge State ON OFF Charge complete OFF ON Charge suspend, timer fault, overvoltage, sleep mode, battery absent(1) OFF OFF (1) bq2411x IC do not have timer fault or battery absent modes www.ti.com 17 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 Table 2. Status Pins Summary (bq24108 only) Charge State STAT1 STAT2 OFF OFF Charge-in-progress ON OFF Charge complete OFF ON Battery over discharge, VI(BAT) < V(SC) ON/OFF (0.5 Hz) OFF Charge suspend, (due to TS pin and internal thermal protection) ON/OFF (0.5 Hz) OFF Precharge timer fault ON/OFF (0.5 Hz) OFF Fast charge timer fault ON/OFF (0.5 Hz) OFF OFF OFF Battery absent Sleep mode PG Output The open-drain PG (power good) indicates when the AC-to-DC adapter (i.e., VCC) is present. The output turns ON when sleep-mode exit threshold, VSLP−EXIT, is detected. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or communicate to the host processor. CE Input (Charge Enable) The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the charge and a high-level VCC signal disables the charge. A high-to-low transition on this pin also resets all timers and fault conditions. Note that the CE pin cannot be pulled up to VTSB voltage. This may create power-up issues. Battery Absent Detection For applications with removable battery packs, bqSWITCHER provides a battery absent detection scheme to reliably detect insertion and/or removal of battery packs. 18 www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 POR or VRCH Detection routine runs on power up and if VBAT drops below refresh threshold due to removing battery or discharging battery. Yes Enable I(DETECT) for t(DETECT) VI(BAT)<V(LOWV) No BATTERY PRESENT, Begin Charge No BATTERY PRESENT, Begin Charge Yes Apply I(WAKE) for t(WAKE) VI(BAT) > VO(REG) −VRCH Yes BATTERY ABSENT Figure 9. Battery Absent Detection for bq2410x ICs only The voltage at the BAT pin is held above the battery recharge threshold, VRCH, by the charged battery following fast charging. When the voltage at the BAT pin falls to the recharge threshold, either by a load on the battery or due to battery removal, the bqSWITCHER begins a battery absent detection test. This test involves enabling a detection current, IDETECT, for a period of tDETECT and checking to see if the battery voltage is below the precharge threshold, VLOWV. Following this, the precharge current, IOPRECHG is applied for a period of tDETECT and the battery voltage is checked again to ensure that it is above the recharge threshold. The purpose of this current is to attempt to close a battery pack with an open protector, if one is connected to the bqSWITCHER. Passing both of the discharge and charging tests indicates a battery absent fault at the STAT pins. Failure of either test starts a new charge cycle. For the absent battery condition, the voltage on the BAT pin rises and falls between the VLOWV and VOREG thresholds indefinitely. www.ti.com 19 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 Timer Fault Recovery As shown in Figure 5, bqSWITCHER provides a recovery method to deal with timer fault conditions. The following summarizes this method. Condition #1 VI(BAT) above recharge threshold (VOREG − VRCH) and timeout fault occurs. Recovery method: bqSWITCHER waits for the battery voltage to fall below the recharge threshold. This could happen as a result of a load on the battery, self-discharge or battery removal. Once the battery falls below the recharge threshold, the bqSWITCHER clears the fault and enters the battery absent detection routine. A POR or CE or TTE toggle also clears the fault. Condition #2 Charge voltage below recharge threshold (VRCH) and timeout fault occurs Recovery method: Under this scenario, the bqSWITCHER applies the IDETECT current. This small current is used to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If the battery voltage goes above the recharge threshold, then the bqSWITCHER disables the IDETECT current and executes the recovery method described for condition #1. Once the battery falls below the recharge threshold, the bqSWITCHER clears the fault and enters the battery absent detection routine. A POR or CE toggle also clears the fault. Output Overvoltage Protection (Applies To All Versions) The bqSWITCHER provides a built-in overvoltage protection to protect the detect and other components against damages if the battery voltage gets too high, as when the battery is suddenly removed. When an overvoltage condition is detected, this feature turns off the PWM and STATx pins. The fault is cleared once VIBAT drops to the recharge threshold (VOREG − VRCH). FUNCTIONAL DESCRIPTION FOR SYSTEM-CONTROLLED VERSION (bq2411x) For applications requiring charge management under the host system control, the bqSWITCHER (bq2411x) offers a number of control functions. The following section describes these functions. Precharge And Fast Charge Control A low-level signal on the CMODE pin forces the bqSWITCHER to charge at the precharge rate set on the ISET2 pin. A high-level signal forces charge at fast charge rate as set by the ISET1 pin. If the battery reaches the voltage regulation level, VOREG, the bqSWITCHER transitions to voltage regulation phase regardless of the status of the CMODE input. Charge Termination And Safety Timers The charge timers and termination are disabled in the system-controlled versions of the bqSWITCHER. The host system can use the CE input to enable or disable charge. When an overvoltage condition is detected, the charger process stops, and all power FETs are turned off. Inductor, Capacitor, and Sense Resistor Selection Guidelines The bqSWITCHER provides internal loop compensation. With this scheme, best stability occurs when LC resonant frequency, fo is approximately 16 kHz (8 kHz to 32 kHz). Equation (10) can be used to calculate the value of the output inductor and capacitor. Table 2 provides a summary of typical component values for various charge rates. f0 + 20 1 2p ǸLOUT C OUT (10) www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 Table 3. Output Components Summary 0.5 A 1A 2A Output inductor, LOUT CHARGE CURRENT 22 µH 10 µH 4.7 µH Output capacitor, COUT 4.7 µF 10 µF 22 µF (or 2 × 10 µH) ceramic Sense resistor, R(SNS) 0.2 Ω 0.1 Ω 0.05 Ω THERMAL CONSIDERATIONS The SWITCHER is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application Note (SLUA271). The most common measure of package thermal performance is thermal impedance (θJA) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θJA is: q (JA) + TJ * TA P (11) Where: TJ = chip junction temperature TA = ambient temperature P = device power dissipation Factors that can greatly influence the measurement and calculation of θJA include: D D D D D Whether or not the device is board mounted Trace size, composition, thickness, and geometry Orientation of the device (horizontal or vertical) Volume of the ambient air surrounding the device under test and airflow Whether other surfaces are in close proximity to the device being tested The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power FET. It can be calculated from the following equation: P = [Vin × lin − Vbat × Ibat] Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. (See Figure 6.) PCB LAYOUT CONSIDERATION It is important to pay special attention to the PCB layout. The following provides some guidelines: D To obtain optimal performance, the power input capacitors, connected from input to PGND should be placed as close as possible to the bqSWITCHER. The output inductor should be placed directly above the IC and the output capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area from the OUT pin through the LC filter and back to the GND pin. The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads connected across the Rsns back to the IC, close to each other (minimize loop area) or on top of each other on adjacent layers (do not route the sense leads through a high-current path). Use an optional capacitor downstream from the sense resistor if long (inductive) battery leads are used. www.ti.com 21 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 D Place all small signal components (CTTC, RSET1/2 and TS) close to their respective IC pin (do not place components such that routing interrupts power stage currents). All small control signals should be routed away from the high current paths. D The PWB should have a ground plane (return) connected directly to the return of all components through vias (3 vias per capacitor for power-stage capacitors, 3 vias for the IC PGND, 1 via per capacitor for small signal components). A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-small signal) which reduces noise coupling and ground bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is not a ground bounce issue, and having the components segregated minimizes coupling between signals. D The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET. The thermal vias in the IC PowerPAD™ provide the return path connection. D The bqSWITCHER is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application Note (SLUA271). Six 10−13 mil vias are a minimum number of recommended vias, placed in the IC’s power pad, connecting it to a ground thermal plane on the opposite side of the PWB. This plane must be at the same potential as Vss and PGND of this IC. D See the User Guide (SLUU200) for an example of good layout. WAVEFORMS: All waveforms are taken at Lout (IC Out pin). VIN = 7.6 V and the battery was set to 2.6 V, 3.5 V, and 4.2 V for the three waveforms. When the top switch of the converter is on, the waveform is at ~7.5 V, and when off, the waveform is near ground. Note that the ringing on the switching edges is small. This is due to a tight layout (minimized loop areas), a shielded inductor (closed core), and using a low-inductive scope ground lead (i.e., short with minimum loop) . 22 www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 Precharge: The current is low in precharge so the bottom synchronous FET turns off after its minimum on-time which explains the step between ~0 V and −0.5 V. When the bottom FET and top FET are off, the current conducts through the body diode of the bottom FET which results in a diode drop below the ground potential. The initial negative spike is the delay turning on the bottom FET, which is to prevent shoot-through current as the top FET is turning off. Fast Charge: This is captured during the constant-current phase. The two negative spikes are the result of the short delay when switching between the top and bottom FETs. The break-before-make action prevents current shoot-through and results in a body diode drop below ground potential during the break time. www.ti.com 23 bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 Charge during Voltage Regulation and Approaching Termination: Note that this waveform is similar to the precharge waveform. The difference is that the battery voltage is higher so the duty cycle is slightly higher. The bottom FET stays on longer because there is more of a current load than during precharge; it takes longer for the inducator current to ramp down to the current threshold where the synchronous FET is disabled. 24 www.ti.com bq24100, bq24103, bq24105 bq24108, bq24113, bq24115 SLUS606B − JUNE 2004 − REVISED NOVEMBER 2004 Application Note: Charging Battery and Powering System Without Affecting Battery Charge and Termination. LOUT 10 µH bq24100RHL VIN 3 IN OUT 1 4 IN OUT 20 6 VCC PGND 17 2 STAT1 PGND 18 19 STAT2 SNS 15 PG BAT 14 10 µF 5 VTSB 7 CTTC ISET1 8 TTC 16 CE ISET2 9 10 VSS R(SNS) R(SYS) COUT 10 µF PACK+ + R(ISET1) 0.1 µF PACK− VTSB R(ISET2) RT1 TS 12 TEMP PWR PAD VTSB 11 RT2 VIN VIN D1 Adapter Present BATTERY PACK VIN D2 Done D3 Charge UDG−04033 The bqSWITCHER was designed as a stand-alone battery charger but can be easily adapted to power a system load, while considering a few minor issues. Advantages: 1. The charger controller is based only on what current goes through the current-sense resistor (so precharge, constant current, and termination all work well), and is not affected by the system load. 2. The input voltage has been converted to a usable system voltage with good efficiency from the input. 3. Extra external FETs are not needed to switch power source to the battery. 4. The TTC pin can be grounded to disable termination and keep the converter running and the battery fully charged, or let the switcher terminate when the battery is full and then run off of the battery via the sense resistor. Other Issues: 1. If the system load current is large (≥ 1 A) the IR drop across the battery impedance causes the battery voltage to drop below the refresh threshold and start a new charge. The charger would then terminate due to low charge current. Therefore, the charger would cycle between charging and termination. If the load is smaller, the battery would have to discharge down to the refresh threshold resulting in a much slower cycling. Note that grounding the TTC pin keeps the converter on continuously. 2. If TTC is grounded, the battery is kept at 4.2 V (not much different than leaving a fully charged battery set unloaded). 3. The efficiency takes a 2−3% hit when discharging through the sense resistor to the system. www.ti.com 25 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) BQ24100RHL PREVIEW QFN RHL 20 50 TBD Call TI BQ24100RHLR ACTIVE QFN RHL 20 3000 Pb-Free (RoHS) CU NIPDAU Call TI Level-1-260C-UNLIM BQ24103RHLR ACTIVE QFN RHL 20 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM BQ24105RHLR ACTIVE QFN RHL 20 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM BQ24108RHLR ACTIVE QFN RHL 20 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM BQ24113RHLR ACTIVE QFN RHL 20 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM BQ24115RHLR ACTIVE QFN RHL 20 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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