bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC (bqTINY™-III)
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Small 3,5 mm × 4,5 mm QFN Package
Designed for Single-Cell Li-Ion- or
Li-Polymer-Based Portable Applications
Integrated Dynamic Power-Path Management
(DPPM) Feature Allowing the AC Adapter or
the USB Port to Simultaneously Power the
System and Charge the Battery
Power Supplement Mode Allows Battery to
Supplement the USB or AC Input Current
Autonomous Power Source Selection (AC
Adapter or USB)
Integrated USB Charge Control With
Selectable 100-mA and 500-mA Maximum
Input Current Regulation Limits
USB High Current Regulation Limit, 1 A Max
(bq24039 Only)
Dynamic Total Current Management
for USB
Supports Up to 2-A Total Current
3.3-V Integrated LDO Output
Thermal Regulation for Charge Control
Charge Status Outputs for LED or System
Interface Indicates Charge and Fault
Conditions
Reverse Current, Short-Circuit, and Thermal
Protection
Power Good (AC Adapter and USB Port
Present) Status Outputs
Charge Voltage Options: 4.2 V or 4.36 V
Smart Phones and PDA
MP3 Players
Digital Cameras Handheld Devices
Internet Appliances
DESCRIPTION
The bqTINY™-III series of devices are highly integrated Li-ion linear chargers and system power-path
management devices targeted at space-limited portable applications. The bqTINY-III series offer integrated USB-port and DC supply (AC adapter),
power-path
management
with
autonomous
power-source selection, power FETs and current
sensors, high accuracy current and voltage regulation, charge status, and charge termination, in a
single monolithic device.
The bqTINY-III powers the system while independently charging the battery. This feature reduces the
charge and discharge cycles on the battery, allows
for proper charge termination and allows the system
to run with an absent or defective battery pack. This
feature also allows for the system to instantaneously
turn on from an external power source in the case of
a deeply discharged battery pack. The IC design is
focused on supplying continuous power to the system
when available from the AC, USB, or battery sources.
POWER FLOW DIAGRAM (1)
AC Adapter
(2)
AC
OUT
VDC
USB Port
D+
D−
VBUS
System
GND
Q1
PACK+
USB
40 mΩ
BAT
+
PACK−
GND
Q3
bq2403x
Q2
UDG−04082
(1)
See Figure 2 and functional block diagram for more detailed feature information.
(2)
P-FET back gate body diodes are disconnected to prevent body diode conduction.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
bqTINY is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOSFET
gates.
DESCRIPTION (CONTINUED)
The power select pin, PSEL, defines which input source is to be used first (primary source – AC or USB). If the
primary source is not available, then the IC automatically switches over to the other secondary source if available
or the battery as the last option. If the PSEL is set low, the USB input is selected first and if not available, the AC
line is selected (if available) but programmed to a USB input limiting rate (100 mA/500 mA max). This feature
allows the use of one input connector, where the host programs the PSEL pin according to what source is
connected (AC adaptor or USB port).
The bq24039 has replaced the PSEL pin (node now tied high internally – AC priority) with the ISET3 pin that
allows for twice the standard USB input limiting current levels (200 mA/1000 mA), when set to high. This is a
feature for manufacturers that supply their own USB power source that is rated for this higher current level.
The bq24038 replaces USBPG with pin VBSEL, to enable user selection of the charge voltage. In addition, pin
ACPG was modified to PG. PG is active low when either ac power or USB power is detected.
The ISET1 pin programs the battery's fast charge constant current level with a resistor. During normal AC
operation, the input supply provides power to both the OUT (System) and BAT pins. For peak or excessive loads
(typically when operating from the USB power, PSEL = Low) that would cause the input source to enter current
limit (or Q3 - USB FET limiting current) and its source and system voltage (OUT pin) to drop, the dynamic
power-path management (DPPM) feature reduces the charging current attempting to prevent any further drop in
system voltage. This feature allows the selection of a lower current rated adaptor based on the average load
(ISYS-AVG + IBAT-PGM ) rather than a high peak transient load.
ORDERING INFORMATION (1)
TA
–40°C to 125°C
(1)
(2)
(3)
(4)
(5)
2
BATTERY
VOLTAGE (V)
OUT PIN FOR AC
INPUT CONDITIONS
PART
NUMBER (2) (3)
STATUS
PACKAGE
MARKING
4.2
Regulated to 6 V (4)
bq24030RHLR
Released
ANB
4.2
Regulated to 4.4 V (4)
bq24032RHLR
Released
AMZ
4.2
Regulated to 4.4 V (4)
bq24032ARHLR
Released
BPE
4.2
Regulated to 4.4 V (4)
bq24032ARHLT
Released
BPE
4.2
Cutoff for AC overvoltage (5)
bq24035RHLR
Released
ANA
4.2
Cutoff for AC overvoltage (5)
bq24039RHLR
Preview
ANH
4.36
Regulated to 6 V (4)
bq24031RHLR
Preview
BOU
4.36
Regulated to 6 V (4)
bq24031RHLT
Preview
BOU
4.2/4.36 Selectable
Regulated to 4.4 V
bq24038RHLR
Released
BOW
4.2/4.36 Selectable
Regulated to 4.4 V
bq24038RHLT
Released
BOW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The RHL package is available in the following options:
R - taped and reeled in quantities of 3,000 devices per reel.
T - taped and reeled in quantities of 250 devices per reel.
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
If AC < VO(OUT-REG), the AC is connected to the OUT pin by a P-FET, (Q1).
If AC > V(CUT-OFF) the P-FET disconnects the OUT pin from the AC.
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
bq24030, bq24031,
bq24032, bq24032A,
bq24035, bq24038. bq24039
Input voltage
Input voltage
AC (DC voltage wrt (with respect to) VSS)
–0.3 V to 18 V
USB (DC voltage wrt VSS)
–0.3 V to 7 V
BAT, CE, DPPM, ACPG, PSEL, OUT, ISET1, ISET2, ISET3,
STAT1, STAT2, TS, USBPG , PG, VBSEL (all DC voltages wrt
VSS)
–0.3 V to 7 V
LDO (DC voltage wrt VSS)
–0.3 V to VO(OUT) + 0.3 V
TMR
–0.3 V to VO(LDO) + 0.3 V
AC
Input current
Output current
3.5 A
USB
1000 mA
OUT
4A
BAT (2)
–4 A to 3.5 A
Output source current (in
regulation at 3.3 V LDO)
LDO
30 mA
Output sink current
ACPG, STAT1, STAT2, USBPG, PG
1.5 mA
Storage temperature range, Tstg
–65°C to 150°C
Junction temperature range, TJ
–40°C to 150°C
Lead temperature (soldering, 10 seconds)
(1)
(2)
300°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
Negative current is defined as current flowing into the BAT pin.
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage (from AC input)
(1) (2)
MIN
MAX
bq24030/2/2A/5/9, bq24038 (at VBSEL = LOW)
4.35
16.00
bq24031, bq24038 (at VBSEL = HIGH)
4.55
16
4.35
6.0
(1)
VCC
Supply voltage (from USB input)
IAC
Input current, AC
IUSB
Input current, USB
TJ
Operating junction temperature range
(1)
(2)
2
0.5
–40
125
UNIT
V
A
°C
VCC is defined as the greater of AC or USB input.
Verify that power dissipation and junction temperatures are within limits at maximum VCC .
DISSIPATION RATINGS
(1)
PACKAGE
TA ≤ 40°C
POWER RATING
DERATING FACTOR
TA > 40°C
θJA
20-pin RHL (1)
1.81 W
21 mW/°C
46.87 °C/W
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2×3 via matrix.
3
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BIAS CURRENTS
ICC(SPLY)
Active supply current, VCC
VVCC > VVCC(min)
1
2
ICC(SLP)
Sleep current (current into BAT
pin)
V(AC) < V(BAT), V(USB) < V(BAT),
2.6 V ≤ VI(BAT)≤ VO(BAT-REG),
Excludes load on OUT pin
2
5
ICC(AS-STDBY)
AC standby current
VI(AC) ≤ 6V, Total current into AC pin with
chip disabled, Excludes all loads,
CE=LOW, after t(CE-HOLDOFF) delay
200
ICC(USB-STDBY)
USB standby current
Total current into USB pin with chip
disabled, Excludes all loads, CE=LOW,
after t(CE-HOLDOFF) delay
200
ICC(BAT-STDBY)
BAT standby current
Total current into BAT pin with AC and/or
USB present and chip disabled; Excludes all loads (OUT and LDO),
CE=LOW, after t(CE-HOLDOFF) delay,
0°C ≤ TJ≤ 85°C (1)
45
60
IIB(BAT)
Charge done current, BAT
Charge DONE, AC or USB supplying the
load
1
5
6.4
6.8
mA
µA
HIGH AC CUTOFF MODE
VCUT-OFF
Input ac cutoff voltage
(bq24039 is product preview)
VI(AC) > 6.8 V, AC FET (Q1) turns off,
USB FET (Q3) turns on if USB power
present, otherwise BAT FET (Q2) turns
on.
Output regulation voltage
Active only if AC or USB is present,
VI(OUT)≥ VO(LDO) + (IO(LDO) × RDS(on))
6.1
V
LDO OUTPUT
VO(LDO)
Regulation accuracy (2)
IO(LDO)
Output current
RDS(on)
On resistance
C(OUT) (3)
Output capacitance
3.3
–5%
V
5%
20
OUT to LDO
mA
50
Ω
1
µF
OUT PIN-VOLTAGE REGULATION
VO(OUT-REG)
Output
regulation
voltage
bq24030/31
VI(AC)≥ 6 V+VDO
6.0
6.3
bq24032/2A
VI(AC)≥ 4.4 V+VDO
4.4
4.5
bq24038
VBSEL = HIGH or VBSEL = LOW,
VI(AC) > 4.4 V+VDO
4.4
4.5
bq24039
VO(REG) + VDD-AC < VAC < VCUT-OFF
6
6.3
V
OUT PIN – DPPM REGULATION
V(DPPM-SET)
DPPM set point (4)
VDPPM-SET < VOUT
2.6
5
V
I(DPPM-SET)
DPPM current source
AC or USB present
95
100
105
µA
SF
DPPM scale factor
V(DPPM-REG)= V(DPPM-SET) × SF
1.139
1.150
1.162
(1)
(2)
(3)
(4)
4
This includes the quiescent current for the integrated LDO.
In standby mode (CE low) the accuracy is ±10%.
LDO output capacitor not required but one with a value of 0.1 µF is recommended.
V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG).
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI(AC)≥ VCC(min), PSEL=High,
II(AC) = 1 A, (IO(OUT)+ IO(BAT))
300
475
VI(USB)≥ VCC(min), PSEL = Low, or no AC
(bq24039), ISET2 = High
II(USB) = 0.4 A, (IO(OUT)+IO(BAT))
140
180
VI(USB)≥ VCC(min), PSEL = Low, or no AC
(bq24039), ISET2 = Low
II(USB) = 0.08 A, (IO(OUT)+ IO(BAT))
28
36
VI(USB)≥ VCC(min), ISET2 = ISET3 = HIGH,
II(USB) = 0.9 A (IO(OUT)+ IO(BAT)),
bq24039 only
315
405
mV
40
100
mV
OUT PIN – FET (Q1, Q3, AND Q2) DROP-OUT VOLTAGE (RDSon)
V(ACDO)
V(USBDO) (6)
V(BATDO)
AC to OUT dropout voltage (5)
USB to OUT dropout voltage
BAT to OUT dropout voltage
(discharging)
VI
(BAT)≥
3 V, Ii(BAT)= 1.0 A, VCC < Vi(BAT)
mV
OUT PIN - BATTERY SUPPLEMENT MODE
VBSUP1
VBSUP2
Enter battery supplement mode
(battery supplements OUT current
in the presence of input source
Exit battery supplement mode
VI(BAT)> 2 V
VI(OUT)
≤ VI(BAT)
– 60 mV
VI(OUT)
≥ VI(BAT)
– 20 mV
VI(BAT)> 2 V
V
OUT PIN - SHORT CIRCUIT
IOSH1
BAT to OUT short-circuit recovery
Current source between BAT to OUT for
short-circuit recovery to
VI(OUT)≤ VI(BAT) –200 mV
RSHAC
AC to OUT short-circuit limit
VI(OUT) ≤ 1 V
500
RSHVSB
USB to OUT short-circuit limit
VI(OUT) ≤ 1 V
500
10
mA
Ω
BAT PIN CHARGING – PRECHARGE
V(LOWV)
Precharge to fast-charge transition
Voltage on BAT
threshold
TDGL(F)
Deglitch time for fast-charge to
precharge transition (7)
tFALL = 100 ns, 10 mV overdrive,
VI(BAT) decreasing below threshold
IO(PRECHG)
Precharge range
1 V < VI(BAT) < V(LOWV), t < t(PRECHG),
IO(PRECHG) = (K(SET) × V(PRECHG))/ RSET
V(PRECHG)
Precharge set voltage
1 V < VI(BAT) < V(LOWV), t < t(PRECHG)
230
(8) (9)
Vi (BAT) > V(LOWV), VI(OUT) - VI (BAT) >
V(DO-MAX), PSEL = High
IOUT(BAT) = (K(SET) × V(SET) / RSET),
VI(OUT) > VO(OUT-REG) + V(DO-MAX)
100
RPOUT
AC to OUT and USB to OUT
short-circuit pullup
VI(OUT) < 1 V
V(SET)
Battery charge current set voltage (10)
Voltage on ISET1, VVCC≥ 4.35 V,
VI(OUT)- VI(BAT) > V(DO-MAX), VI(BAT) >
V(LOWV)
K(SET)
Charge current set factor, BAT
2.9
3
3.1
22.5
10
V
ms
150
mA
250
270
mV
1000
1500
mA
BAT PIN CHARGING - CURRENT REGULATION
IO(BAT)
AC battery charge current range
Ω
500
2.475
2.500
2.525
100 mA ≤ IO(BAT) ≤ 1 A
400
425
450
10 mA ≤ IO(BAT) ≤ 100 mA (11)
300
450
600
V
(5)
VDO(max), dropout voltage is a function of the FET, RDS(on), and drain current. The dropout voltage increases proportionally to the
increase in current.
(6) RDS(on) of USB FET Q3 is calculated by: (VUSB – VOUT) / (IOUT + IBAT) when II(USB) ≤ II(USB-MIN) (FET fully on, not in regulation).
(7) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
(8) When input current remains below 2 A, the battery charging current may be raised until the thermal regulation limits the charge current.
(9) When PSEL is pulled low, and USBPG is high, the AC input functions as a USB input for bq24039.
(10) For half-charge rate, V(SET) is 1.25 V ± 25 mV for bq24032/32A only.
(11) Specification is for monitoring charge current via the ISET1 pin during voltage regulation mode, not for a reduced fast-charge level.
5
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB PIN INPUT CURRENT REGULATION
I(USB)
USB input current range,
bq24030/1/2/2A/5/8;
bq24039 (12)
VI(BAT) > V(LOWV),
VI(USB) - VI(BAT) > V(DO-MAX), ISET2= Low,
ISET3 = Low, PSEL = Low, or no AC
(bq24039), (13)
VI(BAT) > V(LOWV),
VI(USB) - VI(BAT) > V(DO-MAX), ISET2= High,
ISET3 = Low, PSEL = Low, or no AC
(bq24039), (12)
(14)
100
mA
400
(14)
500
BAT PIN CHARGING VOLTAGE REGULATION, VO (BAT-REG) + V (DO-MAX) < VCC, ITERM < IBAT(OUT) ≤ 1 A
bq24030/2/2A/5/8
VO(BAT-REG)
Battery
charge
voltage
4.2
bq24031
bq24038
Battery charge voltage regulation
accuracy
4.36
VBXL = HI
VBXL = LO
TA = 25°C
V
4.36
4.2
–0.5%
0.5%
–1%
1%
10
150
mA
CHARGE TERMINATION DETECTION
I(TERM)
Charge termination detection
range
VI(BAT) < V(RCH),
I(TERM) = (K(SET) × V(TERM))/ RSET
V(TERM-AC/USB)
bq24032
Charge termination set voltage,
measured on ISET1
VI(BAT) > V(RCH)
235
250
265
mV
V(TERM-AC)
bq24030/1/2A/5/8
AC-charge termination detection
voltage, measured on ISET1
VI(BAT) > V(RCH) , PSEL = High,
ACPG = Low
235
250
265
mV
V(TAPER-USB)
bq24030/1/2A/5/8
USB-charge termination detection
voltage, measured on ISET1
VI(BAT) > V(RCH), PSEL = Low or
PSEL = High and ACPG = High
95
100
130
mV
V(TERM-AC/USB)
bq24039 only
AC/USB charge termination detec- VI(BAT) > V(RCH) , ISET3 = Low
tion voltage, measured on ISET1
VI(BAT) > V(RCH) , ISET3 = High
95
100
130
235
250
265
TDGL(TERM)
Deglitch time for termination detection
tFALL = 100 ns, 10 mV overdrive,
ICHG increasing above or decreasing below threshold
22.5
mV
ms
TEMPERATURE SENSE COMPARATORS
VLTF
High voltage threshold
Temp fault at V(TS) > VLTF
2.465
2.500
2.535
VHTF
Low voltage threshold
Temp fault at V(TS) < VHTF
0.485
0.500
0.515
V
ITS
Temperature sense current source
94
100
106
µA
TDGL(TF)
Deglitch time for temperature fault
detection (15)
R(TMR) = 50 kΩ, VI(BAT) increasing or
decreasing above and below;
100-ns fall time, 10-mv overdrive
22.5
V
ms
BATTERY RECHARGE THRESHOLD
VRCH
Recharge threshold voltage
TDGL(RCH)
Deglitch time for recharge detection (15)
VO(BAT-REG)
–0.075
R(TMR) = 50 kΩ, VI(BAT) increasing
or decreasing below threshold,
100-ns fall time, 10-mv overdrive
VO(BAT-REG)
–0.100
22.5
VO(BAT-REG)
–0.125
V
ms
(12) With the PSEL= low, the bqTINY-III defaults to USB charging. If USB input is ≤ VBAT, then the bqTINY-III charges from the AC input at
the USB charge rate. In this configuration, the specification is 400 mA (min) and 500 mA (max) for bq24030/2/2A/5/8 only.
(13) With the PSEL= low, the bqTINY-III defaults to USB charging. If USB input is ≤ VBAT, then the bqTINY-III charges from the AC input at
the USB charge rate. In this configuration, the specification is 80 mA (min) and 100 mA (max) for bq24030/1/2A/5/8 only; 75 mA (min)
and 100 mA (max) for bq24032.
(14) ISET3 - bq24039 only; ISET3 = High-increases current range by a factor of 2 (min - max)
(15) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
6
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
STAT1, STAT2. ACPG AND USBPG, PG OPEN DRAIN (OD)
VOL
Low-level output saturation voltage
ILKG
Input leakage current
MIN
TYP
MAX
UNIT
0.25
V
5
µA
OUTPUTS (16)
IOL = 5 mA, An external pullup
resistor ≥ 1 K required.
1
ISET2, CE, VBSEL, AND ISET3 INPUTS
VIL
Low-level input voltage
0
VIH
High-level input voltage
1.4
IIL
Low-level input current, CE or
ISET3
–1
IIH
High-level input current, CE or
ISET3
IIL
Low-level input current, ISET2
VISET2 = 0 V
IIH
High-level input current, ISET2
VISET2 = VCC
IIL1
Low-level input current
VBSEL = Low
IIH1
High-level input current
VBSEL = High
t(CE-HLDOFF)
Holdoff time, CE
CE going low only
Low-level input voltage
Falling Hi→Low; 280 K ± 10% applied
when low. (bq24030/2A/5/8)
0.4
V
1
µA
–20
40
5
1
15
4
6
ms
PSEL INPUT
VIL
0.975
(bq24032 only)
VIH
High-level input voltage
Input RPSEL sets external hysteresis
(bq24030/2A/5/8)
(bq24032 only)
IIL
Low-level input current, PSEL
IIH
High-level input current, PSEL
1
1.025
0
0.4
VIL + .01
VIL + .024
V
V
1.4
–1
µA
µA
TIMERS
K(TMR)
Timer set factor
R(TMR) (17)
External resistor limits
t(PRECHG)
Precharge timer
I(FAULT)
Timer fault recovery pullup from
OUT to BAT
t(CHG) = K(TMR) × R(TMR)
0.313
0.414
s/Ω
30
0.360
100
kΩ
0.09 × t(CHG)
0.10 × t(CHG) 0.11 × t(CHG)
1
s
kΩ
CHARGER SLEEP THRESHOLDS (ACPG , PG, and USBPG THRESHOLDS, LOW → POWER GOOD)
V(SLPENT) (18)
V(SLPEXIT)
t(DEGL)
(18)
Sleep-mode entry threshold
V(UVLO)≤ VI(BAT)≤ VO(BAT-REG),
No t(BOOT-UP) delay
Sleep-mode exit threshold
V(UVLO)≤ VI(BAT)≤ VO(BAT-REG),
No t(BOOT-UP) delay
Deglitch time for sleep mode (19)
R(TMR) = 50 kΩ,
V(AC) or V(USB) or decreasing below
threshold, 100-ns fall time, 10-mv overdrive
VVCC ≤
VI(BAT)
+125 mV
VVCC ≥
VI(BAT)
+190 mV
22.5
V
ms
START-UP CONTROL and USB BOOT-UP
t(BOOT-UP)
(16)
(17)
(18)
(19)
Boot-up time
On the first application of USB input
power or AC input with PSEL Low (or
ISET3 low for bq24039)
120
150
180
ms
See Charger Sleep mode for ACPG (VCC = VAC) and USBPS (VCC = VUSB) specifications.
To disable the safety timer and charge termination, tie TMR to the LDO pin.
The IC is considered in sleep mode when both AC and USB are absent (ACPG = USBGP = OPEN DRAIN).
Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
7
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCHING POWER SOURCE TIMING
tSW-BAT
Switching power source from inputs (AC or USB) to battery
tSW-AC/USB
Switching from AC to USB, or,
USB to AC by input source removal. (20)
tSW-PSEL
Switching from AC to USB, or
USB to AC by toggling PSEL,
bq24030/1/2/2A/5/8 only
Only AC power or USB power applied.
Measure from:
[xxPG: Lo → Hi to I(xx) > 5 mA],
xx = AC or USB I(OUT) = 100 mA,
RTRM = 50 K
50
µs
Measure from:
I(AC) < 5 mA to I(USB) > 5 mA or I(USB)
< 5 mA → I(AC) > 5 mA;
I(OUT) = 100 mA, RTMR = 50 K,
ISET2 = hi, ROUT > 15 Ω, VDPPM = 2.5 V
100
50
100
THERMAL SHUTDOWN REGULATION (21)
T(SHTDWN)
TJ(REG)
Temperature trip
TJ (Q1 and Q3 only)
Thermal hysteresis
TJ (Q1 and Q3 only)
155
Temperature regulation limit
TJ (Q2)
115
Undervoltage lockout
Decreasing VCC
2.45
30
°C
135
UVLO
V(UVLO)
Hysteresis
2.50
27
2.65
V
mV
(20) The power handoff is implemented once the PG pin goes high (removed sources PG) which is when the removed source drops to the
battery voltage. if the battery voltage is critically low, the system may lose power unless the system takes control of the PSEL pin and
switches to the available power source prior to shutdown. The USB source often has less current available; so, the system may have to
reduce its load when switching from AC to USB (bq24030/1/2/2A/5/8).
(21) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or
shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically
does not cause a thermal shutdown (input FETs turning off) by itself.
8
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
(1)
DEVICE INFORMATION
2
STAT2
3
18
ACPG / PG
AC
4
17
OUT
BAT
5
16
OUT
BAT
6
15
OUT
ISET2
7
14
TMR
PSEL
8
13
DPPM
ISET1
9 10
11 12
TS
VSS
1
20 19
USBPG / VBSEL
STAT1
CE
(1)
USB
LDO
bq24030RHL − bq24038RHL
RHL PACKAGE
(TOP VIEW)
The bq24031RHL and bq24039RHL, are Product Preview devices.
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
AC
4
ACPG
(1)
I/O
DESCRIPTION
I
Charge input voltage from AC adapter
18
O
AC power-good status output (open-drain)
BAT
5, 6
I/O
Battery input and output.
CE
9
I
Chip enable input (active high)
DPPM
13
I
Dynamic power-path management set point (account for scale factor)
ISET1
10
I/O
ISET2
7
I
Charge current set point for USB port. (High = 500 mA, Low = 100 mA) For bq24032, see half-charge
current mode using ISET2.
ISET3 (2)
8
I
(bq24039 only) Boot-up (Low = enabled, High = disabled); TERM Detect (High = 250 nVm, Low = 100
mV), USB MODE current multiplier (High = x2 of ISET2, Low = x1 of ISET2).
LDO
1
O
3.3-V LDO regulator
OUT
15, 16, 17
O
Output terminal to the system
18
O
AC or USB power-good status output (open-drain)
PSEL (2)
8
I
Power source selection input (Low for USB, High for AC)
STAT1
2
O
Charge status output 1 (open-drain)
STAT2
3
O
Charge status output 2 (open-drain)
TMR
14
I/O
Timer program input programmed by resistor. Disable safety timer and termination by tying TMR to LDO.
TS
12
I/O
Temperature sense input
20
I
USB charge input voltage
19
O
USB power-good status output (open-drain)
VBSEL (3)
19
I
Battery charge voltage selection
VSS
11
–
Ground input (the thermal pad on the underside of the package) There is an internal electrical connection
between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be
connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad as
the primary ground input for the device. VSS pin must be connected to ground at all times.
PG
(1)
USB
USBPG
(1)
(2)
(3)
(1)
Charge current set point for AC input and precharge and termination set point for both AC and USB
Pin 18 is PG for bq24038 and ACPG for bq24030/1/2/2A/5/9.
Pin 8 is PSEL for bq24030/1/2/2A/5/8 and ISET3 for bq24039.
Pin 19 is VBSEL for bq24038 and USBPG for bq24030/1/2/2A/5/9.
9
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
FUNCTIONAL BLOCK DIAGRAM FOR bq24030/2/5 ONLY
(1)(2)
Short−Circuit Recovery
500 Ω
BAT
Short−Circuit
Recovery
USB
Charge
Enable
100 mA /
500 mA
AC
VO(OUT)
OUT
VO(LDO)
Q1
1 kΩ
3.3−V LDO
Fault
Recovery
LDO
10 mA
VSET
500 Ω
+
VIO(AC)
AC Charge
Enable
Short Circuit
Recovery
VI(IUSB−SNS)
VO(OUT)
Q2
Q3
+
VI(BAT)
BAT
VO(OUT−REG)
VI(IUSB−SNS)
USB
VI(ISET1)
ISET1
Reference, Bias & UVLO
VI(IUSB−SNS)
UVLO
VO(BAT−REG)
TMR
Oscillator
VI(BAT)
VI(BAT)
USB
Charge
Enable
+
VO(BAT−REG)
VI(ISET1)
VO(OUT)
DPPM
+
DPPM
I(DPPM) Scaling
BAT
Charge
Enable
VSET
VDPPM
+
+
Disable−
Sleep
VI(BAT)
+
VO(OUT)
TJ(REG)
*
60 mV
+
TJ
V(HTF)
+
Fast Precharge
+
1V
+
100 mA / 500 mA
VSET
200 mV
Suspend
Thermal
Shutdown
TS
1V
+
I(TS)
+
*
V(LTF)
280 kΩ
Power Source Selection
USB Charge Enable
PSEL
AC Charge Enable
CE
BAT Charge Enable
VO(BAT−REG)
Recharge
VBAT
*
Precharge
VBAT
*
Charge
Control
Timer
and
Display
Logic
500 mA/ 100 mA
Fast Precharge
1C − 500 mA
C/S − 100 mA
ISET2
ACPG
V(SET)
VI(ISET1)
Term
USBPG
*
STAT1
VBAT
VAC
VSS
STAT2
Sleep (USB)
VBAT
VUSB
10
Sleep (AC)
*
*
*
Signal Deglitched
(1)
For bq24039 (product preview) see bq24039 Differences in the Functional Descriptions section.
(2)
For bq24038 see bq24038 Differences in the Functional Descriptions section.
UDG−04084
UDG−04084
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
FUNCTIONAL DESCRIPTIONS
CHARGE CONTROL
The bqTINY-III supports a precision Li-ion or Li-polymer charging system suitable for single-cell portable devices.
See a typical charge profile, application circuit, and an operational flow chart in Figure 1 through Figure 4,
respectively.
Pre-Conditioning
Phase
Current Regulation Phase
Voltage Regulation and Charge Termination Phase
Regulation
Voltage
Regulation
Current
Charge
Voltage
Minimum
Charge
Voltage
Charge
Complete
Charge
Current
Pre−
Conditioning
and Term
Detect
UDG−04087
Figure 1. Charge Profile
bq24030/1/2/2A/5
AC Adapter
VDC
4
AC
1
10 µF
10 µF
GND
LDO
OUT 15
10 µF
OUT 16
D+
D−
VBUS
System
OUT 17
20 USB
10 µF
14 TMR
RTMR
PACK+
BAT
5
BAT
6
Battery Pack
1 µF
+
7 ISET2
PACK−
GND
USB Port
2
STAT1
3
STAT2
TS 12
TEMP
19 USBPG
18 ACPG
DPPM 13
9
CE
ISET1 10
8
PSEL
RSET
RDPPM
VSS 11
Control and
Status Signals
UDG−04083
Figure 2. Typical Application Circuit
11
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
FUNCTIONAL DESCRIPTIONS (continued)
POR
SLEEP MODE
Vcc > V I(OUT)
checked at all
times?
No
Indicate SLEEP
MODE
Yes
V I(OUT)< V (LOWV)
Yes
Regulate
IO(PRECHG)
Reset and Start
t(PRECHG)timer
Indicate Charge−
In−Progress
?
No
Reset all timers,
Start t (CHG) timer
Regulate Current
or Voltage
Indicate Charge−
In−Progress
No
V I(OUT) <V(LOWV)
Yes
Yes
No
t(PRECHG)
Expired?
t (CHG)
Expired?
Yes
No
Yes
Yes
Fault Condition
V I(OUT) <V(LOWV)
?
Indicate Fault
No
VI(OUT)> V(RCH)
?
I(TERM)
No
detection?
No
Enable I
(FAULT)
current
Yes
No
Yes
V I(OUT)> V (RCH)
?
Turn off charge
Yes
Yes
Indicate DONE
No
Disable I(FAULT)
current
V I(OUT) < V (RCH)
?
Figure 3. Charge Control Operational Flow Chart
12
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
FUNCTIONAL DESCRIPTIONS (continued)
bq24039 Differences
The bq24039 operates differently from other core parts when dealing with PSEL, USB charge levels, and charge
termination levels. Pin 8 is changed fro PSEL to ISET3. However, the PSEL function was tied high internally,
making the input AC adaptor the first choice when present. When AC is present, the PSEL pin is not externally
available to transfer to the USB input (toggle PSEL low).
The ISET3 pin, when set high, can be thought of as a 2x multiplier for the ISET2 current program level (USB
100/500 mA -> 200/1000 mA). The ISET3 also programs the termination level to C/10 when set high and C/25
when set low, for all charging sources.
bq24038 Differences
The bq24038 replaces USBPG with pin VBSEL, to enable user selection of the charge voltage. In addition, pin
ACPG was modified to PG. PG is active low when either ac power or USB power is detected.
Autonomous Power Source Selection, PSEL Control Pin
The PSEL pin selects the priority of the input sources (high = AC, low = USB), if that primary source is not
available (based on ACPG, USBPG signal), then it uses the secondary source. If neither input source is
available, then the battery is selected as the source. With the PSEL input high, the bqTINY-III attempts to charge
from the AC input. If AC input is not present, the USB is selected. If both inputs are available, the AC adapter
has priority. With the PSEL input low, the bqTINY-III defaults to USB charging. If USB input is grounded, then the
bqTINY-III charges from the AC input at the USB charge rate (as selected by ISET2). This feature can be used in
system where AC and USB power source selection is done elsewhere. The PSEL function is summarized in
Table 1.
Table 1. Power Source Selection Function Summary (1)
PSEL STATE
Low
High
(1)
(2)
(3)
(4)
AC
USB
CHARGE
SOURCE
MAXIMUM
CHARGE RATE (2)
SYSTEM
POWER
SOURCE
USB BOOT-UP
FEATURE
Present (3)
Absent
AC
ISET2
AC
Enabled
Absent (4)
Present
USB
ISET2
USB
Enabled
Present
Present
USB
ISET2
USB
Enabled
Absent
Absent
N/A
N/A
Battery
Disabled
Present
Absent
AC
ISET1
AC
Disabled
Absent
Present
USB
ISET2
USB
Disabled
Present
Present
AC
ISET1
AC
Disabled
Absent
Absent
N/A
N/A
Battery
Disabled
Table 1 is for all ICs with the following exception: For bq24039, the PSEL is tied high internally and ISET3 determines if bootup is
enabled (ISET3 = Low = ENABLED; ISET3 = High = DISABLED).
Battery charge rate is always set by ISET1, but may be reduced by a limited input source (ISET2 USB mode) and IOUT system load.
Present is defined as input being at a higher voltage than the BAT voltage (sources power good is low).
AC Absent is defined as AC input not present (ACPG is High) or Q1 turned off due to overvoltage in bq24035/39.
Boot-Up Sequence
In order to facilitate the system start-up and USB enumeration, the bqTINY-III offers a proprietary boot-up
sequence. On the first application of power to the bqTINY-III, this feature enables the 100-mA USB charge rate
for a period of approximately 150 ms, (t(BOOT-UP)), ignoring the ISET2 and CE inputs setting. At the end of this
period, the bqTINY-III implements CE and ISET2 inputs settings. Table 1 indicates when this feature is enabled.
See Figure 13.
13
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
Power-Path Management
The bqTINY-III powers the system while independently charging the battery. This features reduces the charge
and discharge cycles on the battery, allows for proper charge termination, and allows the system to run with an
absent or defective battery pack. This feature gives the system priority on input power, allowing the system to
power up with a deeply discharged battery pack. This feature works as follows (note that PSEL is assumed HIGH
for this discussion).
AC Adapter
(2)
AC
OUT
VDC
USB Port
System
GND
D+
D−
VBUS
Q1
PACK+
USB
40 mΩ
BAT
+
PACK−
GND
Q3
bq2403x
Q2
UDG−04082
Figure 4. Power-Path Management
Case 1: AC Mode (PSEL = High)
System Power
In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (see
Figure 4). For bq24030/1, Q1 acts as a switch as long as the AC input remains at or below 6 V (VO(OUT-REG)).
Once the AC voltage goes above 6 V, Q1 starts regulating the output voltage at 6 V. For bq24035/39, once the
AC voltage goes above VCUT-OFF (~6.4 V), Q1 turns off. For bq24032/2A/8, the output is regulated at 4.4 V from
the AC input. Note that switch Q3 is turned off for both devices. If the system load exceeds the capacity of the
supply, the output voltage drops down to the battery's voltage.
Charge Control
When AC is present, the battery is charged through switch Q2 based on the charge rate set on the ISET1 input.
Dynamic Power-Path Management (DPPM)
This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting,
or removal of the input supply. If the voltage on the OUT pin drops to a preset value, V(DPPM) × SF, due to a
limited amount of input current, then the battery charging current is reduced until the output voltage stops
dropping. The DPPM control tries to reach a steady-state condition where the system gets its needed current and
the battery is charged with the remaining current. No active control limits the current to the system; therefore, if
the system demands more current than the input can provide, the output voltage drops just below the battery
voltage and Q2 turns on which supplements the input current to the system. DPPM has three main advantages.
1. This feature allows the designer to select a lower power wall adapter, if the average system load is moderate
compared to its peak power. For example, if the peak system load is 1.75 A, average system load is 0.5 A
and battery fast-charge current is 1.25 A, the total peak demand could be 3 A. With DPPM, a 2-A adaptor
could be selected instead of a 3.25-A supply. During the system peak load of 1.75 A and charge load of 1.25
A, the smaller adaptor’s voltage drops until the output voltage reaches the DPPM regulation voltage
threshold. The charge current is reduced until there is no further drop on the output voltage. The system gets
its 1.75-A charge and the battery charge current is reduced from 1.25 A to 0.25 A. When the peak system
load drops to 0.5 A, the charge current returns to 1 A and the output voltage returns to its normal value.
2. Using DPPM provides a power savings compared to configurations without DPPM. Without DPPM, if the
system current plus charge current exceed the supply’s current limit, then the output is pulled down to the
battery. Linear chargers dissipate the unused power (VIN-VOUT) × ILOAD. The current remains high (at current
limit) and the voltage drop is large for maximum power dissipation. With DPPM, the voltage drop is less
(VIN-V(DPPM-REG)) to the system which means better efficiency. The efficiency for charging the battery is the
same for both cases. The advantages include less power dissipation, lower system temperature, and better
overall efficiency.
14
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
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SLUS618C – AUGUST 2004 – REVISED JUNE 2005
3. The DPPM sustains the system voltage no matter what causes it to drop, if at all possible. It does this by
reducing the noncritical charging load while maintaining the maximum power output of the adaptor.
Note that the DPPM voltage, V(DPPM), is programmed as follows:
V (DPPM) I (DPPM) R(DPPM) SF
(1)
where
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly
proportional to the programmed charging current. When the programmed charging current is reduced, due to
DPPM, the ISET1 and TMR voltages are reduced and the timer’s clock is proportionally slowed, extending the
safety time. In normal operation, V(TMR) = 2.5 V, when the clock is slowed the voltage V(TMR) us reduced,
Wgeb V(TMR) = 1.25 V, the safety timer has a value close to 2 times the normal operation timer value. See
Figure 5 through Figure 8.
Case 2: USB (PSEL = Low) bq24030/1/2/2A/8
System Power
In this case, the system load is powered directly from the USB port through the internal switch Q3 (see
Figure 14). Note in this case, Q3 regulates the total current to the 100 mA or 500 mA level, as selected on the
ISET2 input. Switch Q1 is turned off in this mode. If the system and battery load is less than the selected
regulated limit, then Q3 is fully on and VOUT is approximately (V(USB)-V(USB-DO)). The systems power management
is responsible for keeping its system load below the USB current level selected (if the battery is critically low or
missing). Otherwise, the output drops to the battery voltage; therefore, the system should have a low power
mode for USB power application. The DPPM feature keeps the output from dropping below its programmed
threshold, due to the battery charging current, by reducing the charging current.
Charge Control
When USB is present and selected, Q3 regulates the input current to the value selected by the ISET2 pin
(0.1/0.5 A). The charge current to the battery is set by the ISET1 resistor (typically > 0.5 A). Because the charge
current typically is programmed for more current than Q3 allows, the output voltage drops to the battery voltage
or DPPM voltage, whichever is higher. If the DPPM threshold is reached first, the charge current is reduced until
VOUT stops dropping. If VOUT drops to the battery voltage, the battery is able to supplement the input current to
the system.
Dynamic Power-Path Management (DPPM)
The theory of operation is the same as described in CASE 1, except that Q3 restricts the amount of input current
delivered to the output and battery instead of the input supply.
Note that the DPPM voltage, V(DPPM), is programmed as follows:
V (DPPM) I (DPPM) R(DPPM) SF
(2)
where
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
Feature Plots
Figure 5 illustrates DPPM and battery supplement modes as the output current (IOUT) is increased; channel 1
(CH1) VAC = 5.4 V; channel 2 (CH2) VOUT; channel 3 (CH3) IOUT = 0 to 2.2 A to 0 A; channel 4 (CH4) VBAT = 3.5
V; I(PGM-CHG) = 1 A. In typical operation, bq24032 (VOUT = 4.4 Vreg), through an AC adaptor overload condition and
recovery. The AC input is set for ~5.1 V (1.5 A current limit), I(CHG) = 1 A, V(DPPM-SET) = 3.7 V, V(DPPM-OUT) = 1.15 ×
V(DPPM-SET) = 4.26 V, VBAT = 3.5 V, PSEL = H, and USB input is not connected. The output load is increased from
15
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
0 A to ~2.2 A and back to 0 A as shown in the bottom waveform. As the IOUT load reaches 0.5 A, along with the
1-A charge current, the adaptor starts to current limit, the output voltage drops to the DPPM-OUT threshold of
4.26 V. This is DPPM mode. The AC input tracks the output voltage by the dropout voltage of the AC FET. The
battery charge current is then adjusted back as necessary to keep the output voltage from falling any further.
Once the output load current exceeds the input current, the battery has to supplement the excess current and the
output voltage falls just below the battery voltage by the dropout voltage of the battery FET. This is the battery
supplement mode. When the output load current is reduced, the operation described is reversed as shown. If the
DPPM-OUT voltage was set below the battery voltage, during input current limiting, the output falls directly to the
battery's voltage.
Under USB operation, when the loads exceeds the programmed input current thresholds a similar pattern is
observed. If the output load exceeds the available USB current, the output instantly goes into the battery
supplement mode.
VAC
VOUT
VOUT Reg. @ 4.4 V (bq24032)
VDPPM − OUT = 4.26 V, DPPM Mode
VOUT VBAT, BAT Supplement Mode
ICHG
IOUT
Figure 5. DPPM and Battery Supplement Modes
Figure 6 illustrates when PSEL is toggled low for 500 µs. Power transfers from AC to USB to AC; channel 1
(CH1) VAC = 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel
4 (CH4) VBAT = 3.5 V; and I(PGM-CHG) = 1 A. When the PSEL went low (1st div), the AC FET opened, and the
output fell until the USB FET turned on. Turning off the active source before turning on the replacement source is
referred to as break-before-make switching. The rate of discharge on the output is a function of system
capacitance and load. Note the cable IR drop in the AC and USB inputs when they are under load. At the 4th
division, the output has reached steady-state operation at the DPPM voltage level (charge current has been
reduced due to the limited USB input current). At the 6th division, the PSEL goes high and the USB FET turns off
followed by the AC FET turning on. The output returns to its regulated value, and the battery returns to its
programmed current level.
16
bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
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SLUS618C – AUGUST 2004 – REVISED JUNE 2005
Break Before Make
VAC
VUSB
VOUT
System Capacitance
Powering System
VBAT
DPPM Mode
USB is Charging System Capacitance
Hi
PSEL
Low
Figure 6. Toggle PSEL Low
Figure 7 illustrates when AC is removed, power transfers to USB; PSEL = H (AC primary source); channel 1
(CH1) VAC = 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel
4 (CH4) VBAT = 3.5 V; and I(PGM-CHG) = 1 A. The power transfer from AC to USB only takes place after the primary
source (AC) is considered bad (too low, VAC<=VBAT + 125 mV) indicated by the ACPG FET turning off (open
drain not shown). Thus, the output drops down to the battery voltage before the USB source is connected (6th
div). The output starts to recover when the USB FET starts to limit the input current (7th div) and the output drops
to the DPPM voltage threshold.
USB Input Current Limit is Reached.
DPPM Mode
VUSB
VOUT
VAC
VBAT
AC Declared Not Present, USB Power Applied
Figure 7. Remove AC – PWR XFER to USB
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SLUS618C – AUGUST 2004 – REVISED JUNE 2005
Figure 8 illustrates when AC (low battery) is removed, power transfers to USB; PSEL = H; channel 1 (CH1) VAC
= 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4)
VBAT = 2.25 V; and I(PGM-CHG) = 1 A. This figure is the same as where the battery has more capacity. Note that
the output drops to the battery voltage before switching to USB power. A resistor divider between AC and ground
tied to PSEL can toggle the power transfer earlier if necessary.
VUSB
VOUT
DPPM Mode
VAC
VBAT
Figure 8. Remove AC (Low Battery) – PWR XFER to USB
Figure 9 illustrates when AC is applied, power transfers from USB to AC; PSEL = H; channel 1 (CH1) VAC = 5.4
V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT =
3.5 V; and I(PGM-CHG) = 1 A. The charger is set for AC priority but is running off USB until AC is applied. When AC
is applied (1st div) and the USB FET opens (2nd div), the AC FET closes (3rd div) and the output recovers from
the DPPM threshold (8th div).
VAC
VUSB
VOUT
VBAT
Break Before Make
VOUT Returns to Regulation (4.4 V, bq24032)
Charging Current Returns to Ipgm
DPPM Mode
Figure 9. Apply AC – PWR XFER From USB to AC
Figure 10 illustrates when USB is removed, power transfers from USB to AC; PSEL = L; channel 1 (CH1) VAC =
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SLUS618C – AUGUST 2004 – REVISED JUNE 2005
5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT
= 3.5 V; and I(PGM-CHG) = 1 A. The USB source is removed (2nd div) and the output drops to the battery voltage
(declares USB bad, 4th div) and switches to AC (in USB mode) and recovers similar to the figure that is switching
to USB power. This power transfer occurred with PSEL low, which means that the AC input is regulated as if it
were a USB.
AC is Applied (USB Mode)
VAC
AC Hits USB (ISET2) limit
DPPM Mode
VOUT
VUSB
VBAT
USB Declared not Present
Figure 10. Remove USB – PWR XFER From USB to AC
Figure 11 illustrates when the battery is absent, power transfers to USB; PSEL = H; channel 1 (CH1) VAC = 5.4
V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT;
I(PGM-CHG) = 1 A. Note the saw-tooth waveform due to cycling between charge done and refresh (new charge).
VAC
VUSB
VOUT
VBAT
BAT PIN Capacitance Discharging to Refresh Threshold
Charging (Step) Followed by Charge Done
Figure 11. Battery Absent – PWR XFER to USB
19
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Figure 12 illustrates when a battery is inserted for power up; channel 1 (CH1) VAC = 0 V; channel 2 (CH2) VUSB
= 0 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A for VOUT > 2 V; channel 4 (CH4) VBAT = 3.5 V; C(DPPM)
= 0 pF. When there are no power sources and the battery is inserted, the output tracks the battery voltage if
there is no load (<10 mA of load) on the output, as shown. If a load is present that keeps the output more than
200 mV below the battery, a short-circuit condition is declared. At this time, the load has to be removed to
recover. A capacitor can be placed on the DPPM pin to delay implementing the short-circuit mode and get
unrestricted (not limited) current.
VBAT
VOUT
Figure 12. Insert Battery – Power-Up Output via BAT
Figure 13 illustrates USB bootup and power-up via USB; channel 1 (CH1) V(USH) = 0 to 5 V; channel 2 (CH2)
USB input current (0.2 A/div); PSEL = Low; CE = High; ISET2 = High; VBAT = 3.85 V; V(DPPM) = 3.0 V (V(DPPM) ×
1.15 < VBAT, otherwise DPPM mode increases time duration). When a USB source is applied (if AC is not
present), the CE pin and ISET2 pin are ignored during the boot-up time and a maximum input current of 100 mA
is made available to the OUT or BAT pins. After the boot-up time, the IC implements the CE and ISET2 pins as
programmed.
20
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bq24032A, bq24035, bq24038, bq24039
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SLUS618C – AUGUST 2004 – REVISED JUNE 2005
VUSB
IUSB
Figure 13. USB Boot-Up Power-Up
Battery Temperature Monitoring
The bqTINY-III continuously monitors battery temperature by measuring the voltage between the TS and VSS
pins. An internal current source provides the bias for most-common 10 kΩ negative-temperature coefficient
thermistors (NTC) (see Figure 14). The device compares the voltage on the TS pin against the internal V(LTF) and
V(HTF) thresholds to determine if charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds
is detected, the device immediately suspends the charge. The device suspends charge by turning off the power
FET and holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to
the normal range. The allowed temperature range for 103AT-type thermistor is 0°C to 45°C. However, the user
may increase the range by adding two external resistors. See Figure 15.
PACK+
bqTINYIII
TS
VLTF
HTF
PACK−
TS
NTC
9
LTF
+
ITS
PACK−
ITS
PACK+
bqTINYIII
+
LTF
BATTERY
PACK
RT1 TEMP
VLTF
RT2
HTF
VHTF
9
NTC
BATTERY
PACK
VHTF
UDG−04086
UDG−04085
Figure 14. TS Pin Configuration
Figure 15. TS Pin Thresholds
Battery Pre-Conditioning
During a charge cycle, if the battery voltage is below the V(LOWV) threshold, the bqTINY-III applies a precharge
current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor connected between
the ISET1 and VSS, RSET, determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in
the specifications table. Note that this applies to both AC and USB charging.
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I O (PRECHG) V(PRECHG) K(SET)
RSET
(3)
The bqTINY-III activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not
reached within the timer period, the bqTINY-III turns off the charger and enunciates FAULT on the STAT1 and
STAT2 pins. The timeout is extended if the charge current is reduced by DPPM. See the Timer Fault Recovery
section for additional details.
Battery Charge Current
The bqTINY-III offers on-chip current regulation with programmable set point. The resistor connected between
the ISET1 and VSS, RSET, determines the charge level. The charge level may be reduced to give the system
priority on input current (see DPPM). The V(SET) and K(SET) parameters are specified in the specifications table.
V(SET) K(SET)
I O (OUT) RSET
(4)
When powered from a USB port, the input current available (0.1 A/0.5 A) is typically less than the programmed
(ISET1) charging current, and therefore, the DPPM feature attempts to keep the output from being pulled down
by reducing the charging current.
For the bq24032/2A/8 the charge level, during AC operation only (PSEL = High), can be changed by a factor of 2
by setting the ISET2 pin high (full charge) or low (half charge). The voltage on the ISET1 pin, VSET1, is divided
by 2 when in the half constant current charge mode. Note that with PSEL low, the ISET2 pin controls only the
0.1 A/0.5 A USB current level.
See the section titled Power-Path Management for additional details.
Battery Voltage Regulation
The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the
battery pack. The bqTINY-III monitors the battery-pack voltage between the BAT and VSS pins. When the
battery voltage rises to the VO(REG) threshold, the voltage regulation phase begins and the charging current
begins to taper down.
If the battery is absent, the BAT pin cycles between charge done (VO(REG)) and charging (battery refresh
threshold, ~4.1 V). See Figure 11.
See Figure 12 for power up by battery insertion.
As a safety backup, the bqTINY-III also monitors the charge time in the charge mode. If charge is not terminated
within this time period, t(CHG), the bqTINY-III turns off the charger and enunciates FAULT on the STAT1 and
STAT2 pins. See the DPPM operation under Case 1 for information on extending the safety timer during DPPM
operation. See theTimer Fault Recovery section for additional details.
Power Handoff
The design goal of the IC is to keep the system powered at all times (OUT pin), first by either input, AC or USB,
priority chosen by PSEL (PSEL feature set high internally on bq24039), and lastly by the battery. The input
power source is only considered present if its power-good status is low. There is a break-before-make switching
action when switching between AC to USB or USB to AC, for tSW-AC/USB, where the system capacitance should
hold up the system voltage. Note that the transfer of power occurs when the sources power-good pin goes high
(open-drain output high = power not present), which is when the input source drops to the battery's voltage. If the
battery is below a useable voltage, the system may reset. Typically, prior to losing the input power, the battery
would have some useable capacity, and a system reset would be avoided. If the battery was dead or missing,
the system would lose power unless the PSEL pin was used to transfer power prior to shutdown.
If this is a concern, there is a simple external solution. Externally toggling the PSEL (bq24030/1/2/2A/5/8) pin
immediately starts the power-transfer process (does not wait for input to drop to the battery's voltage). This can
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bq24032A, bq24035, bq24038, bq24039
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SLUS618C – AUGUST 2004 – REVISED JUNE 2005
be implemented by a resistor divider between the AC input and ground with the PSEL pin tied between R1 (top
resistor) and R2 (resistor to ground). The resistor values are chosen such that the divider voltage will be at 1 V
(PSEL threshold) when the AC has dropped to its critical voltage (user defined). An internal ~280-kΩ resistor is
applied when PSEL < 1 V, to provide hysteresis. Choose R2 between 10 kΩ and 60 kΩ and V(ac-critical) between
3.5 V and 4.5 V. R1 can be found using the following equation:
R1 = R2 (V(ac-critical) – 1 V); V(ac-reset) = 1 + R1 (R2+280 k)/(280 k × R2);
Example: If R2 = 30 kΩ and V(ac-critical) = 4 V; R1 = 30 kΩ(4 V – 1 V) = 90 kΩ, V(ac-reset) = 1+ 90k (30 k+280
k)/(280 k×30 k) = 4.32 V. Therefore, for a 90 kΩ/30 kΩ divider, the bias on PSEL would switch power from AC to
USB (USBPG = L) when the VAC dropped to 4 V (independent of VBAT) and switches back when the VAC
recovers to 4.32 V. See Figure 6 through Figure 10.
Temperature Regulation and Thermal Protection
In order to maximize charge rate, the bqTINY-III features a junction temperature regulation loop. If the power
dissipation of the IC results in a junction temperature greater than the TJ(REG) threshold, the bqTINY-III throttles
back on the charge current in order to maintain a junction temperature around the TJ(REG) threshold. To avoid
false termination, the termination detect function is disabled while in this mode.
The bqTINY-III also monitors the junction temperature, TJ, of the die and disconnects the OUT pin from AC or
USB inputs if TJ exceeds T(SHTDWN). This operation continues until TJ falls below T(SHTDWN) by the hysteresis level
specified in the specification table.
The battery supplement mode has no thermal protection. The Q2 FET continues to connect the battery to the
output (system), if input power is not sufficient; however, a short-circuit protection circuit limits the battery
discharge current such that the maximum power dissipation of the part is not exceeded under typical design
conditions.
Charge Timer Operation
As a safety backup, the bqTINY-III monitors the charge time in the charge mode. If the termination threshold is
not detected within the time period, t(CHG), the bqTINY-III turns off the charger and enunciates FAULT on the
STAT1 and STAT2 pins. The resistor connected between the TMR and VSS, RTMR, determines the timer period.
The K(TMR) parameter is specified in the specifications table. In order to disable the charge timer, eliminate RTMR,
connect the TMR pin directly to the LDO pin. Note that this action eliminates all safety timers, disables
termination, and also clears any timer fault. TMR pin should not be left floating.
t (CHG) K(TMR) R(TMR)
(5)
While in the thermal regulation mode or DPPM mode, the bqTINY-III dynamically adjusts the timer period in order
to provide the additional time needed to fully charge the battery. This proprietary feature is designed to prevent
against early or false termination. The maximum charge time in this mode, t(CHG-TREG), is calculated by
Equation 6.
t (CHG) V(SET)
t (CHGTREG) V (SETREG)
(6)
Note that because this adjustment is dynamic and changes as the ambient temperature changes and the charge
level changes, the timer clock is adjusted. It is difficult to estimate a total safety time without integrating the
above equation over the charge cycle. Therefore, understanding the theory that the safety time is adjusted
inversely proportionately with the charge current and the battery is a current-hour rating, the safety time
dynamically adjusts appropriately.
The V(SET) parameter is specified in the specifications table. V(SET-TREG) is the voltage on the ISET pin during the
thermal regulation or DPPM mode and is a function of charge current. (Note that charge current is dynamically
adjusted during the thermal regulation or DPPM mode.)
I (OUT) R(SET)
V (SETTREG) K(SET)
(7)
All deglitch times also adjusted proportionally to t(CHG-TREG).
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Charge Termination and Recharge
The bqTINY-III monitors the voltage on the ISET1 pin, during voltage regulation, to determine when termination
should occur (C/10 – 250 mV, C/25 – 100 mV). Once the termination threshold, I(TERM), is detected the bqTINY-III
terminates charge. The resistor connected between the ISET1 and VSS, RSET, programs the fast charge current
level (C level, VISET1 = 2.5 V) and thus the C/10 and C/25 current termination threshold levels. The V(TERM) and
K(SET) parameters are specified in the specifications table. Note that this applies to both AC and USB charging.
V(TERM) K(SET)
I (TERM) R SET
(8)
After charge termination, the bqTINY-III re-starts the charge once the voltage on the OUT pin falls below the
V(RCH) threshold. This feature keeps the battery at full capacity at all times.
LDO Regulator
The bqTINY-III provides a 3.3-V LDO regulator. This regulator is typically used to power USB transceiver or
drivers in portable applications. Note that this LDO is only enabled when either AC or USB inputs are present. If
the CE pin is low (chip disabled) and AC or USB is present, the LDO is powered by the battery. This is to ensure
low input current when the chip is disabled.
Sleep and Standby Modes
The bqTINY-III charger circuitry enters the low-power sleep mode if both AC and USB are removed from the
circuit. This feature prevents draining the battery into the bqTINY-III during the absence of input supplies. Note
that in sleep mode, Q2 remains on (i.e., battery connected to the OUT pin) in order for the battery to continue
supplying power to the system.
The bqTINY-III enters the low-power standby mode if while AC or USB is present, the CE input is low. In this
suspend mode, internal power FETs Q1 and Q3 (see the block diagram) are turned off, the BAT input is used to
power the system through OUT pin, and the LDO remains on (powered from output). This feature is designed to
limit the power drawn from the input supplies (such as USB suspend mode).
Charge Status Outputs
The open-drain (OD) STAT1 and STAT2 outputs indicate various charger operations as shown in Table 2. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off. Note that this assumes CE = High.
Table 2. Status Pins Summary
CHARGE STATE
STAT1
Precharge in progress
ON
STAT2
ON
Fast charge in progress
ON
OFF
Charge done
OFF
ON
Charge suspend (temperature), timer fault, and sleep mode
OFF
OFF
ACPG, USBPG Outputs (Power Good), bq24030/1/2/2A/5/9
The two open-drain pins, ACPG, USBPG (AC and USB power good), indicate when the AC adapter or USB port
is present and above the battery voltage. The corresponding output turns ON (low) when exiting sleep mode
(input voltage above battery voltage). This output is turned off in the sleep mode (open drain). The ACPG,
USBPG pins can be used to drive an LED or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off.
PG Output (Power Good), bq24038
The open-drain pin PG indicates when either the AC adapter or USB port is present and above the battery
voltage. This output is turned off in sleep mode (open drain). The PG pin can be used to drive a LED or
communicate with the host processor.
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CE Input (Chip Enable)
The CE (chip enable) digital input is used to disable or enable the IC. A high-level signal on this pin enables the
chip, and a low-level signal disables the device and initiates the standby mode. The bqTINY-III enters the
low-power standby mode when the CE input is low with either AC or USB present. In this suspend mode, internal
power FETs Q1 and Q3 (see block diagram) are turned off; the battery (BAT pin) is used to power the system via
Q2 and the OUT pin which also powers the LDO. This feature is designed to limit the power drawn from the input
supplies (such as USB suspend mode).
VBSEL INput (Battery Voltage Selection), bq24038
The VBSEL (battery voltage select) digital input pin can be used to set the charge voltage to 4.2 V typical
(VBSEL = low) or 4.36 V typical (VBSEL = high). If VBSEL is left open, an internal current source pulldown
ensures that the charge voltage is set to 4.2 V typical.
Charge Disable Functions
The DPPM input can be used to disable the charge process. This can be accomplished by floating the DPPM
mode. Note that this applies to both AC and USB charging.
Timer Fault Recovery
As shown in Figure 3, bqTINY-III provides a recovery method to deal with timer fault conditions. The following
summarizes this method:
Condition 1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs.
Recovery Method: bqTINY-III waits for the battery voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge, or battery removal. Once the battery falls below the
recharge threshold, the bqTINY-III clears the fault and starts a new charge cycle. A POR or CE toggle also clears
the fault.
Condition 2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs.
Recovery Method: Under this scenario, the bqTINY-III applies the I(FAULT) current. This small current is used to
detect a battery removal condition and remains on as long as the battery voltage stays below the recharge
threshold. If the battery voltage goes above the recharge threshold, then the bqTINY-III disables the I(FAULT)
current and executes the recovery method described for condition 1. Once the battery falls below the recharge
threshold, the bqTINY-III clears the fault and starts a new charge cycle. A POR or CE toggle also clears the fault.
Short-Circuit Recovery
The output can experience two types of short-circuit protection, one associated with the input and one with the
battery.
If the output drops below ~1 V, an input short-circuit condition is declared and the input FETs (AC and USB) are
turned off. To recover from this state, a 500-Ω pullup resistor from each input is applied (switched) to the output.
To recover, the load on the output has to be reduced {Rload > 1 V × 500 Ω/ (Vin–Vout)} such that the pullup
resistor is able to lift the output voltage above 1 V, for the input FETs to be turned back on.
If the output drops 200 mV below the battery voltage, the battery FET is considered in short circuit and the
battery FET turns off. To recover from this state, there is a 10-mA current source from the battery to the output.
Once the output load is reduced, such that the 10-mA current source can pick up the output within 200 mV of the
battery, the FET turns back on.
If the short is removed, and the minimum system load is still too large [R<(VBat-200 nV) / 10 mA], the
short-circuit protection can be temporarily defeated. The battery short-circuit protection can be disabled
(recommended only for a short time) if the voltage on the DPPM pin is less than 1 V. Pulsing this pin below 1 V,
for a few microseconds, should be enough to recover.
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This short-circuit disable feature was implemented mainly for power up when inserting a battery. Because the
BAT input voltage rises much faster than the OUT voltage (Vout<Vbat-200 mV), with most any capacitive load on
the output, the part can get stuck in short-circuit mode. Placing a capacitor between the DPPM pin and ground
slows the VDPPM rise time, during power up, and delays the short-circuit protection. Too large a capacitance on
this pin (too much of a delay) could allow too-high currents if the output was shorted to ground. The
recommended capacitance is 1 nF to 10 nF. The VDPPM rise time is a function of the 100-µA DPPM current
source, the DPPM resistor, and the capacitor added.
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bq24032A, bq24035, bq24038, bq24039
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SLUS618C – AUGUST 2004 – REVISED JUNE 2005
APPLICATION INFORMATION
Selecting the Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on each input (AC and USB). A
0.1-µF ceramic capacitor, placed in close proximity to AC and USB to VSS pins, works well. In some applications
depending on the power supply characteristics and cable length, it may be necessary to add an additional 10-µF
ceramic capacitor to each input.
The bqTINY-III only requires a small output capacitor for loop stability. A 0.1-µF ceramic capacitor placed
between the OUT and VSS pin is typically sufficient.
The integrated LDO requires a maximum of 1-µF ceramic capacitor on its output. The output does not require a
capacitor for a steady-state load but a 0.1-µF minimum capacitance is recommended.
It is recommended to install a minimum of 33-µF capacitor between the BAT pin and VSS (in parallel with the
battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).
Thermal Considerations
The bqTINY-III is packaged in a thermally enhanced MLP package. The package includes a QFN thermal pad to
provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment (SLUA271).
The power pad should be tied to the VSS plane. The most common measure of package thermal performance is
thermal impedance (θJA) measured (or modeled) from the chip junction to the air surrounding the package
surface (ambient).
The mathematical expression for θJA is:
T TA
JA J
P
(9)
where
TJ = chip junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• whether or not the device is board mounted
• trace size, composition, thickness, and geometry
• orientation of the device (horizontal or vertical)
• volume of the ambient air surrounding the device under test and airflow
• whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from Equation 10:
P V IN V OUT I OUT I BAT V OUT VBAT I BAT
(10)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 1. Typically the Li-ion battery's voltage
quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery
above 3 V). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the minimum
battery voltage because the system board and charging device does not have time to reach a maximum
temperature due to the thermal mass of the assembly during the early stages of fast charge. This theory is easily
verified by performing a charge cycle on a discharged battery while monitoring the battery voltage and chargers
power pad temperature.
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SLUS618C – AUGUST 2004 – REVISED JUNE 2005
APPLICATION INFORMATION (continued)
PCB Layout Considerations
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from input terminals to VSS and the output filter
capacitors from OUT to VSS should be placed as close as possible to the bqTINY-II, with short trace runs to
both signal and VSS pins.
• All low-current VSS connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
• The high-current charge paths into AC and USB and from the BAT and OUT pins must be sized
appropriately for the maximum charge current in order to avoid voltage drops in these traces.
• The bqTINY-III is packaged in a thermally enhanced MLP package. The package includes a QFN thermal
pad to provide an effective thermal contact between the device and the printed-circuit board. Full PCB design
guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment
(SLUA271).
28
PACKAGE OPTION ADDENDUM
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8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24030RHLR
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24030RHLRG4
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24032ARHLR
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24032ARHLRG4
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24032ARHLT
ACTIVE
QFN
RHL
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24032RHLR
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24032RHLRG4
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24035RHLR
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24035RHLRG4
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24038RHLR
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24038RHLT
ACTIVE
QFN
RHL
20
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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information may not be available for release.
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to Customer on an annual basis.
Addendum-Page 1
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