AGERE DSP1629

Data Sheet
March 2000
DSP1629 Digital Signal Processor
1 Features
■
Optimized for digital cellular applications with a bit
manipulation unit for higher coding efficiency.
■
On-chip, programmable, PLL clock synthesizer.
■
10 ns and 16.7 ns instruction cycle times at 3.0 V, and
19.2 ns and 12.5 ns instruction cycle times at 2.7 V,
respectively.
■
Mask-programmable memory map option: The
DSP1629x16 features 16 Kwords on-chip dual-port
RAM. The DSP1629x10 features 10 Kwords on-chip
dual-port RAM. Both feature 48 Kwords on-chip ROM
with a secure option.
■
Low power consumption:
— <1.9 mW/MIPS typical at 2.7 V.
■
Flexible power management modes:
— Standard sleep: 0.2 mW/MIPS at 2.7 V.
— Sleep with slow internal clock: 0.7 mW at 2.7 V.
— Hardware STOP (pin halts DSP): <20 µA.
■
Mask-programmable clock options: small signal, and
CMOS.
■
144 PBGA package (13 mm x 13 mm) available.
■
Sequenced accesses to X and Y external memory.
■
Object code and pin compatible with the DSP1627.
■
Single-cycle squaring.
■
16 x 16-bit multiplication and 36-bit accumulation in
one instruction cycle.
■
Instruction cache for high-speed, program-efficient,
zero-overhead looping.
■
Dual 25 Mbits/s serial I/O ports with multiprocessor
capability:
— 16-bit data channel, 8-bit protocol channel.
■
8-bit parallel host interface:
— Supports 8- or 16-bit transfers.
— Motorola* or Intel † compatible.
■
8-bit control I/O interface.
■
256 memory-mapped I/O ports.
■
IEEE ‡ P1149.1 test port (JTAG boundary scan).
* Motorola is a registered trademark of Motorola, Inc.
† Intel is a registered trademark of Intel Corporation.
‡ IEEE is a registered trademark of The Institute of Electrical
and Electronics Engineers, Inc.
■
Full-speed in-circuit emulation hardware development system on-chip.
■
Supported by DSP1629 software and hardware
development tools.
2 Description
The DSP1629 is Lucent Technologies Microelectronics
Group’s first digital signal processor offering 100 MIPS
operation at 3.0 V and 80 MIPS operation at 2.7 V with a
reduction in power consumption. Designed specifically
for applications requiring low power dissipation in digital
cellular systems, the DSP1629 is a signal-coding device
that can be programmed to perform a wide variety of
fixed-point signal processing functions. The device is
based on the DSP1600 core with a bit manipulation unit
for enhanced signal coding efficiency. The DSP1629 includes a mix of peripherals specifically intended to support processing-intensive but cost-sensitive applications
in the area of digital wireless communications.
The DSP1629x16 contains 16 Kwords of internal dualport RAM (DPRAM), which allows simultaneous access
to two RAM locations in a single instruction cycle. The
DSP1629x10 supports the use of 10 Kwords of DPRAM.
Both devices contain 48 Kwords of internal ROM (IROM).
The DSP1629 is object code compatible with the
DSP1627 while providing more memory. The DSP1629 is
pin compatible with the DSP1627. Note that TRST (JTAG
test reset) replaces a VDD pin.
The DSP1629 supports 2.7 V, and 3.0 V operation and
flexible power management modes required for portable
cellular terminals. Several control mechanisms achieve
low-power operation, including a STOP pin for placing the
DSP into a fully static, halted state and a programmable
power control register used to power down unused onchip I/O units. These power management modes allow
for trade-offs between power reduction and wake-up latency requirements. During system standby, power consumption is reduced to less than 20 µA.
The on-chip clock synthesizer can be driven by an external clock whose frequency is a fraction of the instruction
rate.
The device is packaged in a 144-pin PBGA, a 100-pin
BQFP, or a 100-pin TQFP and is available with 10 ns and
16.7 ns instruction cycle times at 3.0 V, and 19.2 ns and
12.5 ns instruction cycle times at 2.7 V, respectively.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
Table of Contents
Contents
1
2
3
4
5
6
7
8
2
Page
Features.............................................................. 1
Description .......................................................... 1
Pin Information.................................................... 3
Hardware Architecture ........................................ 8
4.1
DSP1629 Architectural Overview ............. 8
4.2
DSP1600 Core Architectural Overview .. 11
4.3
Interrupts and Trap ................................. 12
4.4
Memory Maps and Wait-States .............. 17
4.5
External Memory Interface (EMI)............ 20
4.6
Bit Manipulation Unit (BMU) ................... 21
4.7
Serial I/O Units (SIOs) ............................ 21
4.8
Parallel Host Interface (PHIF)................. 23
4.9
Bit Input/Output Unit (BIO)...................... 24
4.10 Timer ...................................................... 25
4.11 JTAG Test Port....................................... 25
4.12 Clock Synthesis ...................................... 27
4.13 Power Management ............................... 30
Software Architecture ....................................... 37
5.1
Instruction Set......................................... 37
5.2
Register Settings .................................... 46
5.3
Instruction Set Formats .......................... 56
Signal Descriptions ........................................... 62
6.1
System Interface..................................... 62
6.2
External Memory Interface ..................... 64
6.3
Serial Interface #1 .................................. 65
6.4
Parallel Host Interface or Serial
Interface #2 and Control I/O Interface .... 66
6.5
Control I/O Interface ............................... 66
6.6
JTAG Test Interface ............................... 67
Mask-Programmable Options ........................... 68
7.1
Input Clock Options ................................ 68
7.2
Memory Map Options ............................. 68
7.3
ROM Security Options............................ 68
Device Characteristics ...................................... 69
8.1
Absolute Maximum Ratings.................... 69
Contents
Page
8.2
Handling Precautions.............................. 69
8.3
Recommended Operating Conditions..... 69
8.4
Package Thermal Considerations........... 70
9 Electrical Characteristics and Requirements .... 71
9.1
Power Dissipation ................................... 74
10 Timing Characteristics for 3.0 V Operation ....... 76
10.1 DSP Clock Generation............................ 77
10.2 Reset Circuit ........................................... 78
10.3 Reset Synchronization............................ 79
10.4 JTAG I/O Specifications.......................... 80
10.5 Interrupt .................................................. 81
10.6 Bit Input/Output (BIO) ............................. 82
10.7 External Memory Interface...................... 83
10.8 PHIF Specifications ................................ 87
10.9 Serial I/O Specifications.......................... 93
10.10 Multiprocessor Communication .............. 98
11 Timing Characteristics for 2.7 V Operation ....... 99
11.1 DSP Clock Generation.......................... 100
11.2 Reset Circuit ......................................... 101
11.3 Reset Synchronization.......................... 102
11.4 JTAG I/O Specifications........................ 103
11.5 Interrupt ................................................ 104
11.6 Bit Input/Output (BIO) ........................... 105
11.7 External Memory Interface.................... 106
11.8 PHIF Specifications .............................. 110
11.9 Serial I/O Specifications........................ 116
11.10 Multiprocessor Communication ............ 121
12 Outline Diagrams ............................................ 122
12.1 100-Pin BQFP (Bumpered Quad
Flat Pack).............................................. 122
12.2 100-Pin TQFP (Thin Quad Flat
Pack)..................................................... 123
12.3 144-Pin PBGA (Plastic Ball Grid
Array) .................................................... 124
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
14
VSS
92
89
OLD1
93
DO1
OCK1
94
SYNC1
ICK1
95
90
ILD1
96
91
VSS
DI1
97
98
OBE1
IBF1
99
DB15
1
VDD
DB14
2
DB13
3
DB12
4
DB11
5
VSS
6
DB10
7
DB9
8
DB8
9
DB7
10
DB5
DB6
11
100
VSS
12
13
VDD
3 Pin Information
88
VDD
DB4
15
87
SADD1
DB3
16
86
DOEN1
DB2
17
85
OCK2/PCSN
DB1
18
84
DO2/PSTAT
DB0
19
83
SYNC2/PBSEL
ILD2/PIDS
PIN #1
IDENTIFIER
ZONE
IO
20
82
ERAMHI
21
81
OLD2/PODS
VDD
22
80
IBF2/PIBF
ERAMLO
23
79
OBE2/POBE
EROM
24
78
ICK2/PB0
RWN
VSS
25
77
DI2/PB1
26
76
VSS
EXM
27
75
DOEN2/PB2
AB15
AB14
28
74
SADD2/PB3
29
73
TRST
VDD
30
72
IOBIT0/PB4
AB13
31
71
IOBIT1/PB5
AB12
AB11
32
70
IOBIT2/PB6
33
69
IOBIT3/PB7
AB10
34
68
VEC3/IOBIT4
AB9
35
67
VEC2/IOBIT5
AB8
36
66
VEC1/IOBIT6
AB7
37
65
VEC0/IOBIT7
38
64
VSS
50
51
52
53
54
55
56
57
58
59
60
61
62
63
TRAP
RSTB
CKO
VDD
TCK
TMS
TDO
TDI
VDDA
CKI
CKI2
VSSA
49
VSS
IACK
48
INT0
STOP
47
44
AB2
INT1
43
AB3
46
42
AB4
45
41
AB5
AB0
40
AB1
39
VDD
AB6
VSS
DSP1629
5-4218 (F).c
Figure 1. DSP1629 BQFP Pin Diagram
Lucent Technologies Inc.
3
Data Sheet
March 2000
DSP1629 Digital Signal Processor
DB5
DB6
DB7
DB8
DB9
DB10
VSS
DB11
DB12
DB13
DB14
DB15
VDD
OBE1
IBF1
VSS
DI1
ILD1
ICK1
OCK1
OLD1
DO1
SYNC1
VSS
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
DB3
98
DB4
99
1
VDD
VSS
100
3 Pin Information (continued)
75
VDD
2
74
SADD1
3
73
DOEN1
DB2
4
72
OCK2/PCSN
DB1
5
71
DO2/PSTAT
DB0
6
70
SYNC2/PBSEL
IO
7
69
ILD2/PIDS
ERAMHI
8
68
OLD2/PODS
VDD
9
67
IBF2/PIBF
ERAMLO
10
66
OBE2/POBE
EROM
11
65
ICK2/PB0
RWN
12
64
DI2/PB1
VSS
13
63
VSS
DSP1629
48
49
50
CKI2
VSSA
TDO
CKI
45
TMS
47
44
TCK
TDI
43
VDD
VDDA
42
CKO
46
41
VSS
39
51
40
VEC0/IOBIT7
25
RSTB
24
VSS
TRAP
AB7
38
VEC1/IOBIT6
52
37
53
IACK
23
STOP
VEC2/IOBIT5
AB8
36
54
VSS
22
35
VEC3/IOBIT4
AB9
34
AB10
55
INT0
IOBIT3/PB7
21
INT1
IOBIT2/PB6
56
33
57
20
32
19
AB11
AB0
AB12
AB1
IOBIT1/PB5
31
58
AB2
18
29
IOBIT0/PB4
AB13
30
59
AB3
17
AB4
TRST
VDD
28
AB14
60
27
SADD2/PB3
16
AB5
DOEN2/PB2
61
AB6
62
15
26
14
VDD
EXM
AB15
5-4219 (F).c
Figure 2. DSP1629 TQFP Pin Diagram
4
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
3 Pin Information (continued)
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
G
VSS
H
VDD
J
VDDA
K
VSSA
SPARE PACKAGE BALLS
SHOULD BE TIED TO
"SOFT GND" OR "SIG GND"
L
M
5-5224 (C)
Note: Solder balls viewed through package.
Figure 3. 144-Pin Plastic Ball Grid Array (Top View)
Lucent Technologies Inc.
5
Data Sheet
March 2000
DSP1629 Digital Signal Processor
3 Pin Information (continued)
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. The functionality of CKI and CKI2
pins are mask-programmable (see Section 7, Mask-Programmable Options). Input levels on all I and I/O type pins
are designed to remain at full CMOS levels when not driven by the DSP.
Table 1. Pin Descriptions
PBGA Pin
BQFP Pin
TQFP Pin
B6, A6, B5, A5, 1, 2, 3, 4, 5, 88, 89, 90, 91,
B4, A4, B3, A3, 7, 8, 9, 10, 92, 94, 95, 96,
B2, A2, A1, B1, 11, 12, 15, 97, 98, 99, 2,
3, 4, 5, 6
C2, C1, C3, D1 16, 17, 18, 19
D2
20
7
E1
21
8
Symbol
DB[15:0]
Type
Name/Function
I/O* External Memory Data Bus 15—0.
IO
ERAMHI
O†
O†
E2
23
10
ERAMLO
O†
F1
F2
G1
G2, H1, H2, J1,
J2, K1, K2, L1,
L2, M1, K3, M2,
L3, M3, L4, M4
11
12
14
15, 16, 18, 19,
20, 21, 22, 23,
24, 27, 28, 29,
30, 31, 32, 33
EROM
RWN
EXM
AB[15:0]
O†
O†
I
O*
L5
M5
L6
M6
L7
M7
L8
M8
L9
M9
L10
24
25
27
28, 29, 31,
32, 33, 34,
35, 36, 37,
40, 41, 42,
43, 44, 45, 46
47
48
50
51
52
53
54
56
57
58
59
34
35
37
38
39
40
41
43
44
45
46
INT1
INT0
IACK
STOP
TRAP
RSTB
CKO
TCK
TMS
TDO
TDI
I
I
O*
I
I/O*
I
O†
I
I‡
O§
I‡
L11
M11
K10
L12
K11
K12
J11
J12
H11
H12
G11
61
62
65
66
67
68
69
70
71
72
73
48
49
52
53
54
55
56
57
58
59
60
CKI**
CKI2**
VEC0/IOBIT7
VEC1/IOBIT6
VEC2/IOBIT5
VEC3/IOBIT4
IOBIT3/PB7
IOBIT2/PB6
IOBIT1/PB5
IOBIT0/PB4
TRST
I
I
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I‡
Data Address 0x4000 to 0x40FF I/O Enable.
Data Address 0x8000 to 0xFFFF External RAM
Enable.
Data Address 0x4100 to 0x7FFF External RAM
Enable.
Program Address External ROM Enable.
Read/Write Not.
External ROM Enable.
External Memory Address Bus 15—0.
Vectored Interrupt 1.
Vectored Interrupt 0.
Interrupt Acknowledge.
STOP Input Clock.
Nonmaskable Program Trap/Breakpoint Indication.
Reset Bar.
Processor Clock Output.
JTAG Test Clock.
JTAG Test Mode Select.
JTAG Test Data Output.
JTAG Test Data Input.
Mask-Programmable Input Clock Option
CMOS
Small Signal
VAC
CKI
VCM
VSSA
Vectored Interrupt Indication 0/Status/Control Bit 7.
Vectored Interrupt Indication 1/Status/Control Bit 6.
Vectored Interrupt Indication 2/Status/Control Bit 5.
Vectored Interrupt Indication 3/Status/Control Bit 4.
Status/Control Bit 3/PHIF Data Bus Bit 7.
Status/Control Bit 2/PHIF Data Bus Bit 6.
Status/Control Bit 1/PHIF Data Bus Bit 5.
Status/Control Bit 0/PHIF Data Bus Bit 4.
JTAG Test Reset.
* 3-states when RSTB = 0, or by JTAG control.
† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running.
‡ Pull-up devices on input.
§ 3-states by JTAG control.
** See Section 7, Mask-Programmable Options.
†† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
6
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
3 Pin Information (continued)
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions.
Table 1. Pin Descriptions (continued)
PBGA Pin
G12
BQFP Pin
74
TQFP Pin
Symbol
Type
Name/Function
61
SADD2/PB3†† I/O* SIO2 Multiprocessor Address/PHIF
Data Bus Bit 3.
F11
75
62
DOEN2/PB2 I/O* SIO2 Data Output Enable/PHIF Data
Bus Bit 2.
F12
77
64
DI2/PB1
I/O* SIO2 Data Input/PHIF Data Bus Bit 1.
E11
78
65
ICK2/PB0
I/O* SIO2 Input Clock/PHIF Data Bus Bit 0.
E12
79
66
OBE2/POBE
O* SIO2 Output Buffer Empty/PHIF Output Buffer Empty.
D11
80
67
IBF2/PIBF
O* SIO2 Input Buffer Full/PHIF Input Buffer Full.
D12
81
68
OLD2/PODS I/O* SIO2 Output Load/PHIF Output Data
Strobe.
C11
82
69
ILD2/PIDS
I/O* SIO2 Input Load/PHIF Input Data
Strobe.
C12
83
70
SYNC2/PBSEL I/O* SIO2 Multiprocessor Synchronization/
PHIF Byte Select.
C10
84
71
DO2/PSTAT I/O* SIO2 Data Output/PHIF Status Register Select.
B12
85
72
OCK2/PCSN I/O* SIO2 Output Clock/PHIF Chip Select
Not.
B11
86
73
DOEN1
I/O* SIO1 Data Output Enable.
A12
87
74
I/O* SIO1 Multiprocessor Address.
SADD1††
A11
90
77
SYNC1
I/O* SIO1 Multiprocessor Synchronization.
B10
91
78
DO1
O* SIO1 Data Output.
A10
92
79
OLD1
I/O* SIO1 Output Load.
B9
93
80
OCK1
I/O* SIO1 Output Clock.
A9
94
81
ICK1
I/O* SIO1 Input Clock.
B8
95
82
ILD1
I/O* SIO1 Input Load.
A8
96
83
DI1
I SIO1 Data Input.
B7
98
85
IBF1
O* SIO1 Input Buffer Full.
A7
99
86
OBE1
O* SIO1 Output Buffer Empty.
6, 15, 26, 93, 1, 13,
VSS
P Ground.
D4, D5, D6, D7, D8, E4,
E5, E6, E7, E8, E9, F4, F5, 38, 49, 64, 25, 36, 51,
76, 89, 97 63, 76, 84
F6, F7, F8, F9, G4, G5,
G6, G7, G8, G9, H4, H5,
H6, H7, H8, H9, J4, J5, J6,
J7, J8, J9
VDD
C4, C5, C6, C7, C8, D3, 14, 22, 30, 100, 9, 17,
P Power Supply.
D9, D10, E3, E10, F3, F10, 39, 55, 88, 26, 42, 75,
100
87
G3, G10, H3, H10, J3, J10,
K4, K5, K6, K7, K8, K9
P Analog Power Supply.
M10
60
47
VDDA
M12
63
50
VSSA
P Analog Ground.
C9
—
—
—
— No Die Connect—unused.
* 3-states when RSTB = 0, or by JTAG control.
† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running.
‡ Pull-up devices on input.
§ 3-states by JTAG control.
** See Section 7, Mask-Programmable Options.
†† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
Lucent Technologies Inc.
7
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture
The DSP1629 device is a 16-bit, fixed-point programmable digital signal processor (DSP). The DSP1629
consists of a DSP1600 core together with on-chip memory and peripherals. Added architectural features give
the DSP1629 high program efficiency for signal coding
applications.
4.1 DSP1629 Architectural Overview
Figure 4 shows a block diagram of the DSP1629. The
following modules make up the DSP1629.
DSP1600 Core
The DSP1600 core is the heart of the DSP1629 chip.
The core contains data and address arithmetic units,
and control for on-chip memory and peripherals. The
core provides support for external memory wait-states
and on-chip, dual-port RAM and features vectored interrupts and a trap mechanism.
DSP1600 core automatically controls the EMUX. Instructions can transparently reference external memory
from either set of internal buses. A sequencer allows a
single instruction to access both the X and the Y external memory spaces.
Clock Synthesis
The DSP powers up with a 1X input clock (CKI/CKI2) as
the source for the processor clock. An on-chip clock
synthesizer (PLL) can also be used to generate the system clock for the DSP, which will run at a frequency multiple of the input clock. The clock synthesizer is
deselected and powered down on reset. For low-power
operation, an internally generated slow clock can be
used to drive the DSP. If both the clock synthesizer and
the internally generated slow clock are selected, the
slow clock will drive the DSP; however, the synthesizer
will continue to run.
The clock synthesizer and other programmable clock
sources are discussed in Section 4.12. The use of these
programmable clock sources for power management is
discussed in Section 4.13.
Dual-Port RAM (DPRAM)
Bit Manipulation Unit (BMU)
The DSP1629x16 contains 16 banks of zero wait-state
memory and the DSP1629x10 contains 10 banks of
zero wait-state memory. Each bank consists of 1K
16-bit words and has separate address and data ports
to the instruction/coefficient and data memory spaces.
A program can reference memory from either space.
The DSP1600 core automatically performs the required
multiplexing. If references to both ports of a single bank
are made simultaneously, the DSP1600 core automatically inserts a wait-state and performs the data port access first, followed by the instruction/coefficient port
access.
A program can be downloaded from slow, off-chip memory into DPRAM, and then executed without wait-states.
DPRAM is also useful for improving convolution performance in cases where the coefficients are adaptive.
Since DPRAM can be downloaded through the JTAG
port, full-speed remote in-circuit emulation is possible.
DPRAM can also be used for downloading self-test
code via the JTAG port.
The BMU extends the DSP1600 core instruction set to
provide more efficient bit operations on accumulators.
The BMU contains logic for barrel shifting, normalization, and bit field insertion/extraction. The unit also contains a set of 36-bit alternate accumulators. The data in
the alternate accumulators can be shuffled with the data
in the main accumulators. Flags returned by the BMU
mesh seamlessly with the DSP1600 conditional instructions.
Bit Input/Output (BIO)
The BIO provides convenient and efficient monitoring
and control of eight individually configurable pins. When
configured as outputs, the pins can be individually set,
cleared, or toggled. When configured as inputs, individual pins or combinations of pins can be tested for patterns. Flags returned by the BIO mesh seamlessly with
conditional instructions.
Serial Input/Output Units (SIO and SIO2)
Read-Only Memory (ROM)
The DSP1629 contains 48K 16-bit words of zero waitstate mask-programmable ROM for program and fixed
coefficients.
External Memory Multiplexer (EMUX)
The EMUX is used to connect the DSP1629 to external
memory and I/O devices. It supports read/write operations from/to instruction/coefficient memory (X memory
space) and data memory (Y memory space). The
8
SIO and SIO2 offer asynchronous, full-duplex, doublebuffered channels that operate at up to 25 Mbits/s (for
20 ns instruction cycle in a nonmultiprocessor configuration), and easily interface with other Lucent Technologies fixed-point DSPs in a multiple-processor
environment. Commercially available codecs and timedivision multiplex (TDM) channels can be interfaced to
the serial I/O ports with few, if any, additional components. SIO2 is identical to SIO.
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
An 8-bit serial protocol channel may be transmitted in addition to the address of the called processor in multiprocessor mode. This feature is useful for transmitting high-level framing information or for error detection and correction.
SIO2 and BIO are pin-multiplexed with the PHIF.
DB[15:0] AB[15:0]
RWN
I/O
EXM
EROM ERAMHI ERAMLO
JTAG
BOUNDARY SCAN *
EXTERNAL MEMORY INTERFACE & EMUX
ioc
DUAL-PORT
RAM
16K/10K x 16†
ROM
48K x 16
YAB
YDB
XDB
XAB
BMU
aa0
DSP1600 CORE
TDI
ID *
TCK
BYPASS *
TMS
HDS
TRST
TRACE *
ar0
TIMER
ar1
timerc
ar2
VEC[3:0] OR IOBIT[7:4]
timer0
ar3
SIO
PHIF
DO2 OR PSTAT
sdx(OUT)
phifc
OLD2 OR PODS
OCK2 OR PCSN
PSTAT *
OBE2 OR POBE
ILD2 OR PIDS
JCON *
aa1
IDB
ICK2 OR PB0
TDO
BREAKPOINT *
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
SYNC2 OR PBSEL
jtag
M
U
X
DI1
ICK1
ILD1
srta
powerc
pllc
SIO2
pdx0(IN)
tdms
sdx2(OUT)
pdx0(OUT)
DI2 OR PB1
sdx(IN)
BIO
sbit
IBF2 OR PIBF
cbit
DOEN2 OR PB2
SADD2 OR PB3
srta2
IBF1
DO1
OCK1
OLD1
OBE1
tdms2
sioc
sdx2(IN)
saddx
SYNC1
SADD1
DOEN1
sioc2
IO BIT[3:0] OR PB[7:4]
saddx2
5-4142 (F).f
* These registers are accessible through the pins only.
† 16K x 16 for the DSP1629x16, 10K x 16 for the DSP1629x10.
Figure 4. DSP1629 Block Diagram
Lucent Technologies Inc.
9
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Table 2. DSP1629 Block Diagram Legend
Symbol
aa<0—1>
ar<0—3>
BIO
BMU
BREAKPOINT
BYPASS
cbit
Dual-Port RAM
EMUX
HDS
ID
IDB
ioc
JCON
jtag
pdx0(in)
pdx0(out)
PHIF
phifc
pllc
powerc
PSTAT
saddx
saddx2
sbit
sdx(in)
sdx2(in)
sdx(out)
sdx2(out)
SIO
SIO2
sioc
sioc2
srta
srta2
tdms
tdms2
TIMER
timer0
timerc
TRACE
XAB
XDB
YAB
YDB
10
Name
Alternate Accumulators.
Auxiliary BMU Registers.
Bit Input/Output Unit.
Bit Manipulation Unit.
Four Instruction Breakpoint Registers.
JTAG Bypass Register.
Control Register for BIO.
Internal RAM (16 Kwords for DSP1629x16, 10 Kwords for DSP1629x10).
External Memory Multiplexer.
Hardware Development System.
JTAG Device Identification Register.
Internal Data Bus.
I/O Configuration Register.
JTAG Configuration Registers.
16-bit Serial/Parallel Register.
Parallel Data Transmit Input Register 0.
Parallel Data Transmit Output Register 0.
Parallel Host Interface.
Parallel Host Interface Control Register.
Phase-Locked Loop Control Register.
Power Control Register.
Parallel Host Interface Status Register.
Multiprocessor Protocol Register.
Multiprocessor Protocol Register for SIO2.
Status Register for BIO.
Serial Data Transmit Input Register.
Serial Data Transmit Input Register for SIO2.
Serial Data Transmit Output Register.
Serial Data Transmit Output Register for SIO2.
Serial Input/Output Unit.
Serial Input/Output Unit #2.
Serial I/O Control Register.
Serial I/O Control Register for SIO2.
Serial Receive/Transmit Address Register.
Serial Receive/Transmit Address Register for SIO2.
Serial I/O Time-division Multiplex Signal Control Register.
Serial I/O Time-division Multiplex Signal Control Register for SIO2.
Programmable Timer.
Timer Running Count Register.
Timer Control Register.
Program Discontinuity Trace Buffer.
Program Memory Address Bus.
Program Memory Data Bus.
Data Memory Address Bus.
Data Memory Data Bus.
Lucent Technologies Inc.
Data Sheet
March 2000
4 Hardware Architecture (continued)
Parallel Host Interface (PHIF)
The PHIF is a passive, 8-bit parallel port which can interface to an 8-bit bus containing other Lucent Technologies DSPs (e.g., DSP1620, DSP1627, DSP1628,
DSP1629, DSP1611, DSP1616, DSP1617, DSP1618),
microprocessors, or peripheral I/O devices. The PHIF
port supports either Motorola or Intel protocols, as well
as 8-bit or 16-bit transfers, configured in software. The
port data rate depends upon the instruction cycle rate.
A 25 ns instruction cycle allows the PHIF to support
data rates up to 11.85 Mbytes/s, assuming the external
host device can transfer 1 byte of data in 25 ns.
The PHIF is accessed in two basic modes: 8-bit or
16-bit mode. In 16-bit mode, the host determines an access of the high or low byte. In 8-bit mode, only the low
byte is accessed. Software-programmable features allow for a glueless host interface to microprocessors
(see Section 4.8, Parallel Host Interface).
DSP1629 Digital Signal Processor
In systems with multiple processors, the processors
may be configured such that any processor reaching a
breakpoint will cause all the other processors to be
trapped (see Section 4.3, Interrupts and Trap).
Pin Multiplexing
In order to allow flexible device interfacing while maintaining a low package pin count, the DSP1629 multiplexes 16 package pins between BIO, PHIF, VEC[3:0],
and SIO2.
Upon reset, the vectored interrupt indication signals,
VEC[3:0], are connected to the package pins while
IOBIT[4:7] are disconnected. Setting bit 12, EBIOH, of
the ioc register connects IOBIT[4:7] to the package pins
and disconnects VEC[3:0].
Upon reset, the parallel host interface (PHIF) is connected to the package pins while the second serial port
(SIO2) and IOBIT[3:0] are disconnected. Setting bit 10,
ESIO2, of the ioc register connects the SIO2 and
IOBIT[3:0] and disconnects the PHIF.
Timer
Power Management
The timer can be used to provide an interrupt at the expiration of a programmed interval. The interrupt may be
single or repetitive. More than nine orders of magnitude
of interval selection are provided. The timer may be
stopped and restarted at any time.
Many applications, such as portable cellular terminals,
require programmable sleep modes for power management. There are three different control mechanisms for
achieving low-power operation: the powerc control
register, the STOP pin, and the AWAIT bit in the alf register. The AWAIT bit in the alf register allows the processor to go into a power-saving standby mode until an
interrupt occurs. The powerc register configures various
power-saving modes by controlling internal clocks and
peripheral I/O units. The STOP pin controls the internal
processor clock. The various power management options may be chosen based on power consumption and/
or wake-up latency requirements.
Hardware Development System (HDS) Module
The on-chip HDS performs instruction breakpointing
and branch tracing at full speed without additional offchip hardware. Using the JTAG port, the breakpointing
is set up, and the trace history is read back. The port
works in conjunction with the HDS code in the on-chip
ROM and the hardware and software in a remote computer. The HDS code must be linked to the user's application code and reside in the first 4 Kwords of ROM.
The on-chip HDS cannot be used with the secure ROM
masking option (see Section 7.3, ROM Security Options).
Four hardware breakpoints can be set on instruction addresses. A counter can be preset with the number of
breakpoints to receive before trapping the core. Breakpoints can be set in interrupt service routines. Alternately, the counter can be preset with the number of cache
instructions to execute before trapping the core.
Every time the program branches instead of executing
the next sequential instruction, the addresses of the instructions executed before and after the branch are
caught in circular memory. The memory contains the
last four pairs of program discontinuities for hardware
tracing.
Lucent Technologies Inc.
4.2 DSP1600 Core Architectural Overview
Figure 5 shows a block diagram of the DSP1600 core.
System Cache and Control Section (SYS)
This section of the core contains a 15-word cache memory and controls the instruction sequencing. It handles
vectored interrupts and traps, and also provides decoding for registers outside of the DSP1600 core. SYS
stretches the processor cycle if wait-states are required
(wait-states are programmable for external memory accesses). SYS sequences downloading via JTAG of selftest programs to on-chip, dual-port RAM.
The cache loop iteration count can be specified at run
time under program control as well as at assembly time.
11
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Data Arithmetic Unit (DAU)
The data arithmetic unit (DAU) contains a 16 x 16-bit
parallel multiplier that generates a full 32-bit product in
one instruction cycle. The product can be accumulated
with one of two 36-bit accumulators. The accumulator
data can be directly loaded from, or stored to, memory
in two 16-bit words with optional saturation on overflow.
The arithmetic logic unit (ALU) supports a full set of
arithmetic and logical operations on either 16- or 32-bit
data. A standard set of flags can be tested for conditional ALU operations, branches, and subroutine calls. This
procedure allows the processor to perform as a powerful 16- or 32-bit microprocessor for logical and control
applications. The available instruction set is fully compatible with the DSP1627 instruction set. See Section
5.1 for more information on the instruction set.
The user also has access to two additional DAU registers. The psw register contains status information from
the DAU (see Table 26, Processor Status Word Register). The arithmetic control register, auc, is used to configure some of the features of the DAU (see Table 27)
including single-cycle squaring. The auc register alignment field supports an arithmetic shift left by one and
left or right by two. The auc register is cleared by reset.
The counters c0 to c2 are signed, 8 bits wide, and may
be used to count events such as the number of times
the program has executed a sequence of code. They
are controlled by the conditional instructions and provide a convenient method of program looping.
Y Space Address Arithmetic Unit (YAAU)
The YAAU supports high-speed, register-indirect, compound, and direct addressing of data (Y) memory. Four
general-purpose, 16-bit registers, r0 to r3, are available
in the YAAU. These registers can be used to supply the
read or write addresses for Y space data. The YAAU
also decodes the 16-bit data memory address and outputs individual memory enables for the data access.
The YAAU can address the six 1 Kword banks of onchip DPRAM or three external data memory segments.
Up to 48 Kwords of off-chip RAM are addressable, with
16K addresses reserved for internal RAM.
Two 16-bit registers, rb and re, allow zero-overhead
modulo addressing of data for efficient filter implementations. Two 16-bit signed registers, j and k, are used to
hold user-defined postmodification increments. Fixed
increments of +1, –1, and +2 are also available. Four
compound-addressing modes are provided to make
read/write operations more efficient.
12
The YAAU allows direct (or indexed) addressing of data
memory. In direct addressing, the 16-bit base register
(ybase) supplies the 11 most significant bits of the address. The direct data instruction supplies the remaining
5 bits to form an address to Y memory space and also
specifies one of 16 registers for the source or destination.
X Space Address Arithmetic Unit (XAAU)
The XAAU supports high-speed, register-indirect, instruction/coefficient memory addressing with postmodification of the register. The 16-bit pt register is used for
addressing coefficients. The signed register i holds a
user-defined postincrement. A fixed postincrement of
+1 is also available. Register PC is the program
counter. Registers pr and pi hold the return address for
subroutine calls and interrupts, respectively.
The XAAU decodes the 16-bit instruction/coefficient address and produces enable signals for the appropriate
X memory segment. The addressable X segments are
48 Kwords of internal ROM, up to 16 Kwords of DPRAM
for the DSP1629x16 or up to 10 Kwords of DPRAM for
the DSP1629x10, and external ROM.
The locations of these memory segments depend upon
the memory map selected (see Table 5). A security
mode can be selected by mask option. This prevents
unauthorized access to the contents of on-chip ROM
(see Section 7, Mask-Programmable Options).
4.3 Interrupts and Trap
The DSP1629 supports prioritized, vectored interrupts
and a trap. The device has eight internal hardware
sources of program interrupt and two external interrupt
pins. Additionally, there is a trap pin and a trap signal
from the hardware development system (HDS). A software interrupt is available through the icall instruction.
The icall instruction is reserved for use by the HDS.
Each of these sources of interrupt and trap has a unique
vector address and priority assigned to it. DSP16A interrupt compatibility is not maintained.
The software interrupt and the traps are always enabled
and do not have a corresponding bit in the ins register.
Other vectored interrupts are enabled in the inc register
(see Table 29, Interrupt Control (inc) Register) and
monitored in the ins register (see Table 30, Interrupt
Status (ins) Register). When the DSP1629 goes into an
interrupt or trap service routine, the IACK pin is asserted. In addition, pins VEC[3:0] encode which interrupt/
trap is being serviced. Table 4 details the encoding
used for VEC[3:0].
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
i (16)
SYS
cloop (7)
ins (16)
alf (16)
inc (16)
mwait (16)
XDB
XAAU
MUX
ADDER
CACHE
CONTROL
1
XAB
pr (16)
pc (16)
pi (16)
pt (16)
IDB
BRIDGE
YAAU
DAU
yh (16)
x (16)
YDB
yl (16)
j (16)
–1, 0, 1, 2
k (16)
16 x 16 MPY
32
p (32)
MUX
SHIFT (–2, 0, 1, 2)
ADDER
MUX
YAB
rb (16)
36
ALU/SHIFT
c0 (8)
c2 (8)
auc (16)
a0 (36)
a1 (36)
re (16)
MUX
c1 (8)
CMP
r0 (16)
psw (16)
r1 (16)
r2 (16)
16
ybase (16)
r3 (16)
EXTRACT/SAT
5-1741 (F).b
Figure 5. DSP1600 Core Block Diagram
Lucent Technologies Inc.
13
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Table 3. DSP1600 Core Block Diagram Legend
Symbol
16 x 16 MPY
a0—a1
alf
ALU/SHIFT
auc
c0—c2
cloop
CMP
DAU
i
IDB
inc
ins
j
k
MUX
mwait
p
PC
pi
pr
psw
pt
r0—r3
rb
re
SYS
x
XAAU
XAB
XDB
YAAU
YAB
YDB
ybase
y
Name
16-bit x 16-bit Multiplier.
Accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l).*
AWAIT, LOWPR, Flags.
Arithmetic Logic Unit/Shifter.
Arithmetic Unit Control.
Counters 0—2.
Cache Loop Count.
Comparator.
Digital Arithmetic Unit.
Increment Register for the X Address Space.
Internal Data Bus.
Interrupt Control.
Interrupt Status.
Increment Register for the Y Address Space.
Increment Register for the Y Address Space.
Multiplexer.
External Memory Wait-states Register.
Product Register (16-bit halves specified as p, pl).
Program Counter.
Program Interrupt Return Register.
Program Return Register.
Processor Status Word.
X Address Space Pointer.
Y Address Space Pointers.
Modulo Addressing Register (begin address).
Modulo Addressing Register (end address).
System Cache and Control Section.
Multiplier Input Register.
X Space Address Arithmetic Unit.
X Space Address Bus.
X Space Data Bus.
Y Space Address Arithmetic Unit.
Y Space Address Bus.
Y Space Data Bus.
Direct Addressing Base Register.
DAU Register (16-bit halves specified as y, yl).
* F3 ALU instructions with immediates require specifying the high half of the accumulators as a0h and a1h.
14
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Signaling Interrupt Service Status
Interruptibility
Five pins of DSP1629 are devoted to signaling interrupt
service status. The IACK pin goes high while any interrupt or user trap is being serviced, and goes low when
the ireturn instruction from the service routine is issued.
Four pins, VEC[3:0], carry a code indicating which of the
interrupts or trap is being serviced. Table 4 contains the
encodings used by each interrupt.
Vectored interrupts are serviced only after the execution
of an interruptible instruction. If more than one vectored
interrupt is asserted at the same time, the interrupts are
serviced sequentially according to their assigned priorities. See Table 4 for the priorities assigned to the vectored interrupts. Interrupt service routines, branch and
conditional branch instructions, cache loops, and instructions that only decrement one of the RAM pointers,
r0 to r3 (e.g., *r3−
− −), are not interruptible.
A trap is similar to an interrupt, but it gains control of the
processor by branching to the trap service routine even
when the current instruction is noninterruptible. It may
not be possible to return to normal instruction execution
from the trap service routine since the machine state
cannot always be saved. In particular, program execution cannot be continued from a trapped cache loop or
interrupt service routine. While in a trap service routine,
another trap is ignored.
When set to 1, the status bits in the ins register indicate
that an interrupt has occurred. The processor must
reach an interruptible state (completion of an interruptible instruction) before an enabled vectored interrupt will
be acted on. An interrupt will not be serviced if it is not
enabled. Polled interrupt service can be implemented
by disabling the interrupt in the inc register and then
polling the ins register for the expected event.
Vectored Interrupts
Tables 29 and 30 show the inc and ins registers. A logic
1 written to any bit of inc enables (or unmasks) the associated interrupt. If the bit is cleared to a logic 0, the interrupt is masked. Note that neither the software
interrupt nor traps can be masked.
The occurrence of an interrupt that is not masked will
cause the program execution to transfer to the memory
location pointed to by that interrupt's vector address, assuming no other interrupt is being serviced (see Table
4, Interrupt Vector Table). The occurrence of an interrupt that is masked causes no automatic processor action, but will set the corresponding status bit in the ins
register. If a masked interrupt occurs, it is latched in the
ins register, but the interrupt is not taken. When unlatched, this latched interrupt will initiate automatic processor interrupt action. See the DSP1611/17/18/27
Digital Signal Processor Information Manual for a more
detailed description of the interrupts.
Lucent Technologies Inc.
Traps due to HDS breakpoints have no effect on either
the IACK or VEC[3:0] pins. Instead, they show the interrupt state or interrupt source of the DSP when the trap
occurred.
Clearing Interrupts
The PHIF interrupts (PIBF and POBE) are cleared by
reading or writing the parallel host interface data transmit registers pdx0[in] and pdx0[out], respectively. The
SIO and SIO2 interrupts (IBF, IBF2, OBE, and OBE2)
are cleared one instruction cycle AFTER reading or writing the serial data registers, (sdx[in], sdx2[in], sdx[out],
or sdx2[out]). To account for this added latency, the
user must ensure that a single instruction (NOP or any
other valid DSP16XX instruction) follows the sdx register read or write instruction prior to exiting an interrupt
service routine (via an ireturn or goto pi instruction) or
before checking the ins register for the SIO flag status.
Adding this instruction ensures that interrupts are not
reported incorrectly following an ireturn or that stale
flags are not read from the ins register. The JTAG interrupt (JINT) is cleared by reading the jtag register.
Three of the vectored interrupts are cleared by writing to
the ins register. Writing a 1 to the INT0, INT1, or TIME
bits in the ins will cause the corresponding interrupt status bit to be cleared to a logic 0. The status bit for these
vectored interrupts is also cleared when the ireturn instruction is executed, leaving set any other vectored interrupts that are pending.
Traps
The TRAP pin of the DSP1629 is a bidirectional signal.
At reset, it is configured as an input to the processor.
Asserting the TRAP pin will force a user trap. The trap
mechanism is used for two purposes. It can be used by
an application to rapidly gain control of the processor for
asynchronous time-critical event handling (typically for
catastrophic error recovery). It is also used by the HDS
for breakpointing and gaining control of the processor.
Separate vectors are provided for the user trap (0x46)
and the HDS trap (0x3). Traps are not maskable.
15
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Table 4. Interrupt Vector Table
Source
No Interrupt
Software Interrupt
INT0
JINT
INT1
TIME
IBF2
OBE2
Reserved
Reserved
Reserved
IBF
OBE
PIBF
POBE
TRAP from HDS
TRAP from User
Vector
—
0x2
0x1
0x42
0x4
0x10
0x14
0x18
0x1c
0x20
0x24
0x2c
0x30
0x34
0x38
0x3
0x46
Priority
—
1
2
3
4
7
8
9
10
11
12
14
15
16
17
18
19 = highest
VEC[3:0]
0x0
0x1
0x2
0x8
0x9
0xc
0xd
0xe
0x0
0x1
0x2
0x3
0x4
0x5
0x6
*
0x7
Issued by
—
icall
pin
jtag in
pin
timer
SIO2 in
SIO2 out
—
—
—
SIO in
SIO out
PHIF in
PHIF out
breakpoint, jtag, or pin
pin
* Traps due to HDS breakpoints have no effect on VEC[3:0] pins.
A trap has four cycles of latency. At most, two instructions will execute from the time the trap is received at
the pin to when it gains control. An instruction that is executing when a trap occurs is allowed to complete before the trap service routine is entered. (Note that the
instruction could be lengthened by wait-states.) During
normal program execution, the pi register contains either the address of the next instruction (two-cycle instruction executing) or the address following the next
instruction (one-cycle instruction executing). In an interrupt service routine, pi contains the interrupt return address. When a trap occurs during an interrupt service
routine, the value of the pi register may be overwritten.
Specifically, it is not possible to return to an interrupt
service routine from a user trap (0x46) service routine.
Continuing program execution when a trap occurs during a cache loop is also not possible.
The HDS trap causes circuitry to force the program
memory map to MAP1 (with on-chip ROM starting at address 0x0) when the trap is taken. The previous memory map is restored when the trap service routine exits by
issuing an ireturn. The map is forced to MAP1 because
the HDS code, if present, resides in the on-chip ROM.
Using the Lucent Technologies development tools, the
TRAP pin may be configured to be an output, or an input
vectoring to address 0x3. In a multiprocessor environment, the TRAP pins of all the DSPs present can be tied
16
together. During HDS operations, one DSP is selected
by the host software to be the master. The master processor's TRAP pin is configured to be an output.
The TRAP pins of the slave processors are configured
as inputs. When the master processor reaches a breakpoint, the master's TRAP pin is asserted. The slave processors will respond to their TRAP input by beginning to
execute the HDS code.
AWAIT Interrupt (Standby or Sleep Mode)
Setting the AWAIT bit (bit 15) of the alf register (alf =
0x8000) causes the processor to go into a power-saving
standby or sleep mode. Only the minimum circuitry on
the chip required to process an incoming interrupt remains active. After the AWAIT bit is set, one additional
instruction will be executed before the standby powersaving mode is entered. A PHIF or SIO word transfer
will complete if already in progress. The AWAIT bit is reset when the first interrupt occurs. The chip then wakes
up and continues executing.
Two nop instructions should be programmed after the
AWAIT bit is set. The first nop (one cycle) will be executed before sleeping; the second will be executed after
the interrupt signal awakens the DSP and before the interrupt service routine is executed.
Lucent Technologies Inc.
Data Sheet
March 2000
4 Hardware Architecture (continued)
The AWAIT bit should be set from within the cache if the
code which is executing resides in external ROM where
more than one wait-state has been programmed. This
ensures that an interrupt will not disturb the device from
completely entering the sleep state.
For additional power savings, set ioc = 0x0180 and timerc = 0x0040 in addition to setting alf = 0x8000. This will
hold the CKO pin low and shut down the timer and prescaler (see Table 38 and Table 31).
For a description of the control mechanisms for putting
the DSP into low-power modes, see Section 4.13, Power Management.
4.4 Memory Maps and Wait-States
The DSP1600 core implements a modified Harvard architecture that has separate on-chip 16-bit address and
data buses for the instruction/coefficient (X) and data
(Y) memory spaces. Table 5 shows the instruction/coefficient memory space maps for both the DSP1629x16
and DSP1629x10.
The DSP1629 provides a multiplexed external bus
which accesses external RAM (ERAM) and ROM
(EROM). Programmable wait-states are provided for
external memory accesses. The instruction/coefficient
memory map is configurable to provide application flexibility. Table 6 shows the data memory space, which
has one map.
Instruction/Coefficient Memory Map Selection
In determining which memory map to use, the processor evaluates the state of two parameters. The first is
the LOWPR bit (bit 14) of the alf register. The LOWPR
bit of the alf register is initialized to 0 automatically at reset. LOWPR controls the starting address in memory
assigned to 1K banks of dual-port RAM. If LOWPR is
low, internal dual-port RAM begins at address 0xC000.
If LOWPR is high, internal dual-port RAM begins at address 0x0. LOWPR also moves IROM from 0x0 in
MAP1 to 0x4000 in MAP3, and EROM from 0x0 in
MAP2 to 0x4000 in MAP4.
The second parameter is the value at reset of the EXM
pin (pin 27 or pin 14, depending upon the package
type). EXM determines whether the internal 48 Kwords
ROM (IROM) will be addressable in the memory map.
The Lucent Technologies development system tools,
together with the on-chip HDS circuitry and the JTAG
port, can independently set the memory map. Specifically, during an HDS trap, the memory map is forced to
Lucent Technologies Inc.
DSP1629 Digital Signal Processor
MAP1. The user's map selection is restored when the
trap service routine has completed execution.
MAP1
MAP1 has the IROM starting at 0x0 and 1 Kword banks
of DPRAM starting at 0xC000. MAP1 is used if
DSP1629 has EXM low at reset and the LOWPR parameter is programmed to zero. It is also used during an
HDS trap.
MAP2
MAP2 differs from MAP1 in that the lowest 48 Kwords
reference external ROM (EROM). MAP2 is used if EXM
is high at reset, the LOWPR parameter is programmed
to zero, and an HDS trap is not in progress.
MAP3
MAP3 has the 1 Kword banks of DPRAM starting at
address 0x0. In MAP3, the 48 Kwords of IROM start at
0x4000. MAP3 is used if EXM is low at reset, the LOWPR bit is programmed to 1, and an HDS trap is not in
progress. Note that this map is not available if the secure mask-programmable option has been ordered.
MAP4
MAP4 differs from MAP3 in that addresses above
0x4000 reference external ROM (EROM). This map is
used if the LOWPR bit is programmed to 1, an HDS trap
is not in progress, and, either EXM is high during reset,
or the secure mask-programmable option has been ordered.
Whenever the chip is reset using the RSTB pin, the default memory map will be MAP1 or MAP2, depending
upon the state of the EXM pin at reset. A reset through
the HDS will not reinitialize the alf register, so the previous memory map is retained.
Boot from External ROM
After RSTB goes from low to high, the DSP1629 comes
out of reset and fetches an instruction from address
zero of the instruction/coefficient space. The physical
location of address zero is determined by the memory
map in effect. If EXM is high at the rising edge of RSTB,
MAP2 is selected. MAP2 has EROM at location zero;
thus, program execution begins from external memory.
If EXM is high and INT1 is low when RSTB rises, the
mwait register defaults to 15 wait-states for all external
memory segments. If INT1 is high, the mwait register
defaults to 0 wait-states.
17
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Table 5. Instruction/Coefficient Memory Maps
DSP1629x16
X Address
AB[0:15]
0
4K
6K
12K
16K
20K
24K
28K
32K
36K
40K
44K
48K
52K
54K
56K
60K—64K
0x0000
0x1000
0x1800
0x3000
0x4000
0x5000
0x6000
0x7000
0x8000
0x9000
0xA000
0xB000
0xC000
0xD000
0xD800
0xE000
0xFFFF
MAP 1*
EXM = 0
LOWPR = 0†
IROM
(48K)
MAP 2
EXM = 1
LOWPR = 0
EROM
(48K)
DPRAM
(16K)
DPRAM
(16K)
MAP 1*
EXM = 0
LOWPR = 0†
IROM
(48K)
MAP 2
EXM = 1
LOWPR = 0
EROM
(48K)
MAP 3‡
EXM = 0
LOWPR = 1
DPRAM
(16K)
MAP 4
EXM = 1
LOWPR = 1
DPRAM
(16K)
IROM
(48K)
EROM
(48K)
MAP 3‡
EXM = 0
LOWPR = 1
DPRAM
(10K)
MAP 4
EXM = 1
LOWPR = 1
DPRAM
(10K)
Reserved
(6K)
IROM
(48K)
Reserved
(6K)
EROM
(48K)
DSP1629x10
X Address
AB[0:15]
0
4K
6K
10K
12K
16K
20K
24K
28K
32K
36K
40K
44K
48K
52K
54K
56K
58K
60K—64K
0x0000
0x1000
0x1800
0x2800
0x3000
0x4000
0x5000
0x6000
0x7000
0x8000
0x9000
0xA000
0xB000
0xC000
0xD000
0xD800
0xE000
0xE800
0xFFFF
DPRAM
(10K)
DPRAM
(10K)
Reserved
(6K)
Reserved
(6K)
* MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
† LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
‡ MAP3 is not available if the secure mask-programmable option is selected.
18
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Table 6. Data Memory Maps
1629x16 Data Memory Map (Not to Scale)
Decimal
Address
0
Address in
r0, r1, r2, r3
0x0000
1629x10 Data Memory Map (Not to Scale)
Decimal
Address
0
Address in
r0, r1, r2, r3
0x0000
Segment
10K
0x2800
Reserved
(6 K)
16K
0x4000
IO
16,640
0x4100
ERAMLO
32K
0x8000
ERAMHI
64K – 1
0xFFFF
DPRAM[1:10]
Segment
DPRAM[1:16]
16K
0x4000
IO
16,640
0x4100
ERAMLO
32K
0x8000
ERAMHI
Wait-States
64K – 1
0xFFFF
On the data memory side (see Table 6), the 1K banks
of dual-port RAM are located starting at address 0. Addresses from 0x4000 to 0x40FF reference a 256-word
memory-mapped I/O segment (IO). Addresses from
0x4100 to 0x7FFF reference the low external data RAM
segment (ERAMLO). Addresses above 0x8000 reference high external data RAM (ERAMHI).
Lucent Technologies Inc.
The number of wait-states (from 0 to 15) used when accessing each of the four external memory segments
(ERAMLO, IO, ERAMHI, and EROM) is programmable
in the mwait register (see Table 36). When the program
references memory in one of the four external segments, the internal multiplexer is automatically switched
to the appropriate set of internal buses, and the associated external enable of ERAMLO, IO, ERAMHI, or
EROM is issued. The external memory cycle is automatically stretched by the number of wait-states configured in the appropriate field of the mwait register.
19
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
4.5 External Memory Interface (EMI)
The external memory interface supports read/write operations from instruction/coefficient memory, data
memory, and memory-mapped I/O devices. The
DSP1629 provides a 16-bit external address bus,
AB[15:0], and a 16-bit external data bus, DB[15:0].
These buses are multiplexed between the internal buses for the instruction/coefficient memory and the data
memory. Four external memory segment enables,
ERAMLO, IO, ERAMHI, and EROM, select the external
memory segment to be addressed.
If a data memory location with an address between
0x4100 and 0x7FFF is addressed, ERAMLO is asserted
low.
If one of the 256 external data memory locations, with
an address greater than or equal to 0x4000, and less
than or equal to 0x40FF, is addressed, IO is asserted
low. IO is intended for memory-mapped I/O.
If a data memory location with an address greater than
or equal to 0x8000 is addressed, ERAMHI is asserted
low. When the external instruction/coefficient memory is
addressed, EROM is asserted low.
The flexibility provided by the programmable options of
the external memory interface (see Table 36, mwait
Register and Table 38, ioc Register) allows the
DSP1629 to interface gluelessly with a variety of commercial memory chips.
Each of the four external memory segments, ERAMLO,
IO, ERAMHI, and EROM, has a number of wait-states
that is programmable (from 0 to 15) by writing to the
mwait register. When the program references memory
in one of the four external segments, the internal multiplexer is automatically switched to the appropriate set of
internal buses, and the associated external enable of
ERAMLO, IO, ERAMHI, or EROM is issued. The external memory cycle is automatically stretched by the number of wait-states in the appropriate field of the mwait
register.
When writing to external memory, the RWN pin goes
low for the external cycle. The external data bus,
DB[15:0], is driven by the DSP1629 starting halfway
through the cycle. The data driven on the external data
bus is automatically held after the cycle for one additional clock period unless an external read cycle immediately follows.
The DSP1629 has one external address bus and one
external data bus for both memory spaces. Since some
instructions provide the capability of simultaneous access to both X space and Y space, some provision must
be made to avoid collisions for external accesses. The
20
Data Sheet
March 2000
DSP1629 has a sequencer that does the external X access first, and then the external Y access, transparently
to the programmer. Wait-states are maintained as programmed in the mwait register. For example, let two instructions be executed: the first reads a coefficient from
EROM and writes data to ERAM; the second reads a
coefficient from EROM and reads data from ERAM. The
sequencer carries out the following steps at the external
memory interface: read EROM, write ERAM, read EROM, and read ERAM. Each step is done in sequential
one-instruction cycle steps, assuming zero wait-states
are programmed. Note that the number of instruction
cycles taken by the two instructions is four. Also, in this
case, the write hold time is zero.
The DSP1629 allows writing into external instruction/
coefficient memory. By setting bit 11, WEROM, of the
ioc register (see Table 38), writing to (or reading from)
data memory or memory-mapped I/O asserts the
EROM strobe instead of ERAMLO, IO, or ERAMHI.
Therefore, with WEROM set, EROM appears in both Y
space (replacing ERAM) and X space, in its normal position.
Bit 14 of the ioc register (see Table 38), EXTROM, may
be used with WEROM to download to a full 64K of external memory. When WEROM and EXTROM are both
asserted, address bit 15 (AB15) is held low, aliasing the
upper 32K of external memory into the lower 32K.
When an access to internal memory is made, the
AB[15:0] bus holds the last valid external memory address. Asserting the RSTB pin low 3-states the AB[15:0]
bus. After reset, the AB[15:0] value is undefined.
The leading edge of the memory segment enables can
be delayed by approximately one-half a CKO period by
programming the ioc register (see Table 38). This is
used to avoid a situation in which two devices drive the
data bus simultaneously.
Bits 7, 8, and 13 of the ioc register select the mode of
operation for the CKO pin (see Table 38). Available options are a free-running unstretched clock, a wait-stated
sequenced clock (runs through two complete cycles
during a sequenced external memory access), and a
wait-stated clock based on the internal instruction cycle.
These clocks drop to the low-speed internal ring oscillator when SLOWCKI is enabled (see 4.13, Power Management). The high-to-low transitions of the wait-stated
clock are synchronized to the high-to-low transition of
the free-running clock. Also, the CKO pin provides either a continuously high level, a continuously low level,
or changes at the rate of the internal processor clock.
This last option, only available with the small-signal input clock options, enables the DSP1629 CKI input buffer to deliver a full-rate clock to other devices while the
DSP1629 itself is in one of the low-power modes.
Lucent Technologies Inc.
Data Sheet
March 2000
4 Hardware Architecture (continued)
4.6 Bit Manipulation Unit (BMU)
The BMU interfaces directly to the main accumulators in
the DAU providing the following features:
■
Barrel shifting—logical and arithmetic, left and right
shift
■
Normalization and extraction of exponent
■
Bit-field extraction and insertion
These features increase the efficiency of the DSP in applications such as control or data encoding and decoding. For example, data packing and unpacking, in which
short data words are packed into one 16-bit word for
more efficient memory storage, is very easy.
In addition, the BMU provides two auxiliary accumulators, aa0 and aa1. In one instruction cycle, 36-bit data
can be shuffled, or swapped, between one of the main
accumulators and one of the alternate accumulators.
The ar<0—3> registers are 16-bit registers that control
the operations of the BMU. They store a value that determines the amount of shift or the width and offset
fields for bit extraction or insertion. Certain operations in
the BMU set flags in the DAU psw register and the alf
register (see Table 26, Processor Status Word (psw)
Register, and Table 35, alf Register). The ar<0—3> registers can also be used as general-purpose registers.
The BMU instructions are detailed in Section 5.1. For a
thorough description of the BMU, see the DSP1611/17/
18/27 Digital Signal Processor Information Manual.
4.7 Serial I/O Units (SIOs)
The serial I/O ports on the DSP1629 device provide a
serial interface to many codecs and signal processors
with little, if any, external hardware required. Each highspeed, double-buffered port (sdx and sdx2) supports
back-to-back transmissions of data. SIO and SIO2 are
identical. The output buffer empty (OBE and OBE2) and
input buffer full (IBF and IBF2) flags facilitate the reading and/or writing of each serial I/O port by programor interrupt-driven I/O. There are four selectable active
clock speeds.
A bit-reversal mode provides compatibility with either
the most significant bit (MSB) first or least significant bit
(LSB) first serial I/O formats (see Table 22, Serial I/O
Control Registers (sioc and sioc2)). A multiprocessor
I/O configuration is supported. This feature allows up to
eight DSP161X devices to be connected together on an
SIO port without requiring external glue logic.
The serial data may be internally looped back by setting
the SIO loopback control bit, SIOLBC, of the ioc regisLucent Technologies Inc.
DSP1629 Digital Signal Processor
ter. SIOLBC affects both the SIO and SIO2. The data
output signals are wrapped around internally from the
output to the input (DO1 to DI1 and DO2 to DI2). To exercise loopback, the SIO clocks (ICK1, ICK2, OCK1,
and OCK2) should either all be in the active mode,
16-bit condition, or each pair should be driven from one
external source in passive mode. Similarly, pins ILD1
(ILD2) and OLD1 (OLD2) must both be in active mode
or tied together and driven from one external frame
clock in passive mode. During loopback, DO1, DO2,
DI1, DI2, ICK1, ICK2, OCK1, OCK2, ILD1, ILD2, OLD1,
OLD2, SADD1, SADD2, SYNC1, SYNC2, DOEN1, and
DOEN2 are 3-stated.
Setting DODLY = 1 (sioc and sioc2) delays DO by one
phase of OCK so that DO changes on the falling edge
of OCK instead of the rising edge (DODLY = 0). This reduces the time available for DO to drive DI and to be valid for the rising edge of ICK, but increases the hold time
on DO by half a cycle on OCK.
Programmable Modes
Programmable modes of operation for the SIO and
SIO2 are controlled by the serial I/O control registers
(sioc and sioc2). These registers, shown in Table 22,
are used to set the ports into various configurations.
Both input and output operations can be independently
configured as either active or passive. When active, the
DSP1629 generates load and clock signals. When passive, load and clock signal pins are inputs.
Since input and output can be independently configured, each SIO has four different modes of operation.
Each of the sioc registers is also used to select the frequency of active clocks for that SIO. Finally, these registers are used to configure the serial I/O data formats.
The data can be 8 or 16 bits long, and can also be input/
output MSB first or LSB first. Input and output data formats can be independently configured.
Multiprocessor Mode
The multiprocessor mode allows up to eight devices
that support multiprocessor mode (codecs or DSP16XX
devices) to be connected together to provide data transmission among any of the multiprocessor devices in the
system. Either of the DSP1629’s SIO ports (SIO or
SIO2) may be independently used for the multiprocessor mode. The multiprocessor interface is a four-wire interface, consisting of a data channel, an address/
protocol channel, a transmit/receive clock, and a sync
signal (see Figure 6). The DI1 and DO1 pins of all the
DSPs are connected to transmit and receive the data
channel. The SADD1 pins of all the DSPs are connected to transmit and receive the address/protocol channel. ICK1 and OCK1 should be tied together and driven
from one source. The SYNC1 pins of all the DSPs are
connected.
21
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
In the configuration shown in Figure 6, the master DSP
(DSP0) generates active SYNC1 and OCK1 signals
while the slave DSPs use the SYNC1 and OCK1 signals
in passive mode to synchronize operations. In addition,
all DSPs must have their ILD1 and OLD1 signals in active mode.
While ILD1 and OLD1 are not required externally for
multiprocessor operation, they are used internally in the
DSP's SIO. Setting the LD field of the master's sioc register to a logic level 1 will ensure that the active generation of SYNC1, ILD1, and OLD1 is derived from OCK1
(see Table 22). With this configuration, all DSPs should
use ICK1 (tied to OCK1) in passive mode to avoid conflicts on the clock (CK) line (see the DSP1611/17/18/27
Digital Signal Processor Information Manual for more
information).
Four registers (per SIO) configure the multiprocessor
mode: the time-division multiplexed slot register (tdms
or tdms2), the serial receive and transmit address register (srta or srta2), the serial data transmit register (sdx
or sdx2), and the multiprocessor serial address/protocol
register (saddx or saddx2).
Multiprocessor mode requires no external logic and
uses a TDM interface with eight 16-bit time slots per
frame. The transmission in any time slot consists of
16 bits of serial data in the data channel and 16 bits of
address and protocol information in the address/protocol channel. The address information consists of the
transmit address field of the srta register of the transmitting device. The address information is transmitted concurrently with the transmission of the first 8 bits of data.
The protocol information consists of the transmit protocol field written to the saddx register and is transmitted
concurrently with the last 8 bits of data (see Table 25,
Multiprocessor Protocol Register). Data is received or
recognized by other DSP(s) whose receive address
matches the address in the address/protocol channel.
Each SIO port has a user-programmable receive address and transmit address associated with it. The
transmit and receive addresses are programmed in the
srta register.
In order to prevent multiple bus drivers, only one DSP
can be programmed to transmit in a particular time slot.
In addition, it is important to note that the address/protocol channel is 3-stated in any time slot that is not being
driven.
Therefore, to prevent spurious inputs, the address/protocol channel should be pulled up to VDD with a 5 kΩ resistor, or it should be guaranteed that the bus is driven
in every time slot. (If the SYNC1 signal is externally generated, then this pull-up is required for correct initialization.)
Each SIO also has a fully decoded transmitting address
specified by the srta register transmit address field (bits
7—0). This is used to transmit information regarding the
destination(s) of the data. The fully decoded receive address specified by the srta register receive address field
(bits 15—8) determines which data will be received.
The SIO protocol channel data is controlled via the saddx register. When the saddx register is written, the lower
8 bits contain the 8-bit protocol field. On a read, the
high-order 8 bits read from saddx are the most recently
received protocol field sent from the transmitting DSP's
saddx output register. The low-order 8 bits are read as
0s.
An example use of the protocol channel is to use the top
3 bits of the saddx value as an encoded source address
for the DSPs on the multiprocessor bus. This leaves the
remaining 5 bits available to convey additional control
information, such as whether the associated field is an
opcode or data, or whether it is the last word in a transfer, etc. These bits can also be used to transfer parity information about the data. Alternatively, the entire field
can be used for data transmission, boosting the bandwidth of the port by 50%.
Using SIO2
The SIO2 functions the same as the SIO. Please refer
to Pin Multiplexing in Section 4.1 for a description of pin
multiplexing of BIO, PHIF, VEC[3:0], and SIO2.
In multiprocessor mode, each device can send data in
a unique time slot designated by the tdms register transmit slot field (bits 7—0). The tdms register has a fully decoded transmit slot field in order to allow one DSP1629
device to transmit in more than one time slot. This procedure is useful for multiprocessor systems with less
than eight DSP1629 devices when a higher bandwidth
is necessary between certain devices in that system.
The DSP operating during time slot 0 also drives
SYNC1.
22
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
SYNC
SADD
DO
DI
ICK
OCK
DSP 7
SYNC
SADD
DO
DI
ICK
OCK
DSP 1
SYNC
SADD
ICK
OCK
DO
DI
DSP 0
5 kΩ
DATA CHANNEL
VDD
CLOCK
ADDRESS/PROTOCOL CHANNEL
SYNC SIGNAL
5-4181 (F).a
Figure 6. Multiprocessor Communication and Connections
4.8 Parallel Host Interface (PHIF)
The DSP1629 has an 8-bit parallel host interface for
rapid transfer of data with external devices. This parallel
port is passive (data strobes provided by an external device) and supports either Motorola or Intel microcontroller protocols. The PHIF also provides for 8-bit or
16-bit data transfers. As a flexible host interface, it requires little or no glue logic to interface to other devices
(e.g., microcontrollers, microprocessors, or another
DSP).
The data path of the PHIF consists of a 16-bit input buffer, pdx0(in), and a 16-bit output buffer, pdx0(out). Two
output pins, parallel input buffer full (PIBF) and parallel
output buffer empty (POBE), indicate the state of the
buffers. In addition, there are two registers used to control and monitor the PHIF's operation: the parallel host
interface control register (phifc, see Table 28), and the
PHIF status register (PSTAT, see Table 8). The PSTAT
register, which reflects the state of the PIBF and POBE
flags, can only be read by an external device when the
PSTAT input pin is asserted. The phifc register defines
the programmable options for this port.
The function of the pins, PIDS and PODS, is programmable to support both the Intel and Motorola protocols.
The pin, PCSN, is an input that, when low, enables
PIDS and PODS (or PRWN and PDS, depending on the
protocol used). While PCSN is high, the DSP1629 ignores any activity on PIDS and/or PODS. If a DSP1629
is intended to be continuously accessed through the
PHIF port, PCSN should be grounded. If PCSN is low
and their respective bits in the inc register are set, the
Lucent Technologies Inc.
assertion of PIDS and PODS by an external device
causes the DSP1629 device to recognize an interrupt.
Programmability
The parallel host interface can be programmed for 8-bit
or 16-bit data transfers using bit 0, PMODE, of the phifc
register. Setting PMODE selects 16-bit transfer mode.
An input pin controlled by the host, PBSEL, determines
an access of either the high or low bytes. The assertion
level of the PBSEL input pin is configurable in software
using bit 3 of the phifc register, PBSELF. Table 7 summarizes the port's functionality as controlled by the
PSTAT and PBSEL pins and the PBSELF and PMODE
fields.
For 16-bit transfers, if PBSELF is zero, the PIBF and
POBE flags are set after the high byte is transferred. If
PBSELF is one, the flags are set after the low byte is
transferred. In 8-bit mode, only the low byte is accessed, and every completion of an input or output access
sets PIBF or POBE.
Bit 1 of the phifc register, PSTROBE, configures the
port to operate either with an Intel protocol where only
the chip select (PCSN) and either of the data strobes
(PIDS or PODS) are needed to make an access, or with
a Motorola protocol where the chip select (PCSN), a
data strobe (PDS), and a read/write strobe (PRWN) are
needed. PIDS and PODS are negative assertion data
strobes while the assertion level of PDS is programmable through bit 2, PSTRB, of the phifc register.
23
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Finally, the assertion level of the output pins, PIBF and POBE, is controlled through bit 4, PFLAG. When PFLAG is
set low, PIBF and POBE output pins have positive assertion levels. By setting bit 5, PFLAGSEL, the logical OR of
PIBF and POBE flags (positive assertion) is seen at the output pin PIBF. By setting bit 7 in phifc, PSOBEF, the polarity of the POBE flag in the status register, PSTAT, can be changed. PSOBEF has no effect on the POBE pin.
Pin Multiplexing
Please refer to Pin Multiplexing in Section 4.1 for a description of BIO, PHIF, VEC[3:0], and SIO2 pins.
Table 7. PHIF Function (8-bit and 16-bit Modes)
PMODE Field
0 (8-bit)
0
0
0
1 (16-bit)
1
1
1
PSTAT Pin
0
0
1
1
0
0
1
1
PBSEL Pin
0
1
0
1
0
1
0
1
PBSELF Field = 0
pdx0 low byte
reserved
PSTAT
reserved
pdx0 low byte
pdx0 high byte
PSTAT
reserved
PBSELF Field = 1
reserved
pdx0 low byte
reserved
PSTAT
pdx0 high byte
pdx0 low byte
reserved
PSTAT
Table 8. pstat Register as Seen on PB[7:0]
Bit
Field
7
6
5
4
2
RSVD
4.9 Bit Input/Output Unit (BIO)
The BIO controls the directions of eight bidirectional
control I/O pins, IOBIT[7:0]. If a pin is configured as an
output, it can be individually set, cleared, or toggled. If a
pin is configured as an input, it can be read and/or tested.
The lower half of the sbit register (see Table 33) contains current values (VALUE[7:0]) of the eight bidirectional pins IOBIT[7:0]. The upper half of the sbit register
(DIREC[7:0]) controls the direction of each of the pins.
A logic 1 configures the corresponding pin as an output;
a logic 0 configures it as an input. The upper half of the
sbit register is cleared upon reset.
The cbit register (see Table 34) contains two 8-bit fields,
MODE/MASK[7:0] and DATA/PAT[7:0]. The values of
DATA/PAT[7:0] are cleared upon reset. The meaning of
a bit in either field depends on whether it has been configured as an input or an output in sbit. If a pin has been
configured to be an output, the meanings are MODE
and DATA. For an input, the meanings are MASK and
PAT (pattern). Table 9 shows the functionality of the
MODE/MASK and DATA/PAT bits based on the direction selected for the associated IOBIT pin.
Those bits that have been configured as inputs can be
individually tested for 1 or 0. For those inputs that are
being tested, there are four flags produced: allt (all true),
24
3
1
PIBF
0
POBE
allf (all false), somet (some true), and somef (some
false). These flags can be used for conditional branch or
special instructions. The state of these flags can be
saved and restored by reading and writing bits 0 to 3 of
the alf register (see Table 35).
Table 9. BIO Operations
DIREC[n]*
1 (Output)
1 (Output)
1 (Output)
1 (Output)
0 (Input)
0 (Input)
0 (Input)
0 (Input)
MODE/
MASK[n]
0
0
1
1
0
0
1
1
DATA/
PAT[n]
0
1
0
1
0
1
0
1
Action
Clear
Set
No Change
Toggle
No Test
No Test
Test for Zero
Test for One
* 0 ≤ n ≤ 7.
If a BIO pin is switched from being configured as an output to being configured as an input and then back to being configured as an output, the pin retains the previous
output value.
Pin Multiplexing
Please refer to Pin Multiplexing in Section 4.1 for a
description of BIO, PHIF, VEC[3:0], and SIO2 pins.
Lucent Technologies Inc.
Data Sheet
March 2000
4 Hardware Architecture (continued)
4.10 Timer
The interrupt timer is composed of the timerc (control)
register, the timer0 register, the prescaler, and the
counter itself. The timer control register (see Table 31,
timerc Register) sets up the operational state of the timer and prescaler. The timer0 register is used to hold the
counter reload value (or period register) and to set the
initial value of the counter. The prescaler slows the
clock to the timer by a number of binary divisors to allow
for a wide range of interrupt delay periods.
The counter is a 16-bit down counter that can be loaded
with an arbitrary number from software. It counts down
to 0 at the clock rate provided by the prescaler. Upon
reaching 0 count, a vectored interrupt to program address 0x10 is issued to the DSP1629, providing the interrupt is enabled (bit 8 of inc and ins registers). The
counter will then either wait in an inactive state for another command from software, or will automatically repeat the last interrupting period, depending upon the
state of the RELOAD bit in the timerc register.
When RELOAD is 0, the counter counts down from its
initial value to 0, interrupts the DSP1629, and then
stops, remaining inactive until another value is written to
the timer0 register. Writing to the timer0 register causes
both the counter and the period register to be written
with the specified 16-bit number. When RELOAD is 1,
the counter counts down from its initial value to 0, interrupts the DSP1629, automatically reloads the specified
initial value from the period register into the counter,
and repeats indefinitely. This provides for either a single
timed interrupt event or a regular interrupt clock of arbitrary period.
The timer can be stopped and started by software, and
can be reloaded with a new period at any time. Its count
value, at the time of the read, can also be read by software. Due to pipeline stages, stopping and starting the
timer may result in one inaccurate count or prescaled
period. When the DSP1629 is reset, the bottom 6 bits of
the timerc register and the timer0 register and counter
are initialized to 0. This sets the prescaler to CKO/2*,
turns off the reload feature, disables timer counting, and
initializes the timer to its inactive state. The act of resetting the chip does not cause a timer interrupt. Note that
the period register is not initialized on reset.
The T0EN bit of the timerc register enables the clock to
the timer. When T0EN is a 1, the timer counts down towards 0. When T0EN is a 0, the timer holds its current
count.
DSP1629 Digital Signal Processor
The PRESCALE field of the timerc register selects one
of 16 possible clock rates for the timer input clock (see
Table 31, timerc Register).
Setting the DISABLE bit of the timerc register to a logic
1 shuts down the timer and the prescaler for power savings. Setting the TIMERDIS, bit 4, in the powerc register
has the same effect of shutting down the timer. The
DISABLE bit and the TIMERDIS bit are cleared by writing a 0 to their respective registers to restore the normal
operating mode.
4.11 JTAG Test Port
The DSP1629 uses a JTAG/IEEE 1149.1 standard fivewire test port (TDI, TDO, TCK, TMS, TRST) for self-test
and hardware emulation. An instruction register, a
boundary-scan register, a bypass register, and a device
identification register have been implemented. The device identification register coding for the DSP1629 is
shown in Table 37. The instruction register (IR) is 4 bits
long. The instruction for accessing the device ID is 0xE
(1110). The behavior of the instruction register is summarized in Table 10. Cell 0 is the LSB (closest to TDO).
Table 10. JTAG Instruction Register
IR Cell #:
Parallel Input?
Always Logic 1?
Always Logic 0?
3
Y
N
N
2
Y
N
N
1
N
N
Y
0
N
Y
N
The first line shows the cells in the IR that capture from
a parallel input in the capture-IR controller state. The
second line shows the cells that always load a logic 1 in
the capture-IR controller state. The third line shows the
cells that always load a logic 0 in the capture-IR controller state. Cell 3 (MSB of IR) is tied to status signal PINT,
and cell 2 is tied to status signal JINT. The state of these
signals can therefore be captured during capture-IR and
shifted out during SHIFT-IR controller states.
Boundary-Scan Register
All of the chip's inputs and outputs are incorporated in a
JTAG scan path shown in Table 11. The types of
boundary-scan cells are as follows:
■
I = input cell
■
O = 3-state output cell
■
B = bidirectional (I/O) cell
■
OE = 3-state control cell
■
DC = bidirectional control cell
* Frequency of CKO/2 is equivalent to either CKI/2 for the PLL bypassed or related to CKI by the PLL multiplying factors. See Section 4.12, Clock Synthesis.
Lucent Technologies Inc.
25
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Note that the direction of shifting is from TDI to cell 104 to cell 103 . . . to cell 0 of TDO.
Table 11. JTAG Boundary-Scan Register
Cell
Type
0
OE
1
2
3
4
5
6
7
8
9
10—25
26
27
28—31
32—36
37
38—48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
O
I
DC
B
I
O
I
OE
I
O
I
O
O
B
DC
B
O
O
I
DC
B
DC
B
DC
B
DC
B
OE
O
DC
B
DC
B
DC
B
DC
Signal Name/Function
Cell
Type
Controls cells 1, 27—31
69
B
CKO
RSTB
Controls cell 4
TRAP
STOP†
IACK
INT0
Controls cells 6, 10—25, 49, 50, 78, 79
INT1
AB[0:15]
EXM
RWN
EROM, ERAMLO, ERAMHI, IO
DB[0:4]
Controls cells 32—36, 38—48
DB[5:15]
OBE1
IBF1
DI1
Controls cell 53
ILD1
Controls cell 55
ICK1
Controls cell 57
OCK1
Controls cell 59
OLD1
Controls cell 61
DO1
Controls cell 63
SYNC1
Controls cell 65
SADD1
Controls cell 67
DOEN1
Controls cell 69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
—
DC
B
DC
B
DC
B
DC
B
O
O
DC
B
DC
B
DC
B
DC
B
DC
B
DC
B
DC
B
DC
B
DC
B
DC
B
DC
B
DC
B
I
—
Signal Name/Function
OCK2/PCSN*
Controls cell 71
DO2/PSTAT*
Controls cell 73
SYNC2/PBSEL*
Controls cell 75
ILD2/PIDS*
Controls cell 77
OLD2/PODS*
IBF2/PIBF*
OBE2/POBE*
Controls cell 81
ICK2/PB0*
Controls cell 83
DI2/PB1*
Controls cell 85
DOEN2/PB2*
Controls cell 87
SADD2/PB3*
Controls cell 89
IOBIT0/PB4*
Controls cell 91
IOBIT1/PB5*
Controls cell 93
IOBIT2/PB6*
Controls cell 95
IOBIT3/PB7*
Controls cell 97
VEC3/IOBIT4*
Controls cell 99
VEC2/IOBIT5*
Controls cell 101
VEC1/IOBIT6*
Controls cell 103
VEC0/IOBIT7*
CKI‡
—
* Please refer to Pin Multiplexing in Section 4.1 for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.
† Note that shifting a zero into this cell in the mode to scan a zero into the chip will disable the processor clocks just as the STOP pin will.
‡ When the JTAG SAMPLE instruction is used, this cell will have a logic one regardless of the state of the pin.
26
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
4.12 Clock Synthesis
SLOWCKI
powerc
fSLOW CLOCK
RING
OSCILLATOR
CKI INPUT CLOCK
fCKI
fCKI
VCO CLOCK
fVCO
M
U
X
INTERNAL
PROCESSOR
CLOCK
fINTERNAL CLOCK
÷2
LOCK
PLLSEL
(FLAG TO INDICATE LOCK
CONDITION OF PLL)
÷N
PHASE
DETECTOR
CHARGE
PUMP
VCO
PLLEN
pllc
LOOP
FILTER
Nbits[2:0]
÷M
PLL/SYNTHESIZER
Mbits[4:0]
LF[3:0]
5-4520 (F)
Figure 7. Clock Source Block Diagram
The DSP1629 provides an on-chip, programmable
clock synthesizer. Figure 7 is the clock source diagram.
The 1X CKI input clock, the output of the synthesizer, or
a slow internal ring oscillator can be used as the source
for the internal DSP clock. The clock synthesizer is
based on a phase-locked loop (PLL), and the terms
clock synthesizer and PLL are used interchangeably.
On powerup, CKI is used as the clock source for the
DSP. This clock is used to generate the internal processor clocks and CKO, where fCKI = fCKO. Setting the appropriate bits in the pllc control register (described in
Table 32) will enable the clock synthesizer to become
the clock source. The powerc register, which is discussed in Section 4.13, can override the selection to
stop clocks or force the use of the slow clock for lowpower operation.
Lucent Technologies Inc.
PLL Control Signals
The input to the PLL comes from one of the three maskprogrammable clock options: CMOS, or small-signal.
The PLL cannot operate without an external input clock.
To use the PLL, the PLL must first be allowed to stabilize and lock to the programmed frequency. After the
PLL has locked, the LOCK flag is set and the lock detect
circuitry is disabled. The synthesizer can then be used
as the clock source. Setting the PLLSEL bit in the pllc
register will switch sources from fCKI to fVCO/2 without
glitching. It is important to note that the setting of the pllc
register must be maintained. Otherwise, the PLL will
seek the new set point. Every time the pllc register is
written, the LOCK flag is reset.
27
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
The frequency of the PLL output clock, fVCO, is determined by the values loaded into the 3-bit N divider and
the 5-bit M divider. When the PLL is selected and
locked, the frequency of the internal processor clock is
related to the frequency of CKI by the following equations:
fVCO = fCKI * M/N
fINTERNAL CLOCK = fCKO = fVCO ÷ 2
The frequency of the VCO, fVCO, must fall within the
range listed in Table 63. Also note that fVCO must be at
least twice fCKI.
The coding of the Mbits and Nbits is described as follows:
Mbits = M − 2
if (N = 1)
Nbits = 0x7
else
Nbits = N − 2
where N ranges from 1 to 8 and M ranges from 2 to 20.
The loop filter bits LF[3:0] should be programmed according to Table 64.
28
Data Sheet
March 2000
Two other bits in the pllc register control the PLL. Clearing the PLLEN bit powers down the PLL; setting this bit
powers up the PLL. Clearing the PLLSEL bit deselects
the PLL so that the DSP is clocked by a 1X version of
the CKI input; setting the PLLSEL bit selects the PLLgenerated clock for the source of the DSP internal processor clock. The pllc register is cleared on reset and
powerup. Therefore, the DSP comes out of reset with
the PLL deselected and powered down. M and N should
be changed only while the PLL is deselected. The values of M and N should not be changed when powering
down or deselecting the PLL.
As previously mentioned, the PLL also provides a user
flag, LOCK, to indicate when the loop has locked. When
this flag is not asserted, the PLL output is unstable. The
DSP should not be switched to the PLL-based clock
without first checking that the lock flag is set. The lock
flag is cleared by writing to the pllc register. When the
PLL is deselected, it is necessary to wait for the PLL to
relock before the DSP can be switched to the PLLbased clock. Before the input clock is stopped, the PLL
should be powered down. Otherwise, the LOCK flag will
not be reset and there may be no way to determine if the
PLL is stable, once the input clock is applied again.
The lock-in time depends on the frequency of operation
and the values programmed for M and N (see Table 64).
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
PLL Programming Examples
The following section of code illustrates how the PLL would be initialized on powerup, assuming the following operating conditions:
■
CKI input frequency = 10 MHz
■
Internal clock and CKO frequency = 50 MHz
■
VCO frequency = 100 MHz
■
Input divide down count N = 2 (Set Nbits[2:0] = 000 to get N = 2, as described in Table 32.)
■
Feedback down count M = 20 (Set Mbits[4:0] = 10010 to get M = 18 + 2 = 20, as described in Table 32.)
The device would come out of reset with the PLL disabled and deselected.
pllinit: pllc = 0x2912
pllc = 0xA912
call pllwait
pllc = 0xE912
goto start
pllwait: if lock return
goto pllwait
/*
/*
/*
/*
/*
Running CKI input clock at 10 MHz, set up counters in PLL */
Power on PLL, but PLL remains deselected */
Loop to check for LOCK flag assertion */
Select high-speed, PLL clock */
User's code, now running at 50 MHz */
Programming examples which illustrate how to use the PLL with the various power management modes are listed
in Section 4.13.
Latency
The switch between the CKI-based clock and the PLL-based clock is synchronous. This method results in the actual
switch taking place several cycles after the PLLSEL bit is changed. During this time, actual code can be executed,
but it will be at the previous clock rate. Table 12 shows the latency times for switching between CKI-based and PLLbased clocks. In the example given, the delay to switch to the PLL source is 1—4 CKO cycles and to switch back is
11—31 CKO cycles.
Table 12. Latency Times for Switching Between CKI and PLL-Based Clocks
Switch to PLL-Based Clock
Switch from PLL-based Clock
Minimum Latency (Cycles)
1
M/N + 1
Maximum Latency (Cycles)
N+2
M + M/N + 1
Frequency Accuracy and Jitter
When using the PLL to multiply the input clock frequency up to the instruction clock rate, it is important to realize
that although the average frequency of the internal clock and CKO will have about the same relative accuracy as
the input clock, noise sources within the DSP will produce jitter on the PLL clock such that each individual clock
period will have some error associated with it. The PLL is guaranteed only to have sufficiently low jitter to operate
the DSP, and thus, this clock should not be used as an input to jitter-sensitive devices in the system.
VDDA and VSSA Connections
The PLL has its own power and ground pins, VDDA and VSSA. Additional filtering should be provided for VDDA in the
form of a ferrite bead connected from V DDA to VDD and two decoupling capacitors (4.7 µF tantalum in parallel with
a 0.01 µF ceramic) from VDDA to VSS. VSSA can be connected directly to the main ground plane. This recommendation is subject to change and may need to be modified for specific applications depending on the characteristics
of the supply noise.
Note: For devices with the CMOS clock input option, the CKI2 pin should be connected to VSSA.
Lucent Technologies Inc.
29
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
4.13 Power Management
There are three different control mechanisms for putting
the DSP1629 into low-power modes: the powerc control
register, the STOP pin, and the AWAIT bit in the alf register. The PLL can also be disabled with the PLLEN bit
of the pllc register for more power saving.
Powerc Control Register Bits
The powerc register has 10 bits that power down various portions of the chip and select the clock source:
XTLOFF: Assertion of the XTLOFF bit powers down the
small-signal input circuit, disabling the internal processor clock. Since the small-signal input circuit takes
many cycles to stabilize, care must be taken with the
turn-on sequence, as described later.
SLOWCKI: Assertion of the SLOWCKI bit selects the
ring oscillator as the clock source for the internal processor clock instead of CKI or the PLL. When CKI or the
PLL is selected, the ring oscillator is powered down.
Switching of the clocks is synchronized so that no partial or short clock pulses occur. Two nops should follow
the instruction that sets or clears SLOWCKI.
NOCK: Assertion of the NOCK bit synchronously turns
off the internal processor clock, regardless of whether
its source is provided by CKI, the PLL, or the ring oscillator. The NOCK bit can be cleared by resetting the chip
with the RSTB pin, or asserting the INT0 or INT1 pins.
Two nops should follow the instruction that sets NOCK.
The PLL remains running, if enabled, while NOCK is
set.
INT0EN: This bit allows the INT0 pin to asynchronously
clear the NOCK bit, thereby allowing the device to continue program execution from where it left off without
any loss of state. No chip reset is required. It is recommended that, when INT0EN is to be used, the INT0
interrupt be disabled in the inc register so that an unintended interrupt does not occur. After the program resumes, the INT0 interrupt in the ins register should be
cleared.
INT1EN: This bit enables the INT1 pin to be used as the
NOCK clear, exactly like INT0EN previously described.
The following control bits power down the peripheral
I/O units of the DSP. These bits can be used to further
reduce the power consumption during standard sleep
mode.
30
SIO1DIS: This is a powerdown signal to the SIO1 I/O
unit. It disables the clock input to the unit, thus eliminating any sleep power associated with the SIO1. Since
the gating of the clocks may result in incomplete transactions, it is recommended that this option be used in
applications where the SIO1 is not used or when reset
may be used to reenable the SIO1 unit. Otherwise, the
first transaction after reenabling the unit may be corrupted.
SIO2DIS: This bit powers down the SIO2 in the same
way SIO1DIS powers down the SIO1.
PHIFDIS: This is a powerdown signal to the parallel
host interface. It disables the clock input to the unit, thus
eliminating any sleep power associated with the PHIF.
Since the gating of the clocks may result in incomplete
transactions, it is recommended that this option be used
in applications where the PHIF is not used, or when reset may be used to reenable the PHIF. Otherwise, the
first transaction after reenabling the unit may be corrupted.
TIMERDIS: This is a timer disable signal which disables
the clock input to the timer unit. Its function is identical
to the DISABLE field of the timerc control register. Writing a 0 to the TIMERDIS field will continue the timer operation.
Figure 8 shows a functional view of the effect of the bits
of the powerc register on the clock circuitry. It shows
only the high-level operation of each bit. Not shown are
the bits that power down the peripheral units.
STOP Pin
Assertion (active-low) of the STOP pin has the same effect as setting the NOCK bit in the powerc register. The
internal processor clock is synchronously disabled until
the STOP pin is returned high. Once the STOP pin is returned high, program execution will continue from
where it left off without any loss of state. No chip reset
is required. The PLL remains running, if enabled, during
STOP assertion.
The pllc Register Bits
The PLLEN bit of the pllc register can be used to power
down the clock synthesizer circuitry. Before shutting
down the clock synthesizer circuitry, the system clock
should be switched to either CKI using the PLLSEL bit
of pllc, or to the ring oscillator using the SLOWCKI bit of
powerc.
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
PLLEN
XTLOFF
OFF
CKI2
RING
OSCILLATOR
SMALL SIGNAL
CLOCK
PLL
DEEP
SLEEP
ON
fSLOW CLOCK
fVCO/2
MASK-PROGRAMMABLE
OPTION
CKI
fCKI
CMOS
INPUT
CLOCK
SYNC.
MUX
PLLSEL
SLOWCKI
STOP
HW STOP
SW STOP
NOCK
CLEAR NOCK
DEEP
SLEEP
DISABLE
SYNC.
GATE
RSTB
fINTERNAL CLOCK
INT0
INTERNAL
PROCESSOR
CLOCK
INT0EN
INT1
INT1EN
5-4124 (F).h
Notes:
The functions in the shaded ovals are bits in the powerc control register. The functions in the nonshaded ovals are bits in the pllc control register.
Deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock.
The switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur.
When the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is powered down.
PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc.
Figure 8. Power Management Using the powerc and the pllc Registers
Lucent Technologies Inc.
31
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Await Bit of the alf Register
Setting the AWAIT bit of the alf register causes the processor to go into the standard sleep state or power-saving standby mode. Operation of the AWAIT bit is the
same as in the DSP1610, DSP1611, DSP1616,
DSP1617, and DSP1618. In this mode, the minimum
circuitry required to process an incoming interrupt remains active, and the PLL remains active if enabled. An
interrupt will return the processor to the previous state,
and program execution will continue. The action resulting from setting the AWAIT bit and the action resulting
from setting bits in the powerc register are mostly independent. As long as the processor is receiving a clock,
whether slow or fast, the DSP may be put into standard
sleep mode with the AWAIT bit. Once the AWAIT bit is
set, the STOP pin can be used to stop and later restart
the processor clock, returning to the standard sleep
state. If the processor clock is not running, however, the
AWAIT bit cannot be set.
Power Management Sequencing
There are important considerations for sequencing the
power management modes. The small-signal clock input
circuit has a start-up delay which must be taken into account, and the PLL requires a delay to reach lock-in. Also, the chip may or may not need to be reset following a
return from a low-power state.
Devices with a small-signal input clocking option may
use the XTLOFF bit in the powerc register to power
down the on-chip oscillator or small-signal circuitry,
thereby reducing the power dissipation. When reenabling the oscillator or the small-signal circuitry, it is important to bear in mind that a start-up interval exists
during which time the clocks are not stable.
32
Two scenarios exist here:
1. Immediate Turn-Off, Turn-On with RSTB: This scenario applies to situations where the target device is
not required to execute any code while the small-signal input circuit is powered down and where restart
from a reset state can be tolerated. In this case, the
processor clock derived from either the oscillator or
the small-signal input is running when XTLOFF is asserted. This effectively stops the internal processor
clock. When the system chooses to reenable the oscillator or small-signal input, a reset of the device will
be required. The reset pulse must be of sufficient duration for the small-signal start-up interval to be satisfied (required for the small-signal input circuit to
reach its dc operating point). A minimum reset pulse
of 20 µs will be adequate. The falling edge of the reset signal, RSTB, will asynchronously clear the
XTLOFF field, thus reenabling the power to the
small-signal circuitry. The target DSP will then start
execution from a reset state, following the rising
edge of RSTB.
2. Running from Slow Clock While XTLOFF Active: The
second scenario applies to situations where the device needs to continue execution of its target code.
In this case, the device switches to the slow ring oscillator clock first, by enabling the SLOWCKI field.
Then, if the small-signal input is being used, power
down this circuitry by writing a 1 to the XTLOFF field.
Two nops are needed in between the two write operations to the powerc register. The target device will
then continue execution of its code at slow speed,
while the small-signal input clock is turned off.
Switching from the slow clock back to the high-speed
clock is then accomplished in three user steps. First,
XTLOFF is cleared. Then, a user-programmed routine sets the internal timer to a delay to wait for the
small-signal input oscillations to become stable.
When the timer counts down to zero, the high-speed
clock is selected by clearing the SLOWCKI field, either in the timer's interrupt service routine or following a timer polling loop. If PLL operation is desired,
then an additional routine is necessary to enable the
PLL and wait for it to lock.
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Power Management Examples Without the PLL
The following examples show the more significant options for reducing the power dissipation. These are valid only
if the pllc register is set to disable and deselect the PLL (PLLEN = 0, PLLSEL = 0).
Standard Sleep Mode. This is the standard sleep mode. While the processor is clocked with a high-speed clock,
CKI, the alf register's AWAIT bit is set. Peripheral units may be turned off to further reduce the sleep power.
powerc = 0X00F0
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
cont: . . .
powerc = 0x0
/*
/*
/*
/*
/*
Turn off peripherals, core running with CKI */
Set alf register in cache loop if running from */
external memory with >1 wait state */
Stop internal processor clock, interrupt circuits */
active */
/*
/*
/*
/*
Needed for bedtime execution. Only sleep power */
consumed here until.... interrupt wakes up the device */
User code executes here */
Turn peripheral units back on */
Sleep with Slow Internal Clock. In this case, the ring oscillator is selected to clock the processor before the device
is put to sleep. This will reduce the power dissipation while waiting for an interrupt to continue program execution.
powerc = 0x40F0
2*nop
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
cont: . . .
powerc = 0x00F0
2*nop
powerc = 0x0000
/*
/*
/*
/*
/*
/*
Turn off peripherals and select slow clock */
Wait for it to take effect */
Set alf register in cache loop if running from */
external memory with >1 wait state */
Stop internal processor clock, interrupt circuits */
active */
/*
/*
/*
/*
/*
/*
Needed for bedtime execution. Reduced sleep power */
consumed here.... Interrupt wakes up the device */
User code executes here */
Select high-speed clock */
Wait for it to take effect */
Turn peripheral units back on */
Note that, in this case, the wake-up latency is determined by the period of the ring oscillator clock.
Sleep with Slow Internal Clock and Small-Signal Disabled. If the target device contains the small-signal clock
option, the clock input circuitry can be powered down to further reduce power. In this case, the slow clock must be
selected first.
powerc = 0x40F0
2*nop
powerc = 0xC0F0
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
powerc = 0x40F0
call xtlwait
cont: powerc = 0x00F0
2*nop
powerc = 0x0000
/*
/*
/*
/*
/*
/*
/*
Turn off peripherals and select slow clock */
Wait for it to take effect */
Turn off the small-signal input buffer */
Set alf register in cache loop if running from */
external memory with >1 wait state */
Stop internal processor clock, interrupt circuits */
active */
/*
/*
/*
/*
/*
/*
/*
Needed for bedtime execution. Reduced sleep power */
consumed here.... Interrupt wakes up the device */
Clear XTLOFF, reenable small-signal */
Wait until small-signal is stable */
Select high-speed clock */
Wait for it to take effect */
Turn peripheral units back on */
Note that, in this case, the wake-up latency is dominated by the small-signal start-up period.
Lucent Technologies Inc.
33
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Software Stop. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to reenable the
clocks.The power management must be done in correct sequence.
powerc = 0x4000
2*nop
powerc = 0xD000
inc = NOINT0
sopor:powerc = 0xF000
3*nop
cont: powerc = 0x4000
call waitxtl
powerc = 0x0
2*nop
ins = 0x0010
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
SLOWCKI asserted */
Wait for it to take effect */
XTLOFF asserted if applicable and INT0EN asserted */
Disable the INT0 interrupt */
NOCK asserted, all clocks stop */
Minimum switching power consumed here */
Some nops will be needed */
INT0 pin clears the NOCK field, clocking resumes */
INT0EN cleared and XTLOFF cleared, if applicable*/
Wait for the small-signal to */
stabilize, if applicable*/
Clear SLOWCKI field, back to high speed */
Wait for it to take effect */
Clear the INT0 status bit */
In this case also, the wake-up latency is dominated by the small-signal start-up period.
The previous examples do not provide an exhaustive list of options available to the user. Many different clocking
possibilities exist for which the target device may be programmed, depending on:
■
The clock source to the processor.
■
Whether the user chooses to power down the peripheral units.
■
The operational state of the small-signal clock input, powered or unpowered.
■
Whether the internal processor clock is disabled through hardware or software.
■
The combination of power management modes the user chooses.
■
Whether or not the PLL is enabled.
An example subroutine for xtlwait follows:
xtlwait:
loop1:
34
timer0 = 0x2710
timerc = 0x0010
inc = 0x0000
a0 = ins
a0 = a0 & 0x0100
if eq goto loop1
ins = 0x0100
return
/*
/*
/*
/*
/*
/*
/*
/*
Load a count of 10,000 into the timer
Start the timer with a PRESCALE of two
Disable the interrupts
Poll the ins register
Check bit 8 (TIME) of the ins register
Loop if the bit is not set
Clear the TIME interrupt bit
Return to the main program
*/
*/
*/
*/
*/
*/
*/
*/
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
4 Hardware Architecture (continued)
Power Management Examples with the PLL
The following examples show the more significant options for reducing power dissipation if operation with the PLL
clock synthesizer is desired.
Standard Sleep Mode, PLL Running. This mode would be entered in the same manner as without the PLL. While
the input to the clock synthesizer, CKI, remains running, the alf register's AWAIT bit is set. The PLL will continue to
run and dissipate power. Peripheral units may be turned off to further reduce the sleep power.
powerc = 0x00F0
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
cont: . . .
powerc = 0x0
/*
/*
/*
/*
/*
Turn off peripherals, core running with PLL */
Set alf register in cache loop if running from */
external memory with >1 wait state */
Stop internal processor clock, interrupt circuits */
active */
/*
/*
/*
/*
Needed for bedtime execution. Only sleep power plus PLL */
power consumed here.... Interrupt wakes up the device */
User code executes here */
Turn peripheral units back on */
Sleep with Slow Internal Clock, PLL Running. In this case, the ring oscillator is selected to clock the processor
before the device is put to sleep. This will reduce power dissipation while waiting for an interrupt to continue program
execution.
powerc = 0x40F0
2*nop
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
cont: . . .
powerc = 0x00F0
2*nop
powerc = 0x0000
Lucent Technologies Inc.
/*
/*
/*
/*
/*
/*
Turn off peripherals and select slow clock */
Wait for slow clock to take effect */
Set alf register in cache loop if running from */
external memory with >1 wait state */
Stop internal processor clock, interrupt circuits */
active */
/*
/*
/*
/*
/*
/*
/*
Needed for bedtime execution. Reduced sleep power, PLL */
power, and ring oscillator power consumed here... */
Interrupt wakes up the device */
User code executes here */
Select high-speed PLL based clock */
Wait for it to take effect */
Turn peripheral units back on */
35
DSP1629 Digital Signal Processor
Data Sheet
March 2000
4 Hardware Architecture (continued)
Sleep with Slow Internal Clock and Small-Signal Disabled, PLL Disabled. If the target device contains the smallsignal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow
clock must be selected first, and then the PLL must be disabled, since the PLL cannot run without the clock input
circuitry being active.
powerc = 0x40F0
2*nop
pllc = 0x29F2
powerc = 0xC0F0
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
powerc = 0x40F0
call xtlwait
pllc = 0xE9F2
call pllwait
cont: powerc = 0x00F0
2*nop
powerc = 0x0000
/*
/*
/*
/*
/*
/*
/*
/*
Turn off peripherals and select slow clock */
Wait for slow clock to take effect */
Disable PLL (assume N = 1,M = 20, LF = 1001) */
Disable small-signal input buffer */
Set alf register in cache loop if running from */
external memory with >1 wait state */
Stop internal processor clock, interrupt circuits */
active */
/*
/*
/*
/*
/*
/*
/*
/*
/*
Needed for bedtime execution. Reduced sleep power
consumed here.... Interrupt wakes up device */
Clear XTLOFF, leave PLL disabled */
Wait until small-signal is stable */
Enable PLL, continue to run off slow clock */
Loop to check for LOCK flag assertion */
Select high-speed PLL based clock */
Wait for it to take effect */
Turn peripherals back on */
Software Stop, PLL Disabled. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to
reenable the clocks. The power management must be done in the correct sequence, with the PLL being disabled
before shutting down the clock input buffer.
powerc = 0x4000
2*nop
pllc = 0x29F2
powerc = 0xD000
sopor:powerc = 0xF000
3*nop
cont: powerc = 0x4000
call xtlwait
pllc = 0xE9F2
call pllwait
powerc = 0x0
2*nop
ins = 0x0010
36
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
SLOWCKI asserted */
Wait for slow clock to take effect */
Disable PLL (assume N = 1, M = 20, LF = 1001) */
XTLOFF asserted, if applicable and INT0EN
asserted */
NOCK asserted, all clocks stop */
Minimum switching power consumed here */
Some nops will be needed */
INT0 pin clears NOCK field, clocking resumes */
INTOEN cleared and XTLOFF cleared, if applicable */
Wait until small-signal is stable */
if applicable */
Enable PLL, continue to run off slow clock */
Loop to check for LOCK flag assertion */
Select high-speed PLL based clock */
Wait for it to take effect */
Clear the INT0 status bit */
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture
Multiply/ALU Instructions
5.1 Instruction Set
Note that the function statements and transfer statements in Table 13 are chosen independently. Any function statement (F1) can be combined with any transfer
statement to form a valid multiply/ALU instruction. If either statement is not required, a single statement from
either column also constitutes a valid instruction. The
number of cycles to execute the instruction is a function
of the transfer column. (An instruction with no transfer
statement executes in one instruction cycle.) Whenever
PC, pt, or rM is used in the instruction and points to external memory, the programmed number of wait-states
must be added to the instruction cycle count. All multiply/ALU instructions require one word of program memory. The no-operation (nop) instruction is a special-case
encoding of a multiply/ALU instruction and executes in
one cycle. The assembly-language representation of a
nop is either nop or a single semicolon.
The DSP1629 processor has seven types of instructions: multiply/ALU, special function, control, F3 ALU,
BMU, cache, and data move. The multiply/ALU instructions are the primary instructions used to implement signal processing algorithms. Statements from this group
can be combined to generate multiply/accumulate, logical, and other ALU functions and to transfer data between memory and registers in the data arithmetic unit.
The special function instructions can be conditionally
executed based on flags from the previous ALU or BMU
operation, the condition of one of the counters, or the
value of a pseudorandom bit in the DSP1629 device.
Special function instructions perform shift, round, and
complement functions. The F3 ALU instructions enrich
the operations available on accumulators. The BMU instructions provide high-performance bit manipulation.
The control instructions implement the goto and call
commands. Control instructions can also be executed
conditionally. Cache instructions are used to implement
low-overhead loops, conserve program memory, and
decrease the execution time of certain multiply/ALU instructions. Data move instructions are used to transfer
data between memory and registers or between accumulators and registers. See the DSP1611/17/18/27
Digital Signal Processor Information Manual for a detailed description of the instruction set.
The following operators are used in describing the instruction set:
■
*
16 x 16-bit –> 32-bit multiplication or registerindirect addressing when used as a prefix to an
address register or denotes direct addressing
when used as a prefix to an immediate
■
+
36-bit addition†
■
–
36-bit subtraction†
■
>>
Arithmetic right shift
■
>>> Logical right shift
■
<<
■
<<< Logical left shift
■
|
36-bit bitwise OR†
■
&
36-bit bitwise AND†
■
^
36-bit bitwise EXCLUSIVE OR†
■
:
Compound address swapping, accumulator
shuffling
■
~
One's complement
A single-cycle squaring function is provided in
DSP1629. By setting the X = Y = bit in the auc register,
any instruction that loads the high half of the y register
also loads the x register with the same value. A subsequent instruction to multiply the x register and y register
results in the square of the value being placed in the p
register. The instruction a0 = p p = x*y y = *r0++ with
the X = Y = bit set to one will read the value pointed to
by r0, load it to both x and y, multiply the previously
fetched value of x and y, and transfer the previous product to a0. A table of values pointed to by r0 can thus be
squared in a pipeline with one instruction cycle per each
value. Multiply/ALU instructions that use x = X transfer
statements (such as a0 = p p = x*y y = *r0++ x = *pt++)
are not recommended for squaring because pt will be
incremented even though x is not loaded from the value
pointed to by pt. Also, the same conflict wait occurrences from reading the same bank of internal memory or
reading from external memory apply, since the X space
fetch occurs (even though its value is not used).
Arithmetic left shift
† These are 36-bit operations. One operand is 36-bit data in an accumulator; the other operand may be 16, 32, or 36 bits.
Lucent Technologies Inc.
37
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 13. Multiply/ALU Instructions
Function Statement
p=x*y
Transfer Statement†
y=Y
x=X
aD = p
p=x*y
aD = aS + p
p=x*y
y[l] = Y
1/1
aD = aS – p
p=x*y
aT[l] = Y
1/1
x=Y
Y
Y = y[l]
Y = aT[l]
1/1
1/1
2/2
2/2
2/2
2/2
2/2
aD = p
aD = aS + p
aD = aS – p
aD = y
aD = aS + y
aD = aS – y
aD = aS & y
aD = aS | y
aD = aS ^ y
aS – y
aS & y
y = aT
x=X
Cycles (Out/In Cache)‡
2/1
Z:y
x=X
Z:y[l]
Z:aT[l]
2/1
† The l in [ ] is an optional argument that specifies the low 16 bits of aT or y.
‡ Add cycles for:
1. When an external memory access is made in X or Y space and wait-states are programmed, add the number of wait-states.
2. If an X space access and a Y space access are made to the same bank of DPRAM in one instruction, add one cycle.
Note: For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corresponding CLR bit in the auc register is zero. auc is cleared by reset.
Table 14. Replacement Table for Multiply/ALU Instructions
Replace
aD, aS, aT
X
Y
Z
38
Value
a0, a1
*pt++, *pt++i
Meaning
One of two DAU accumulators.
X memory space location pointed to by pt. pt is postmodified by +1 and
i, respectively.
*rM, *rM++, *rM--, rM++j
RAM location pointed to by rM (M = 0, 1, 2, 3). rM is postmodified by
0, +1, –1, or j, respectively.
*rMzp, *rMpz, *rMm2, *rMjk Read/Write compound addressing. rM (M = 0, 1, 2, 3) is used twice.
First, postmodified by 0, +1, –1, or j, respectively; and, second, postmodified by +1, 0, +2, or k, respectively.
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Special Function Instructions
All forms of the special function require one word of program memory and execute in one instruction cycle. (If PC
points to external memory, add programmed wait-states.)
aD = aS >> 1 }
aD = aS >> 4
aD = aS >> 8
aD = aS >> 16
Arithmetic right shift (sign preserved) of 36-bit accumulators
aD = aS
—
Load destination accumulator from source accumulator
aD = –aS
—
2's complement
aD = ~aS*
—
1's complement
aD = rnd(aS)
—
Round upper 20 bits of accumulator
aDh = aSh + 1 —
Increment upper half of accumulator (lower half cleared)
aD = aS + 1
—
Increment accumulator
aD = y
—
Load accumulator with 32-bit y register value with sign extend
aD = p
—
Load accumulator with 32-bit p register value with sign extend
aD = aS << 1 }
aD = aS << 4
aD = aS << 8
aD = aS << 16
Arithmetic left shift (sign not preserved) of the lower 32 bits of accumulators
(upper 4 bits are sign-bit-extended from bit 31 at the completion of the shift)
The above special functions can be conditionally executed, as in:
if CON instruction
and with an event counter
ifc CON instruction
which means:
if CON is true then
c1 = c1 + 1
instruction
c2 = c1
else
c1 = c1 + 1
The above special function statements can be executed unconditionally by writing them directly, e.g., a0 = a1.
Table 15. Replacement Table for Special Function Instructions
Replace
aD
aS
CON
Value
a0, a1
Meaning
One of two DAU accumulators.
See Table 17 for definitions of mnemonics.
mi, pl, eq, ne, gt, le, lvs, lvc, mvs, mvc, c0ge,
c0lt, c1ge, c1lt, heads, tails, true, false, allt, allf,
somet, somef, oddp, evenp, mns1, nmns1, npint,
njint, lock
* This function is not available for the DSP16A.
Lucent Technologies Inc.
39
DSP1629 Digital Signal Processor
Data Sheet
March 2000
5 Software Architecture (continued)
Control Instructions
All control instructions executed unconditionally execute in two cycles, except icall which takes three cycles. Control
instructions executed conditionally execute in three instruction cycles. (If PC, pt, or pr point to external memory, add
programmed wait-states.) Control instructions executed unconditionally require one word of program memory, while
control instructions executed conditionally require two words. Control instructions cannot be executed from the
cache.
goto JA†
goto pt
call JA†
call pt
icall‡
return
ireturn
(goto pr)
(goto pi)
† The goto JA and call JA instructions should not be placed in the last or next-to-last instruction before the boundary of a 4 Kwords page. If
the goto or call is placed there, the program counter will have incremented to the next page and the jump will be to the next page, rather than
to the desired current page.
‡ The icall instruction is reserved for development system use.
The above control instructions, with the exception of ireturn and icall, can be conditionally executed. For example:
if le goto 0x0345
Table 16. Replacement Table for Control Instructions
Replace
CON
JA
40
Value
mi, pl, eq, ne, gt, le, nlvs, lvc, mvs, mvc, c0ge, c0lt,
c1ge, c1lt, heads, tails, true, false, allt, allf, somet,
somef, oddp, evenp, mns1, nmns1, npint, njint, lock
12-bit value
Meaning
See Table 17 for definitions of mnemonics.
Least significant 12 bits of absolute address
within the same 4 Kwords memory section.
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Conditional Mnemonics (Flags)
Table 17 lists mnemonics used in conditional execution of special function and control instructions.
Table 17. DSP1629 Conditional Mnemonics
Test
pl
eq
gt
lvs
mvs
c0ge
c1ge
heads
true
allt
somet
oddp
mns1
npint
lock
Meaning
Result is nonnegative (sign bit is bit 35). ≥ 0
Result is equal to 0. = 0
Result is greater than 0. > 0
Logical overflow set.*
Mathematical overflow set.†
Counter 0 greater than or equal to 0.
Counter 1 greater than or equal to 0.
Pseudorandom sequence bit set.
The condition is always satisfied in an if instruction.
All True, all BIO input bits tested compared
successfully.
Some True, some BIO input bits tested compared successfully.
Odd Parity, from BMU operation.
Minus 1, result of BMU operation.
Not PINT, used by hardware development
system.
The PLL has achieved lock and is stable.
Test
mi
ne
le
lvc
mvc
c0lt
c1lt
tails
false
allf
somef
evenp
nmns1
njint
—
Meaning
Result is negative. < 0
Result is not equal to 0. ≠ 0
Result is less than or equal to 0. ≤ 0
Logical overflow clear.
Mathematical overflow clear.
Counter 0 less than 0.
Counter 1 less than 0.
Pseudorandom sequence bit clear.
The condition is never satisfied in an if instruction.
All False, no BIO input bits tested compared
successfully.
Some False, some BIO input bits tested did
not compare successfully.
Even Parity, from BMU operation.
Not Minus 1, result of BMU operation.
Not JINT, used by hardware development
system.
—
* Result is not representable in the 36-bit accumulators (36-bit overflow).
† Bits 35—31 are not the same (32-bit overflow).
Notes:
Testing the state of the counters (c0 or c1) automatically increments the counter by one.
The heads or tails condition is determined by a randomly set or cleared bit, respectively. The bit is randomly set with a probability of 0.5. A random
rounding function can be implemented with either heads or tails. The random bit is generated by a ten-stage pseudorandom sequence generator
(PSG) that is updated after either a heads or tails test. The pseudorandom sequence may be reset by writing any value to the pi register, except
during an interrupt service routine (ISR). While in an ISR, writing to the pi register updates the register and does not reset the PSG. If not in an
ISR, writing to the pi register resets the PSG. (The pi register is updated, but will be written with the contents of the PC on the next instruction.)
Interrupts must be disabled when writing to the pi register. If an interrupt is taken after the pi write, but before pi is updated with the PC value,
the ireturn instruction will not return to the correct location. If the RAND bit in the auc register is set, however, writing the pi register never resets
the PSG.
Lucent Technologies Inc.
41
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
F3 ALU Instructions
These instructions are implemented in the DSP1600 core. They allow accumulator two-operand operations with either another accumulator, the p register, or a 16-bit immediate operand (IM16). The result is placed in a destination
accumulator that can be independently specified. All operations are done with the full 36 bits. For the accumulator
with accumulator operations, both inputs are 36 bits. For the accumulator with p register operations, the p register
is sign-extended into bits 35—32 before the operation. For the accumulator high with immediate operations, the immediate is sign-extended into bits 35—32 and the lower bits 15—0 are filled with zeros, except for the AND operation, for which they are filled with ones. These conventions allow the user to do operations with 32-bit immediates
by programming two consecutive 16-bit immediate operations. The F3 ALU instructions are shown in Table 18.
Table 18. F3 ALU Instructions
F3 ALU Instructions*
Cachable (One-Cycle)
aD = aS + aT
aD = aS – aT
aD = aS & aT
aD = aS | aT
aD = aS ^ aT
aS – aT
aS & aT
aD = aS + p
aD = aS – p
aD = aS & p
aD = aS | p
aD = aS ^ p
aS – p
aS & p
Not Cachable (Two-Cycle)†
aD = aSh + IM16
aD = aSh – IM16
aD = aSh & IM16
aD = aSh | IM16
aD = aSh ^ IM16
aSh – IM16
aSh & IM16
aD = aSl + IM16
aD = aSl – IM16
aD = aSl & IM16
aD = aSl | IM16
aD = aSl ^ IM16
aSl – IM16
aSl & IM16
* If PC points to external memory, add programmed wait-states.
† The h and l are required notation in these instructions.
Note: The F3 ALU instructions that do not have a destination accumulator are used to set flags for conditional operations, i.e., bit test operations.
F4 BMU Instructions
The bit manipulation unit in the DSP1629 provides a set of efficient bit manipulation operations on accumulators. It
contains four auxiliary registers, ar<0—3> (arM, M = 0, 1, 2, 3), two alternate accumulators (aa0—aa1), which can
be shuffled with the working set, and four flags (oddp, evenp, mns1, and nmns1). The flags are testable by conditional instructions and can be read and written via bits 4—7 of the alf register. The BMU also sets the LMI, LEQ,
LLV, and LMV flags in the psw register.
LMI = 1 if negative (i.e., bit 35 = 1)
LEQ = 1 if zero (i.e., bits 35—0 are 0)
LLV = 1 if (a) 36-bit overflow, or if (b) illegal shift on field width/offset condition
LMV = 1 if bits 31—35 are not the same (32-bit overflow)
The BMU instructions and cycle times follow. (If PC points to external memory, add programmed wait-states.) All
BMU instructions require 1 word of program memory unless otherwise noted. Please refer to the DSP1611/17/18/
27 Digital Signal Processor Information Manual for further discussion of the BMU instructions.
42
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
■
Barrel Shifter:
aD = aS >> IM16
Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word.
aD = aS >> arM
Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle.
aD = aS >> aS
Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle.
aD = aS >>> IM16
Logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word.
aD = aS >>> arM
Logical right shift by arM (32-bit shift, 0s filled in); 1-cycle.
aD = aS >>> aS
Logical right shift by aS (32-bit shift, 0s filled in); 2-cycle.
aD = aS << IM16
Arithmetic left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.
aD = aS << arM
Arithmetic left shift by arM (36-bit shift, 0s filled in); 1-cycle.
aD = aS << aS
Arithmetic left shift by aS (36-bit shift, 0s filled in); 2-cycle.
aD = aS <<< IM16
Logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.
aD = aS <<< arM
Logical left shift by arM (36-bit shift, 0s filled in); 1-cycle.
aD = aS <<< aS
Logical left shift by aS (36-bit shift, 0s filled in); 2-cycle.
†
†
†
† Not the same as the special function arithmetic left shift. Here, the guard bits in the destination accumulator are shifted into, not sign-extended.
■
■
Normalization and Exponent Computation:
aD = exp(aS)
Detect the number of redundant sign bits in accumulator; 1-cycle.
aD = norm(aS, arM)
Normalize aS with respect to bit 31, with exponent in arM; 1-cycle.
Bit Field Extraction and Insertion:
aD = extracts(aS, IM16) Extraction with sign extension, field specified as immediate; 2-cycle, 2-word.
aD = extracts(aS, arM) Extraction with sign extension, field specified in arM; 1-cycle.
aD = extractz(aS, IM16) Extraction with zero extension, field specified as immediate; 2-cycle, 2-word.
aD = extractz(aS, arM) Extraction with zero extension, field specified in arM; 1-cycle.
aD = insert(aS, IM16)
Bit field insertion, field specified as immediate; 2-cycle, 2-word.
aD = insert(aS, arM)
Bit field insertion, field specified in arM; 2-cycle.
Note: The bit field to be inserted or extracted is specified as follows. The width (in bits) of the field is the upper byte
of the operand (immediate or arM), and the offset from the LSB is in the lower byte.
■
Alternate Accumulator Set:
aD = aS:aa0
Shuffle accumulators with alternate accumulator 0 (aa0); 1-cycle.
aD = aS:aa1
Shuffle accumulators with alternate accumulator 1 (aa1); 1-cycle.
Note: The alternate accumulator gets what was in aS. aD gets what was in the alternate accumulator.
Table 19. Replacement Table for F3 ALU Instructions and F4 BMU Instructions
Replace
aD, aT, aS
IM16
arM
Lucent Technologies Inc.
Value
a0 or a1
immediate
ar<0—3>
Meaning
One of the two accumulators.
16-bit data, sign-, zero-, or one-extended as appropriate.
One of the auxiliary BMU registers.
43
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Cache Instructions
Cache instructions require one word of program memory. The do instruction executes in one instruction cycle, and
the redo instruction executes in two instruction cycles. (If PC points to external memory, add programmed waitstates.) Control instructions and long immediate values cannot be stored inside the cache. The instruction formats
are as follows:
■
do K {
■
instr1
■
instr2
■
.
■
.
■
.
■
instrN
■
}
■
redo K
Table 20. Replacement Table for Cache Instructions
Replace
K
Instruction
Encoding
cloop†
N
1 to 127
1 to 15
Meaning
Number of times the instructions are to be executed taken from bits 0—6 of the cloop
register.
Number of times the instructions to be executed is encoded in the instruction.
1 to 15 instructions can be included.
† The assembly-language statement, do cloop (or redo cloop), is used to specify that the number of iterations is to be taken from the cloop
register. K is encoded as 0 in the instruction encoding to select cloop.
When the cache is used to execute a block of instructions, the cycle timings of the instructions are as follows:
1. In the first pass, the instructions are fetched from program memory and the cycle times are the normal out-ofcache values, except for the last instruction in the block of N instructions. This instruction executes in two cycles.
2. During pass two through pass K – 1, each instruction is fetched from cache and the in-cache timings apply.
3. During the last (Kth) pass, the block of instructions is fetched from cache and the in-cache timings apply, except
that the timing of the last instruction is the same as if it were out-of-cache.
4. If any of the instructions access external memory, programmed wait-states must be added to the cycle counts.
The redo instruction treats the instructions currently in the cache memory as another loop to be executed K times.
Using the redo instruction, instructions are reexecuted from the cache without reloading the cache.
The number of iterations, K, for a do or redo can be set at run time by first moving the number of iterations into the
cloop register (7 bits unsigned), and then issuing the do cloop or redo cloop. At the completion of the loop, the
value of cloop is decremented to 0; hence, cloop needs to be written before each do cloop or redo cloop.
44
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Data Move Instructions
Data move instructions normally execute in two instruction cycles. (If PC or rM point to external memory, any programmed wait-states must be added. In addition, if PC and rM point to the same bank of DPRAM, then one cycle
must be added.) Immediate data move instructions require two words of program memory; all other data move instructions require only one word. The only exception to these statements is a special case immediate load (short
immediate) instruction. If a YAAU register is loaded with a 9-bit short immediate value, the instruction requires only
one word of memory and executes in one instruction cycle. All data move instructions, except those doing long immediate loads, can be executed from within the cache. The data move instructions are as follows:
■
R = IM16
■
aT[l] = R
■
SR = IM9
■
Y=R
■
R=Y
■
Z:R
■
R = aS[l]
■
DR = *(OFFSET)
■
(OFFSET) = DR
Table 21. Replacement Table for Data Move Instructions
Replace
R
DR
aS, aT
Y
Value
Meaning
—
Any of the registers in Table 51
r<0—3>, a0[l], a1[l], y[l], p, pl, x, Subset of registers accessible with direct addressing.
pt, pr, psw
a0, a1
High half of accumulator.
rM,
rM++,
rM--,
rM++j
Same as in multiply/ALU instructions.
*
*
*
*
Z
*rMzp, *rMpz, *rMm2, *rMjk
Same as in multiply/ALU instructions.
IM16
IM9
OFFSET
16-bit value
9-bit value
5-bit value from instruction
11-bit value in base register
SR
r<0—3>, rb, re, j, k
Long immediate data.
Short immediate data for YAAU registers.
Value in bits [15:5] of ybase register form the 11 most significant
bits of the base address. The 5-bit offset is concatenated to this to
form a 16-bit address.
Subset of registers for short immediate.
Notes:
sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable.
When signed registers less than 16 bits wide (c0, c1, c2) are read, their contents are sign-extended to 16 bits. When unsigned registers less than
16 bits wide are read, their contents are zero-extended to 16 bits.
Loading an accumulator with a data move instruction does not affect the flags.
Lucent Technologies Inc.
45
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
5.2 Register Settings
Tables 22 through 38 describe the programmable registers of the DSP1629 device. Table 40 describes the register
settings after reset.
Note that the following abbreviations are used in the tables:
■
x = don't care
■
R = read only
■
W = read/write
The reserved (RSVD) bits in the tables should always be written with zeros to make the program compatible with
future chip versions.
Table 22. Serial I/O Control Registers
sioc
Bit
Field
10
DODLY
9
LD
Field
DODLY
Value
0
1
LD
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK
MSB
OLD
ILD
OCK
ICK
OLEN
ILEN
8
7
CLK
6
MSB
5
OLD
4
ILD
3
OCK
2
ICK
1
OLEN
0
ILEN
Description
DO changes on the rising edge of OCK.
DO changes on the falling edge of OCK. This delay in driving DO increases the hold
time on DO by half a cycle of OCK.
In active mode, ILD1 and/or OLD1 = ICK1/16, active SYNC1 = ICK1/[128/256*].
In active mode, ILD1 and/or OLD1 = OCK1/16, active SYNC1 = OCK1/[128/256*].
Active clock = CKI/2 (1X).
Active clock = CKI/6 (1X).
Active clock = CKI/8 (1X).
Active clock = CKI/10 (1X).
LSB first.
MSB first.
OLD1 is an input (passive mode).
OLD1 is an output (active mode).
ILD1 is an input (passive mode).
ILD1 is an output (active mode).
OCK1 is an input (passive mode).
OCK1 is an output (active mode).
ICK1 is an input (passive mode).
ICK1 is an output (active mode).
16-bit output.
8-bit output.
16-bit input.
8-bit input.
* See tdms register, SYNC field.
sioc2†
Bit
Field
10
DODLY2
9
LD2
8
7
CLK2
6
MSB2
5
OLD2
4
ILD2
3
OCK2
2
ICK2
1
OLEN2
0
ILEN2
† The bit definitions of the sioc2 register are identical to the sioc register bit definitions.
46
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 23. Time-Division Multiplex Slot Registers
tdms
Bit
Field
9
SYNCSP
8
MODE
Field
Value
SYNCSP*
0
†
1
MODE
TRANSMIT SLOT
SYNC
0
1
1xxxxxx
x1xxxxx
xx1xxxx
xxx1xxx
xxxx1xx
xxxxx1x
xxxxxx1
1
0
7
6
5
4
3
TRANSMIT SLOT
2
1
0
SYNC
Description
SYNC1 = ICK1/128 if LD = 0*.
SYNC1 = OCK1/128 if LD = 1*.
SYNC1 = ICK1/256 if LD = 0*.
SYNC1 = OCK1/256 if LD = 1*.
Multiprocessor mode off; DOEN1 is an input (passive mode).
Multiprocessor mode on; DOEN1 is an output (active mode).
Transmit slot 7.
Transmit slot 6.
Transmit slot 5.
Transmit slot 4.
Transmit slot 3.
Transmit slot 2.
Transmit slot 1.
Transmit slot 0, SYNC1 is an output (active mode).
SYNC1 is an input (passive mode).
* See sioc register, LD field.
tdms2‡
Bit
Field
9
SYNCSP2*
8
MODE2
7
6
5
4
3
TRANSMIT SLOT2
2
1
0
SYNC2
* See sioc register, LD field.
† Select this mode when in multiprocessor mode.
‡ The tdms2 register bit definitions are identical to the tdms register bit definitions.
Lucent Technologies Inc.
47
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 24. Serial Receive/Transmit Address Registers
srta
Bit
Field
15
14
13
12
11
10
RECEIVE ADDRESS
Field
RECEIVE ADDRESS
TRANSMIT ADDRESS
9
Value
1xxxxxxx
x1xxxxxx
xx1xxxxx
xxx1xxxx
xxxx1xxx
xxxxx1xx
xxxxxx1x
xxxxxxx1
1xxxxxxx
x1xxxxxx
xx1xxxxx
xxx1xxxx
xxxx1xxx
xxxxx1xx
xxxxxx1x
xxxxxxx1
8
7
6
5
4
3
2
TRANSMIT ADDRESS
1
0
1
0
Description
Receive address 7.
Receive address 6.
Receive address 5.
Receive address 4.
Receive address 3.
Receive address 2.
Receive address 1.
Receive address 0.
Transmit address 7.
Transmit address 6.
Transmit address 5.
Transmit address 4.
Transmit address 3.
Transmit address 2.
Transmit address 1.
Transmit address 0.
srta2*
Bit
Field
15
14
13
12
11
10
RECEIVE ADDRESS2
9
8
7
6
5
4
3
2
TRANSMIT ADDRESS2
* The srta2 field definitions are identical to the srta register field definitions.
Table 25. Multiprocessor Protocol Registers
saddx
Bit Field
Write
Read
15—8
X
Read Protocol Field [7:0]
7—0
Write Protocol Field [7:0]
0
15—8
X
Read Protocol2 Field [7:0]
7—0
Write Protocol2 Field [7:0]
0
saddx2†
Bit Field
Write
Read
† The saddx2 field definitions are identical to the saddx register field definitions.
48
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 26. Processor Status Word (psw) Register
Bit
Field
15
14
13
DAU FLAGS
Field
12
11
X
Value
Wxxx
xWxx
xxWx
xxxW
W
Wxxx
xWxx
xxWx
xxxW
W
Wxxx
xWxx
xxWx
xxxW
*
DAU FLAGS
a1[V]
a1[35:32]
a0[V]
a0[35:32]
10
X
9
a1[V]
8
7
6
a1[35:32]
5
4
a0[V]
3
2
1
0
a0[35:32]
Description
LMI—logical minus when set (bit 35 = 1).
LEQ—logical equal when set (bit [35:0] = 0).
LLV—logical overflow when set.
LMV— mathematical overflow when set.
Accumulator 1 (a1) overflow when set.
Accumulator 1 (a1) bit 35.
Accumulator 1 (a1) bit 34.
Accumulator 1 (a1) bit 33.
Accumulator 1 (a1) bit 32.
Accumulator 0 (a0) overflow when set.
Accumulator 0 (a0) bit 35.
Accumulator 0 (a0) bit 34.
Accumulator 0 (a0) bit 33.
Accumulator 0 (a0) bit 32.
* The DAU flags can be set by either BMU or DAU operations.
Table 27. Arithmetic Unit Control (auc) Register†
Bit
Field
8
RAND
7
X=Y=
6
Field
RAND
Value
0
X=Y=
1
0
1
CLR
SAT
ALIGN
1xx
x1x
xx1
1x
x1
00
01
10
11
5
CLR
4
3
2
SAT
1
0
ALIGN
Description
Pseudorandom sequence generator (PSG) reset by writing the pi
register only outside an interrupt service routine.
PSG never reset by writing the pi register.
Normal operation.
All instructions which load the high half of the y register also load
the x register, allowing single-cycle squaring with p = x * y.
Clearing yl is disabled (enabled when 0).
Clearing a1l is disabled (enabled when 0).
Clearing a0l is disabled (enabled when 0).
a1 saturation on overflow is disabled (enabled when 0).
a0 saturation on overflow is disabled (enabled when 0).
a0, a1 ← p.
a0, a1 ← p/4.
a0, a1 ← p x 4 (and zeros written to the two LSBs).
a0, a1 ← p x 2 (and zero written to the LSB).
† The auc is 9 bits [8:0]. The upper 7 bits [15:9] are always zero when read and should always be written with zeros to make the program
compatible with future chip versions. The auc register is cleared at reset.
Lucent Technologies Inc.
49
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 28. Parallel Host Interface Control (phifc) Register
Bit
Field
15—7
RSVD
6
PSOBEF
Field
Value
PMODE
0
1
0
1
0
1
0
1
PSTROBE
PSTRB
PBSELF
PFLAG
PFLAGSEL
PSOBEF
0
1
0
1
0
1
5
PFLAGSEL
4
PFLAG
3
PBSELF
2
PSTRB
1
PSTROBE
0
PMODE
Description
8-bit data transfers.
16-bit data transfers.
Intel protocol: PIDS and PODS data strobes.
Motorola protocol: PRWN and PDS data strobes.
When PSTROBE = 1, PODS pin (PDS) active-low.
When PSTROBE = 1, PODS pin (PDS) active-high.
In either mode, PBSEL pin = 0 → pdx0 low byte. See Table 7.
If PMODE = 0, PBSEL pin = 1 → pdx0 low byte.
If PMODE = 1, PBSEL pin = 0 → pdx0 high byte.
PIBF and POBE pins active-high.
PIBF and POBE pins active-low.
Normal.
PIBF flag ORed with POBE flag and output on PIBF pin; POBE pin unchanged (output buffer empty).
Normal.
POBE flag as read through PSTAT register is active-low.
Table 29. Interrupt Control (inc) Register
Bit
Field
15
JINT*
14—11
RSVD
10
OBE2
9
IBF2
8
TIME
7—6
RSVD
5—4
INT[1:0]
3
PIBF
2
POBE
1
OBE
0
IBF
* JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Lucent Technologies development system tools.
Encoding: A 0 disables an interrupt; a 1 enables an interrupt.
Table 30. Interrupt Status (ins) Register
Bit
Field
15
JINT
14—11
RSVD
10
OBE2
9
IBF2
8
TIME
7—6
RSVD
5—4
INT[1:0]
3
PIBF
2
POBE
1
OBE
0
IBF
Encoding: A 0 indicates no interrupt. A 1 indicates an interrupt has been recognized and is pending or being serviced. If a 1 is written to bits 4, 5, or 8 of ins, the corresponding interrupt is cleared.
50
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 31. timerc Register
Bit
Field
15—7
RSVD
Field
DISABLE
6
DISABLE
Value
0
1
0
1
0
1
—
RELOAD
T0EN
PRESCALE
5
RELOAD
4
T0EN
3—0
PRESCALE
Description
Timer enabled.
Timer and prescaler disabled. The period register and timer0 are not reset.
Timer stops after counting down to 0.
Timer automatically reloads and repeats indefinitely.
Timer holds current count.
Timer counts down to 0.
See table below.
PRESCALE Field
PRESCALE
0000
0001
0010
0011
0100
0101
0110
0111
Frequency of
Timer Interrupts
CKO/2
CKO/4
CKO/8
CKO/16
CKO/32
CKO/64
CKO/128
CKO/256
PRESCALE
1000
1001
1010
1011
1100
1101
1110
1111
Frequency of
Timer Interrupts
CKO/512
CKO/1024
CKO/2048
CKO/4096
CKO/8192
CKO/16384
CKO/32768
CKO/65536
Table 32. Phase-Locked Loop Control (pllc) Register
Bit
Field
Field
PLLEN
PLLSEL
ICP
RSVD
LF[3:0]
Nbits[2:0]
Mbits[4:0]
15
PLLEN
Value
0
1
0
1
—
0
—
—
—
Lucent Technologies Inc.
14
PLLSEL
13
ICP
12
RSVD
11—8
LF[3:0]
7—5
Nbits[2:0]
4—0
Mbits[4:0]
Description
PLL powered down.
PLL powered up.
DSP internal clock taken directly from CKI.
DSP internal clock taken from PLL.
Charge pump current selection (see Table 64 for proper value).
—
Loop filter setting (see Table 64 for proper value).
Encodes N, 1 ≤ N ≤ 8, where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111, then N = 1.
Encodes M, 2 ≤ M ≤ 20, where M = Mbits[4:0] + 2, fINTERNAL CLOCK = fCKI x (M/(2N)).
51
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 33. sbit Register
Bit
Field
15
14
Field
DIREC
VALUE
13
12
11
DIREC[7:0]
Value
1xxxxxxx
x1xxxxxx
xx1xxxxx
xxx1xxxx
xxxx1xxx
xxxxx1xx
xxxxxx1x
xxxxxxx1
Rxxxxxxx
xRxxxxxx
xxRxxxxx
xxxRxxxx
xxxxRxxx
xxxxxRxx
xxxxxxRx
xxxxxxxR
10
9
8
7
6
5
4
3
VALUE[7:0]
2
1
0
Description
IOBIT7 is an output (input when 0).
IOBIT6 is an output (input when 0).
IOBIT5 is an output (input when 0).
IOBIT4 is an output (input when 0).
IOBIT3 is an output (input when 0).
IOBIT2 is an output (input when 0).
IOBIT1 is an output (input when 0).
IOBIT0 is an output (input when 0).
Reads the current value of IOBIT7.
Reads the current value of IOBIT6.
Reads the current value of IOBIT5.
Reads the current value of IOBIT4.
Reads the current value of IOBIT3.
Reads the current value of IOBIT2.
Reads the current value of IOBIT1.
Reads the current value of IOBIT0.
Table 34. cbit Register
Bit
Field
15
14
13
12
MODE/MASK[7:4]
11
10
9
8
MODE/MASK[3:0]
7
6
5
4
DATA/PAT[7:4]
3
2
1
0
DATA/PAT[3:0]
DIREC[n]*
MODE/MASK[n]
DATA/PAT[n]
Action
1 (Output)
1 (Output)
1 (Output)
1 (Output)
0 (Input)
0 (Input)
0 (Input)
0 (Input)
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Clear
Set
No Change
Toggle
No Test
No Test
Test for Zero
Test for One
* 0 ≤ n ≤ 7.
52
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 35. alf Register
Bit
Field
15
AWAIT
Field
AWAIT
Value
1
0
1
0
—
LOWPR
FLAGS
14
LOWPR
13—0
FLAGS
Action
Power-saving standby mode or standard sleep enabled.
Normal operation.
The internal DPRAM is addressed beginning at 0x0000 in X space.
The internal DPRAM is addressed beginning at 0xc000 in X space.
See table below.
Bit
13—8
7
6
5
4
3
2
1
0
Flag
Reserved
nmns1
mns1
evenp
oddp
somef
somet
allf
allt
Use
—
NOT-MINUS-ONE from BMU
MINUS-ONE from BMU
EVEN PARITY from BMU
ODD PARITY from BMU
SOME FALSE from BIO
SOME TRUE from BIO
ALL FALSE from BIO
ALL TRUE from BIO
Table 36. mwait Register
Bit
Field
15—12
EROM[3:0]
11—8
ERAMHI[3:0]
7—4
IO[3:0]
3—0
ERAMLO[3:0]
If the EXM pin is high and the INT1 is low upon reset, the mwait register is initialized to all 1s (15 wait-states for all
external memory). Otherwise, the mwait register is initialized to all 0s (0 wait-states) upon reset.
Table 37. DSP1629 32-Bit JTAG ID Register
Bit
Field
31
RSVD
Field
RSVD
SECURE
30
SECURE
ROMCODE
Value
0
0
1
01
11
—
PART ID
0x29
CLOCK
ROMCODE Letter
Value
A
0
Lucent Technologies Inc.
B
1
29—28
CLOCK
27—19
ROMCODE
18—12
PART ID
11—0
0x03B
Mask-Programmable Features
—
Nonsecure ROM option.
Secure ROM option.
Small-signal input clock option.
CMOS level input clock option.
Users ROMCODE ID:
The ROMCODE ID is the 9-bit binary value of the following expression:
(20 x value for first letter) + (value of second letter), where the values of the letters
are in the following table. For example, ROMCODE GK is (20 x 6) + (9) = 129
or 0 1000 0001.
DSP1629.
C
2
D
3
E
4
F
5
G
6
H
7
J
8
K
9
L M N P R S T U W Y
10 11 12 13 14 15 16 17 18 19
53
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 38. ioc Register*
Bit
Field
15
RSVD
14
13
12
EXTROM CKO2 EBIOH
11
WEROM
10
ESIO2
9
SIOLBC
8—7
CKO[1:0]
6—4
RSVD
3—0
DENB[3:0]
* The field definitions for the ioc register are different from the DSP1610.
ioc Fields
ioc Field
EXTROM
CKO2
EBIOH
WEROM
ESIO2
SIOLBC
CKO[1:0]
DENB3
DENB2
DENB1
DENB0
Description
If 1, sets AB15 low during external memory accesses when WEROM = 1.
CKO configuration (see below).
If 1, enables high half of BIO, IOBIT[4:7], and disables VEC[3:0] from pins.
If 1, allows writing into external program (X) memory.
If 1, enables SIO2 and low half of BIO, and disables PHIF from pins.
If 1, DO1 and DO2 looped back to DI1 and DI2.
CKO configuration (see below).
If 1, delay EROM.
If 1, delay ERAMHI.
If 1, delay IO.
If 1, delay ERAMLO.
CKO2
—
0
0
CKO1
—
0
0
CKO0
—
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1X
CKI
CKI/(1 + W)
1
0
CKI
CKI/(1 + W)
CKO Output
PLL
CKI x M/(2N)
CKI x (M/(2N)) / [1 + W]
1
0
CKI
CKI x (M/(2N)) / [1 + W]
Reserved
Reserved
Description
—
Free-running clock.*,
†
Wait-stated clock.*, †, ‡
Held high.
Held low.
Output of CKI buffer.
Sequenced, wait-stated clock.*, †, ‡, **
* The phase of CKI is synchronized by the rising edge of RSTB.
† When SLOWCKI is enabled in the powerc register, these options reflect the low-speed internal ring oscillator.
‡ The wait-stated clock reflects the internal instruction cycle and may be stretched based on the mwait register setting (see Table 36). During
sequenced external memory accesses, it completes one cycle.
** The sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based on the mwait
register setting (see Table 36).
54
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 39. powerc Register
The powerc register configures various power management modes.
Bit
15
14
13
12
11
10
9—8
7
6
5
4
3—0
Field XTLOFF SLOWCKI NOCK INT0EN RSVD INT1EN RSVD SIO1DIS SIO2DIS PHIFDIS TIMERDIS RSVD
Note: The reserved (RSVD) bits should always be written with zeros to make the program compatible with future chip versions.
powerc fields
Field
XTLOFF
SLOWCKI
NOCK
INT0EN
INT1EN
SIO1DIS
SIO2DIS
PHIFDIS
TIMERDIS
Description
1 = powerdown small-signal clock input.
1 = select ring oscillator clock (internal slow clock).
1 = disable internal processor clock.
1 = INT0 clears NOCK field.
1 = INT1 clears NOCK field.
1 = disable SIO1.
1 = disable SIO2.
1 = disable PHIF.
1 = disable timer.
A • indicates that this bit is unknown on powerup reset and unaffected on subsequent reset. An S indicates that this
bit shadows the PC. P indicates the value on an input pin, i.e., the bit in the register reflects the value on the corresponding input pin.
Table 40. Register Settings After Reset
Register
r0
r1
r2
r3
j
k
Bits 15—0
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
Register
inc
ins
sdx2
saddx
cloop
mwait
Bits 15—0
0000000000000000
0000010000000110
••••••••••••••••
••••••••••••••••
000000000•••••••
rb
re
pt
pr
pi
i
p
pl
x
y
yl
auc
psw
c0
c1
c2
sioc
0000000000000000
0000000000000000
••••••••••••••••
••••••••••••••••
SSSSSSSSSSSSSSSS
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
0000000000000000
••••00••••••••••
••••••••••••••••
•••••••••••••••
••••••••••••••••
••••••0000000000
saddx2
sioc2
cbit
sbit
ioc
jtag
0000000000000000
••••••••••••••••
••••••0000000000
••••••••••••••••
00000000PPPPPPPP
0000000000000000
••••••••••••••••
a0
a0l
a1
a1l
timerc
timer0
tdms2
srta2
powerc
pllc
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••00000000
0000000000000000
••••••0000000000
••••••••••••••••
0000000000000000
0000000000000000
srta
sdx
tdms
phifc
pdx0
ybase
••••••••••••••••
••••••••••••••••
••••••0000000000
0000000000000000
0000000000000000
••••••••••••••••
ar0
ar1
ar2
ar3
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
alf
00000000••••••••
†
† If EXM is high and INT1 is low when RSTB goes high, mwait will contain all ones instead of all zeros.
Lucent Technologies Inc.
55
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
5.3 Instruction Set Formats
This section defines the hardware-level encoding of the DSP1629 device instructions.
Multiply/ALU Instructions
Format 1: Multiply/ALU Read/Write Group
Field
Bit
15
T
13
14
12
D
10
11
S
9
F1
8
7
8
7
8
7
8
7
6
5
X
4
3
2
Y
6
5
X
4
3
2
6
5
X
4
3
2
6
5
X
4
3
3
1
0
1
0
1
0
2
1
0
CON
2
1
0
aT
0
1
2
1
0
Format 1a: Multiply/ALU Read/Write Group
Field
Bit
15
T
13
14
12
aT
10
11
S
9
F1
Y
Format 2: Multiply/ALU Read/Write Group
Field
Bit
15
T
13
14
12
D
10
11
S
9
F1
Y
Format 2a: Multiply/ALU Read/Write Group
Field
Bit
15
T
13
14
12
aT
10
11
S
9
F1
Y
Special Function Instructions
Format 3: F2 ALU Special Functions
Field
Bit
15
T
13
14
12
11
D
10
S
9
F2
11
D
S
F3
Immediate Operand (IM16)
10
9
8
7
6
8
7
6
5
4
Format 3a: F3 ALU Operations
Field
Bit
T
15
14
13
12
SRC2
5
4
3
Format 3b: BMU Operations
Field
Bit
56
T
15
14
13
12
11
D
S
F4[3—1]
Immediate Operand (IM16)
10
9
8
7
6
0
F4[0]
5
4
AR
3
2
1
0
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Control Instructions
Format 4: Branch Direct Group
Field
Bit
T
15
14
JA
13
12
11
10
9
8
7
6
5
11
10
B
9
8
7
6
5
4
3
2
1
0
Reserved
4
3
2
1
1
0
1
0
Format 5: Branch Indirect Group
Field
Bit
15
14
T
13
12
0
0
Format 6: Conditional Branch Qualifier/Software Interrupt (icall)
Note that a branch instruction immediately follows except for a software interrupt (icall).
Field
Bit
15
14
T
13
12
11
SI
10
12
11
aT
10
Reserved
8
7
9
6
5
4
CON
3
2
6
5
4
3
Data Move Instructions
Format 7: Data Move Group
Field
Bit
15
14
T
13
R
9
8
7
Y/Z
2
Format 8: Data Move (immediate operand—2 words)
Field
Bit
T
15
14
13
D
12
11
R
Immediate Operand (IM16)
9
8
7
6
5
10
Reserved
4
3
2
1
0
1
0
0
0
Format 9: Short Immediate Group
Field
Bit
15
14
T
13
I
12
11
10
9
9
9
8
7
Short Immediate Operand (IM9)
6
5
4
3
2
Format 9a: Direct Addressing
Field
Bit
15
14
T
13
12
11
R/W
10
T
13
12
11
10
DR
8
7
6
1
5
8
7
6
5
4
OFFSET
3
2
1
4
K
3
Cache Instructions
Format 10: Do/Redo
Field
Bit
15
14
Lucent Technologies Inc.
N
2
1
57
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 43. aT Field
Specifies transfer accumulator.
Field Descriptions
aT
0
1
Table 41. T Field
Specifies the type of instruction.
T
0000x
00010
00011
00100
00101
00110
00111
01000
01000
01001
01001
01010
01011
01011
01100
01101
01110
01111
1000x
10010
10011
10100
10101
10110
10111
11000
11000
11001
11010
11011
11100
11101
11110
11110
11111
Operation
goto JA
Short imm j, k, rb, re
Short imm r0, r1, r2, r3
Y = a1[l]
F1
Z : aT[l]
F1
Y
F1
aT[l] = Y
F1
Bit 0 = 0, aT = R
Bit 0 = 1, aTl = R
Bit 10 = 0, R = a0
Bit 10 = 1, R = a0l
R = IM16
Bit 10 = 0, R = a1
Bit 10 = 1, R = a1l
Y=R
Z:R
do, redo
R=Y
call JA
ifc CON
F2
if CON
F2
Y = y[l]
F1
Z : y[l]
F1
x=Y
F1
y[l] = Y
F1
Bit 0 = 0, branch indirect
Bit 0 = 1, F3 ALU
y = a0 x = X
F1
Cond. branch qualifier
y = a1 x = X
F1
Y = a0[l]
F1
Z:y x=X
F1
Bit 5 = 0, F4 ALU (BMU)
Bit 5 = 1, direct addressing
y=Y x=X
F1
Table 42. D Field
Specifies a destination accumulator.
D
0
1
58
Register
Accumulator 0
Accumulator 1
Format
4
9
9
1
2a
1
1a
7
7
7
7
8
7
7
7
7
10
7
4
3
3
1
2
1
1
5
3a
1
6
1
1
2
3b
9a
1
Register
Accumulator 1
Accumulator 0
Table 44. S Field
Specifies a source accumulator.
S
0
1
Register
Accumulator 0
Accumulator 1
Table 45. F1 Field
Specifies the multiply/ALU function.
F1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operation
aD = pp = x * y
aD = aS + pp = x * y
p=x*y
aD = aS – pp = x * y
aD = p
aD = aS + p
nop
aD = aS – p
aD = aS | y
aD = aS ^ y
aS & y
aS – y
aD = y
aD = aS + y
aD = aS & y
aD = aS – y
Table 46. X Field
Specifies the addressing of ROM data in two-operand
multiply/ALU instructions. Specifies the high or low half
of an accumulator or the y register in one-operand multiply/ALU instructions.
X
Operation
Two-Operand Multiply/ALU
0
*pt++
1
*pt++i
One-Operand Multiply/ALU
0
aTl, yl
1
aTh, yh
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 49. F2 Field
Specifies the special function to be performed.
Table 47. Y Field
Specifies the form of register indirect addressing with
postmodification.
Y
0000
Operation
*r0
0001
*r0++
*r0--
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
*r0++j
*r1
*r1++
*r1-*r1++j
*r2
*r2++
*r2-*r2++j
*r3
1110
*r3++
*r3--
1111
*r3++j
Table 48. Z Field
Specifies the form of register indirect compound addressing with postmodification.
Z
0000
Operation
*r0zp
0001
*r0pz
0010
*r0m2
0011
*r0jk
0100
*r1zp
0101
*r1pz
0110
*r1m2
0111
*r1jk
1000
*r2zp
1001
*r2pz
1010
*r2m2
1011
*r2jk
1100
*r3zp
1101
*r3pz
1110
*r3m2
1111
*r3jk
Lucent Technologies Inc.
F2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operation
aD = aS >> 1
aD = aS << 1
aD = aS >> 4
aD = aS << 4
aD = aS >> 8
aD = aS << 8
aD = aS >> 16
aD = aS << 16
aD = p
aDh = aSh + 1
aD = ~aS
aD = rnd(aS)
aD = y
aD = aS + 1
aD = aS
aD = – aS
Table 50. CON Field
Specifies the condition for special functions and conditional control instructions.
CON
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
Condition
mi
pl
eq
ne
lvs
lvc
mvs
mvc
heads
tails
c0ge
c0lt
c1ge
c1lt
Other
codes
Reserved
CON
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
—
Condition
true
false
gt
le
allt
allf
somet
somef
oddp
evenp
mns1
nmns1
npint
njint
lock
—
59
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
Table 52. B Field
Table 51. R Field
Specifies the type of branch instruction (except software
interrupt).
Specifies the register for data move instructions.
R
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Register
r0
r1
r2
r3
j
k
rb
re
pt
pr
pi
i
p
pl
pllc
Reserved
x
y
yl
auc
psw
c0
c1
c2
sioc
srta
sdx
tdms
phifc
pdx0
Reserved
ybase
R
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Register
inc
ins
sdx2
saddx
cloop
mwait
saddx2
sioc2
cbit
sbit
ioc
jtag
Reserved
Reserved
Reserved
Reserved
a0
a0l
a1
a1l
timerc
timer0
tdms2
srta2
powerc
Reserved
ar0
ar1
ar2
ar3
Reserved
alf
B
000
001
010
011
1xx
Operation
return
ireturn
goto pt
call pt
Reserved
Table 53. DR Field
DR Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Register
r0
r1
r2
r3
a0
a0l
a1
a1l
y
yl
p
pl
x
pt
pr
psw
Table 54. I Field
Specifies a register for short immediate data move instructions.
I
00
01
10
11
Register
r0/j
r1/k
r2/rb
r3/re
Table 55. SI Field
Specifies when the conditional branch qualifier instruction should be interpreted as a software interrupt instruction.
SI
0
1
60
Operation
Not a software interrupt
Software interrupt
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
5 Software Architecture (continued)
N Field
Number of instructions to be loaded into the cache. Zero
implies redo operation.
K Field
Number of times the N instructions in cache are to be
executed. Zero specifies use of value in cloop register.
JA Field
12-bit jump address.
R/W Field
A zero specifies a write, *(O) = DR.
A one specifies a read, DR = *(O).
Table 56. F3 Field
Specifies the operation in an F3 ALU instruction.
F3
1000
1001
1010
1011
1101
1110
1111
aD = aS[h, l]
aD = aS[h, l]
aS[h, l]
aS[h, l]
aD = aS[h, l]
aD = aS[h, l]
aD = aS[h, l]
Operation
|
{aT, IM16, p}
^
{aT, IM16, p}
&
{aT, IM16, p}
–
{aT, IM16, p}
+
{aT, IM16, p}
&
{aT, IM16, p}
–
{aT, IM16, p}
Table 58. BMU Encodings
F4
0000
0001
0000
0001
1000
1001
1000
1001
1100
1101
1100
1101
0000
0001
1110
0010
1110
0010
1110
1010
0111
0111
AR
00xx
00xx
10xx
10xx
0000
0000
1000
1000
0000
0000
1000
1000
1100
11xx
0000
00xx
0100
01xx
1000
10xx
0000
0001
Operation
aD = aS >> arM
aD = aS << arM
aD = aS >>> arM
aD = aS <<< arM
aD = aS >> aS
aD = aS << aS
aD = aS >>> aS
aD = aS <<< aS
aD = aS >> IM16
aD = aS << IM16
aD = aS >>> IM16
aD = aS <<< IM16
aD = exp(aS)
aD = norm(aS, arM)
aD = extracts(aS, IM16)
aD = extracts(aS, arM)
aD = extractz(aS, IM16)
aD = extractz(aS, arM)
aD = insert(aS, IM16)
aD = insert(aS, arM)
aD = aS:aa0
aD = aS:aa1
Note: xx encodes the auxiliary register to be used; 00 (ar0), 01(ar1),
10 (ar2), or 11(ar3).
Table 57. SRC2 Field
Specifies operands in an F3 ALU instruction.
SRC2
00
10
01
11
Lucent Technologies Inc.
Operands
aSl, IM16
aSh, IM16
aS, aT
aS, p
61
Data Sheet
March 2000
DSP1629 Digital Signal Processor
6 Signal Descriptions
AB[15:0]
16
DB[15:0]
16
RWN
EXTERNAL
MEMORY
INTERFACE
EXM
2
4
EROM
ERAMHI
IO
RSTB
CKO
CKI2
CKI
STOP
INT[1:0]
VEC[3:0] OR IOBIT[4:7]
IACK
TRAP
SYSTEM
INTERFACE
OR
CONTROL I/O
INTERFACE
ERAMLO
PSTAT OR DO2
DSEL
PODS OR OLD2
PCSN OR OCK2
DO1
POBE OR OBE2
DSP1629
PBSEL OR SYNC2
OLD1
PB0 OR ICK2
OCK1
OBE1
SERIAL
INTERFACE #1
PIDS OR ILD2
PARALLEL HOST
INTERFACE
OR
SERIAL INTERFACE #2
AND CONTROL I/O
INTERFACE
PB1 OR DI2
DI1
ILD1
PIBF OR IBF2
ICK1
PB2 OR DOEN2
PB3 OR SADD2
IBF1
4
SYNC1
PB[7:4] OR IOBIT[3:O]
SADD1
DOEN1
TRST
JTAG TEST
INTERFACE
TDI
TDO
TCK
TMS
5-4006 (F).i
Figure 9. DSP1629 Pinout by Interface
Figure 9 shows the pinout for the DSP1629. The signals
can be separated into five interfaces as shown. These
interfaces and the signals that comprise them are described below.
6.1 System Interface
The system interface consists of the clock, interrupt,
and reset signals for the processor.
RSTB
Reset: Negative assertion. A high-to-low transition
causes the processor to enter the reset state. The auc,
powerc, sioc, sioc2, phifc, pdx0, tdms, tdms2, timerc,
timer0, sbit (upper byte), inc, ins (except OBE, OBE2,
62
and PODS status bits set), alf (upper 2 bits, AWAIT and
LOWPR), ioc, rb, and re registers are cleared. The
mwait register is initialized to all 0s (zero wait-states)
unless the EXM pin is high and the INT1 pin is low. In
that case, the mwait register is initialized to all 1s (15
wait-states).
Reset clears IACK, VEC[3:0]/IOBIT[4:7], IBF, and IBF2.
The DAU condition flags are not affected by reset.
IOBIT[7:0] are initialized as inputs. If any of the IOBIT
pins are switched to outputs (by writing sbit), their initial
value will be logic zero (see Table 40, Register Settings
After Reset).
Upon negation of the signal, the processor begins execution at location 0x0000 in the active memory map
(see Section 4.4, Memory Maps and Wait-States).
Lucent Technologies Inc.
Data Sheet
March 2000
6 Signal Descriptions (continued)
DSP1629 Digital Signal Processor
■
A free-running output clock that runs at the CKI rate,
independent of the powerc register setting. This option is only available with the small-signal clock options. When the PLL is selected, the CKO frequency
equals the input CKI frequency regardless of how the
PLL is programmed.
■
A logic 0.
■
A logic 1.
CKI
Input Clock: A mask-programmable option selects one
of three possible input buffers for the CKI pin (see Section 7, Mask-Programmable Options, and Table 1, Pin
Descriptions). The internal CKI from the output of the
selected input buffer can then drive the internal processor clock directly (1X) or drive the on-chip PLL (see Section 4.13). The PLL allows the CKI input clock to be at a
lower frequency than the internal processor clock.
CKI2
Input Clock 2: Used with mask-programmable input
clock options which require an external small signal differential across CKI and CKI2 (see Table 1, Pin Descriptions). When the CMOS option is selected, this pin
should be tied to VSSA.
STOP
Stop Input Clock: Negative assertion. A high-to-low
transition synchronously stops all of the internal processor clocks leaving the processor in a defined state. Returning the pin high will synchronously restart the
processor clocks to continue program execution from
where it left off without any loss of state. This hardware
feature has the same effect as setting the NOCK bit in
the powerc register (see Table 39).
CKO
Clock Out: Buffered output clock with options programmable via the ioc register (see Table 38). The selectable
CKO options (see Tables 38 and 29) are as follows:
■
A free-running output clock at the frequency of the internal processor clock; runs at the internal ring oscillator frequency when SLOWCKI is enabled.
■
A wait-stated clock based on the internal instruction
cycle; runs at the internal ring oscillator frequency
when SLOWCKI is enabled.
■
A sequenced, wait-stated clock based on the EMI sequencer cycle; runs at the internal ring oscillator frequency when SLOWCKI is enabled.
Lucent Technologies Inc.
INT[1:0]
Processor Interrupts 0 and 1: Positive assertion.
Hardware interrupt inputs to the DSP1629. Each is enabled via the inc register. When enabled and asserted,
each cause the processor to vector to the memory location described in Table 4. INT1 is used in conjunction
with EXM to select the desired reset initialization of the
mwait register (see Table 36). When both INT0 and
RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a
3-state condition.
VEC[3:0]
Interrupt Output Vector: These four pins indicate
which interrupt is currently being serviced by the device.
Table 4 shows the code associated with each interrupt
condition. VEC[3:0] are multiplexed with IOBIT[4:7].
IACK
Interrupt Acknowledge: Positive assertion. IACK
signals when an interrupt is being serviced by the
DSP1629. IACK remains asserted while in an interrupt
service routine, and is cleared when the ireturn instruction is executed.
TRAP
Trap Signal: Positive assertion. When asserted, the
processor is put into the trap condition, which normally
causes a branch to the location 0x0046. The hardware
development system (HDS) can configure the trap pin
to cause an HDS trap, which causes a branch to location 0x0003. Although normally an input, the pin can be
configured as an output by the HDS. As an output, the
pin can be used to signal an HDS breakpoint in a multiple processor environment.
63
Data Sheet
March 2000
DSP1629 Digital Signal Processor
6 Signal Descriptions (continued)
EROM
6.2 External Memory Interface
External ROM Enable Signal: Negative assertion.
When asserted, the signal indicates an access to external program memory (see Table 5, Instruction/Coefficient Memory Maps). This signal's leading edge can be
delayed via the ioc register (see Table 38).
The external memory interface is used to interface the
DSP1629 to external memory and I/O devices. It supports read/write operations from/to program and data
memory spaces. The interface supports four external
memory segments. Each external memory segment
can have an independent number of software-programmable wait-states. One hardware address is decoded,
and an enable line is provided, to allow glueless I/O interfacing.
AB[15:0]
External Memory Address Bus: Output only. This 16bit bus supplies the address for read or write operations
to the external memory or I/O. During external memory
accesses, AB[15:0] retain the value of the last valid external access.
DB[15:0]
External Memory Data Bus: This 16-bit bidirectional
data bus is used for read or write operations to the external memory or I/O.
RWN
Read/Write Not: When a logic 1, the pin indicates that
the memory access is a read operation. When a logic 0,
the memory access is a write operation.
ERAMHI
External RAM High Enable Signal: Negative assertion. When asserted, the signal indicates an access to
external data memory addresses 0x8000 through
0xFFFF (see Table 6, Data Memory Map). This signal's
leading edge can be delayed via the ioc register (see
Table 38).
ERAMLO
External RAM Low Enable Signal: Negative assertion. When asserted, the signal indicates an access to
external data memory addresses 0x4100 through
0x7FFF (see Table 6, Data Memory Map). This signal's
leading edge can be delayed via the ioc register (see
Table 38).
IO
External I/O Enable Signal: Negative assertion. When
asserted, the signal indicates an access to external data
memory addresses 0x4000 through 0x40FF (see
Table 6, Data Memory Map). This memory segment is
intended for memory-mapped I/O. This signal's leading
edge can be delayed via the ioc register (see Table 38).
EXM
External Memory Select: Input only. This signal is
latched into the device on the rising edge of RSTB. The
value of EXM latched in determines whether the internal
ROM is addressable in the instruction/coefficient memory map. If EXM is low, internal ROM is addressable. If
EXM is high, only external ROM is addressable in the
instruction/coefficient memory map (see Table 5, Instruction/Coefficient Memory Maps). EXM chooses between MAP1 or MAP2 and between MAP3 or MAP4.
64
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
6 Signal Descriptions (continued)
OCK1
6.3 Serial Interface #1
Output Clock: The clock for serial output data. In active
mode, OCK1 is an output; in passive mode, OCK1 is an
input, according to the sioc register OCK field (see Table 22). Input has typically 0.7 V hysteresis.
The serial interface pins implement a full-featured synchronous/asynchronous serial I/O channel. In addition,
several pins offer a glueless TDM interface for multiprocessing communication applications (see Figure 6, Multiprocessor Communications and Connections).
OLD1
Data Input: Serial data is latched on the rising edge of
ICK1, either LSB or MSB first, according to the sioc register MSB field (see Table 22).
Output Load: The clock for loading the output shift register, osr, from the output buffer sdx[out]. A falling edge
of OLD1 indicates the beginning of a serial output word.
In active mode, OLD1 is an output; in passive, OLD1 is
an input, according to the sioc register OLD field (see
Table 22). Input has typically 0.7 V hysteresis.
ICK1
OBE1
Input Clock: The clock for serial input data. In active
mode, ICK1 is an output; in passive mode, ICK1 is an
input, according to the sioc register ICK field (see Table
22). Input has typically 0.7 V hysteresis.
Output Buffer Empty: Positive assertion. OBE1 is asserted when the output buffer, sdx[out], is emptied
(moved to the output shift register for transmission). It is
cleared with a write to the buffer, as in sdx = a0. OBE1
is also set by asserting RSTB.
DI1
ILD1
SADD1
Input Load: The clock for loading the input buffer,
sdx[in], from the input shift register isr. A falling edge of
ILD1 indicates the beginning of a serial input word. In
active mode, ILD1 is an output; in passive mode, ILD1
is an input, according to the sioc register ILD field (see
Table 22). Input has typically 0.7 V hysteresis.
IBF1
Input Buffer Full: Positive assertion. IBF1 is asserted
when the input buffer, sdx[in], is filled. IBF1 is negated
by a read of the buffer, as in a0 = sdx. IBF1 is also negated by asserting RSTB.
Serial Address: Negative assertion. A 16-bit serial bit
stream typically used for addressing during multiprocessor communication between multiple DSP16xx devices.
In multiprocessor mode, SADD1 is an output when the
tdms time slot dictates a serial transmission; otherwise,
it is an input. Both the source and destination DSP can
be identified in the transmission. SADD1 is always an
output when not in multiprocessor mode and can be
used as a second 16-bit serial output. See the
DSP1611/17/18/27 Digital Signal Processor Information Manual for additional information. SADD1 is 3stated when DOEN1 is high. When used on a bus,
SADD1 should be pulled high through a 5 kΩ
Ω resistor.
DO1
SYNC1
Data Output: The serial data output from the output
shift register (osr), either LSB or MSB first (according to
the sioc register MSB field). DO1 changes on the rising
edges of OCK1. DO1 is 3-stated when DOEN1 is high.
DOEN1
Data Output Enable: Negative assertion. An input
when not in the multiprocessor mode. DO1 and SADD1
are enabled only if DOEN1 is low. DOEN1 is bidirectional when in the multiprocessor mode (tdms register
MODE field set). In the multiprocessor mode, DOEN1
indicates a valid time slot for a serial output.
Lucent Technologies Inc.
Multiprocessor Synchronization: Typically used in
the multiprocessor mode, a falling edge of SYNC1 indicates the first word (time slot 0) of a TDM I/O stream
and causes the resynchronization of the active ILD1
and OLD1 generators. SYNC1 is an output when the
tdms register SYNC field is set (i.e., selects the master
DSP and uses time slot 0 for transmit). As an input,
SYNC1 must be tied low unless part of a TDM interface.
When used as an output, SYNC1 = [ILD1/OLD1]/8 or
16, depending on the setting of the SYNCSP field of the
tdms register. When configured as described above,
SYNC1 can be used to generate a slow clock for SIO
operations. Input has typically 0.7 V hysteresis.
65
Data Sheet
March 2000
DSP1629 Digital Signal Processor
6 Signal Descriptions (continued)
PODS
6.4 Parallel Host Interface or Serial Interface
#2 and Control I/O Interface
Parallel Output Data Strobe: An input pin, software
configurable to support both Intel and Motorola protocols.
This interface pin multiplexes a parallel host interface
with a second serial I/O interface and a 4-bit I/O interface. The interface selection is made by writing the
ESIO2 bit in the ioc register (see Table 38 and Section
4.1). The functions and signals for the second SIO correspond exactly with those in SIO #1. Therefore, the pin
descriptions below discuss only PHIF and BIO pin functionality.
In Intel mode: Negative assertion. When PODS is pulled
low by an external device, the DSP1629 places the contents of the parallel output register, pdx0, onto the PB
bus.
PB[7:0]
PIBF
Parallel I/O Data Bus: This 8-bit bidirectional bus is
used to input data to, or output data from, the PHIF.
Parallel Input Buffer Full: An output pin with positive
assertion; configurable in software. This flag is cleared
after reset, indicating an empty input buffer pdx0[in].
Note that PB[3:0] are pin multiplexed with SIO2 functionality, and PB[7:4] are pin multiplexed with BIO unit
pins IOBIT[3:0] (see Section 4.1).
PCSN
Peripheral Chip Select Not: Negative assertion. PCSN
is an input. While PCSN is low, the data strobes PIDS
and PODS are enabled. While PCSN is high, the
DSP1629 ignores any activity on PIDS and PODS.
PBSEL
Peripheral Byte Select: An input pin, configurable in
software. Selects the high or low byte of pdx0 available
for host accesses.
PSTAT
Peripheral Status Select: PSTAT is an input. When a
logic 0, the PHIF will output the pdx0[out] register on the
PB bus. When a logic 1, the PHIF will output the contents of the PSTAT register on PB[7:0].
PIDS
Parallel Input Data Strobe: An input pin, software configurable to support both Intel and Motorola protocols.
In Intel mode: Negative assertion. PIDS is pulled low by
an external device to indicate that data is available on
the PB bus. The DSP latches data on the PB bus on the
rising edge (low-to-high transition) of PIDS or PCSN,
whichever comes first.
In Motorola mode: PIDS/PRWN functions as a read/
write strobe. The external device sets PIDS/PRWN to a
logic 0 to indicate that data is available on the PB bus
(write operation by the external device). A logic 1 on
PIDS/PRWN indicates an external read operation by the
external device.
66
In Motorola mode: Software-configurable assertion level. The external device uses PODS/PDS as its data
strobe for both read and write operations.
PIBF is set immediately after the rising edge of PIDS or
PCSN, indicating that data has been latched into the
pdx0[in] register. When the DSP1629 reads the contents of this register, emptying the buffer, the flag is
cleared.
Configured in software, PIBF may become the logical
OR of the PIBF and POBE flags.
POBE
Parallel Output Buffer Empty: An output pin with positive assertion; configurable in software. This flag is set
after reset, indicating an empty output buffer pdx0[out].
POBE is set immediately after the rising edge of PODS
or PCSN, indicating that the data in pdx0[out] has been
driven onto the PB bus. When the DSP1629 writes to
pdx0[out], filling the buffer, this flag is cleared.
6.5 Control I/O Interface
This interface is used for status and control operations
provided by the bit I/O unit of the DSP1629. It is pin multiplexed with the PHIF and VEC[3:0] pins (see Section
4.1). Setting the ESIO2 and EBIOH bits in the ioc register provides a full 8-bit BIO interface at the associated
pins.
IOBIT[7:0]
I/O Bits [7:0]: Each of these bits can be independently
configured as either an input or an output. As outputs,
they can be independently set, toggled, or cleared. As
inputs, they can be tested independently or in combinations for various data patterns.
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
6 Signal Descriptions (continued)
TDO
6.6 JTAG Test Interface
Test Data Output: JTAG serial output signal. Serialscanned data and status bits are output on this pin.
The JTAG test interface has features that allow programs and data to be downloaded into the DSP via four
pins. This provides extensive test and diagnostic capability. In addition, internal circuitry allows the device to
be controlled through the JTAG port to provide on-chip
in-circuit emulation. Lucent Technologies provides
hardware and software tools to interface to the on-chip
HDS via the JTAG port.
Note: The DSP1629 provides all JTAG/IEEE 1149.1
standard test capabilities including boundary
scan. See the DSP1611/17/18/27 Digital Signal
Processor Information Manual for additional information on the JTAG test interface.
TMS
Test Mode Select: JTAG mode control signal that,
when combined with TCK, controls the scan operations.
This pin has an internal pull-up resistor.
TCK
Test Clock: JTAG serial shift clock. This signal clocks
all data into the port through TDI, and out of the port
through TDO, and controls the port by latching the TMS
signal inside the state-machine controller.
TRST
TDI
Test Data Input: JTAG serial input signal. All serialscanned data and instructions are input on this pin. This
pin has an internal pull-up resistor.
Lucent Technologies Inc.
Test Reset: Negative assertion. JTAG test reset. When
asserted low, asynchronously resets JTAG TAP controller. In an application environment, this pin must be
asserted prior to or concurrent with RSTB. This pin has
an internal pull-up resistor.
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Data Sheet
March 2000
DSP1629 Digital Signal Processor
7 Mask-Programmable Options
The DSP1629 contains a ROM that is mask-programmable. The selection of several programmable features is
made when a custom ROM is encoded. These features select the input clock options, the instruction/coefficient
memory map option, and the hardware emulation or ROM security option, as summarized in Table 59.
Table 59. DSP1629 ROM Options
Features
Input Clock
Memory Map
ROM Security
Options
CMOS Level
Small Signal
DSP1629x16
DSP1629x10
Nonsecure
Secure
Comments
2.7 V and 3 V
2.7 V and 3 V
16 Kwords DPRAM
10 Kwords DPRAM
Specify and link 1629hds.v# * ,
allows emulation.
Specify and link crc16.v# †,
no emulation capability.
* 1629hds.v# (# indicates the current version number) is the relocatable HDS object code. It uses approximately 140 words
and must reside in the first 4 Kwords of ROM.
† crc16.v# is the cyclic redundancy check object code. It uses approximately 75 words and must reside in the first 4 Kwords
of ROM. See the DSP1600 Support Tools Manual for detailed information.
7.1 Input Clock Options
For all input options, the input clock CKI can run at some fraction of the internal clock frequency by setting the PLL
multiplication factors appropriately (see Section 4.12, Clock Synthesis). When the PLL is bypassed, the input clock
CKI frequency is the internal clock frequency.
7.2 Memory Map Options
The DSP1629 offers a DSP1629x16 or a DSP1629x10 where the difference is in the memory maps. The
DSP1629x16 contains 16 Kwords of internal RAM (DPRAM). The DSP1629x10 supports the use of only 10 Kwords
of DPRAM. See Section 4.4 Memory Maps and Wait-States for further description.
7.3 ROM Security Options
The DSP1600 hardware development system (HDS) provides on-chip in-circuit emulation and requires that the relocatable HDS code be linked to the application code. This code's object file is called 1629hds.v#, where # is a
unique version identifier. Refer to the DSP1629-ST software tools release for more specific information. If on-chip
in-circuit emulation is desired, a nonsecure ROM must be chosen. If ROM security is desired with the DSP1629, the
HDS cannot be used. To provide testing of the internal ROM contents on a secure ROM device, a cyclic redundancy
check (CRC) program is called by and linked with the user's source code. The CRC code resides in the first
4 Kwords of ROM.
See the DSP1600 Support Tools Manual for more detailed information.
68
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
8 Device Characteristics
8.1 Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
External leads can be bonded and soldered safely at temperatures of up to 300 °C. (TBD for 144-pin PBGA)
Voltage Range on VDD with Respect to Ground Using Devices Designed
for 3 V Operation ..............................................................................................................................–0.5 V to +4.6 V
Voltage Range on Any Pin ............................................................................................. VSS – 0.5 V to VDD + 0.5 V
Power Dissipation................................................................................................................................................ 1 W
Ambient Temperature Range ......................................................................................................... –40 °C to +85 °C
Storage Temperature Range .................................................................................................................... –65 °C to +150 °C
8.2 Handling Precautions
All MOS devices must be handled with certain precautions to avoid damage due to the accumulation of static
charge. Although input protection circuitry has been incorporated into the devices to minimize the effect of this static
buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling and mounting. Lucent Technologies employs a human-body model for ESD-susceptibility testing. Since the failure voltage of
electronic devices is dependent on the current, voltage, and hence, the resistance and capacitance, it is important
that standard values be employed to establish a reference by which to compare test data. Values of 100 pF and
1500 Ω are the most common and are the values used in the Lucent Technologies human-body model test circuit.
The breakdown voltage for the DSP1629 is greater than 2000 V.
8.3 Recommended Operating Conditions
Table 60. Recommended Operating Conditions
Maximum
Instruction
Rate (MIPS)
Device
Speed
Input Clock
Package
52
19.2 ns
CMOS, Small-signal
80
12.5 ns
CMOS, Small-signal
60
16.7 ns
CMOS, Small-signal
100
10 ns
CMOS, Small-signal
PBGA
BQFP
or TQFP
PBGA
BQFP
or TQFP
PBGA
BQFP
or TQFP
PBGA
BQFP
or TQFP
Supply Voltage
VDD (V)
Min
Max
2.7
3.3
Ambient
Temperature TA (°°C)
Min
Max
–40
85
2.7
3.3
–40
85
3.0
3.6
–40
85
3.0
3.6
–40
85
The ratio of the instruction cycle rate to the input clock frequency is 1:1 without the PLL (referred to as 1X operation)
and M/(2N) with the PLL selected (see Section 4.12). Device speeds greater than 50 MIPS do not support 1X
operation; use the PLL.
Lucent Technologies Inc.
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DSP1629 Digital Signal Processor
Data Sheet
March 2000
8 Device Characteristics (continued)
8.4 Package Thermal Considerations
The recommended operating temperature specified above is based on the maximum power, package type, and
maximum junction temperature. The following equations describe the relationship between these parameters. If the
applications' maximum power is less than the worst-case value, this relationship determines a higher maximum ambient temperature or the maximum temperature measured at top dead center of the package.
TA = TJ – P x ΘJA
TTDC = TJ – P x ΘJ-TDC
where TA is the still-air ambient temperature and TTDC is the temperature measured by a thermocouple at the top
dead center of the package.
Maximum Junction Temperature (TJ) in 100-Pin BQFP ..................................................................................100 °C
100-pin BQFP Maximum Thermal Resistance in Still-Air-Ambient (ΘJA) ..................................................... 55 °C/W
100-pin BQFP Maximum Thermal Resistance, Junction to Top Dead Center (ΘJ-TDC)............................... 12 °C/W
Maximum Junction Temperature (TJ) in 100-Pin TQFP ..................................................................................100 °C
100-pin TQFP Maximum Thermal Resistance in Still-Air-Ambient (ΘJA) ..................................................... 30 °C/W
100-pin TQFP Maximum Thermal Resistance, Junction to Top Dead Center (ΘJ-TDC) ................................. 6 °C/W
Maximum Junction Temperature (TJ) in 144-Pin PBGA..................................................................................100 °C
144-pin PBGA Maximum Thermal Resistance in Still-Air-Ambient (ΘJA) .......................... TBD (estimated 30 °C/W)
144-pin PBGA Maximum Thermal Resistance, Junction to Top Dead Center (ΘJ-TDC)..................................... TBD
WARNING: Due to package thermal constraints, proper precautions in the user's application should be taken to avoid exceeding the maximum junction temperature of 100 °C. Otherwise, the device will
be affected adversely.
70
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
9 Electrical Characteristics and Requirements
The following electrical characteristics are preliminary and are subject to change. Electrical characteristics refer to
the behavior of the device under specified conditions. Electrical requirements refer to conditions imposed on the
user for proper operation of the device. The parameters below are valid for the conditions described in Section 8.3,
Recommended Operating Conditions.
Table 61. Electrical Characteristics and Requirements
Parameter
Input Voltage:
Low
High
Input Current (except TMS, TDI):
Low (VIL = 0 V, VDD = 5.25 V)
High (VIH = 5.25 V, VDD = 5.25 V)
Input Current (TMS, TDI):
Low (VIL = 0 V, VDD = 5.25 V)
High (VIH = 5.25 V, VDD = 5.25 V)
Output Low Voltage:
Low (IOL = 2.0 mA)
Low (IOL = 50 µA)
Output High Voltage:
High (IOH = –2.0 mA)
High (IOH = –50 µA)
Output 3-State Current:
Low (VDD = 5.25 V, VIL = 0 V)
High (VDD = 5.25 V, VIH = 5.25 V)
Input Capacitance
Symbol
Min
Max
Unit
VIL
VIH
–0.3
0.7 * VDD
0.3 * VDD
VDD + 0.3
V
V
IIL
IIH
–5
—
—
5
µA
µA
IIL
IIH
–100
—
—
5
µA
µA
VOL
VOL
—
—
0.4
0.2
V
V
VOH
VOH
VDD – 0.7
VDD – 0.2
—
—
V
V
IOZL
IOZH
CI
–10
—
—
—
10
5
µA
µA
pF
Table 62. Electrical Requirements for Mask-Programmable Input Clock Options
Parameter
CKI CMOS Level Input Voltage:
Low
High
Small-signal Peak-to-peak Voltage
(on CKI)*
Small-signal Input Duty Cycle†
Small-signal Input Voltage Range
(pins: CKI, CKI2)
Small-signal Buffer Frequency Range
Symbol
Min
Max
Unit
VIL
VIH
Vpp
–0.3
0.7 * VDD
0.6
0.3 * VDD
VDD + 0.3
—
V
V
V
DCyc
Vin
45
0.2 * VDD
55
0.6 * VDD
%
V
fss
—
35
MHz
* The small-signal buffer must be used in single-ended mode where an ac waveform (sine or square) is applied to CKI and a dc
voltage approximately equal to the average value of CKI is applied to CKI2, as shown in the figure below. The maximum allowable
ripple on CKI2 is 100 mV.
† Duty cycle for a sine wave is defined as the percentage of time during each clock cycle that the voltage on CKI exceeds the voltage
on CKI2.
CKI
CKI2
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71
Data Sheet
March 2000
DSP1629 Digital Signal Processor
9 Electrical Characteristics and Requirements (continued)
Table 63. PLL Electrical Specifications, VCO Frequency Ranges
Parameter
VCO frequency range (VDD = 3 V ± 10%)
VCO frequency range (VDD = 3.0 V – 3.6 V)
Input Jitter at CKI
*
Symbol
fVCO
Min
50
Max
160
Unit
MHz
fVCO
—
50
—
200
200
MHz
ps-rms
* The M and N counter values in the pllc register must be set so that the VCO will operate in the appropriate range (see Table 63). Choose the
lowest value of N and then the appropriate value of M for
fINTERNAL CLOCK = fCKI x (M/(2N)) = fVCO/2.
Table 64. PLL Electrical Specifications and pllc Register Settings
M
VDD
pllc13 (ICP)
23—24
21—22
19—20
16—18
12—15
8—11
2—7
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
1
1
1
1
1
1
1
pllc12
Reserved
0
0
0
0
0
0
0
pllc[11:8]
(LF[3:0])
1011
1010
1001
1000
0111
0110
0100
Typical Lock-in Time (µ
µs)*
30
30
30
30
30
30
30
* Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which the PLL output clock is unstable. The
DSP must operate from the 1X CKI input clock or from the slow ring oscillator while the PLL is locking. Completion of the lock-in interval is
indicated by assertion of the LOCK flag.
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Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
9 Electrical Characteristics and Requirements (continued)
VDD
VOH (V)
VDD – 0.1
DEVICE
UNDER
TEST
VDD – 0.2
VOH
IOH
VDD – 0.3
VDD – 0.4
0
5
10
15
20
25
30
35
40
45
50
IOH (mA)
5-4007 (F).a
Figure 10. Plot of VOH vs. IOH Under Typical Operating Conditions
0.4
VOL (V)
0.3
DEVICE
UNDER
TEST
0.2
VOL
IOL
0.1
0
0
5
10
15
20
25
30
35
40
45
50
I OL (mA)
5-4008 (F).b
Figure 11. Plot of VOL vs. IOL Under Typical Operating Conditions
Lucent Technologies Inc.
73
Data Sheet
March 2000
DSP1629 Digital Signal Processor
9 Electrical Characteristics and Requirements (continued)
9.1 Power Dissipation
Power dissipation is highly dependent on DSP program activity and the frequency of operation. The typical power
dissipation listed is for a selected application. The following electrical characteristics are preliminary and are subject
to change.
Table 65. Power Dissipation and Wake-Up Latency
Operating Mode
(Unused inputs at VDD or VSS)
VDD=
Normal Operation ioc = 0x0180
PLL Disabled
CKI & CKO = 40 MHz
CMOS
Small Signal
Typical Power Dissipation (mW)
Wake-Up Latency
I/O Units ON
powerc[7:4] = 0x0
3V
I/O Units OFF
powerc[7:4] = 0xf
3V
(PLL Not Used
(PLL Used
During Wake State) During Wake State)
3V
3V
93.7
96.3
91.2
93.7
—
—
—
—
0.17
2.75
0.17
2.75
—
—
—
—
96.7
99.3
94.2
96.7
—
—
—
—
CKI & CKO = 0 MHz
CMOS
Small Signal
Normal Operation ioc = 0x0180
PLL Enabled pllc = 0xFC0E
CKI = 10 MHz CKO = 40 MHz
CMOS
Small Signal
Power Management Modes CKO = 40 MHz
Standard Sleep, External Interrupt
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
CMOS
Small Signal
14.0
16.3
9.3
12.0
3T*
3T*
3T* + tL†
3T* + tL†
16.5
18.9
11.2
14.0
—
—
3T*
3T*
0.7
3.7
0.5
3.5
5.0 µs
5.0 µs
5.0 µs + tL†
5.0 µs + tL†
3.3
6.1
2.9
5.5
—
—
5.0 µs
5.0 µs
Standard Sleep, External Interrupt
alf[15] = 1, ioc = 0x0180
PLL Enabled During Sleep
CMOS
Small Signal
Sleep with Slow Internal Clock
Small Signal Enabled
powerc[15:14] = 01,
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
CMOS
Small Signal
Sleep with Slow Internal Clock
Small Signal Enabled
powerc[15:14] = 01,
alf[15] = 1, ioc = 0x0180
PLL Enabled During Sleep
CMOS
Small Signal
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
† tL = PLL lock time (see Table 64).
74
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
9 Electrical Characteristics and Requirements (continued)
Table 65. Power Dissipation and Wake-Up Latency (continued)
Typical Power Dissipation (mW)
Operating Mode
Wake-Up Latency
I/O Units ON
powerc[7:4] = 0x0
3V
I/O Units OFF
powerc[7:4] = 0xf
3V
(PLL Not Used
During Wake State)
3V
(PLL Used
During Wake State)
3V
0.40
0.30
20 µs
20 µs + tL†
0.060
0.060
3T*
3T* + tL†
Small Signal
Hardware Stop (STOP = VSS)
powerc[15:12] = 0000
PLL Disabled During STOP
0.060
0.060
20 µs
20 µs + tL†
CMOS
0.060
1.20
0.060
1.20
3T*
3T*
—
—
2.5
3.6
2.5
3.6
3T*
3T*
3T*
3T*
(Unused inputs at VDD or VSS)
VDD=
Sleep with Slow Internal Clock
Small Signal Disabled
powerc[15:14] = 11,
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
Small Signal
Software Stop
powerc[15:12] = 0011
PLL Disabled During STOP
CMOS
Software Stop
powerc[15:12] = 1111
PLL Disabled During STOP
Small Signal
Hardware Stop (STOP = VSS)
powerc[15:12] = 0000
PLL Enabled During STOP
CMOS
Small Signal
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
† tL = PLL lock time (see Table 64).
The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the
basis of the application by adding C x VDD/2 x f for each output, where C is the additional load capacitance and f is
the output frequency.
Power dissipation due to the input buffers is highly dependent on the input voltage level. At full CMOS levels, essentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the threshold of VDD/2, high currents can flow. Although input and I/O buffers may be left untied (since the input voltage levels
of the input and I/O buffers are designed to remain at full CMOS levels when not driven by the DSP), it is still recommended that unused input and I/O pins be tied to VSS or VDD through a 10 kΩ resistor to avoid application ambiguities. Further, if I/O pins are tied high or low, they should be pulled fully to V SS or VDD.
WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high currents may flow.
Lucent Technologies Inc.
75
DSP1629 Digital Signal Processor
Data Sheet
March 2000
10 Timing Characteristics for 3.0 V Operation
The following timing characteristics and requirements are preliminary information and are subject to change. Timing
characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions
imposed on the user for proper operation of the device. All timing data is valid for the following conditions:
TA = –40 °C to +85 °C (See Section 8.3.)
VDD = 3.0 V to 3.6 V, VSS = 0 V (See Section 8.3.)
Capacitance load on outputs (CL) = 50 pF, except for CKO, where CL = 20 pF.
Output characteristics can be derated as a function of load capacitance (CL).
All outputs: 0.03 ns/pF ≤ dt/dCL ≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge.
For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF
x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time.
Test conditions for inputs:
■
Rise and fall times of 4 ns or less
■
Timing reference levels for delays = VIH, VIL
Test conditions for outputs (unless noted otherwise):
■
CLOAD = 50 pF; except for CKO, where CLOAD = 20 pF
■
Timing reference levels for delays = VIH, VIL
■
3-state delays measured to the high-impedance state of the output driver
For the timing diagrams, see Table 62 for input clock requirements.
Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.
76
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.1 DSP Clock Generation
t1
t3
t2
1X CKI*
t4
t5
CKO†
t6, t6a
CKO‡
EXTERNAL MEMORY CYCLE
W = 1§
5-4009 (F).a
*
†
‡
§
See Table 62 for input clock electrical requirements.
Free-running clock.
Wait-stated clock (see Table 38).
W = number of wait-states.
Figure 12. I/O Clock Timing Diagram
Table 66. Timing Requirements for Input Clock
Abbreviated Reference
t1
t2
t3
Parameter
Clock In Period (high to high)
Clock In Low Time (low to high)
Clock In High Time (high to low)
Min
20†
10
10
Max
—‡
—
—
Unit
ns
ns
ns
† Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.
‡ Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.
Table 67. Timing Characteristics for Input Clock and Output Clock
Abbreviated Reference
t4
t5
t6
t6a
Parameter
Clock Out High Delay
Clock Out Low Delay (high to low)
Clock Out Period (low to low)
Clock Out Period with SLOWCKI Bit Set in powerc
Register (low to low)
Min
—
—
T†
0.74
Max
10
10
—
3.8
Unit
ns
ns
ns
µs
† T = internal clock period, set by CKI or by CKI and the PLL parameters.
Lucent Technologies Inc.
77
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.2 Reset Circuit
The DSP1629 has two external reset pins: RSTB and TRST. At initial powerup, or if the supply voltage falls below
VDD MIN* and a device reset is required, both TRST and RSTB must be asserted to initialize the device. Figure 13
shows two separate events:
■
Chip reset at initial powerup.
■
Chip reset following a drop in power supply.
Note: The TRST pin must be asserted even if the JTAG controller is not used by the application.
* See Table 60, Recommended Operating Conditions.
V DD MIN
VDD
RAMP
t146
0.4 V
t9
RSTB,
TRST
VDD MIN
t153
0.4 V
t8
t153
t146
t9
t8
VIH
VIL
t10
t10
t11
t11
OUTPUT VOH
PINS *
VOL
CKI †
5-4010 (F).a
* When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state
condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, and RWN outputs remain high, and CKO remains a
free-running clock.
† See Table 62 for input clock electrical requirements.
Figure 13. Powerup Reset and Chip Reset Timing Diagram
Table 68. Timing Requirements for Powerup Reset and Chip Reset
Abbreviated Reference
t8
t9
t146
t153
Parameter
RSTB and TRST Reset Pulse (low to high)
VDD Ramp
VDD MIN to RSTB Low
CMOS
Small-signal
RSTB (low to high)
Min
6T
—
2T
20
Max
—
10
—
—
Unit
ns
ms
ns
µs
—
54
ns
Min
—
—
Max
100
100
Unit
ns
ns
Table 69. Timing Characteristics for Powerup Reset and Chip Reset
Abbreviated Reference
t10
t11
Parameter
RSTB Disable Time (low to 3-state)
RSTB Enable Time (high to valid)
Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high currents may flow.
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Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.3 Reset Synchronization
t5 + 2 x t6
CKI*
VIH
VIL
t126
RSTB
VIH
VIL
CKO
VIH
VIL
CKO
VIH
VIL
5-4011 (F).a
* See Table 62 for input clock electrical requirements.
Notes:
CKO1 and CKO2 are two possible CKO states before reset. CKO is free-running.
If the rising edge of RSTB (low to high) is captured instead by the falling edge of CKO (high to low), CKO and CKI will be in-phase at t5 + 2 x t6.
Figure 14. Reset Synchronization Timing
Table 70. Timing Requirements for Reset Synchronization Timing
Abbreviated Reference
t126
Lucent Technologies Inc.
Parameter
Reset Setup (high to high)
Min
3
Max
T/2 – 1
Unit
ns
79
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.4 JTAG I/O Specifications
t12
t155
t13
TCK
t14
VIH
VIL
t15
t156
t16
TMS
VIH
VIL
t17
t18
VIH
TDI
VIL
t19
t20
TDO
VOH
VOL
5-4017 (F)
Figure 15. JTAG Timing Diagram
Table 71. Timing Requirements for JTAG Input/Output
Abbreviated Reference
t12
t13
t14
t155
t156
t15
t16
t17
t18
Parameter
TCK Period (high to high)
TCK High Time (high to low)
TCK Low Time (low to high)
TCK Rise Transition Time (low to high)
TCK Fall Transition Time (high to low)
TMS Setup Time (valid to high)
TMS Hold Time (high to invalid)
TDI Setup Time (valid to high)
TDI Hold Time (high to invalid)
Min
50
22.5
22.5
0.6
0.6
7.5
2
7.5
2
Max
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
Min
—
0
Max
19
—
Unit
ns
ns
Table 72. Timing Characteristics for JTAG Input/Output
Abbreviated Reference
t19
t20
80
Parameter
TDO Delay (low to valid)
TDO Hold (low to invalid)
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.5 Interrupt
CKO*
V OH
V OL
t21
INT[1:0]
V IH
V IL
t22
t23
IACK†
t25
V OH
V OL
t24
t26
VEC[3:0]
V OH
V OL
5-4018 (F)
* CKO is free-running.
† IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion.
Figure 16. Interrupt Timing Diagram
Table 73. Timing Requirements for Interrupt
Abbreviated Reference
t21
t22
Parameter
Interrupt Setup (high to low)
INT Assertion Time (high to low)
Min
19
2T
Max
—
—
Unit
ns
ns
Min
—
—
—
—
Max
T/2 + 10
12.5
10
12.5
Unit
ns
ns
ns
ns
Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.
Table 74. Timing Characteristics for Interrupt
Abbreviated Reference
t23
t24
t25
t26
Parameter
IACK Assertion Time (low to high)
VEC Assertion Time (low to high)
IACK Invalid Time (low to low)
VEC Invalid Time (low to low)
Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.
Lucent Technologies Inc.
81
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.6 Bit Input/Output (BIO)
t144
CKO
V OH
V OL
t29
V OH
IOBIT
(OUTPUT) V O L
VALID OUTPUT
t28
t27
IOBIT
(INPUT)
V IH
DATA INPUT
V IL
5-4019 (F).a
Figure 17. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit)
Table 75. Timing Requirements for BIO Input Read
Abbreviated Reference
t27
t28
Parameter
IOBIT Input Setup Time (valid to high)
IOBIT Input Hold Time (high to invalid)
Min
15
0
Max
—
—
Unit
ns
ns
Min
—
1
Max
9
—
Unit
ns
ns
Table 76. Timing Characteristics for BIO Output
Abbreviated Reference
t29
t144
Parameter
IOBIT Output Valid Time (low to valid)
IOBIT Output Hold Time (low to invalid)
t144
CKO
VOH –
V O L–
t29
IOBIT
VOH –
(OUTPUT)
V O L–
VALID OUTPUT
t141
IOBIT
(INPUT)
VIH –
V I L–
t142
TEST INPUT
5-4019 (F).b
Figure 18. Write Outputs and Test Inputs (cbit = Immediate)
Table 77. Timing Requirements for BIO Input Test
Abbreviated Reference
t141
t142
82
Parameter
IOBIT Input Setup Time (valid to low)
IOBIT Input Hold Time (low to invalid)
Min
15
0
Max
—
—
Unit
ns
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.7 External Memory Interface
The following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external
memory enables unless so stated. See the DSP1611/17/18/27 Digital Signal Processor Information Manual for a
detailed description of the external memory interface including other functional diagrams.
CKO
VOH
VOL
t33
t34
VOH
ENABLE
VOL
W* = 0
5-4020 (F).b
* W = number of wait-states.
Figure 19. Enable Transition Timing
Table 78. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO)
Abbreviated Reference
t33
t34
Parameter
CKO to ENABLE Active (low to low)
CKO to ENABLE Inactive (low to high)
Min
0
–1
Max
4.5
4
Unit
ns
ns
Table 79. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F)
Abbreviated Reference
t33
Lucent Technologies Inc.
Parameter
CKO to Delayed ENABLE Active (low to low)
Min
T/2
Max
T/2 + 7
Unit
ns
83
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
(MWAIT = 0 x 2222)
W* = 2
CKO
V OH
V OL
t127
ENABLE
V OH
V OL
t129
t130
DB
V IH
READ DATA
V IL
t150
t128
AB
V OH
V OL
READ ADDRESS
5-4021 (F).a
* W = number of wait-states.
Figure 20. External Memory Data Read Timing Diagram
Table 80. Timing Characteristics for External Memory Access
Abbreviated Reference
Parameter
t127
Enable Width (low to high)
t128
Address Valid (enable low to valid)
Min
T(1 + W) – 1.5
—
Max
—
2
Unit
ns
ns
Table 81. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO)
Abbreviated Reference
Parameter
t129
Read Data Setup (valid to enable high)
t130
Read Data Hold (enable high to hold)
t150
External Memory Access Time (valid to valid)
84
Min
12
0
—
Max
—
—
T(1 + W) – 13
Unit
ns
ns
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
(MWAIT = 0x1002)
W* = 2
CKO
ERAMLO
DB
W* = 1
VOH
VOL
VOH
VOL
VOH
VOL
WRITE DATA
READ
t131
EROM
VOH
VOL
t132
t133
RWN
t134
VOH
VOL
t135
t136
AB
VOH
VOL
WRITE ADDRESS
READ ADDRESS
5-4022 (F).a
* W = number of wait-states.
Figure 21. External Memory Data Write Timing Diagram
Table 82. Timing Characteristics for External Memory Data Write (All Enables)
Abbreviated Reference
t131
t132
t133
t134
t135
t136
Lucent Technologies Inc.
Parameter
Min
Write Overlap (enable low to 3-state)
—
RWN Advance (RWN high to enable high)
0
RWN Delay (enable low to RWN low)
0
Write Data Setup (data valid to RWN high)
T(1 + W)/2 – 3
RWN Width (low to high)
T(1 + W) – 4
Write Address Setup (address valid to RWN low)
0
Max
0
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
85
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
(MWAIT = 0x1002)
W* = 2
CKO
ERAMLO
EROM
W* = 1
VOH
VOL
VOH
VOL
VOH
VOL
t131
DB
VOH
VOL
WRITE
READ
t137
t138
RWN
VOH
VOL
t139
AB
VOH
VOL
WRITE ADDRESS
READ ADDRESS
5-4023 (F).a
* W = number of wait-states.
Figure 22. Write Cycle Followed by Read Cycle
Table 83. Timing Characteristics for Write Cycle Followed by Read Cycle
Abbreviated Reference
t131
t137
t138
t139
86
Parameter
Write Overlap (enable low to 3-state)
Write Data 3-state (RWN high to 3-state)
Write Data Hold (RWN high to data hold)
Write Address Hold (RWN high to address hold)
Min
—
—
0
0
Max
0
2
—
—
Unit
ns
ns
ns
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.8 PHIF Specifications
For the PHIF, read means read by the external user (output by the DSP); write is similarly defined. The 8-bit reads/writes
are identical to one-half of a 16-bit access.
16-bit READ
16-bit WRITE
VIH–
PCSN
PODS
VIL–
VIH–
VIL–
t41
t42
t44
VIH–
PIDS
VIL–
t43
PBSEL
VIH–
VIL–
t47
t45
PSTAT
t48
t46
VIH–
VIL–
t49
VIH–
PB[7:0]
t50
t154
t51
t52
VIL–
5-4036 (F)
Figure 23. PHIF Intel Mode Signaling (Read and Write) Timing Diagram
Table 84. Timing Requirements for PHIF Intel Mode Signaling
Abbreviated Reference
t41
t42
t43
t44
t45*
t46*
t47*
t48*
t51*
t52*
*
Parameter
PODS to PCSN Setup (low to low)
PCSN to PODS Hold (high to high)
PIDS to PCSN Setup (low to low)
PCSN to PIDS Hold (high to high)
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
PB Write to PCSN Setup (valid to high)
PCSN to PB Write Hold (high to invalid)
Min
0
0
0
0
4
0
6
0
10
4
Max
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also be
initiated and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, whichever comes
last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low, i f PODS goes low
after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction is initiated by PCSN or
PIDS going low, whichever comes last. An input transaction is completed by PCSN or PIDS going high, whichever comes first. All requirements
referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal.
Table 85. Timing Characteristics for PHIF Intel Mode Signaling
Abbreviated Reference
t49*
t50*
t154
*
Parameter
PCSN to PB Read (low to valid)
PCSN to PB Read Hold (high to invalid)
PCSN to PB Read 3-state (high to 3-state)
Min
—
0
—
Max
12
—
8
Unit
ns
ns
ns
This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also
be initiated and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, whichever
comes last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low, if PODS
goes low after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction is initiated
by PCSN or PIDS going low, whichever comes last. An input transaction is completed by PCSN or PIDS going high, whichever comes first. All
requirements referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal.
Lucent Technologies Inc.
87
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
16-bit WRITE
16-bit READ
8-bit READ
8-bit WRITE
t55
t55
PCSN
VIH
VIL
t56
t55
PODS
t56
VIH
VIL
t56
PIDS
t56
t55
VIH
VIL
t56
PBSEL
VOH
VOL
t53
POBE
t53
VOH
VOL
t54
t54
PIBF
VOH
VOL
5-4037 (F).a
Figure 24. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram
Table 86. Timing Requirements for PHIF Intel Mode Signaling
Abbreviated Reference
t55
t56
Parameter
PCSN/PODS/PIDS Pulse Width (high to low)
PCSN/PODS/PIDS Pulse Width (low to high)
Min
20.5
20.5
Max
—
—
Unit
ns
ns
Min
—
Max
17
Unit
ns
—
17
ns
Table 87. Timing Characteristics for PHIF Intel Mode Signaling
Abbreviated Reference
t53*
t54*
Parameter
†
PCSN/PODS to POBE (high to high)
PCSN/PIDS to PIBF† (high to high)
* t53 should be referenced to the rising edge of PCSN or PODS, whichever comes first. t54 should be referenced to the rising edge of PCSN
or PIDS, whichever comes first.
† POBE and PIBF may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 and t54
apply to the inverted levels as well as those shown.
88
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
16-bit READ
16-bit WRITE
VI H
PCSN
VIL
t42
VI H
PDS VIL
t41
PRWN
t47
t48
t44
VI H
VIL
t45
PSTAT
t44
VIL
t43
PBSEL
t43
VI H
t46
VI H
VIL
t49
t50
t154
t51
t52
PB[7:0]
5-4038 (F).a
Figure 25. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram
Table 88. Timing Requirements for PHIF Motorola Mode Signaling
Abbreviated Reference
t41
t42
t43
t44
t45*
t46*
t47*
t48*
t51*
t52*
Parameter
PDS† to PCSN Setup (valid to low)
PCSN to PDS† Hold (high to invalid)
PRWN to PCSN Setup (valid to low)
PCSN to PRWN Hold (high to invalid)
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
PB Write to PCSN Setup (valid to high)
PCSN to PB Write Hold (high to invalid)
Min
0
0
4
0
4
0
6
0
10
4
Max
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can
also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last.
For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low
after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to
PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 49 and 50. POBE and PIBF may be programmed to
be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 89. Timing Characteristics for PHIF Motorola Mode Signaling
Abbreviated Reference
Parameter
t49*
PCSN to PB Read (low to valid)
t50*
PCSN to PB Read Hold (high to invalid)
t154
PCSN to PB Read 3-state (high to 3-state)
Min
—
0
—
Max
12
—
8
Unit
ns
ns
ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can
also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last.
For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low
after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to
PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
Lucent Technologies Inc.
89
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
16-bit READ
16-bit WRITE
8-bit WRITE
8-bit READ
t55
t55
PCSN
VIH–
VIL–
t56
t55
PDS
t56
VIL–
t56
PIDS
t56
VIH–
t55
VIH–
VIL–
t56
PBSEL
VOH–
VOL–
t53
POBE
t53
VOH–
VOL–
t54
t54
PIBF
VOH–
VOL–
5-4039 (F).a
Figure 26. PHIF Motorola Mode Signaling (Pulse Period and Flags) Timing Diagram
Table 90. Timing Characteristics for PHIF Motorola Mode Signaling
Abbreviated Reference
t53*
t54*
Parameter
PCSN/PDS to POBE† (high to high)
PCSN/PDS† to PIBF† (high to high)
†
Min
—
—
Max
17
17
Unit
ns
ns
* An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For example, t53 and t54 should be referenced to
PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first.
All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or
complete a transaction.
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 49 and 50. POBE and PIBF may be programmed to
be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 91. Timing Requirements for PHIF Motorola Mode Signaling
Abbreviated Reference
Parameter
t55
PCSN/PDS/PRWN Pulse Width (high to low)
t56
PCSN/PDS/PRWN Pulse Width (low to high)
90
Min
20
20
Max
—
—
Unit
ns
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
V IH
PCSN
PODS (PDS*)
PIDS (PRWN*)
V IL
V IH
V IL
V IH
V IL
t47
PBSEL
t48
V IH
V IL
t46
t45
PSTAT
V IH
V IL
t49
PB[7:0]
V OH
t50
t154
V OL
5-4040 (F).a
* Motorola mode signal name.
Figure 27. PHIF Intel or Motorola Mode Signaling (Status Register Read) Timing Diagram
Table 92. Timing Requirements for Intel and Motorola Mode Signaling (Status Register Read)
Abbreviated Reference
t45†
t46‡
t47†
t48‡
Parameter
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
Min
4
0
6
0
Max
—
—
—
—
Unit
ns
ns
ns
ns
† t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last.
‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.
Table 93. Timing Characteristics for Intel and Motorola Mode Signaling (Status Register Read)
Abbreviated Reference
t49†
t50‡
t154
Parameter
PCSN to PB Read (low to valid)
PCSN to PB Read Hold (high to invalid)
PCSN to PB Read 3-state (high to 3-state)
Min
—
0
Max
12
—
Unit
ns
ns
—
8
ns
† t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last.
‡ t46, t48, t154, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.
Lucent Technologies Inc.
91
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
RSTB
VIH–
VIL–
t57
POBE
VOH–
VOL–
PIBF
VOH–
VOL–
t58
5-4775 (F)
Figure 28. PHIF, PIBF, and POBE Reset Timing Diagram
Table 94. PHIF Timing Characteristics for PHIF, PIBF, and POBE Reset
Abbreviated Reference
t57
t58
Parameter
RSTB Disable to POBE/PIBF* (high to valid)
RSTB Enable to POBE/PIBF* (low to invalid)
Min
—
3
Max
25
25
Unit
ns
ns
* After reset, POBE and PIBF always go to the levels shown, indicating output buffer empty and input buffer empty. The DSP program, however,
may later invert the definition of the logic levels for POBE and PIBF. t57 and t58 continue to apply.
CKO
VIH–
VIL–
t59
†
VOH–
VOL–
†
VOH–
VOL–
POBE
t59
PIBF
5-4776 (F)
† POBE and PIBF can be programmed to be active-high or active-low. They are shown active-high. The timing characteristic for active-low is
the same as for active-high.
Figure 29. PHIF, PIBF, and POBE Disable Timing Diagram
Table 95. PHIF Timing Characteristics for POBE and PIBF Disable
Abbreviated Reference
t59
92
Parameter
CKO to POBE/PIBF Disable (high/low to disable)
Min
—
Max
20
Unit
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.9 Serial I/O Specifications
t70
ICK
ILD
VIH–
VIL–
VIH–
VIL–
t72
t71
t75
t74
t73
t75
t77
DI
VIH–
VIL–
IBF
VOH–
VOL–
t78
B0
BN – 1*
B1
B0
t79
5-4777 (F)
* N = 16 or 8 bits.
Figure 30. SIO Passive Mode Input Timing Diagram
Table 96. Timing Requirements for Serial Inputs
Abbreviated Reference
t70
t71
t72
t73
t74
t75
t77
t78
Parameter
Clock Period (high to high)†
Clock Low Time (low to high)
Clock High Time (high to low)
Load High Setup (high to high)
Load Low Setup (low to high)
Load High Hold (high to invalid)
Data Setup (valid to high)
Data Hold (high to invalid)
Min
40
18
18
8
8
0
7
0
Max
—‡
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
† For multiprocessor mode, see note in Section 11.10.
‡ Device is fully static; t70 is tested at 200 ns.
Table 97. Timing Characteristics for Serial Outputs
Abbreviated Reference
t79
Lucent Technologies Inc.
Parameter
IBF Delay (high to high)
Min
—
Max
35
Unit
ns
93
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
ICK
VOH–
VOL–
t101
t76a
ILD
VOH–
VOL–
DI
VIH–
VIL–
*
t77
t78
B0
B1
BN – 1
B0
t79
IBF
VOH–
VOL–
5-4778 (F)
* ILD goes high during bit 6 (of 0:15), N = 8 or 16.
Figure 31. SIO Active Mode Input Timing Diagram
Table 98. Timing Requirements for Serial Inputs
Abbreviated Reference
t77
t78
Parameter
Data Setup (valid to high)
Data Hold (high to invalid)
Min
7
0
Max
—
—
Unit
ns
ns
Table 99. Timing Characteristics for Serial Outputs
Abbreviated Reference
t76a
t101
t79
94
Parameter
ILD Delay (high to low)
ILD Hold (high to invalid)
IBF Delay (high to high)
Min
—
3
—
Max
35
—
35
Unit
ns
ns
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
t80
OCK
t82
t81
t85
t84
VIH–
VIL–
t83
OLD
VIH–
VIL–
DO*
VOH–
VOL–
t85
t88
t87
B0
t94
SADD
VOH–
VOL–
DOEN
VIH–
VIL–
OBE
VOH–
VOL–
t90
B1
t92
t90
B7
t93
AD0
AD1
BN – 1
t89
t93
AD7
AS7
t95
t96
5-4796 (F)
* See sioc register, MSB field, to determine if B0 is the MSB or LSB. See sioc register, ILEN field, to determine if the DO word length is 8 bits
or 16 bits.
Figure 32. SIO Passive Mode Output Timing Diagram
Table 100. Timing Requirements for Serial Inputs
Abbreviated Reference
t80
t81
t82
t83
t84
t85
Parameter
†
Clock Period (high to high)
Clock Low Time (low to high)
Clock High Time (high to low)
Load High Setup (high to high)
Load Low Setup (low to high)
Load Hold (high to invalid)
Min
40
Max
‡
18
18
8
8
0
—
—
—
—
—
—
Min
—
—
—
3
—
3
—
—
—
Max
35
35
35
—
35
—
35
35
35
Unit
ns
ns
ns
ns
ns
ns
† For multiprocessor mode, see note in Section 11.10.
‡ Device is fully static; t80 is tested at 200 ns.
Table 101. Timing Characteristics for Serial Outputs
Abbreviated Reference
t87
t88
t89
t90
t92
t93
t94
t95
t96
Lucent Technologies Inc.
Parameter
Data Delay (high to valid)
Enable Data Delay (low to active)
Disable Data Delay (high to 3-state)
Data Hold (high to invalid)
Address Delay (high to valid)
Address Hold (high to invalid)
Enable Delay (low to active)
Disable Delay (high to 3-state)
OBE Delay (high to high)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
95
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
OCK
VOH–
VOL–
t102
t86a
OLD
VOH–
VOL–
DO
VOH–
VOL–
*
t88
B0
t94
SADD
t87
VOH–
VOL–
t92
AD0
t90
B1
t90
B7
t93
AD1
BN – 1
t89
t93
AD7
AS7
t95
DOEN
VIH–
VIL–
OBE
VOH–
VOL–
t96
5-4797 (F)
* OLD goes high at the end of bit 6 of 0:15.
Figure 33. SIO Active Mode Output Timing Diagram
Table 102. Timing Characteristics for Serial Output
Abbreviated Reference
t86a
t102
t87
t88
t89
t90
t92
t93
t94
t95
t96
96
Parameter
OLD Delay (high to low)
OLD Hold (high to invalid)
Data Delay (high to valid)
Enable Data Delay (low to active)
Disable Data Delay (high to 3-state)
Data Hold (high to invalid)
Address Delay (high to valid)
Address Hold (high to invalid)
Enable Delay (low to active)
Disable Delay (high to 3-state)
OBE Delay (high to high)
Min
—
3
—
—
—
3
—
3
—
—
—
Max
35
—
35
35
35
—
35
—
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
CKO
VOH–
VOL–
ICK
VOH–
VOL–
OCK
VOH–
VOL–
ICK/OCK*
ILD
OLD
SYNC
t97
t98
t99
t100
VOH–
t76a
t101
t76b
t101
t86a
t102
t86b
t102
t103
t105
t104
t105
VOH–
VOL–
VOH–
VOL–
VOH–
VOL–
5-4798 (F)
* See sioc register, LD field.
Figure 34. Serial I/O Active Mode Clock Timing
Table 103. Timing Characteristics for Signal Generation
Abbreviated Reference
t97
t98
t99
t100
t76a
t76b
t101
t86a
t86b
t102
t103
t104
t105
Lucent Technologies Inc.
Parameter
ICK Delay (high to high)
ICK Delay (high to low)
OCK Delay (high to high)
OCK Delay (high to low)
ILD Delay (high to low)
ILD Delay (high to high)
ILD Hold (high to invalid)
OLD Delay (high to low)
OLD Delay (high to high)
OLD Hold (high to invalid)
SYNC Delay (high to low)
SYNC Delay (high to high)
SYNC Hold (high to invalid)
Min
—
—
—
—
—
—
3
—
—
3
—
—
3
Max
18
18
18
18
35
35
—
35
35
—
35
35
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
97
Data Sheet
March 2000
DSP1629 Digital Signal Processor
10 Timing Characteristics for 3.0 V Operation (continued)
10.10 Multiprocessor Communication
TIME SLOT 1
TIME SLOT 2
OCK/ICK
t113
t112
t112
SYNC
VIH–
VIL–
DO/D1
VOH–
VOL–
t113
*
t116
B15
B0
t117
B1
B7
B8
B15
B0
t114
t122
t121
AD0
SADD
AD1
AD7
t120
DOEN
AS0
t115
AS7
AD0
t120
VOH–
VOL–
5-4799 (F)
* Negative edge initiates time slot 0.
Figure 35. SIO Multiprocessor Timing Diagram
Note: All serial I/O timing requirements and characteristics still apply, but the minimum clock period in passive
multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.
Table 104. Timing Requirements for SIO Multiprocessor Communication
Abbreviated Reference
t112
t113
t114
t115
Parameter
Sync Setup (high/low to high)
Sync Hold (high to high/low)
Address Setup (valid to high)
Address Hold (high to invalid)
Min
35
0
12
0
Max
—
—
—
—
Unit
ns
ns
ns
ns
Min
Max
Unit
—
—
—
—
—
35
30
25
35
30
ns
ns
ns
ns
ns
Table 105. Timing Characteristics for SIO Multiprocessor Communication
Abbreviated Reference†
t116
t117
t120
t121
t122
Parameter
Data Delay (bit 0 only) (low to valid)
Data Disable Delay (high to 3-state)
DOEN Valid Delay (high to valid)
Address Delay (bit 0 only) (low to valid)
Address Disable Delay (high to 3-state)
† With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.
98
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation
The following timing characteristics and requirements are preliminary information and are subject to change. Timing
characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions
imposed on the user for proper operation of the device. All timing data is valid for the following conditions:
TA = –40 °C to +85 °C (See Section 8.3.)
VDD = 3 V ± 10%, VSS = 0 V (See Section 8.3.)
Capacitance load on outputs (CL) = 50 pF, except for CKO, where CL = 20 pF.
Output characteristics can be derated as a function of load capacitance (CL).
All outputs: 0.03 ns/pF ≤ dt/dCL ≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge.
For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF
x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time.
Test conditions for inputs:
■
Rise and fall times of 4 ns or less
■
Timing reference levels for delays = VIH, VIL
Test conditions for outputs (unless noted otherwise):
■
CLOAD = 50 pF; except for CKO, where CLOAD = 20 pF
■
Timing reference levels for delays = VIH, VIL
■
3-state delays measured to the high-impedance state of the output driver
For the timing diagrams, see Table 62 for input clock requirements.
Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.
Lucent Technologies Inc.
99
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.1 DSP Clock Generation
t1
t3
t2
1X CKI*
t4
t5
CKO†
t6, t6a
CKO‡
EXTERNAL MEMORY CYCLE
W = 1§
5-4009 (F).a
*
†
‡
§
See Table 62 for input clock electrical requirements.
Free-running clock.
Wait-stated clock (see Table 38).
W = number of wait-states.
Figure 36. I/O Clock Timing Diagram
Table 106. Timing Requirements for Input Clock
t1
Clock In Period (high to high)
19.2 ns and 12.5 ns†
Min
Max
Unit
‡
20
ns
—
t2
t3
Clock In Low Time (low to high)
Clock In High Time (high to low)
10
10
Abbreviated Reference
Parameter
—
—
ns
ns
† Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.
‡ Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.
Table 107. Timing Characteristics for Input Clock and Output Clock
Abbreviated Reference
Parameter
t4
t5
t6
t6a
Clock Out High Delay
Clock Out Low Delay (high to low)
Clock Out Period (low to low)
Clock Out Period with SLOWCKI Bit Set
in powerc Register (low to low)
19.2 ns
Min
Max
—
14
—
14
†
—
T
0.74
3.8
12.5 ns
Min
Max
—
10
—
10
†
—
T
0.74
3.8
Unit
ns
ns
ns
µs
† T = internal clock period, set by CKI or by CKI and the PLL parameters.
100
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.2 Reset Circuit
The DSP1629 has two external reset pins: RSTB and TRST. At initial powerup, or if the supply voltage falls below
VDD MIN* and a device reset is required, both TRST and RSTB must be asserted to initialize the device. Figure 37
shows two separate events:
■
Chip reset at initial powerup.
■
Chip reset following a drop in power supply.
Note: The TRST pin must be asserted even if the JTAG controller is not used by the application.
* See Table 60, Recommended Operating Conditions.
V DD MIN
VDD
RAMP
t146
0.4 V
t9
RSTB,
TRST
VDD MIN
t153
0.4 V
t8
t153
t146
t9
t8
VIH
VIL
t10
t10
t11
t11
OUTPUT VOH
PINS*
VOL
CKI †
5-4010 (F).a
* When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state
condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, and RWN outputs remain high, and CKO remains a
free-running clock.
† See Table 62 for input clock electrical requirements.
Figure 37. Powerup Reset and Chip Reset Timing Diagram
Table 108. Timing Requirements for Powerup Reset and Chip Reset
Abbreviated Reference
t8
t9
t146
t153
Parameter
RSTB and TRST Reset Pulse (low to high)
VDD Ramp
VDD MIN to RSTB Low
CMOS
Small-signal
RSTB (low to high)
Min
6T
—
2T
—
Max
—
10
—
—
54
Unit
ns
ms
ns
µs
ns
Min
—
—
Max
100
100
Unit
ns
ns
Table 109. Timing Characteristics for Powerup Reset and Chip Reset
Abbreviated Reference
t10
t11
Parameter
RSTB Disable Time (low to 3-state)
RSTB Enable Time (high to valid)
Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high currents may flow.
Lucent Technologies Inc.
101
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.3 Reset Synchronization
t5 + 2 x t6
CKI*
VIH
VIL
t126
RSTB
VIH
VIL
CKO
VIH
VIL
CKO
VIH
VIL
5-4011 (F).a
* See Table 62 for input clock electrical requirements.
Notes:
CKO1 and CKO2 are two possible CKO states before reset. CKO is free-running.
If the rising edge of RSTB (low to high) is captured instead by the falling edge of CKO (high to low), CKO and CKI will be in-phase at t5 + 2 x t6.
Figure 38. Reset Synchronization Timing
Table 110. Timing Requirements for Reset Synchronization Timing
Abbreviated Reference
t126
102
Parameter
Reset Setup (high to high)
Min
3
Max
T/2 – 1
Unit
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.4 JTAG I/O Specifications
t12
t155
t13
TCK
t14
VIH
VIL
t15
t156
t16
TMS
VIH
VIL
t17
t18
VIH
TDI
VIL
t19
t20
TDO
VOH
VOL
5-4017 (F)
Figure 39. JTAG Timing Diagram
Table 111. Timing Requirements for JTAG Input/Output
Abbreviated Reference
t12
t13
t14
t155
t156
t15
t16
t17
t18
Parameter
TCK Period (high to high)
TCK High Time (high to low)
TCK Low Transition Time (low to high)
TCK Rise Transition Time (low to high)
TCK Fall Transition Time (high to low)
TMS Setup Time (valid to high)
TMS Hold Time (high to invalid)
TDI Setup Time (valid to high)
TDI Hold Time (high to invalid)
Min
50
22.5
22.5
0.6
0.6
7.5
2
7.5
2
Max
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
Min
—
0
Max
19
—
Unit
ns
ns
Table 112. Timing Characteristics for JTAG Input/Output
Abbreviated Reference
t19
t20
Lucent Technologies Inc.
Parameter
TDO Delay (low to valid)
TDO Hold (low to invalid)
103
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.5 Interrupt
CKO*
V OH
V OL
t21
INT[1:0]
V IH
V IL
t22
t23
IACK†
t25
V OH
V OL
t24
t26
VEC[3:0]
V OH
V OL
5-4018 (F)
* CKO is free-running.
† IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion.
Figure 40. Interrupt Timing Diagram
Table 113. Timing Requirements for Interrupt
Abbreviated Reference
t21
t22
Parameter
Interrupt Setup (high to low)
INT Assertion Time (high to low)
Min
19
2T
Max
—
—
Unit
ns
ns
Max
T/2 + 10
12.5
10
12.5
Unit
ns
ns
ns
ns
Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.
Table 114. Timing Characteristics for Interrupt
Abbreviated Reference
t23
t24
t25
t26
Parameter
IACK Assertion Time (low to high)
VEC Assertion Time (low to high)
IACK Invalid Time (low to low)
VEC Invalid Time (low to low)
Min
—
—
—
—
Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.
104
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.6 Bit Input/Output (BIO)
t144
CKO
V OH
V OL
t29
V OH
IOBIT
(OUTPUT) V OL
VALID OUTPUT
t28
t27
IOBIT
(INPUT)
V IH
DATA INPUT
V IL
5-4019 (F).a
Figure 41. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit)
Table 115. Timing Requirements for BIO Input Read
Abbreviated Reference
t27
t28
Parameter
IOBIT Input Setup Time (valid to high)
IOBIT Input Hold Time (high to invalid)
Min
15
0
Max
—
—
Unit
ns
ns
Min
—
1
Max
9
—
Unit
ns
ns
Table 116. Timing Characteristics for BIO Output
Abbreviated Reference
t29
t144
Parameter
IOBIT Output Valid Time (low to valid)
IOBIT Output Hold Time (low to invalid)
t144
CKO
VOH –
V O L–
t29
IOBIT
VOH –
(OUTPUT) V O L–
VALID OUTPUT
t141
IOBIT
(INPUT)
VIH –
V I L–
t142
TEST INPUT
5-4019 (F).b
Figure 42. Write Outputs and Test Inputs (cbit = Immediate)
Table 117. Timing Requirements for BIO Input Test
Abbreviated Reference
t141
t142
Lucent Technologies Inc.
Parameter
IOBIT Input Setup Time (valid to low)
IOBIT Input Hold Time (low to invalid)
Min
15
0
Max
—
—
Unit
ns
ns
105
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.7 External Memory Interface
The following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external
memory enables unless so stated. See the DSP1611/17/18/27 Digital Signal Processor Information Manual for a
detailed description of the external memory interface including other functional diagrams.
CKO
VOH
VOL
t33
t34
VOH
ENABLE
VOL
W* = 0
5-4020 (F).b
* W = number of wait-states.
Figure 43. Enable Transition Timing
Table 118. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO)
Abbreviated Reference
t33
t34
Parameter
CKO to ENABLE Active (low to low)
CKO to ENABLE Inactive (low to high)
Min
0
–1
Max
5
4.5
Unit
ns
ns
Table 119. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F)
Abbreviated Reference
t33
106
Parameter
CKO to Delayed ENABLE Active (low to low)
Min
T/2
Max
T/2 + 7
Unit
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
(MWAIT = 0 x 2222)
W* = 2
CKO
V OH
V OL
t127
ENABLE
V OH
V OL
t129
t130
V IH
DB
READ DATA
V IL
t150
t128
AB
V OH
V OL
READ ADDRESS
5-4021 (F).a
* W = number of wait-states.
Figure 44. External Memory Data Read Timing Diagram
Table 120. Timing Characteristics for External Memory Access
Abbreviated Reference
t127
t128
Parameter
Enable Width (low to high)
Address Valid (enable low to valid)
Min
T(1 + W) – 1.5
—
Max
—
2.5
Unit
ns
ns
Table 121. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO)
Abbreviated
Reference
t129
t130
t150
19.2 ns
Min
Max
Read Data Setup (valid to enable high)
15
—
Read Data Hold (enable high to hold)
0
—
External Memory Access Time (valid to valid) — T(1 + W) – 15
Lucent Technologies Inc.
Parameter
12.5 ns
Unit
Min
Max
13
—
ns
0
—
ns
—
T(1 + W) – 14 ns
107
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
(MWAIT = 0x1002)
W* = 2
CKO
ERAMLO
DB
W* = 1
VOH
VOL
VOH
VOL
VOH
VOL
WRITE DATA
READ
t131
EROM
VOH
VOL
t132
t133
RWN
t134
VOH
VOL
t135
t136
AB
VOH
WRITE ADDRESS
VOL
READ ADDRESS
5-4022 (F).a
* W = number of wait-states.
Figure 45. External Memory Data Write Timing Diagram
Table 122. Timing Characteristics for External Memory Data Write (All Enables)
Abbreviated
Reference
t131
t132
t133
t134
t135
t136
108
Parameter
19.2 ns
12.5 ns
Min
Max
Min
Max
Write Overlap (enable low to 3-state)
—
0
—
0
RWN Advance (RWN high to enable high)
0
—
0
—
RWN Delay (enable low to RWN low)
0
—
0
—
Write Data Setup (data valid to RWN high)
T(1 + W)/2 – 4 — T(1 + W)/2 – 3 —
RWN Width (low to high)
T(1 + W) – 5
—
T(1 + W) – 4
—
Write Address Setup (address valid to RWN low)
0
—
0
—
Unit
ns
ns
ns
ns
ns
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
(MWAIT = 0x1002)
W* = 2
CKO
ERAMLO
EROM
W* = 1
VOH
VOL
VOH
VOL
VOH
VOL
t131
DB
VOH
VOL
WRITE
READ
t137
t138
RWN
VOH
VOL
t139
AB
VOH
VOL
WRITE ADDRESS
READ ADDRESS
5-4023 (F).a
* W = number of wait-states.
Figure 46. Write Cycle Followed by Read Cycle
Table 123. Timing Characteristics for Write Cycle Followed by Read Cycle
Abbreviated Reference
t131
t137
t138
t139
Lucent Technologies Inc.
Parameter
Write Overlap (enable low to 3-state)
Write Data 3-state (RWN high to 3-state)
Write Data Hold (RWN high to data hold)
Write Address Hold (RWN high to address hold)
Min
—
—
0
0
Max
0
2
—
—
Unit
ns
ns
ns
ns
109
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.8 PHIF Specifications
For the PHIF, read means read by the external user (output by the DSP); write is similarly defined. The 8-bit reads/
writes are identical to one-half of a 16-bit access.
16-bit READ
16-bit WRITE
VIH–
PCSN
PODS
VIL–
VIH–
VIL–
t41
t42
t44
VIH–
PIDS
VIL–
t43
PBSEL
VIH–
VIL–
t47
t45
PSTAT
t48
t46
VIH–
VIL–
t49
VIH–
PB[7:0]
t50
t154
t51
t52
VIL–
5-4036 (F)
Figure 47. PHIF Intel Mode Signaling (Read and Write) Timing Diagram
Table 124. Timing Requirements for PHIF Intel Mode Signaling
Abbreviated Reference
t41
t42
t43
t44
t45*
t46*
t47*
t48*
t51*
t52*
Parameter
PODS to PCSN Setup (low to low)
PCSN to PODS Hold (high to high)
PIDS to PCSN Setup (low to low)
PCSN to PIDS Hold (high to high)
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
PB Write to PCSN Setup (valid to high)
PCSN to PB Write Hold (high to invalid)
Min
0
0
0
0
4
0
6
0
10
4
Max
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can
also be initiated and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, whichever comes last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low,
if PODS goes low after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction
is initiated by PCSN or PIDS going low, whichever comes last. An input transaction is completed by PCSN or PIDS going high, whichever
comes first. All requirements referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal.
Table 125. Timing Characteristics for PHIF Intel Mode Signaling
Abbreviated Reference
t49*
t50*
t154
Parameter
PCSN to PB Read (low to valid)
PCSN to PB Read Hold (high to invalid)
PCSN to PB Read 3-state (high to 3-state)
Min
—
0
—
Max
12
—
8
Unit
ns
ns
ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can
also be initiated and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, whichever comes last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low,
if PODS goes low after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction
is initiated by PCSN or PIDS going low, whichever comes last. An input transaction is completed by PCSN or PIDS going high, whichever
comes first. All requirements referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal.
110
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
16-bit WRITE
16-bit READ
8-bit READ
8-bit WRITE
t55
t55
PCSN
VIH
VIL
t56
t55
PODS
t56
VIH
VIL
t56
PIDS
t56
t55
VIH
VIL
t56
PBSEL
VOH
VOL
t53
POBE
t53
VOH
VOL
t54
t54
PIBF
VOH
VOL
5-4037 (F).a
Figure 48. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram
Table 126. Timing Requirements for PHIF Intel Mode Signaling
Abbreviated Reference
t55
t56
Parameter
PCSN/PODS/PIDS Pulse Width (high to low)
PCSN/PODS/PIDS Pulse Width (low to high)
Min
20.5
20.5
Max
—
—
Unit
ns
ns
Max
17
17
Unit
ns
ns
Table 127. Timing Characteristics for PHIF Intel Mode Signaling
Abbreviated Reference
t53*
t54*
Parameter
PCSN/PODS to POBE† (high to high)
PCSN/PIDS to PIBF† (high to high)
Min
—
—
* t53 should be referenced to the rising edge of PCSN or PODS, whichever comes first. t54 should be referenced to the rising edge of
PCSN or PIDS, whichever comes first.
† POBE and PIBF may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 and
t54 apply to the inverted levels as well as those shown.
Lucent Technologies Inc.
111
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
16-bit READ
16-bit WRITE
VI H
PCSN
VIL
t42
VI H
PDS VIL
t41
t43
t44
t47
t48
VI H
PRWN
VIL
t43
PBSEL
t44
VI H
VIL
t45
PSTAT
t46
VI H
VIL
t49
t50
t154
t51
t52
PB[7:0]
5-4038 (F).a
Figure 49. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram
Table 128. Timing Requirements for PHIF Motorola Mode Signaling
Abbreviated Reference
t41
Min
0
Max
—
Unit
ns
0
—
ns
t43
PCSN to PDS† Hold (high to invalid)
PRWN to PCSN Setup (valid to low)
4
—
ns
0
—
ns
t42
Parameter
PDS† to PCSN Setup (valid to low)
t44
PCSN to PRWN Hold (high to invalid)
t45*
PSTAT to PCSN Setup (valid to low)
4
—
ns
t46*
PCSN to PSTAT Hold (high to invalid)
0
—
ns
t47*
PBSEL to PCSN Setup (valid to low)
6
—
ns
t48*
PCSN to PBSEL Hold (high to invalid)
0
—
ns
t51*
PB Write to PCSN Setup (valid to high)
10
—
ns
t52*
PCSN to PB Write Hold (high to invalid)
4
—
ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can
also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last.
For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low
after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to
PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 49 and 50. POBE and PIBF may be programmed to
be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 129. Timing Characteristics for PHIF Motorola Mode Signaling
Abbreviated Reference
t49*
t50*
t154
Parameter
PCSN to PB Read (low to valid)
PCSN to PB Read Hold (high to invalid)
PCSN to PB Read 3-state (high to 3-state)
Min
—
0
—
Max
12
—
8
Unit
ns
ns
ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can
also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last.
For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low
after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to
PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
112
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
16-bit READ
16-bit WRITE
8-bit READ
8-bit WRITE
t55
t55
PCSN
VIH–
VIL–
t56
t55
PDS
t56
VIH–
VIL–
t56
PRWN
t56
t55
VIH–
VIL–
t56
PBSEL
VOH–
VOL–
t53
POBE
t53
VOH–
VOL–
t54
t54
PIBF
VOH–
VOL–
5-4039 (F).a
Figure 50. PHIF Motorola Mode Signaling (Pulse Period and Flags) Timing Diagram
Table 130. Timing Characteristics for PHIF Motorola Mode Signaling
Abbreviated Reference
t53*
PCSN/PDS†
Parameter
t54*
PCSN/PDS†
to
POBE†
to
PIBF†
(high to high)
(high to high)
Min
—
Max
17
Unit
ns
—
17
ns
* An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For example, t53 and t54 should be referenced
to PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first.
All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or
complete a transaction.
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 49 and 50. POBE and PIBF may be programmed to
be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 131. Timing Requirements for PHIF Motorola Mode Signaling
Abbreviated Reference
Parameter
t55
PCSN/PDS/PRWN Pulse Width (high to low)
t56
PCSN/PDS/PRWN Pulse Width (low to high)
Lucent Technologies Inc.
Min
20
20
Max
—
—
Unit
ns
ns
113
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
V IH
PCSN
PODS (PDS*)
PIDS (PRWN*)
V IL
V IH
V IL
V IH
V IL
t47
PBSEL
t48
V IH
V IL
t46
t45
PSTAT
V IH
V IL
t49
PB[7:0]
V OH
t50
t154
V OL
5-4040 (F).a
* Motorola mode signal name.
Figure 51. PHIF Intel or Motorola Mode Signaling (Status Register Read) Timing Diagram
Table 132. Timing Requirements for Intel and Motorola Mode Signaling (Status Register Read)
Abbreviated Reference
t45†
t46‡
t47†
t48‡
Parameter
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
Min
4
0
6
0
Max
—
—
—
—
Unit
ns
ns
ns
ns
† t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last.
‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.
Table 133. Timing Characteristics for Intel and Motorola Mode Signaling (Status Register Read)
Abbreviated Reference
t49†
t50‡
t154
Parameter
PCSN to PB Read (low to valid)
PCSN to PB Read Hold (high to invalid)
PCSN to PB Read 3-state (high to 3-state)
Min
—
0
—
Max
12
—
8
Unit
ns
ns
ns
† t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last.
‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.
114
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
RSTB
VIH–
VIL–
POBE
VOH–
VOL–
PIBF
VOH–
VOL–
t57
t58
5-4775 (F)
Figure 52. PHIF, PIBF, and POBE Reset Timing Diagram
Table 134. PHIF Timing Characteristics for PHIF, PIBF, and POBE Reset
Abbreviated Reference
t57
t58
Parameter
RSTB Disable to POBE/PIBF* (high to valid)
RSTB Enable to POBE/PIBF* (low to invalid)
Min
—
3
Max
25
25
Unit
ns
ns
* After reset, POBE and PIBF always go to the levels shown, indicating output buffer empty and input buffer empty. The DSP program, however,
may later invert the definition of the logic levels for POBE and PIBF. t57 and t58 continue to apply.
CKO
VIH–
VIL–
t59
†
VOH–
VOL–
†
VOH–
VOL–
POBE
t59
PIBF
5-4776 (F)
† POBE and PIBF can be programmed to be active-high or active-low. They are shown active-high. The timing characteristic for active-low is
the same as for active-high.
Figure 53. PHIF, PIBF, and POBE Disable Timing Diagram
Table 135. PHIF Timing Characteristics for POBE and PIBF Disable
Abbreviated Reference
t59
Lucent Technologies Inc.
Parameter
CKO to POBE/PIBF Disable (high/low to disable)
Min
—
Max
20
Unit
ns
115
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.9 Serial I/O Specifications
t70
VIH–
VIL–
ICK
ILD
VIH–
VIL–
DI
VIH–
VIL–
t72
t71
t75
t74
t73
t75
t77
t78
B0
B1
BN – 1*
B0
t79
VOH–
VOL–
IBF
5-4777 (F)
* N = 16 or 8 bits.
Figure 54. SIO Passive Mode Input Timing Diagram
Table 136. Timing Requirements for Serial Inputs
Abbreviated Reference
t70
t71
t72
t73
t74
t75
t77
t78
Parameter
Clock Period (high to high)†
Min
40
Clock Low Time (low to high)
Clock High Time (high to low)
Load High Setup (high to high)
Load Low Setup (low to high)
Load High Hold (high to invalid)
Data Setup (valid to high)
Data Hold (high to invalid)
Max
—‡
—
—
—
—
—
—
—
18
18
8
8
0
7
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
† For multiprocessor mode, see note in Section 11.10.
‡ Device is fully static; t70 is tested at 200 ns.
Table 137. Timing Characteristics for Serial Outputs
Abbreviated Reference
t79
116
Parameter
IBF Delay (high to high)
Min
—
Max
35
Unit
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
ICK
VOH–
VOL–
t101
t76a
ILD
VOH–
VOL–
DI
VIH–
VIL–
IBF
VOH–
VOL–
*
t77
t78
B0
B1
BN – 1
B0
t79
5-4778 (F)
* ILD goes high during bit 6 (of 0:15), N = 8 or 16.
Figure 55. SIO Active Mode Input Timing Diagram
Table 138. Timing Requirements for Serial Inputs
Abbreviated Reference
t77
t78
Parameter
Data Setup (valid to high)
Data Hold (high to invalid)
Min
7
0
Max
—
—
Unit
ns
ns
Table 139. Timing Characteristics for Serial Outputs
Abbreviated Reference
t76a
t101
t79
Lucent Technologies Inc.
Parameter
ILD Delay (high to low)
ILD Hold (high to invalid)
IBF Delay (high to high)
Min
—
3
—
Max
35
—
35
Unit
ns
ns
ns
117
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
t80
OCK
t82
t81
t85
t84
VIH–
VIL–
t83
OLD
VIH–
VIL–
DO*
VOH–
VOL–
t85
t88
t87
B0
t94
SADD
VOH–
VOL–
DOEN
VIH–
VIL–
OBE
VOH–
VOL–
t92
AD0
t90
B1
t90
B7
t93
AD1
BN – 1
t89
t93
AS7
AD7
t95
t96
5-4796 (F)
* See sioc register, MSB field, to determine if B0 is the MSB or LSB. See sioc register, ILEN field, to determine if the DO word length is 8 bits
or 16 bits.
Figure 56. SIO Passive Mode Output Timing Diagram
Table 140. Timing Requirements for Serial Inputs
Abbreviated Reference
t80
t81
t82
t83
t84
t85
Parameter
high)†
Clock Period (high to
Clock Low Time (low to high)
Clock High Time (high to low)
Load High Setup (high to high)
Load Low Setup (low to high)
Load Hold (high to invalid)
Min
40
Unit
ns
18
18
8
8
0
Max
—‡
—
—
—
—
—
Min
—
—
—
3
—
3
—
—
—
Max
35
35
35
—
35
—
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
† For multiprocessor mode, see note in Section 11.10.
‡ Device is fully static; t80 is tested at 200 ns.
Table 141. Timing Characteristics for Serial Outputs
Abbreviated Reference
t87
t88
t89
t90
t92
t93
t94
t95
t96
118
Parameter
Data Delay (high to valid)
Enable Data Delay (low to active)
Disable Data Delay (high to 3-state)
Data Hold (high to invalid)
Address Delay (high to valid)
Address Hold (high to invalid)
Enable Delay (low to active)
Disable Delay (high to 3-state)
OBE Delay (high to high)
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
OCK
VOH–
VOL–
t102
t86a
OLD
VOH–
VOL–
DO
VOH–
VOL–
*
t88
B0
t94
SADD
t87
VOH–
VOL–
t92
AD0
t90
B1
t90
B7
t93
AD1
BN – 1
t89
t93
AS7
AD7
t95
DOEN
VIH–
VIL–
OBE
VOH–
VOL–
t96
5-4797 (F)
* OLD goes high at the end of bit 6 of 0:15.
Figure 57. SIO Active Mode Output Timing Diagram
Table 142. Timing Characteristics for Serial Output
Abbreviated Reference
t86a
t102
t87
t88
t89
t90
t92
t93
t94
t95
t96
Lucent Technologies Inc.
Parameter
OLD Delay (high to low)
OLD Hold (high to invalid)
Data Delay (high to valid)
Enable Data Delay (low to active)
Disable Data Delay (high to 3-state)
Data Hold (high to invalid)
Address Delay (high to valid)
Address Hold (high to invalid)
Enable Delay (low to active)
Disable Delay (high to 3-state)
OBE Delay (high to high)
Min
—
3
—
—
—
3
—
3
—
—
—
Max
35
—
35
35
35
—
35
—
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
119
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
CKO
VOH–
VOL–
ICK
VOH–
VOL–
OCK
VOH–
VOL–
ICK/OCK*
ILD
OLD
SYNC
t97
t98
t99
t100
VOH–
t76a
t101
t76b
t101
t86a
t102
t86b
t102
t103
t105
t104
t105
VOH–
VOL–
VOH–
VOL–
VOH–
VOL–
5-4798 (F)
* See sioc register, LD field.
Figure 58. Serial I/O Active Mode Clock Timing
Table 143. Timing Characteristics for Signal Generation
Abbreviated Reference
t97
t98
t99
t100
t76a
t76b
t101
t86a
t86b
t102
t103
t104
t105
120
Parameter
ICK Delay (high to high)
ICK Delay (high to low)
OCK Delay (high to high)
OCK Delay (high to low)
ILD Delay (high to low)
ILD Delay (high to high)
ILD Hold (high to invalid)
OLD Delay (high to low)
OLD Delay (high to high)
OLD Hold (high to invalid)
SYNC Delay (high to low)
SYNC Delay (high to high)
SYNC Hold (high to invalid)
Min
—
—
—
—
—
—
3
—
—
3
—
—
3
Max
18
18
18
18
35
35
—
35
35
—
35
35
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
11 Timing Characteristics for 2.7 V Operation (continued)
11.10 Multiprocessor Communication
TIME SLOT 1
TIME SLOT 2
OCK/ICK
t113
t112
t112
SYNC
VIH–
VIL–
DO/D1
VOH–
VOL–
t113
*
t116
B15
B0
B1
t117
B7
B8
B15
B0
t114
t122
t121
AD0
SADD
AD1
AD7
AS0
t120
DOEN
t115
AS7
AD0
t120
VOH–
VOL–
5-4799 (F)
* Negative edge initiates time slot 0.
Figure 59. SIO Multiprocessor Timing Diagram
Note: All serial I/O timing requirements and characteristics still apply, but the minimum clock period in passive
multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.
Table 144. Timing Requirements for SIO Multiprocessor Communication
Abbreviated Reference
t112
t113
t114
t115
Parameter
Sync Setup (high/low to high)
Sync Hold (high to high/low)
Address Setup (valid to high)
Address Hold (high to invalid)
Min
35
0
12
0
Max
—
—
—
—
Unit
ns
ns
ns
ns
Min
—
—
—
—
—
Max
35
30
25
35
30
Unit
ns
ns
ns
ns
ns
Table 145. Timing Characteristics for SIO Multiprocessor Communication
Abbreviated Reference†
t116
t117
t120
t121
t122
Parameter
Data Delay (bit 0 only) (low to valid)
Data Disable Delay (high to 3-state)
DOEN Valid Delay (high to valid)
Address Delay (bit 0 only) (low to valid)
Address Disable Delay (high to 3-state)
† With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.
Lucent Technologies Inc.
121
Data Sheet
March 2000
DSP1629 Digital Signal Processor
12 Outline Diagrams
12.1 100-Pin BQFP (Bumpered Quad Flat Pack)
All dimensions are in millimeters.
22.860 ± 0.305
22.350 ± 0.255
19.050 ± 0.405
13
1
89
14
88
PIN #1
IDENTIFIER
ZONE
EDGE CHAMFER
22.350
± 0.255
19.050
± 0.405
38
22.860
± 0.305
64
39
63
DETAIL A
DETAIL B
4.570 MAX
3.555
± 0.255
SEATING PLANE
0.10
0.760 ± 0.255
0.635 TYP
0.255
0.175 ± 0.025
GAGE PLANE
SEATING PLANE
0.280 ± 0.075
0.91/1.17
DETAIL A
0.150
M
DETAIL B
5-1970 (F)r.10
122
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
12 Outline Diagrams (continued)
12.2 100-Pin TQFP (Thin Quad Flat Pack)
All dimensions are in millimeters.
16.00 ± 0.20
14.00 ± 0.20
PIN #1 IDENTIFIER ZONE
100
76
75
1
14.00
± 0.20
16.00
± 0.20
51
25
26
50
DETAIL A
DETAIL B
1.40 ± 0.05
1.60 MAX
SEATING PLANE
0.08
0.05/0.15
0.50 TYP
1.00 REF
0.106/0.200
0.25
GAGE PLANE
0.19/0.27
SEATING PLANE
0.45/0.75
DETAIL A
Lucent Technologies Inc.
0.08
DETAIL B
M
5-2146 (F)r.14
123
Data Sheet
March 2000
DSP1629 Digital Signal Processor
12 Outline Diagrams (continued)
12.3 144-Pin PBGA (Plastic Ball Grid Array)
All dimensions are in millimeters.
13.00 ± 0.20
11.50
PIN A1
CORNER
+0.70
–0.00
11.50
+0.70
–0.00
13.00
± 0.20
MOLD
COMPOUND
PWB
0.80 ± 0.05
0.36 ± 0.04
1.56 + 0.19
– 0.21
SEATING PLANE
0.20
SOLDER BALL
0.40 ± 0.10
11 SPACES @ 1.00 = 11.00
M
L
K
J
0.50 ± 0.10
H
G
11 SPACES @
1.00 = 11.00
F
E
D
C
B
A
PIN A1
CORNER
1
2
3
4
5
6
7
8
9
10
11
12
5-5205 (F)
124
Lucent Technologies Inc.
Data Sheet
March 2000
DSP1629 Digital Signal Processor
Notes
Lucent Technologies Inc.
125
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Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
March 2000
DS00-206WTEC (Replaces DS00-062WTEC)