Data Sheet February 1998 T7502 Dual PCM Codec with Filters Features Applications ■ +5 V only ■ Speakerphone ■ Automatic powerdown mode ■ Telephone answering device (TAD) ■ Low-power, latch-up-free CMOS technology ■ POTS for ISDN ■ On-chip sample and hold, autozero, and precision voltage reference ■ Differential architecture for high noise immunity and power supply rejection ■ Automatic master clock frequency selection ■ 2.048 MHz or 4.096 MHz fixed data rate ■ Frame sync controlled channel swapping ■ Differential analog I/O ■ 300 Ω output drivers ■ Operating temperature range: –40 °C to +85 °C ■ A-law companding Description The T7502 device is a single-chip, two-channel A-law PCM codec with filters. This integrated circuit provides analog-to-digital and digital-to-analog conversion. It provides the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed (TDM) system. The device features a differential transmit amplifier, and the power receive amplifier is capable of driving 600 Ω differentially. PCM timing is defined by a single frame sync pulse. This device operates in a delayed timing mode (digital data is valid one clock cycle after frame sync goes high). The T7502 is packaged in a 20-pin SOJ. GSX0 DX VFXIN0 VFXIP0 VCM0 – FILTER NETWORK + +2.4 V PCM INTERFACE ENCODER DR GNDD CHANNEL 0 FS VFROP0 FILTER NETWORK DECODER POWERDOWN CONTROL VFRON0 INTERNAL TIMING & CONTROL MCLK GSX1 VFXIN1 VFXIP1 VCM1 CHANNEL 1 VFROP1 VFRON1 BIAS CIRCUITRY & REFERENCE VDD (1) GNDA (2) 5-3609.b Figure 1. Block Diagram Data Sheet February 1998 T7502 Dual PCM Codec with Filters Functional Description The T7502 has one frame sync (FS) input that determines transmit and receive data timing for both channels. The width of the FS pulse determines the order of the two channels on the PCM buses. If FS is nominally one MCLK period wide (see Figure 5), the data for channel 0 is first. If FS is nominally two or more MCLK periods wide (Figure 6), the data for channel 1 is first. During a single 125 µs frame, the frame sync input is supplied a single pulse. The frequency of the master clock must be either 2.048 MHz or 4.096 MHz. Internal circuitry determines the master clock frequency during the powerup reset interval. Powerdown is achieved by removing the FS pulse for at least 500 µs with MCLK active, after which MCLK may be removed. Both channels are powered down together. Powerdown is not guaranteed if MCLK is lost, unless the device is already in the powerdown mode. GSXn RFN RIN VFXINn RIP VFXIPn TO CODEC FILTERS – + VCM0 2.4 V RFP GAIN = RFN RIN 5-3787 Figure 2. Typical Analog Input Section Pin Information VFROP0 1 20 VFROP1 VFRON0 2 19 VFRON1 GNDA0 3 18 GNDA1 VFXIN0 4 17 VFXIN1 VFXIP0 5 16 VFXIP1 15 GSX1 GSX0 6 VCM0 7 T - 7502 - - - EL 14 VCM1 VDD 8 13 FS MCLK 9 12 DR GNDD 10 11 DX 5-3788.a Figure 3. Pin Diagram 2 Lucent Technologies Inc. Data Sheet February 1998 T7502 Dual PCM Codec with Filters Pin Information (continued) Table 1. Pin Descriptions Symbol VFXIN1 VFXIN0 VFXIP1 VFXIP0 GSX1 GSX0 VFROP1 VFROP0 VFRON1 VFRON0 VDD Pin 17 4 16 5 15 6 20 1 19 2 8 Type Name/Function I Voice Frequency Transmitter Negative Input. Analog inverting input to the uncommitted operational amplifier at the transmit filter input. I Voice Frequency Transmitter Positive Input. Analog noninverting input to the uncommitted operational amplifier at the transmit filter input. O Gain Set for Transmitter. Output of the transmit uncommitted operational amplifier. The pin is the input to the transmit differential filters. O Voice Frequency Receiver Positive Output. This pin can drive ≥300 Ω loads. GNDA1 GNDA0 DR 18 3 12 — DX 11 O MCLK 9 I GNDD FS 10 13 — VCM0 VCM1 7 14 O Voice Frequency Receiver Negative Output. This pin can drive ≥300 Ω loads. — +5 V Power Supply. This pin should be bypassed to analog ground with at least 0.1 µF of capacitance as close to the device as possible. VDD serves both analog and digital internal circuits. Analog Grounds. Both ground pins must be connected on the circuit board. AGND serves both analog and digital internal circuits. Receive PCM Data Input. The data on this pin is shifted into the device on the falling edges of MCLK. Sixteen consecutive bits of data (8 bits for channel 0, and 8 bits for channel 1) are entered after the FS pulse has been detected. Transmit PCM Data Output. This pin remains in the high-impedance state except during active transmit time slots. Sixteen consecutive bits of data (8 bits for channel 0 and 8 bits for channel 1) are shifted out on the rising edge of MCLK. Data is shifted out on the rising edge of MCLK. Master Clock Input. The frequency must be 2.048 MHz or 4.096 MHz. This clock serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is required. Digital Ground. Ground connection for the digital circuitry. Frame Sync. This signal is an edge trigger and must be high for a minimum of one MCLK cycle. This signal must be derived from MCLK. If FS is low for 500 µs while MCLK remains active, then the device fully powers down. An internal pull-down device is included on FS. Voltage Common Mode. 2.4 Vdc. I Id* O * Id indicates a pull-down device is included on this lead. Lucent Technologies Inc. 3 Data Sheet February 1998 T7502 Dual PCM Codec with Filters Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Storage Temperature Range Power Supply Voltage Voltage on Any Pin with Respect to Ground Maximum Power Dissipation (package limit) Symbol Tstg VDD — PD Min –55 — –0.5 — Max 150 6.5 0.5 + VDD 600 Unit °C V V mW Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: HBM ESD Threshold Voltage Device Rating T7502 >2000 V Electrical Characteristics Specifications apply for TA = –40 °C to +85 °C, VDD = 5 V ± 5%, MCLK = either 2.048 MHz or 4.096 MHz, and GND = 0 V, unless otherwise noted. dc Characteristics Table 2. Digital Interface Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Current Pins Without Pulldown Input Current Pin with Pull-down Output Current in High-impedance State Input Capacitance 4 Symbol VIL VIH VOL VOH Test Conditions All digital inputs All digital inputs DX, IL = 3.2 mA DX, IL = –3.2 mA DX, IL = –320 µA Any digital input GND < VIN < VDD Min — 2.0 — 2.4 3.5 –10 Typ — — — — — ±0.01 Max 0.8 — 0.4 — — 10 Unit V V V V V µA IOZ Any digital input GND < VIN < VDD DX 2 –30 10 ±0.02 150 30 µA µA CI — — — 5 pF II II Lucent Technologies Inc. Data Sheet February 1998 T7502 Dual PCM Codec with Filters Electrical Characteristics (continued) dc Characteristics (continued) Table 3. Power Dissipation Power measurements are made at MCLK = 4.096 MHz, outputs unloaded. Parameter Powerdown Current Powerup Current Symbol IDDO IDDU Test Conditions MCLK present and FS ≤ 0.4 V MCLK, FS pulse present Min — — Typ 0.1 18 Max 1 25 Unit mA mA Transmission Characteristics Table 4. Analog Interface Parameter Input Resistance, FSXI Input Leakage Current, VFXI Input Capacitance, VFXIN, VFXIP Input Offset Voltage of Uncommitted Op Amp, VFXIN – VFXIP Input Common-mode Voltage Range, VFXIN, VFXIP Input Common-mode Rejection Ratio, VFXIN, VFXIP Gain Bandwidth Product (10 kHz) of Uncommitted Op Amp Equivalent Input Noise Between VFXIN and VFXIP at GSX Output Voltage Range, GSX dc Open-loop Voltage Gain, GSX Differential Output dc Offset Voltage Load Capacitance, GSX Load Resistance, GSX VCM Output Voltage Referenced to GND VCM Output Load Capacitance Load Resistance, VCM Load Resistance, VFRO Load Capacitance, VFRO Output Resistance, VFRO Output Voltage, VFRO Output Leakage Current, VFRO, Powerdown Output Voltage Swing, VFRO Lucent Technologies Inc. Symbol RVFXI IBVFXI — — Test Conditions VFxI = 2.4 V VFxI = 2.4 V — — Max — 2.4 10 5 Unit MΩ µA pF mV — — 1.2 — VDD – 1.75 V — — — 60 — dB — — — 3000 — kHz — — — –30 — dBrnC 0.5 90 –80 — 10 2.25 0 10 300 — — — — ±10 — — 2.35 — — — — 0.3 VDD – 0.5 — 80 50 — 2.5 50 — — 100 3 V dB mV pF kΩ V pF kΩ Ω pF Ω 2.25 2.35 2.5 V –30 ±0.02 30 µA 3.2 — — Vp-p — — AVOL — — — CLX1 — RLX1 — — — — — RLVCM — RLVFRO — CLVFRO — ROVFRO 0 dBm0, 1020 Hz PCM code applied to DR VOR Alternating ± zero A-law PCM code applied to DR IOVFRO — VSWR RL = 300 Ω Min Typ 1.0 — –2.4 ±0.01 — –5 — 5 Data Sheet February 1998 T7502 Dual PCM Codec with Filters Transmission Characteristics (continued) ac Transmission Characteristics Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Table 5. Absolute Gain Parameter Encoder Milliwatt Response (transmit gain tolerance) Decoder Milliwatt Response (receive gain tolerance) Symbol EmW Test Conditions Signal input of 0.775 Vrms A-law Min –0.25 Typ — Max 0.25 Unit dBm0 DmW Measured single-ended relative to 0.775 Vrms A-law, PCM input of 0 dBm0 1020 Hz RL = 10 kΩ –0.25 — 0.25 dBm0 Table 6. Gain Tracking Parameter Transmit Gain Tracking Error Sinusoidal Input Receive Gain Tracking Error Sinusoidal Input Symbol GTX GTR Test Conditions +3 dBm0 to –37 dBm0 –37 dBm0 to –50 dBm0 +3 dBm0 to –37 dBm0 –37 dBm0 to –50 dBm0 Min –0.25 –0.50 –0.25 –0.50 Typ — — — — Max 0.25 0.50 0.25 0.50 Unit dB dB dB dB Table 7. Distortion Parameter Transmit Signal to Distortion Symbol SDX Receive Signal to Distortion SDR Single Frequency Distortion, Transmit SFDX Single Frequency Distortion, Receive SFDR Intermodulation Distortion 6 IMD Test Conditions A-law +3 dBm0 ≤ VFXI ≤ –30 dBm0 A-law –30 dBm0 ≤ VFXI ≤ –40 dBm0 A-law –40 dBm0 ≤ VFxI ≤ –45 dBm0 A-law +3 dBm0 ≤ VFRO ≤ –30 dBm0 A-law –30 dBm0 ≤ VFRO ≤ –40 dBm0 A-law –40 dBm0 ≤ VFRO ≤ –45 dBm0 200 Hz—3400 Hz, 0 dBm0 input, output any other single frequency ≤ 3400 Hz 200 Hz—3400 Hz, 0 dBm0 input, output any other single frequency ≤ 3400 Hz Transmit or receive, two frequencies in the range (300 Hz—3400 Hz) at –6 dBm0 Min 35 29 25 35 29 25 — Typ — — — — — — — Max — — — — — — –38 Unit dB dB dB dB dB dB dBm0 — — –40 dBm0 — — –42 dBm0 Lucent Technologies Inc. Data Sheet February 1998 T7502 Dual PCM Codec with Filters Transmission Characteristics (continued) ac Transmission Characteristics (continued) Table 8. Envelope Delay Distortion Parameter TX Delay, Absolute TX Delay, Relative to 1600 Hz Symbol DXA DXR RX Delay, Absolute RX Delay, Relative to 1600 Hz DRA DRR Round Trip Delay, Absolute DRTA Test Conditions f = 1600 Hz f = 500 Hz—600 Hz f = 600 Hz—800 Hz f = 800 Hz—1000 Hz f = 1000 Hz—1600 Hz f = 1600 Hz—2600 Hz f = 2600 Hz—2800 Hz f = 2800 Hz—3000 Hz f = 1600 Hz f = 500 Hz—1000 Hz f = 1000 Hz—1600 Hz f = 1600 Hz—2600 Hz f = 2600 Hz—2800 Hz f = 2800 Hz—3000 Hz With or between channels f = 1600 Hz Min — — — — — — — — — –40 –30 — — — — Typ — — — — — — — — — — — — — — — Max 230 220 145 75 40 75 105 155 275 — — 90 125 175 470 Unit µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs Overload Compression Figure 4 shows the region of operation for encoder signal levels above the reference input power (0 dBm0). 9 FUNDAMENTAL OUTPUT POWER (dBm) 8 7 6 5 ACCEPTABLE REGION 4 3 2 1 1 2 3 4 5 6 7 8 9 FUNDAMENTAL INPUT POWER (dBm) 5-3586 Figure 4. Overload Compression Lucent Technologies Inc. 7 Data Sheet February 1998 T7502 Dual PCM Codec with Filters Transmission Characteristics (continued) ac Transmission Characteristics (continued) Table 9. Noise Parameter Transmit Noise, A-Law Receive Noise, A-Law Noise, Single Frequency Symbol NXp NRp NRS Power Supply Rejection Transmit Power Supply Rejection Receive Spurious Out-of-Band Signals at VFRO Relative to Input PSRX PSRX SOS Test Conditions Input amplifier gain = 36 dB PCM code is A-law positive one. f = 0 kHz—100 kHz, VFXIN = 0 Vrms, measurement at VFRO, DR = DX VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz—4 kHz f = 4 kHz—50 kHz PCM code is positive one LSB. VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz—4 kHz f = 4 kHz—25 kHz f = 25 kHz—50 kHz 0 dBm0, 300 Hz—3400 Hz input PCM code applied: 4600 Hz—7600 Hz 7600 Hz—8400 Hz 8400 Hz—50 kHz Min — — — Typ Max –68.5 –68 –82 –75 — –53 Unit dBm0p dBm0p dBm0 36 30 — — — — dB dB 36 40 30 — — — — — — dB dB dB — — — — — — –30 –40 –30 dB dB dB Table 10. Receive Gain Relative to Gain at 1.02 kHz Frequency (Hz) Below 3000 3140 3380 3860 4600 and above Min –0.150 –0.570 –0.735 — — Typ ±0.04 ±0.04 –0.50 –10.70 — Max 0.150 0.150 0.010 –9.400 –28 Unit dB dB dB dB dB Max –30 –26 –30 –30 0 0.150 0.150 0.010 –9.400 –32 Unit dB dB dB dB dB dB dB dB dB dB Table 11. Transmit Gain Relative to Gain at 1.02 kHz Frequency (Hz) 16.67 40 50 60 200 300 to 3000 3140 3380 3860 4600 and above 8 Min — — — — –1.800 –0.150 –0.570 –0.735 — — Typ –50 –34 –36 –50 –0.5 ±0.04 ±0.04 –0.50 –10.70 — Lucent Technologies Inc. Data Sheet February 1998 T7502 Dual PCM Codec with Filters Transmission Characteristics (continued) ac Transmission Characteristics (continued) Table 12. Interchannel Crosstalk (Between Channels) RF = ≤400 kΩ* Parameter Symbol Test Conditions Transmit to Receive CTXX-RY f = 300 Hz—3400 Hz Crosstalk 0 dBm0 idle PCM code for channel under test; Transmit Levels 0 dBm0 into any other single-channel VFXIN Receive to Transmit CTRX-XY f = 300 Hz—3400 Hz Crosstalk 0 dBm0 VFXIN = 0 Vrms for channel under test; Receive Levels 0 dBm0 code level on any other single-channel DR Transmit to TransCTXX-XY f = 300 Hz—3400 Hz mit Crosstalk 0 dBm0 applied to any single-channel 0 dBm0 Transmit VFXIN except channel under test, Levels which has VFXIN = 0 Vrms Receive to Receive CTRX-RY f = 300 Hz—3400 Hz Crosstalk 0 dBm0 0 dBm0 code level on any single-channel DR except Receive Levels channel under test which has idle code applied Min — Typ — Max –75 Unit dB — — –75 dB — — –75 dB — — –75 dB * For Table 12, crosstalk into the transmit channels (VFXIN) can be significantly affected by parasitic capacitive feeds from GSX and VFRO outputs. PWB layouts should be arranged to keep these parasitics low. The resistor value of RF (from GSX to VFXIN) should also be kept as low as possible (while maintaining the load on GSX above 10 kΩ per Table 4) to minimize crosstalk. Table 13. Intrachannel Crosstalk (Within Channels) RF = ≤400 kΩ* Parameter Symbol Transmit to Receive CTXX-RX Crosstalk 0 dBm0 Transmit Levels Receive to Transmit CTRX-XX Crosstalk 0 dBm0 Receive Levels Test Conditions f = 300 Hz—3400 Hz idle PCM code for channel under test; 0 dBm0 into VFXIN f = 300 Hz—3400 Hz VFXIN = 0 Vrms for channel under test; 0 dBm0 code level on DR Min — Typ — Max –65 Unit dB — — –65 dB * For Table 13, crosstalk into the transmit channels (VFXIN) can be significantly affected by parasitic capacitive feeds from GSX and VFRO outputs. PWB layouts should be arranged to keep these parasitics low. The resistor value of RF (from GSX to VFXIN) should also be kept as low as possible (while maintaining the load on GSX above 10 kΩ per Table 4) to minimize crosstalk. Lucent Technologies Inc. 9 Data Sheet February 1998 T7502 Dual PCM Codec with Filters Timing Characteristics Table 14. Clock Section (See Figures 5 and 6.) Symbol tMCHMCL1 tCDC tMCH1MCH2 tMCL2MCL1 Parameter Clock Pulse Width Duty Cycle, MC Clock Rise and Fall Time Test Conditions — — — Min 97 40 0 Typ — — — Max — 60 15 Unit ns % ns Test Conditions 0 < CLOAD < 100 pF 0 < CLOAD < 100 pF CLOAD = 0 — — — Min 0 0 10 50 50 50 Typ — — — — — — Max 60 60 100 — — — Unit ns ns ns ns ns ns Test Conditions — — Min 30 15 Typ — — Max — — Unit ns ns Table 15. Transmit Section (See Figures 5 and 6.) Symbol tMCHDV tMCHDV1 tMCHDZ* tFSHMCL tMCLFSH tFSLMCL Parameter Data Enabled on TS Entry Data Delay from MC Data Float on TS Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Low Setup * Timing parameter tMCHDZ is referenced to a high-impedance state. Table 16. Receive Section (See Figures 5 and 6.) Symbol tDVMCL tMCLDV 10 Parameter Receive Data Setup Receive Data Hold Lucent Technologies Inc. Data Sheet February 1998 T7502 Dual PCM Codec with Filters Timing Characteristics (continued) TIME SLOT tMCHMCL1 MCLK 1 tMCH1MCH2 2 tMCLFSH 3 4 5 tFSLMCL tFSHMCL 6 7 8 10 9 11 16 tMCL2MCL1 FS tMCHDV1 tMCHDV CH 0 BIT 2 CH 0 BIT 1 Dx tMCHDZ CH 0 BIT 3 CH 0 BIT 4 CH 0 BIT 5 BIT 1 CH 0 BIT 8 CH 1 BIT 1 CH1 BIT 2 CH 1 BIT 3 CH 1 BIT 8 tMCLDV tDVMCL DR CH 0 BIT 7 CH 0 BIT 6 BIT 3 BIT 2 BIT 4 BIT 6 BIT 5 BIT 7 BIT 8 BIT 1 BIT 2 BIT 3 BIT 8 DR STABLE DR STABLE 5-3581.c Figure 5. Short FS Transmit and Receive Timing (Channel 0 First) TIME SLOT tMCHMCL1 MCLK 1 tMCH1MCH2 2 3 4 5 tMCLFSH 6 tMCL2MCL1 tFSHMCL 7 8 10 9 11 16 tFSLMCL FS tMCHDV1 tMCHDV Dx CH 1 BIT 1 CH 1 BIT 2 CH 1 BIT 3 tMCHDZ CH 1 BIT 4 CH 1 BIT 5 DR BIT 2 DR STABLE CH 1 BIT 7 CH 1 BIT 8 CH 0 BIT 1 CH0 BIT 2 CH 0 BIT 3 CH 0 BIT 8 tMCLDV tDVMCL BIT 1 CH 1 BIT 6 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 1 BIT 2 BIT 3 BIT 8 DR STABLE 5-3581.d Figure 6. Long FS Transmit and Receive Timing (Channel 1 First) Lucent Technologies Inc. 11 Data Sheet February 1998 T7502 Dual PCM Codec with Filters Applications Figure 7 shows one possible analog connection. Fully differential structures used for the inputs minimize the noise gain from the internal 2.4 V bias voltage to the output of the single-ended transmitter op amp. The forward path gain is G, and by using resistors on the positive side that are a factor of 1/(2G + 1) of those on the negative side, the microphone and transformer feeds are kept well balanced. Using this ratio, G can be as low as unity (0 dB) without exceeding the common-mode limit of the op amp. Users have wide latitude when selecting between a balanced amplifier configuration or a single-ended configuration. Single-ended configurations usually need fewer external components (e.g., RIP = ∞ and RFP = 0 in Figure 2) but have two disadvantages: one, dc blocking from the source is typically required; two, internally generated noise at the common-mode pin VCM0 or VCM1 is amplified by G. For G > 10 (20 dB), this noise gain can become the factor that could limit performance. Single-ended configurations can be used even with microphones and transformers (RIP = 0 in these cases), but parasitic issues become somewhat more complex; so single-ended configurations are only suggested for gains of four (12 dB) or less. MICROPHONE GxR R R (2G + 1) GxR – – + + GxR (2G + 1) T7502 2.4 V 2.4 V + + – – R GxR R (2G + 1) (2G + 1) CENTRAL OFFICE LINE SPEAKER SPEAKER DRIVER DR DX MCLK FS DSP 5-3789.c Figure 7. Typical T7502 Application 12 Lucent Technologies Inc. Data Sheet February 1998 T7502 Dual PCM Codec with Filters Outline Diagram 20-Pin SOJ Controlling dimensions are in inches. L N B 1 PIN #1 IDENTIFIER ZONE W H SEATING PLANE 0.10 1.27 TYP 0.51 MAX 0.79 MAX 5-4413r4 Package Description SOJ (Small Outline, J-Lead) Number of Pins (N) 20 Lucent Technologies Inc. Maximum Length (L) 12.95 Package Dimensions Maximum Width Maximum Width Without Leads Including Leads (B) (W) 7.62 8.81 Maximum Height Above Board (H) 3.18 13 Data Sheet February 1998 T7502 Dual PCM Codec with Filters Ordering Information Device Code T - 7502 - - - EL 14 Package 20-Pin SOJ Temperature –40 °C to +85 °C Comcode 107622888 Lucent Technologies Inc. Data Sheet February 1998 T7502 Dual PCM Codec with Filters Notes Lucent Technologies Inc. 15 Data Sheet February 1998 T7502 Dual PCM Codec with Filters For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: [email protected] U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell), FRANCE: (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1998 Lucent Technologies Inc. All Rights Reserved February 1998 DS98-096ALC (Replaces DS96-372ALC) Printed On Recycled Paper