OKI Semiconductor
ML7204-001
FEDL7204-001DIGEST-01
Issue Date: Aug. 12, 2004
VoIP CODEC
GENERAL DESCRIPTION
The ML7204-001 is a speech CODEC for VoIP. As a speech CODEC, this LSI allows selection of
G.729.A/G711 and supports the PLC (Packet Loss Concealment) function.
With an echo canceler that handles 32 ms-delay and FSK detection/generation, DTMF detection/generation, and
tone detection/generation functions, the ML7204-001 is the most suitable LSI for adding the VoIP function to
TAs and routers.
FEATURES
• Power supply voltage
Digital power supply voltage (DVDD0, 1, 2):
3.0 to 3.6 V
Analog power supply voltage (AVDD):
3.0 to 3.6 V
• Speech CODEC:
G.729.A (8 kbps)/G.711 (64 kbps) µ-law and A-law (supports individual setting for transmission and
reception)
Supports ITU-T G.711 Appendix 1 compliant PLC (Packet Loss Concealment) function
Supports the 2-channel processing function (for 3-way communication)
• Built-in FIFO buffer (640 bytes) for transmission/reception data transfer
Allows selection of Frame/DMA (slave) interface
• Echo canceler for handling 32 ms delay
• DTMF detection
• DTMF generation (the tone generation function enables generation of DTMF signals)
• Tone detection:
2 types (1650 Hz and 2100 Hz: Detection frequency can be changed)
• Tone generation:
2 types
• FSK detection
• FSK generation
• Built-in 16-bit timer:
1 channel
• Dial pulse detection function (secondary function of general-purpose I/O ports)
• Dial pulse transmission function (secondary function of general-purpose I/O ports)
• General-purpose I/O ports
64-pin package: Equipped with 7 ports (with some of them having secondary function allocation)
100-pin package: Equipped with 21 ports (with some of them having secondary function allocation)
• Two types of built-in linear PCM CODEC (CODEC_A and CODEC_B)
• Analog interface
CODEC_A side: Incorporates one type each of input amplifier and output amplifier (10 kΩ driving)
CODEC_B side: Incorporates one type each of input amplifier and output amplifier (10 kΩ driving)
• PCM interface coding format:
Allows selection of 16-bit linear/G.711 (64 kbps) µ-law or A-law
• PCM serial transmission rate: 64 kHz to 2.048 MHz (fixed to 2.048 MHz for output)
• PCM time slot assignment function (allows up to 2 slots for input and 1 slot for output individually)
When set to µ-law/A-law: Supports up to 32 slots (BCLK: 2.048 MHz)
When set to 16-bit linear: Supports up to 16 slots (BCLK: 2.048 MHz)
1/42
FEDL7204-001DIGEST-01
OKI Semiconductor
• Master clock frequency:
12.288 MHz (crystal; external input)
• Supports hardware and software power down
• Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
100-pin plastic TQFP (TQFP100-P-1414-0.50-BK)
ML7204-001
(ML7204-001GA)
(ML7204V-001TB)
2/42
VGB
VREGOUT
AVDD
AGND
DGND0
DGND1
DGND2
POWER
OSC
12.288MHz
PLL
CKGN
SYNC(8kHz)
MCK
TXDETA
RXDET
TXDETB
TONE_DET1
TONE_DET0
DTMF_REC
FSK_DET
TONE1_DET
TONE0_DET
FSK_GEN
FGEN_FLAG
TONE_GEN0
(TONEA/ B)
TGEN0_EXFL
TONE_GEN1
(TONEC/ D)
RXGENB_EN
RXGENA_EN
RXGEN
RXGENB
RXGENA
TXGEN
RX_SIG
RXDET
SC_RXEN
G.711
GPIO0
GPIO2
TIMOVF
DC_EN
DP DET
DTMF_DET
DTMF CODE[3:0]
TONE0 DET
TONE1_DET
DP DET
FDET_RQ
FDET_FER/FDET_OER
FGEN FLAG
TIMOVF
DPDET
G.711
Decoder
G.729.A
DPGEN
DC EN
Speech Codec
RX2TX1
_GAIN
TIMER
Note: The I/O pins represented by “ ” can be used for 100-pin packages only.
DTMF_CODE[3:0]
FDET_D[7:0]
DTMF_DET
FDET_RQ
FDET_FER/FDET_OER
TGEN1_EXFL
Various detector paths
RXGEN
RXGAIN_SC
RXGAIN
_CH1
RX1TX2
_GAIN
MGEN_E
XFLAG
MGEN_FRFLA
TXGAIN
_CH2
T S W
DVDD0
DVDD1
+
DVDD2
Rin
G.729.A
TXGAIN Encoder
_CH1
RXGAIN
_CH2
Various generator paths
RXGENA
CODECA_RXEN
ATTr
GPAD Sout
Echo Canceller
Center
Clip
PCM_RXEN1
RXGAIN_ITS2
CH2
VREF
LPF
AF
ATTs
SC_TXEN
TXGAIN_S
TXGEN
PCM RXEN0
RXGAIN_PCM1
G.711
Decoder
RXGAIN_ITS1
PCM Codec
CH1
AVREF
D/A0
LPAD
-
AMP2
Rout
Sin
PCM_TXEN0
RXGAIN_PCM0
TXGAIN
_PCM0
G.711
Encoder
CH2
RXGAIN
STGAINA
TXGAINA CODECA_TXEN
TXDETA
RXGENB
LPEN1
LPEN0
T S W
VFRO0
Linear PCM
Codec
(CODEC_A)
BPF
LPF
CODECB_RXEN
CODECB_TXEN
CH1
10kΩ
AMP0
A/D0
D/A1
RXGAINB
STGAINB
TXGAINB
TXGAIN_PCM1 PCM_TXEN1
RX_SIG
PCM I/F
INT
Control
Register
Frame/DMA
Controller
RX
Buffer1
RX
Buffer0
Bus Control
Unit
TX
Buffer1
TX
Buffer0
TS CONT
AIN0P
10kΩ
BPF
Linear PCM
Codec
(CODEC_B)
A/D1
TXDETB
S/P
AIN0N
GSX0
AMP3
10kΩ
AMP1
10kΩ
P/S
VFRO1
AIN1N
GSX1
8b
16b
PCMO
INTB/
GPIOA[6]
A0-A7
D0-D15
CSB
RDB
WRB
FR0B
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
PCMI
CLKSEL
BCLK
SYNC
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
BLOCK DIAGRAM
4
[3:0]
GPIO
6
[5:0]
GPIO
8
[7:0]
GPIOC
TST1
PDNB
TST0
CLKOUT
XO
XI
3/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
33 DVDD1
34 A0
35 A1
36 A2
37 A3
38 A4
39 A5
40 A6
41 A7
42 PDNB
43 CLKSEL
44 DGND1
45 GPIOA[0]/DPI
46 GPIOA[1]
47 GPIOA[2]/DPO
48 GPIOA[3]
PIN CONFIGURATION (TOP VIEW)
AVDD 49
32 D15
AIN0P 50
31 D14
AIN0N 51
30 D13
GSX0
52
29 D12
GSX1 53
28 D11
AIN1N 54
27 D10
DGND0 16
WRB 15
RDB 14
CSB 13
INTB/GPIOA[6]
12
17 D0
FR1B 11
VBG 64
FR0B 10
18 D1
9
VREGOUT 63
ACK1B/GPIOA[5]
19 D2
8
DVDD2 62
ACK0B/GPIOA[4]
20 D3
7
XO 61
DVDD0
21 D4
6
60
SYNC
XI
5
22 D5
BCLK
DGND2 59
4
23 D6
PCMI
24 D7
58
3
57
AGND
PCMO
VFRO1
2
25 D8
TST0
VFRO0
1
26 D9
56
TST1
AVREF 55
64-Pin Plastic QFP
4/42
: Provided for 100-pin packages only
14
GPIOC[5]
20
FR1B
22
23
24
25
CSB
RDB
WRB
DGND0
INTB/GPIOA[6] 21
19
FR0B
GPIOC[7] 18
GPIOC[6] 17
ACK1B/GPIOA[5] 16
ACK0B/GPIOA[4] 15
13
GPIOC[3]
12
11
DVDD0
10
GPIOC[2]
GPIOC[4]
9
PCMO
8
6
GPIOC[1]
BCLK
5
GPIOC[0]
SYNC
4
7
3
TST0
PCMI
2
NC
1
NC
TST1
AVDD
CLKOUT
GPIOA[2]/DPO
51 NC
52 DVDD1
OKI Semiconductor
53 A0
54 A1
55 A2
56 A3
57 A4
58 A5
59 A6
60 A7
61 PDNB
62 GPIOB[0]
63 GPIOB[1]
64 CLKSEL
65 GPIOB[2]
66 GPIOB[3]
67 DGND1
68 GPIOB[4]
69 GPIOB[5]
70 GPIOA[0]/DPI
71 GPIOA[1]
72 NC
73 NC
74
75 GPIOA[3]
FEDL7204-001DIGEST-01
ML7204-001
76
50 NC
77
49 D15
AIN0P 78
48 D14
AIN0N 79
47 NC
GSX0 80
46 D13
81
GSX1 82
45 D12
AIN1N
83
44 NC
43 D11
AVREF 85
NC
84
42 D10
41 NC
VFRO0 86
40 D9
VFRO1 87
94
32 NC
DVDD2 95
31 D3
96
30 D2
NC
97
29 NC
VREGOUT
98
28 D1
VBG 99
27 D0
AGND
88
39 D8
38 NC
NC
89
37 D7
NC
90
36 D6
DGND2 91
35 NC
XI 92
34 D5
NC
93
33 D4
XO
NC 100
26 NC
100-Pin Plastic TQFP
5/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PIN DESCRIPTIONS
Pin
TQFP100 QFP64
Symbol
I/O
O
I
I
I/O
I/O
O
I
1
2
3
4
5
6
7
—
1
2
—
—
3
4
CLKOUT
TST1
TST0
GPIOC[0]
GPIOC[1]
PCMO
PCMI
8
5
BCLK
When
PDNB
= “0”
“L”
“0”
“0”
I
I
“Hi-z”
I
I
I/O
“L”
I
9
6
SYNC
I/O
“L”
10
11
12
13
14
—
—
7
—
—
GPIOC[2]
GPIOC[3]
DVDD0
GPIOC[4]
GPIOC[5]
I/O
I/O
—
I/O
I/O
I
I
—
I
I
15
8
ACK0B/GPIOA[
4]
I/O
I
16
9
ACK1B/GPIOA[
5]
I/O
I
17
18
—
—
GPIOC[6]
GPIOC[7]
I/O
I/O
I
I
19
10
FR0B
(DMARQ0B)
O
”H”
20
11
FR1B
(DMARQ1B)
O
“H”
21
12
INTB/GPIOA[6]
I/O
“H”
22
23
24
25
13
14
15
16
CSB
RDB
WRB
DGND0
I
I
I
—
I
I
I
—
Description
12.288 MHz clock output
Test control input 1: Normally, input “0”.
Test control input 0: Normally, input “0”.
General-purpose I/O port C [0]
General-purpose I/O port C [1]
PCM data output [Open drain output pin]
PCM data input
CLKSEL = ”0”
PCM shift clock input
CLKSEL = ”1”
PCM shift clock output
CLKSEL = ”0”
PCM synchronous signal 8 kHz input
CLKSEL = ”1”
PCM synchronous signal 8 kHz output
General-purpose I/O port C[2]
General-purpose I/O port C[3]
Digital power supply
General-purpose I/O port C[4]
General-purpose I/O port C[5]
Transmit buffer DMA access acknowledge signal input
(primary function)
General-purpose I/O port A[4] (secondary function) [5
V tolerant pin]
Receive buffer DMA access acknowledge signal input
(primary function)
General-purpose I/O port A [5] (secondary function) [5 V
tolerant pin]
General-purpose I/O port C [6]
General-purpose I/O port C [7]
FR0B:(FD_SEL = ”0”)
Transmit buffer frame signal output
DMARQ0B: (FD_SEL = ”1”)
Transmit buffer DMA access request signal
FR1B: (FD_SEL = ”0”)
Receive buffer frame signal output
DMARQ1B: (FD_SEL = ”1”)
Receive buffer DMA access request signal output
Interrupt request output (primary function)
General-purpose I/O port A [6] (secondary function) [5 V
tolerant pin]
Chip select control input
Read control input
Write control input
Digital ground (0.0 V)
6/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
26
27
28
29
30
31
32
33
34
35
36
37
38
—
17
18
—
19
20
—
21
22
—
23
24
—
NC
D0
D1
NC
D2
D3
NC
D4
D5
NC
D6
D7
NC
—
I/O
I/O
—
I/O
I/O
—
I/O
I/O
—
I/O
I/O
—
When
PDNB
= “0”
—
I
I
—
I
I
—
I
I
—
I
I
—
39
25
D8
I/O
I
40
26
D9
I/O
I
41
—
NC
—
—
42
27
D10
I/O
I
43
28
D11
I/O
I
44
—
NC
—
—
45
29
D12
I/O
I
46
30
D13
I/O
I
47
—
NC
—
—
48
31
D14
I/O
I
49
32
D15
I/O
I
50
51
52
53
54
55
56
57
58
59
60
—
—
33
34
35
36
37
38
39
40
41
NC
NC
DVDD1
A0
A1
A2
A3
A4
A5
A6
A7
—
—
—
I
I
I
I
I
I
I
I
—
—
—
I
I
I
I
I
I
I
I
Pin
TQFP100 QFP64
Symbol
I/O
Description
(Unused)
Data input-output
Data input-output
(Unused)
Data input-output
Data input-output
(Unused)
Data input-output
Data input-output
(Unused)
Data input-output
Data input-output
(Unused)
Data input-output. Fix the input to “L” or “H” when using
the pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
(Unused)
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
(Unused)
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
(Unused)
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
(Unused)
(Unused)
Digital power supply
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
7/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Symbol
I/O
When
PDNB
= “0”
Pin
TQFP100
QFP64
61
42
PDNB
I
“0”
62
63
—
—
GPIOB[0]
GPIOB[1]
I/O
I/O
I
I
64
43
CLKSEL
I
I
65
66
67
68
69
—
—
44
—
—
GPIOB[2]
GPIOB[3]
DGND1
GPIOB[4]
GPIOB[5]
I/O
I/O
—
I/O
I/O
I
I
—
I
I
70
45
GPIOA[0]/DPI
I/O
I
71
72
73
46
—
—
I/O
—
—
I
—
—
74
47
I/O
I
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
48
49
—
50
51
52
—
53
54
—
55
56
57
58
—
—
59
60
—
61
GPIOA[1]
NC
NC
GPIOA[2]/DP
O
GPIOA[3]
AVDD
NC
AIN0P
AIN0N
GSX0
NC
GSX1
AIN1N
NC
AVREF
VFRO0
VFRO1
AGND
NC
NC
DGND2
XI
NC
XO
I/O
—
—
I
I
O
—
O
I
—
O
O
O
—
—
—
—
I
—
O
I
—
—
I
I
“Hi-z”
—
“Hi-z”
I
—
“L”
“Hi-z”
“Hi-z”
—
—
—
—
I
—
“H”
Description
Power-down input
“0”: Power-down reset
”1”: Normal operation
General-purpose I/O port B[0]
General-purpose I/O port B[1]
SYNC/BCLK input-output control input
“0”: SYNC/BCLK are configured to be input
“1”: SYNC/BCLK are configured to be output
General-purpose I/O port B[2]
General-purpose I/O port B[3]
Digital ground (0.0 V)
General-purpose I/O port B[4]
General-purpose I/O port B[5]
General-purpose I/O port A[0] [5 V tolerant pin]
Secondary function: Input pin for dial pulse detection
General-purpose I/O port A[1] [5 V tolerant pin]
(Unused)
(Unused)
General-purpose I/O port A[2] [5 V tolerant pin]
Secondary function: Output pin for dial pulse transmission
General-purpose I/O port A[3] [5 V tolerant pin]
Analog power supply
(Unused)
AMP0 non-inverting input
AMP0 inverted input
AMP0 output (10 kΩ driving)
(Unused)
AMP1 output (10 kΩ driving)
AMP1 inverted input
(Unused)
Analog signal ground (1.4 V)
AMP2 output (10 kΩ driving)
AMP3 output (10 kΩ driving)
Analog ground (0.0 V)
(Unused)
(Unused)
Digital ground (0.0 V)
12.288 MHz crystal interface, 12.288 MHz clock input
(Unused)
12.288 MHz crystal interface
8/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Pin
TQFP100 QFP64
95
96
97
98
99
100
62
—
—
63
64
—
Symbol
I/O
DVDD2
NC
NC
VREGOUT
VBG
NC
—
—
—
—
—
—
When
PDNB
= “0”
—
—
—
—
—
—
Description
Digital power supply
(Unused)
(Unused)
Internal regulator voltage output pin (approx. 2.5 V)
Internal regulator reference voltage output pin
(Unused)
9/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
ABSOLUTE MAXIMUM RATINGS
Parameter
Analog power supply
voltage
Digital power supply
voltage
Analog input voltage
Symbol
Condition
Rating
Unit
AVDD
—
–0.3 to +4.6
V
DVDD
—
–0.3 to +4.6
V
VAIN
VDIN1
Analog pin
Normal digital pin
DVDD = 3.0 to 3.6 V
5 V tolerant pin
DVDD < 3.0 V
—
Ta = 60 °C, per package
—
–0.3 to AVDD+0.3
–0.3 to DVDD+0.3
–0.3 to +6.0
–0.3 to DVDD+0.3
–20 to +20
350
–65 to +150
V
V
V
V
mA
mW
°C
Digital input voltage
VDIN2
Output current
Power dissipation
Storage temperature
IO
PD
Tstg
RECOMMENDED OPERATING CONDITIONS
Parameter
Analog power supply voltage
Digital power supply voltage
Operating temperature range
Digital high-level input voltage
Digital low-level input voltage
Digital input rise time
Digital input fall time
Digital output load capacitance
Digital output load resistance
AVREF bypass capacitor
VREGOUT bypass capacitor
VBG bypass capacitor
Master clock frequency
PCM shift clock frequency
PCM synchronous signal
frequency
Clock duty ratio
PCM synchronous timing
PCM synchronous signal width
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
AVDD
—
3.0
3.3
3.6
V
DVDD
—
3.0
3.3
3.6
V
Ta
—
–20
—
60
°C
DVDD+
0.75 ×
V
—
VIH1
Normal digital pin
0.3
DVDD
0.75 ×
—
5.5
V
VIH2
5 V tolerant pin
DVDD
0.19 ×
V
VIL
Digital pin
–0.3
—
DVDD
tIR
Digital pin
—
2
20
ns
tIF
Digital pin
—
2
20
ns
CDL
Digital pin
—
—
50
pF
RDL
Pull-up resistance, PCMO
500
—
—
Ω
Cvref
Between AVREF-AGND
2.2+0.1
—
4.7+0.1
µF
Cvout
Between VREGOUT-DGND
—
10+0.1
—
µF
CVBG
Between VBG-DGND
—
150
—
pF
Fmck
MCK
–0.01% 12.288 +0.01%
MHz
Fbclk
BCLK (at input)
64
—
2048
kHz
Fsync
SYNC (at input)
—
8.0
—
kHz
DRCLK
tBS
tSB
tWS
MCK, BCLK (at input)
BCLK to SYNC (at input)
SYNC to BCLK (at input)
SYNC (at input)
40
100
100
1BCLK
50
—
—
—
60
—
—
100
%
ns
ns
µs
(Note) On power-on/shut-down sequence
For the analog power supply voltage (AVDD) and the digital power supply voltage (DVDD) to be supplied to
this LSI, it is recommended that power be applied to them simultaneously. However, if simultaneous power-up
is difficult due to the power supply circuit configuration, power them up in the order of DVDD → AVDD.
The power supplies should be shut down in the reverse order of power-on sequence.
10/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Power supply current
Digital input pin
Input leakage current
Digital I/O pin
Output leakage
current
High-level output
voltage
Low-level output
voltage
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max. Unit
Standby state
—
200
500
µA
ISS
(PDNB = ”0”, DVDD = AVDD=3.3 V, Ta = 25°C)
Operating status 1
Speech CODEC activated/PCM I/F not used
—
45
55
mA
IDD1
SC_EN = ”1”, AFEA_EN = ”0”, AFEB_EN = ”1”,
XI, XO: 12.288 MHz crystal connected
Operating status 2
Speech CODEC activated/PCM I/F used
SC_EN = ”1”,PCMI1_EN = ”1”, PCMO1_EN
—
50
65
mA
IDD2
= ”1”,
AFEA_EN=”0”, AFEB_EN=”0”
XI, XO: 12.288 MHz crystal connected
IIH
Vin = DVDD
—
0.01
10
µA
IIL
Vin = DGND
–10
–0.01
—
µA
IOZH
Vou = DVDD
—
0.01
10
µA
IOZL
VOH
VOL1
VOL2
Input capacitance (*1)
CIN1
CIN2
Vout = DGND
Digital input pins, I/O pin
IOH = 4.0 mA
IOH = 0.5 mA (XO pin)
IOH = 1 2.0 mA (CLKOUT pin)
Digital output pins, I/O pin
IOL = –4.0 mA
IOL = –0.5 mA (XO pin)
IO = –12.0 mA (CLKOUT pin)
Open drain output pins
IOL = –12.0 mA
Input pins
I/O pins
–10
—
—
µA
0.78 ×
DVDD
—
—
V
—
—
0.4
V
—
—
0.4
V
—
—
6
10
—
—
pF
pF
*1 Design guaranteed value
11/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Analog Interface
Parameter
Input resistance (*1)
Output load resistance
Output load capacitance
Offset voltage
Output voltage level (*2)
(AVDD = 3.0 to 3.6 V, DVDD0, 1 ,2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
RIN
AIN0N, AIN0P, AIN1N
10
—
—
MΩ
RL
GSX0, GSX1, VFRO0, VFRO1
10
—
—
kΩ
CL
Analog output pins
—
—
50
pF
VOF
VFRO0, VFRO1
–40
—
40
mV
GSX0, GSX1, VFRO0, VFRO1
1.158
1.3
1.458
Vpp
VO
RL = 10kΩ, AMP input 1.3 Vpp
*1 Design guaranteed value
*2 –7.7 dBm (600Ω) = 0 dBm0, +3.17 dBm0 = 1.3 Vpp
12/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
AC Characteristics in Speech CODEC = G.711 (µ-law) Mode
Parameter
Transmit frequency
characteristics
Receive frequency
characteristics
Transmit
signal-to-noise ratio
(*1)
Receive
signal-to-noise ratio
(*1)
Transmit inter-level
loss errors
Receive inter-level
loss errors
Idle channel noise
(*1)
Transmit absolute
level (*2)
Receive absolute level
(*2)
Symbol
LT1
LT2
LT3
LT4
LT5
LT6
LR2
LR3
LR4
LR5
LR6
SDT1
SDT2
SDT3
SDT4
SDT5
SDR1
SDR2
SDR3
SDR4
SDR5
GTT1
GTT2
GTT3
GTT4
GTT5
GTR1
GTR2
GTR3
GTR4
GTR5
NIDLT
NIDLR
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
Frequency (Hz)
Level (dBm0)
0 to 60
25
—
—
dB
300 to 3000
–0.15
—
0.20
dB
1020
Reference
—
0
3300
–0.15
—
0.80
dB
3400
0
—
0.80
dB
3968.75
13
—
—
dB
0 to 3000
–0.15
—
0.20
dB
1020
Reference
—
0
3300
–0.15
—
0.80
dB
3400
0
—
0.80
dB
3968.75
13
—
—
dB
3
35
—
—
dBp
0
35
—
—
dBp
1020
–30
35
—
—
dBp
–40
28
—
—
dBp
–45
23
—
—
dBp
3
35
—
—
dBp
0
35
—
—
dBp
1020
–30
35
—
—
dBp
–40
28
—
—
dBp
–45
23
—
—
dBp
3
–0.2
—
0.2
dB
–10
Reference
—
1020
–40
–0.2
—
0.2
dB
–50
–0.6
—
0.6
dB
–55
–1.2
—
1.2
dB
3
–0.2
—
0.2
dB
–10
Reference
—
1020
–40
–0.2
—
0.2
dB
–50
–0.6
—
0.6
dB
–55
–1.2
—
1.2
dB
Analog input =
—
—
–70
dBm0p
—
AVREF
—
PCMI = ”1”
—
—
–70
dBm0p
AVT
1020
0
0.285
0.320
0.359
Vrms
AVR
1020
0
0.285
0.320
0.359
Vrms
*1 P-message weighted filter used
*2 0.320 Vrms = 0 dBm0 = –7.7 dBm (600Ω)
13/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
AC Characteristics (Gain Setting) in Speech CODEC = G.711 (µ-law) mode
Parameter
Transmit/receive gain
setting accuracy
Symbol
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
GAC
For all gain set values
–1.0
—
1.0
dB
AC Characteristics (Tone Output) in Speech CODEC = G.711 (µ-law) Mode
Parameter
Frequency deviation
Output level
Symbol
fDFT
oLEV
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
For all frequency set values
–1.5
—
1.5
%
For all gain set values
–2.0
—
2.0
dB
AC characteristics (DTMF Detector and Other Detectors) in Speech CODEC = G.711 (µ-law) Mode
Parameter
Detection level accuracy
Symbol
dLAC
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
For all detection level set values
–2.5
—
2.5
dB
AC characteristics (Echo Canceler)
Parameter
Echo attenuation
Erasable echo delay time
Symbol
eRES
tECT
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
—
—
35
—
dB
—
—
—
32
ms
Measuring method
Echo Canceler
ATT
Sin
Sout
Level Meter
Rout
Rin
LPF
5kHz
E.R.L
(echo return loss)
Delay
Echo delay time
White noise generator
14/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Timings of PDNB, XO, and AVREF
Parameter
Power-down signal pulse
width
AVDD supply delay time
Oscillation activation time
AVREF rise time
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
tPDNB
PDNB pin
250
—
—
µs
tAVDDON
txtal
—
—
AVREF = 1.4 (90%)
C5 = 4.7 µF, C6 = 0.1 µF
(See Figure 9)
AVREF = 1.4 (90%)
C5 = 2.2 µF, C6 = 0.1 µF
(See Figure 9)
0
—
—
—
—
20
ns
ms
—
—
600
ms
—
—
300
ms
tAVREF
DVDD
AVDD
DVDDAVDD
90%
DVDD
AVDD
0V
tAVDDON
VREGOUT
Approx.
2.5V
0V
90%
DVDD
PDNB
0V
tPDNB
AVDD
XO
0V
txtal
Approx.
1.4 V
AVREF
0V
tAVREF
Figure 1 Timings of PDNB, XO, and AVREF
(Note)
The capacitance of the AVREF capacitor (C5) affects the AVREF rise time and analog characteristics. If
weight is given to the analog characteristics, specify 4.7 µF, and if it is given to the AVREF rise time, specify
2.2 µF. The electrical characteristics for the analog characteristics that are described above are guaranteed in
both capacitances.
15/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PCM interface
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
fBCLK
CDL = 20 pF (during output)
–0.1%
2.048 +0.1%
MHz
dBCLK
CDL = 20 pF (during output)
45
50
55
%
fSYNC
CDL = 20 pF (during output)
–0.1%
8
+0.1%
kHz
dSYNC
CDL = 20 pF (during output)
45
50
55
%
1
BCLK = 2.048 MHz At output
tBS
BCLK to SYNC (during output)
100
—
—
ns
tSB
SYNC to BCLK (during output)
100
—
—
ns
tDS
50
—
—
ns
PCMI pin
tDH
50
—
—
ns
tSDX
—
—
100
ns
PCMO pin
tXD1
—
—
100
ns
Pull-up resistance RDL = 500Ω
tXD2
—
—
100
ns
CDL = 50 pF
—
—
100
ns
tXD3
Parameter
Bit clock frequency
Bit clock duty ratio
Synchronous signal frequency
Synchronous signal duty ratio
Transmit/receive synchronous
timing
Input setup time
Input hold time
Digital output delay time
Digital output hold time
BCLK
0
1
tBS
2
3
4
5
6
7
8
-
16
tSB
tWS
SYNC
tDS
tDH
MSB
PCMI
LSB
LSB
G.711
16-bit linear
Figure 2 PCM Interface Input Timing (Long Frame)
BCLK
0
1
tBS
2
3
4
5
6
7
8
9
-
17
tSB
tWS
SYNC
tDS
PCMI
tDH
MSB
LSB
G.711
LSB
16-bit linear
Figure 3 PCM Interface Input Timing (Short Frame)
16/42
FEDL7204-001DIGEST-01
OKI Semiconductor
BCLK
0
ML7204-001
1
tBS
2
3
4
5
6
7
8
9
-
17
tSB
tWS
SYNC
tXD1
tXD2
tXD3
MSB
PCMO
tXD3
LSB
LSB
G.711
tSDX
16-bit linear
Figure 4 PCM Interface Output Timing (Long Frame)
BCLK
0
1
tBS
2
3
tXD1
tXD2
4
5
6
7
8
9
10
-
18
tSB
tWS
SYNC
PCMO
MSB
tXD3
tXD3
LSB
LSB
G.711
16-bit linear
Figure 5 PCM Interface Output Timing (Short Frame)
17/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Control Register Interface
Parameter
Address setup time (at Read)
Address hold time (at Read))
Address setup time (at Write)
Address hold time (at Write)
Write data setup time
Write data hold time
CSB setup time (at Read)
CSB hold time (at Read)
CSB setup time (at Write)
CSB hold time (at Write)
WRB pulse width
Read data output delay time
Read data output hold time
RDB pulse width
CSB disable time
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta= –20 to 60°C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
tRAS
10
—
—
ns
tRAH
0
—
—
ns
tWAS
10
—
—
ns
tWAH
10
—
—
ns
tWDS
20
—
—
ns
tWDH
10
—
—
ns
tRCS
10
—
—
ns
CL = 50 pF
tRCH
0
—
—
ns
tWCS
10
—
—
ns
tWCH
10
—
—
ns
tWW
10
—
—
ns
tRDD
—
—
20
ns
tRDH
3
—
—
ns
tRW
25
—
—
ns
tCD
10
—
—
ns
A7-A0
Input
D7-D0
Inputoutput
A2
A1
tWAS
tWAH
tRAS
tRAH
D2
Output
D1
Input
tWDS tWDH
tRDD
tRDH
CSB
Input
tWCS
tWCH
tCD
tRCS
tRCH
WRB
Input
tWW
tRW
RDB
Input
Write timing
Read timing
Figure 6 Control Register Interface
18/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Transmit/Receive Buffer Interface (Frame Mode)
Parameter
FR1B setup time
FR1B output delay time
Address setup time (at Read)
Address hold time (at Read))
Address setup time (at Write)
Address hold time (at Write)
Write data setup time
Write data hold time
CSB setup time (at Read)
CSB hold time (at Read)
CSB setup time (at Write)
CSB hold time (at Write)
WRB pulse width
FR0B setup time
FR0B output delay time
Read data output delay time
Read data output hold time
RDB pulse width
CSB disable time
Symbol
tF1S
tF1D
tRAS
tRAH
tWAS
tWAH
tWDS
tWDH
tRCS
tRCH
tWCS
tWCH
tWW
tF0S
tF0D
tRDD
tRDH
tRW
tCD
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
3
—
—
ns
—
—
20
ns
10
—
—
ns
0
—
—
ns
10
—
—
ns
10
—
—
ns
20
—
—
ns
10
—
—
ns
10
—
—
ns
CL = 50 pF
0
—
—
ns
10
—
—
ns
10
—
—
ns
10
—
—
ns
3
—
—
ns
—
—
20
ns
—
—
30
ns
3
—
—
ns
35
—
—
ns
10
—
—
ns
FR0B
Output
tF0S
tF0D
FR1B
Output
tF1S
tF1D
A7-A0
Input
D15-D0
Inputoutput
A2
A1
tWAS
tWAH
tRAS
tRAH
D1
Input
D2
Output
tWDS tWDH
tRDD
tRDH
CSB
Input
WRB
Input
tWCS
tWCH
tWW
tCD
tRCS
tRCH
tRW
RDB
Input
Write timing
Read timing
Figure 7 Transmit/Receive Buffer Interface (Frame Mode)
19/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Transmit/Receive Buffer Interface (DMA Mode)
Parameter
DMARQ1B setup time
DMARQ1B output delay time
Address setup time (at Read)
Address hold time (at Read))
Address setup time (at Write)
Address hold time (at Write)
Write data setup time
Write data hold time
ACK0B setup time
ACK0B hold time
ACK1B setup time
ACK1B hold time
WRB pulse width
DMARQ0B setup time
DMARQ0B output delay time
Read data output delay time
Read data output hold time
RDB pulse width
ACKB disable time
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
tDR1S
3
—
—
ns
tDR1RD
—
—
30
ns
tDR1FD
—
—
30
ns
tRAS
10
—
—
ns
tRAH
0
—
—
ns
tWAS
10
—
—
ns
tWAH
10
—
—
ns
tWDS
20
—
—
ns
tWDH
10
—
—
ns
tAK0S
10
—
—
ns
CL = 50 pF
tAK0H
0
—
—
ns
tAK1S
10
—
—
ns
tAK1H
10
—
—
ns
tWW
10
—
—
ns
tDR0S
3
—
—
ns
tDR0RD
—
—
30
ns
tDR0FD
—
—
30
ns
tRDD
—
—
30
ns
tRDH
3
—
—
ns
tRW
35
—
—
ns
tAD
10
—
—
ns
DMARQ0B
Output
tDR0S
tDR0RD
tDR0FD
DMARQ1B
Output
tDR1S
tDR1FD
tDR1RD
A7-A0
Input
D15-D0
Inputoutput
A2
A1
tWAS
tWAH
tRAS
tRAH
D2
Output
D1
Input
tWDS tWDH
tRDD
tRDH
ACK0B
Input
tAK0S
tAK0H
ACK1B
Input
WRB
Input
tAK1S
tAK1H
tWW
tAD
tRW
RDB
Input
Write timing
Read timing
Figure 8 Transmit/Receive Buffer Interface (DMA Mode)
20/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PIN FUNCTIONAL DESCRIPTION
AIN0N, AIN0P, GSX0, AIN1N, and GSX1
These are transmit analog input and transmit gain adjustment pins. AIN0N and AIN1N are connected to
inverted input pins of internal transmission amplifiers AMP0 and AMP1, and AIN0P is connected to a
noninverting input pin of AMP0. GSX0 and GSX1 are connected to output pins of AMP0 and AMP1. See
Figure 9 for the gain adjustment.
At power down (PDNB = “0” or SPDN = “1”), outputs of GSX0 and GSX1 are in a high impedance state.
When the application does not use AMP0, short-circuit GSX0 and AIN0N and connect AIN0P with AVREF.
When not using AMP1, short-circuit GSX1 and AIN1N.
VFRO0 and VFRO1
These are receive analog output pins. VFRO0 and VFRO1 are connected to output pins of amplifiers AMP2
and AMP3. Output of output signals, VFRO0 and VFRO1, can be selected using the VFRO0 selection register
(VFRO0_SEL) and VFRO1 selection register (VFRO1_SEL): When output is selected (“1”), the receive signal
is output and when output is not selected (“0”), AVREF (about 1.4 V) is output. In power down mode, these
output pins are set to a high impedance state. It is recommended to use output signals through a DC coupling
capacitor.
(Note)
If output selection is changed while the conversation is in progress, a micronoise is generated. Therefore, it is
recommended to select output before starting a call and then start a call.
Before canceling reset or resetting, it is recommended to select output of VFRO0 and VFRO1 to the AVREF
output side.
GSX1
Gain = R4/R3 <=32(+30dB)
R3 : Variable
R4 : 500k Max.
R4
C2
R3
10kΩ
AIN1N
A/D1
AMP1
C4
Out : 1.3Vp-p Max.
VFRO1
VFRO1_SEL
10kΩ
D/A1
AMP3
GSX0
R2
Gain = R2/R1 <=
32(+30dB)
R1 : Variable
R2 : 500k Max.
C1
R1
10kΩ
AIN0N
A/D0
AIN0P
Out : 1.3Vp-p Max.
C3 VFRO0
AMP0
VFRO0_SEL
10kΩ
D/A0
AMP2
AVREF
C5 +
2.2 to 4.7µF
VREF
C6 0.1µF
Figure 9 Analog Interface
21/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
AVREF
This is an output pin of an analog signal ground potential. With the output potential of about 1.4 V, insert
bypass capacitors of 2.2 to 4.7 µF (aluminum electrolysis type) and 0.1 µF (ceramic type) in parallel. AVREF
outputs 0.0 V at power down. AVREF starts being powered up after power-down reset, the system restarts
from ( PDNB = “1” and SPDN = “0”).
XI and XO
These are the master clock input pin (XI) and the crystal connection pins for the master clock (XI and XO).
Oscillation stops at power down by PDNB or software power down by SPDN. Oscillation starts after
power-down is reset and the clock is supplied to the LSI internal section after oscillation stabilization delay time
has elapsed (about 21.3 ms). Figure 10 shows a master clock input example.
CR0-B7
(SPDN)
To the internal
section
PDNB
XI
XO
R
Crystal
CLKOUT
CR0-B7
(SPDN)
To the internal
section
PDNB
XI
XO
Open
CLKOUT
12.288 MHz
Provisional
C1
C2
Crystal (12.288 MHz)
C1
C2
R
Kyocera Kinseki Corp.
HC-49/U-S [CL=12pF]
8 pF
8 pF
1 MΩ
Figure 10 Example of an Oscillation Circuit and Clock Input
CLKOUT
This is a 12.288 MHz master clock output pin. (Provided for 100-pin packages only)
Since output is disabled in the initial state, set the 12.288 MHz clock output enable control register
(CLKOUT_EN) to “1” when clock output is required.
PDNB
This is a power-down control input pin. A power-down state can be set by setting this pin to “0”. This pin
also functions as an LSI reset pin. To prevent an LSI operation error, use PDNB for the initial power-down
reset after power is applied. To put the LSI into a power-down state, fix PDNB to “0” for 250 µs or more.
LSI power-down reset can be performed by setting the software power down reset control register SPDN to “0”
→ “1” → “0”.
Power-down is released, the initial mode display register (READY) is set to “1” after 200 ms, and various
function setting modes (initial modes) are entered.
See Figure 1 for the timings of PDNB, AVREF, XO, and the initial mode.
(Note)
Turn on the power in a power-down state by PDNB.
When using the LSI by inputting a master clock to the XI pin, first maintain the power-down state (PDNB = 0)
until power is applied to the digital power supply (DVD0, 1, and 2) and the analog power supply (AVDD) (90%
or more) and the master clock is input to the XI pin, then release the power-down state (PDNB = 0 → 1) . In
this case also, fix PDNB to “0” for 250 µs or more.
22/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
DVDD0, DVDD1, DVDD2, and AVDD
These are power supply pins. DVDD0, DVDD1, and DVDD2 are connected to the power supply of a digital
circuit and AVDD is connected to a power supply of an analog circuit. Connect these pins near the LSI and
insert bypass capacitors of 10 µF (electrolysis type) and 0.1 µF (ceramic type) between DGND and AGND in
parallel.
DGND0, DGND1, DGND2, and AGND
These are ground pins. DGND0, DGND1, and DGND2 are connected to grounds of digital circuits and AGND
is connected to a ground of an analog circuit. Connect these pins near the LSI.
VREGOUT
This is an output pin of an internal regulator voltage (about 2.5 V).
Connect a capacitor of about 0.1 µF (ceramic type) in parallel to about 10 µF (ceramic or tantalum type) between
this pin and a ground pin.
VBG
This is a reference output pin for an internal regulator.
Connect a laminated ceramic capacitor of about 150 pF between this pin and a ground pin.
TST0 and TST1
These are input pins for testing. At normal use, input “0”.
23/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
INTB/GPIOA[6]
Primary function: INTB
This in an interrupt request output pin.
When the interrupt cause is changed, this pin outputs a “L” level for about 1.0 µs. When the interrupt factor is
not changed, “H” is output. The interrupt factor can be checked by reading CR16-CR22. Table 1 lists the
interrupt causes.
The interrupt causes can be masked individually in the internal memory (interrupt cause mask control).
Table 1 Interrupt Causes
CR
BIT
B2
CR16
B1
B0
CR17
B0
CR18
B0
B7
B4
CR19
B3
B2
B1
B6
CR20
B4
B3-B0
B3
B2
CR21
B1
B0
B3
B2
CR22
B1
B0
Register name
FSK receive overrun error notification register
(FDET_OER)
FSK receive framing error notification register
(FDET_FER)
FSK receive data read request notification register
(FDET_RQ)
FSK output data setting completion flag
(FGEN_FLAG)
Timer overflow display register (TMOVF)
DSP status register (DSP_ERR)
TONE1 detector detection status register
(TONE1_DET)
TONE0 detector detection status register
(TONE0_DET)
TGEN1 execution flag display register
(TGEN1_EXFLAG)
TGEN0 execution flag display register
(TGEN0_EXFLAG)
Dial pulse detector detection status register
(DP_DET)
DTMF detector detection status register
(DTMF_DET)
DTMF code display register (DTMF_CODE[3:0])
CH2 transmit error status register (TXERR_CH2)
CH1 transmit error status register (TXERR_CH1)
CH2 transmit request notification register
(FR0_CH2)
CH1 transmit request notification register
(FR0_CH1)
CH2 receive error status register (RXERR_CH2)
CH1 receive error status register (RXERR_CH1)
Receive invalid write error notification register
(RXBW_ERR)
Receive request notification register (FR1)
{: With INTB interrupt generation function
Rising
edge
Falling
edge
{
×
{
×
{
×
×
{
{
{
×
×
{
{
{
{
{
{
{
{
{
{
{
{
{
{
{
{
{
{
{
×
{
×
{
{
{
{
{
{
{
×
Remarks
×: Without INTB interrupt generation function
Secondary function: GPIOA[6]
When the primary function/secondary function selection register (GPFA[6]) of GPIOA[6] is set to “1”, this pin
functions as a general-purpose I/O port GPIOA[6].
24/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
A0-A7
These are address input pins for accessing a frame/DMA/control register. Each address is as follows.
Transmit buffer (TX Buffer)
A7-A0 = 80h
Receive buffer (RX Buffer)
A7-A0 = 81h
Control register (CR)
See Tables 5 to 8 for the addresses.
D0-D15
These are data I/O pins for accessing a frame/DMA/control register. Since these pins are I/O pins, connect
pull-up resistors. When an 8-bit bus access is selected in the MCU interface data width selection register
(BW_SEL), pins D0-D7 are enabled. When using the pins with 8-bit bus access (BW_SEL = “1”), fix the input
of high-order D8-D15 to either “0” or “1” since they are constantly in an input state.
CSB
This is a chip select input pin for accessing a frame/control register.
RDB
This is a read enable input pin for accessing a frame/DMA/control register.
WRB
This is a write enable input pin for accessing a frame/DMA/control register.
25/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
FR0B (DMARQ0B)
• FR0B (FRAME/DMA selection register FD_SEL = “0” in frame mode)
This is a transmit frame output pin that outputs data when the transmit buffer for frame access becomes full.
When the transmit buffer becomes full, the pin outputs “L” and retains “L” until the specified number of words
are read from the MCU.
• DMARQ0B (FRAME/DMA selection register FD_SEL = “1” in DMA mode)
This is a DMA request output pin that outputs data when the transmit buffer for DMA access becomes full.
When the transmit buffer becomes full, the pin outputs “L” and the value is reset to “H” automatically when an
acknowledgment signal (ACK0B = “0”) and the fall of a read enable signal (RDB = “1” → “0”) are received
from the MCU side. This operation is repeated until the specified number of words are read from the MCU.
FR1B (DMARQ1B)
• FR1B (FRAME/DMA selection register FD_SEL = “0” in frame mode)
This receive frame output pin outputs data when the receive buffer for frame access becomes empty. When
the receive buffer becomes empty, the pin outputs “L” and retains “L” until the specified number of words are
written from the MCU.
• DMARQ1B (FRAME/DMA selection register FD_SEL = “1” in DMA mode)
This a DMA request output pin that outputs data when the receive buffer for DMA access becomes empty.
When the receive buffer becomes empty, the pin outputs “L” and the value is reset to “H” automatically when
an acknowledgment signal (ACK1B = “0”) and the fall of a write enable signal (WRB = “1” → “0”) are
received from the MCU side. This opeation is repeated until the specified number of words are written from
the MCU side.
ACK0B/GPIOA[4]
Primary function: ACK0B
This is a DMA acknowledgment input pin for DMARQ0B for transmit buffer DMA access; it is enabled in
DMA mode (FD_SEL = “1”).
When using the pin in frame mode (FD_SEL = “0”), fix this pin to “1”.
Secondary function: GPIOA[4]
When the primary function/secondary function registration register (GPFA[4]) of GPIOA[4] is set to “1”, the pin
functions as a general-purpose I/O port GPIOA[4].
ACK1B/GPIOA[5]
Primary function: ACK0B
This is a DMA acknowledgment input pin for DMARQ1B for receive buffer DMA access; it is enabled in DMA
mode (FD_SEL = “1”).
When using this pin in frame mode (FD_SEL = “0”), fix this pin to “1”.
Secondary function: GPIOA[5]
When the primary function/secondary function registration register (GPFA[5]) of GPIOA[5] is set to “1”, the pin
functions as a general-purpose I/O port GPIOA[5].
GPIOA[0], GPIOA[1], GPIOA[2], and GPIOA[3]
These are general-purpose I/O ports A[3:0].
However, the following secondary functions are assigned to GPIOA[0] and GPIOA[2].
Secondary function of GPIOA[0]: Input pin (DPI) of a dial pulse detecter (DPDET)
Secondary function of GPIOA[2]: Output pin (DPO) of a dial pulse transmitter (DPGEN)
26/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
GPIOB[5:0]
This is a general-purpose I/O port B[5:0]. (Provided for 100-pin packages only.)
GPIOC[7:0]
This is a general-purpose I/O port C[7:0]. (Provided for 100-pin packages only.)
CLKSEL
This is an input-output control input pin of SYNC and BCLK. The pin controls input when it is set to “0” and
output when it is set to “1”.
SYNC
This is a 8 kHz synchronous signal I/O pin of PCM signals. When CLKSEL is “0”, constantly input an 8 kHz
clock synchronized with BCLK. When CLKSEL is “1”, this pin outputs an 8 kHz clock synchronized with
BCLK. When the SYNC frame control register (SYNC_SEL) is “0”, long frame synchronization is specified
and when the register is “1”, short frame synchronization is specified.
BCLK
This is a shift clock I/O pin of a PCM signal.
When CLKSEL is “0”, clock input synchronized with SYNC is necessary. When G.711 is selected, input a
clock of 64 kHz to 2.048 MHz and when 16-bit linear is selected, input a clock of 128 kHz to 2.048 MHz.
When CLKSEL is “1”, this pin outputs a clock of 2.048 MHz synchronized with SYNC.
(Remarks) Table 2 shows the input-output control of SYNC and BCLK and the frequencies.
Table 2 SYNC and BCLK Input-Output Control
CLKSEL
SYNC
BCLK
“0”
Input
(8 kHz)
Input
(64 kHz to
2048 kHz)
“1”
Output
(8 kHz)
Output
(2.048 MHz)
Remarks
Always input a clock after start of power supply.
When G.711 is selected, input a clock of 64 kHz to 2.048
MHz.
When 16-bit linear is selected, input a clock of 128 kHz to
2.048 MHz.
At power down, “L” is output.
PCMO
This is a PCM signal output pin. A PCM signal is output synchronized with the rise of BCLK or SYNC.
For the output from PCMO, data is output to only the applicable time slot section according to the selected
coding format and the setting of the time slot position and other sections are set to a high-impedance state. If a
PCM interface is not used, PCMO is set to a high impedance state.
(Note)
Be sure to connect a pull-up resistor externally to the PCMO pin, because the pin is an open drain output pin.
Do not use a pull-up voltage greater than the digital power supply voltage (DVDD).
PCMI
This is a PCM signal input pin. The signal is shifted at falling of BCLK and is input from MSB.
If a PCM interface is not used, fix the input to “0” or “1”.
27/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
FUNCTIONAL DESCRIPTION
Transmit and receive buffers
CONFIGURATION EXAMPLES
Configuration Example 1 (Basic Call, CODEC_A)
TXGAIN_PCM1
GSX1
TXDETB
10kΩ
AIN1N
A/D1
PCM_TXEN1
RX_SIG
BPF
PCM I/F
Encoder
G.711
LPEN0
TXGAINB
AMP1
CODECB_TXEN
TXGAIN_PCM0
P/S
PCM_TXEN0
PCMO
SYNC
Linear PCM
Codec (CODEC_B)
BCLK
TS
CONT
PCM Codec
STGAINB
CLKSEL
RXGAIN_ITS1
Decoder
10kΩ
CODECB_RXEN
RXGAINB
D/A1
VFRO1
G.711
LPEN1
LPF
AMP3
RXGENB
RXGAIN PCM0
RXGAIN_PCM1
PCM_RXEN0
GSX0
G.729.A
TXGAIN_SC
A/D0
BPF
TXGAINA CODECA_TXEN
AMP0
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10kΩ
AIN0N
PCMI
S/P
RXGAIN_ITS2
Sin
LPAD
+
-
ATTs
Center
Clip
TXGAIN Encoder
_CH1
SC_TXEN
GPAD Sout
G.711
ACK1B/
GPIOA[5]
TX
Buffer0
CH1 T
S
W
ACK0B/
GPIOA[4]
TX
Buffer1
CH2
FR1B
FR0B
DC_EN
RX2TX1
_GAIN
Speech Codec
_CH2
Linear PCM
Codec (CODEC_A)
Echo Canceller
AFF
STGAINA
RX1T
_GAIN
RXGAINA
D/A0
CSB
RXGAIN_SC
Rin
ATTr
Rout
RXGAIN
_CH1
LPF
CODECA_RXEN
AMP2
SC_RXEN
RXGENA
RXGEN
RXDET
Decoder
RXGAIN
_CH2
G.711
DVDD2
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
FSK_DET
TXDETB
DVDD1
DTMF_REC
DVDD0
DTMF_CODE[3:0]
DGND2
DGND1
PLL
MCK
CKGN
SYNC (8 kHz)
AGND
CH2
TONE0_DET
TONE_DET1
TONE1_DET
TONE_GEN0
(TONE A/ B)
FGEN_FLAG
TXGEN
DPGEN
RXGENA
DPDET
RXGENA_EN
TGEN0_EXFLAG
Control
Register
GPIO0
DP_DET
RXGEN
FSK_GEN
INT
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
FGEN_FLAG
TIMOVF
Unused
TST1
TST0
PDNB
CLKOUT
VGB
XI
Frame/DMA
Controller
GPIO2
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
RXGENB
RXGENB_EN
OSC
12.288 MHz
XO
TIMOVF
8
6
4
GPIOA
[3:0]
VREGOUT
RXDET
TONE_DET0
TGEN1_EXFLAG
TONE_GEN1
(TONE C/ D)
RX
Buffer1
GPIOC
[7:0]
POWER
TIMER
Generator path
Detector path setting
A0-A7
8b
DC_EN
RX_SIG
AVDD
T
CH1 S
W
VREF
TXDETA
16b
RX
Buffer0
G.729.A
GPIOB
[5:0]
VFRO0
DGND0
RDB
D0-D15
10kΩ
AVREF
WRB
Bus Control
Unit
This example shows the configuration for making calls with an analog telephone set (A-TEL) on the NW side by
connecting the analog telephone interface on the Linear PCM CODEC_A side.
RX_SIG
Linear
PCM
Codec
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
(CODEC_B)
A-TEL
Linear
PCM
Codec
EC
(CODEC_A)
VoIP-NW
RX_SIG
ML7204 (Configuration example 1)
28/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 2 (Basic Call, CODEC_B)
GSX1
TXGAIN PCM1
RX_SIG
TXDETB
10kΩ
AIN1N
A/D1
BPF
PCM_TXEN1
TXGAINB
AMP1
PCM I/F
Encoder
G.711
LPEN0
CODECB_TXEN
P/S
TXGAIN_PCM0 PCM_TXEN0
PCMO
SYNC
Linear PCM
(CODEC_B)
BCLK
TS
CONT
PCM Codec
STGAINB
CLKSEL
RXGAIN_ITS1
Decoder
10kΩ
RXGAINB
D/A1
VFRO1
CODECB_RXEN
G.711
LPEN1
LPF
AMP3
RXGAIN_PCM0
RXGAIN_PCM1
PCM_RXEN0
GSX0
G.729.A
TXGAIN_SC
A/D0
BPF
TXGAINA
AMP0
CODECA_TXEN
Sin
LPAD
+
- ATTs
GPAD Sout
Center
Clip
TXGAIN Encoder
SC_TXEN
G.711
Linear PCM
(CODEC_A)
Echo Canceller
AFF
STGAINA
RX1TX2
_GAIN
RXGAINA
D/A0
Rout
ATTr
RXGAIN_S
Rin
LPF
CODECA
AMP2
G.729.A
RXGAIN
_CH1
Decoder
SC_RXEN
RXGEN
RXGEN
RDB
RXGAIN
_CH2
RXDET
G.711
Generator path
TXDETA
FSK_DET
TXDETB
DVDD1
DTMF_REC
DVDD0
FDET
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
DTMF_CODE[3:0]
DGND2
TGEN1_EXFL
TONE_GEN1
(TONE)
TONE_GEN0
(TONE)
DGND1
CH2
PLL
TONE_DET0
MCK
CKGN
SYNC (8 kHz)
AGND
RXDET
TONE_DET1
TONE0_DET
TONE1_DET
RXGEN
FSK_GEN
INT
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
FGEN_FLAG
TIMOVF
Unused
TST0
PDNB
TST1
CLKOUT
VGB
XI
Control
Register
DP_DET
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
RXGENB
FGEN_FLAG
OSC
12.288 MHz
XO
GPIO2
GPIO0
DPDET
RXGENA
RXGENB_EN
Frame/DMA
Controller
TIMOVF
8
6
GPIOB
[5:0]
POWER
DPGEN
TXGEN
RXGENA_EN
TGEN0_EXFLAG
A0-A7
8b
RX
Buffer1
DC_EN
TIMER
DVDD2
16b
RX
Buffer0
T
CH1 S
W
VREF
Detector path setting
VREGOUT
WRB
CSB
RX_SIG
AVDD
FR0B
Bus Control
Unit
4
GPIOA
[3:0]
VFRO0
DGND0
FR1B
D0-D15
10kΩ
AVREF
ACK0B/
GPIOA[4]
TX
Buffer1
CH2
DC_EN
RX2TX1
_GAIN
Speech Codec
TXGAIN
_CH2
ACK1B/
GPIOA[5]
TX
Buffer0
CH1 T
S
W
GPIOC
[7:0]
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10kΩ
AIN0N
PCMI
S/P
RXGAIN_ITS2
RXGENB
This example shows the configuration for making calls with an analog telephone set (A-TEL) on the NW side by
connecting the analog telephone interface on the Linear PCM CODEC_B side.
RX_SIG
A-TEL
Linear
PCM
Codec
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
(CODEC_B)
Linear
PCM
Codec
EC
(CODEC_A)
VoIP-NW
RX_SIG
ML7204 (Configuration example 2)
29/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 3 (Calling Using Extension with PCM)
GSX1
TXGAIN_PCM1 PCM_TXEN1
TXDETB
10kΩ
AIN1N
A/D1
RX_SIG
BPF
TXGAINB
AMP1
PCM I/F
Encoder
G.711
LPEN0
CODECB_TXEN
TXGAIN_PCM0
P/S
PCM_TXEN0
PCMO
SYNC
Linear PCM
Codec (CODEC_B)
BCLK
TS
CONT
PCM Codec
STGAINB
CLKSEL
RXGAIN_ITS1
Decoder
10kΩ
RXGAINB
D/A1
VFRO1
CODECB_RXEN
G.711
LPEN1
LPF
AMP3
RXGENB
RXGAIN_PCM0
RXGAIN_PCM1
PCM_RXEN0
GSX0
PCM_RXEN1
TXGEN
TXDETA
10kΩ
G.729.A
TXGAIN_SC
AIN0N
A/D0
BPF
TXGAINA
AMP0
AIN0P
CODECA_TXEN
Sin
LPAD
+
-
Linear PCM
Codec (CODEC_A)
PCMI
S/P
RXGAIN_ITS2
ATTs
SC_TXEN
GPAD Sout
G.711
TXGAIN
_CH2
RX1TX2
_GAIN
Echo Canceller
AFF
STGAINA
Center
Clip
TXGAIN
Encoder
_CH1
RX2TX1
_GAIN
ACK1B/
GPIOA[5]
TX
Buffer0
CH1 T
S
W
ACK0B/
GPIOA[4]
TX
Buffer1
CH2
FR1B
FR0B
DC_EN
WRB
Speech Codec
Bus Control
Unit
RDB
CSB
D0-D15
10kΩ
Rout
RXGAINA
D/A0
RXGAIN_S
Rin
CODECA_RXEN
AMP2
SC_RXEN
RXGENA
RXGEN
RXD300ET
G.729.A
Decoder
RXGAIN
_CH2
G.711
VREF
DVDD2
TXDETA
DVDD1
TXDETB
FSK_DET
DTMF_REC
DVDD0
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
DTMF_CODE[3:0]
DGND2
DGND1
PLL
MCK
CKGN
SYNC (8 kHz)
AGND
AVDD
VREGOUT
RXDET
TONE_DET0
TONE0_DET
TONE_DET1
TONE1_DET
TONE_GEN1
(TONE C/ D)
TGEN0_EXFLAG
TONE_GEN0
(TONE A/ B)
FGEN_FLAG
FSK_GEN
TXGEN
RXGENA_EN
RXGENA
RXGENB
RXGENB_EN
RXGEN
DPGEN
DPDET
Frame/DMA
Controller
GPIO2
Control
Register
GPIO0
DP DET
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
INT
FGEN_FLAG
Unused
VGB
TIMOVF
TST0
TST1
PDNB
CLKOUT
XI
8
XO
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288 MHz
6
4
GPIOA
[3:0]
POWER
TGEN1_EXFLAG
TIMOVF
GPIOC
[7:0]
DGND0
TIMER
Generator path
Detector path setting
A0-A7
8b
RX
Buffer1
CH2
DC_EN
RX_SIG
AVREF
16b
RX
Buffer0
T
CH1 S
W
GPIOB
[5:0]
VFRO0
ATTr
LPF
RXGAIN
_CH1
30/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
This example shows the configuration for making calls using extension between two analog telephone sets
(A-TEL1 and A-TEL2) on the equipment that has two or more analog telephone interface ports.
RX_SIG
Linear
PCM
Codec
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
(CODEC_B)
A-TEL1
Linear
PCM
Codec
EC
(CODEC_A)
RX_SIG
ML7204 (Configuration example 3)
RX_SIG
Linear
PCM
Codec
(CODEC_B)
A-TEL2
Linear
PCM
Codec
EC
(CODEC_A)
RX_SIG
ML7204 (Configuration example 3)
31/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 4 (Three-Way Calling: Terminal Side [Two Parties] – NW Side [One Party])
GSX1
TXGAIN_PCM1 PCM_TXEN1
TXDETB
10kΩ
AIN1N
A/D1
RX_SIG
BPF
TXGAINB
AMP1
PCM I/F
Encoder
G.711
LPEN0
CODECB_TXEN
P/S
TXGAIN_PCM0 PCM_TXEN0
PCMO
SYNC
Linear PCM
Codec (CODEC_B)
BCLK
TS
CONT
PCM Codec
STGAINB
CLKSEL
RXGAIN_ITS1
Decoder
10kΩ
RXGAINB
D/A1
VFRO1
CODECB_RXEN
G.711
LPEN1
LPF
AMP3
RXGENB
RXGAIN_PCM0
RXGAIN_PCM1
PCM_RXEN0
GSX0
G.729.A
TXGAIN_SC
A/D0
BPF
TXGAINA
AMP0
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10kΩ
AIN0N
CODECA_TXEN
Sin
LPAD
+
-
ATTs
Center
Clip
TXGAIN
CH1
SC_TXEN
GPAD Sout
Echo Canceller
AFF
STGAINA
Encoder
G.711
TXGAIN
_CH2
Linear PCM
Codec (CODEC_A)
PCMI
S/P
RXGAIN_ITS2
RX2TX1
_GAIN
RX1TX2
_GAIN
ACK1B/
GPIOA[5]
TX
Buffer0
CH1 T
S
W
ACK0B/
GPIOA[4]
TX
Buffer1
CH2
FR1B
FR0B
DC_EN
Speech Codec
WRB
Bus Control
Unit
RDB
CSB
D0-D15
10kΩ
RXGAINA
D/A0
Rout
ATTr
Rin
LPF
CODECA_RXEN
AMP2
SC_RXEN
RXGEN
RXGENA
RXDET
RXGAIN
_CH1
G.729.A
Decoder
RXGAIN
_CH2
G.711
DVDD1
TXDETB
FSK_DET
DTMF_REC
DVDD0
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
DTMF_CODE[3:0]
DGND2
PLL
SYNC (8 kHz)
AGND
VREGOUT
TONE0_DET
RXDET
TONE_DET1
TONE1_DET
FGEN_FLAG
FSK_GEN
RXGENA
DPDET
RXGENA_EN
TGEN0_EXFLAG
TONE_GEN0
(TONE A/B)
TXGEN
DPGEN
RXGENB
RXGENB_EN
RXGEN
TIMOVF
Frame/DMA
Controller
GPIO2
Control
Register
GPIO0
DP_DET
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
INT
FGEN_FLAG
Unused
VGB
TIMOVF
TST1
TST0
PDNB
CLKOUT
XI
8
XO
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288 MHz
6
4
GPIOA
[3:0]
AVDD
TONE_DET0
MCK
CKGN
TGEN1_EXFLAG
TONE_GEN1
(TONE C/D)
RX
Buffer1
GPIOC
[7:0]
DGND0
POWER
TIMER
Generator path
Detector path setting
TXDETA
A0-A7
8b
CH2
VREF
DVDD2
DGND1
T
CH1 S
W
DC_EN
RX_SIG
AVREF
16b
RX
Buffer0
GPIOB
[5:0]
VFRO0
RXGAIN_SC
32/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
This example shows the configuration for making three-way calling between the terminal side (two parties) and
the VoIP NW side (one party).
RX_SIG
Linear
PCM
Codec
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
(CODEC_B)
A-TEL2
Linear
PCM
Codec
EC
(CODEC_A)
RX_SIG
ML7204 (Configuration example 3)
RX_SIG
Linear
PCM
Codec
(CODEC_B)
A-TEL1
Linear
PCM
Codec
EC
(CODEC_A)
VoIP-NW
RX_SIG
ML7204 (Configuration example 4)
33/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 5 (Three-Way Calling: Terminal Side [One Party] – NW Side [Two Parties])
GSX1
TXGAIN_PCM1 PCM_TXEN1
TXDETB
10kΩ
AIN1N
A/D1
RX_SIG
BPF
TXGAINB
AMP1
PCM I/F
Encoder
G.711
LPEN0
CODECB_TXEN
TXGAIN_PCM0
P/S
PCM_TXEN0
PCMO
SYNC
Linear PCM
Codec (CODEC_B)
BCLK
TS
CONT
PCM Codec
STGAINB
CLKSEL
RXGAIN_ITS1
Decoder
10kΩ
RXGAINB
D/A1
VFRO1
CODECB_RXEN
G.711
LPEN1
LPF
AMP3
RXGENB
RXGAIN_PCM0
RXGAIN_PCM1
PCM_RXEN0
GSX0
AIN0N
AIN0P
A/D0
PCM_RXEN1
TXGEN
TXDETA
10kΩ
TXGAIN_SC
G.729.A
BPF
TXGAINA
AMP0
CODECA_TXEN
Sin
LPAD
+
-
ATTs
GPAD Sout
Center
Clip
G.711
Echo Canceller
AFF
STGAINA
ACK0B/
GPIOA[4]
FR1B
TX
Buffer1
CH2
FR0B
DC_EN
RX2TX1
_GAIN
RX1TX2
_GAIN
ACK1B/
GPIOA[5]
TX
Buffer0
CH1 T
S
W
TXGAIN Encoder
SC_TXEN
TXGAIN
_CH2
Linear PCM
Codec (CODEC_A)
PCMI
S/P
RXGAIN_ITS2
WRB
Bus Control
Unit
Speech Codec
RDB
CSB
D0-D15
10kΩ
RXGAINA
D/A0
RXGAIN_SC
Rin
ATTr
CODECA_RXEN
AMP2
SC_RXEN
RXGENA
RXGEN
RXGAIN
_CH1
G.729.A
RXGAIN
_CH2
RXDET
CH2
VREF
TIMER
Generator path
Detector path setting
TXDETA
DVDD2
FSK_DET
TXDETB
DVDD1
DTMF_REC
DVDD0
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
TGEN1_EXFLAG
TONE_GEN1
(TONE C/D)
TONE_GEN0
(TONE A/B)
DGND1
MCK
CKGN
PLL
SYNC (8 kHz)
AGND
TONE_DET0
TONE0_DET
TONE_DET1
TONE1_DET
RXDET
DPDET
RXGENB_EN
RXGENB
RXGEN
FSK_GEN
INT
INTB/
GPIOA[6]
TIMOVF
Unused
PDNB
TST1
TST0
CLKOUT
XO
Control
Register
GPIO
DP D
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
FGEN_FLAG
VGB
XI
GPIO
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288 MHz
VREGOUT
Frame/DMA
Controller
TIMOV
8
6
4
GPIOA
[3:0]
AVDD
TXGEN
RXGENA
FGEN_FLAG
A0-A7
8b
RX
Buffer1
GPIOB
[5:0]
POWER
DPGEN
RXGENA_EN
TGEN0_EXFLAG
DTMF_CODE[3:0]
DGND2
DGND0
G.711
16b
RX
Buffer0
DC_EN
RX_SIG
AVREF
Decoder
T
CH1 S
W
GPIOC
[7:0]
VFRO0
Rout
LPF
This example shows the configuration for making three-way calling between the terminal side (one party) and
VoIP NW side (two parties).
RX_SIG
Linear
PCM
Codec
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
(CODEC_B)
A-TEL
Linear
PCM
Codec
VoIP-NW1
EC
(CODEC_A)
VoIP-NW2
RX_SIG
ML7204 (Configuration example 5)
34/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 6 (Three-Way Calling: Terminal Side [Three Parties])
GSX]1
PCM_TXEN1
TXGAIN_PCM1
TXDETB
10kΩ
AIN1N
A/D1
RX_SIG
BPF
PCM I/F
Encoder
G.711
LPEN0
TXGAINB
AMP1
CODECB_TXEN
TXGAIN_PCM0
P/S
PCM_TXEN0
PCMO
SYNC
Linear PCM
Codec (CODEC_B)
BCLK
TS
CONT
PCM Codec
STGAINB
CLKSEL
RXGAIN_ITS1
Decoder
10kΩ
RXGAINB
D/A1
VFRO1
CODECB_RXEN
G.711
LPEN1
LPF
AMP3
RXGENB
RXGAIN_ITS2
RXGAIN_PCM0
RXGAIN_PCM1
PCM_RXEN0
GSX0
TXGAIN_SC
A/D0
G.729.A
TXGAINA
CODECA_TXEN
Sin
LPAD
+
- ATTs
Center
Clip
TXGAIN
_CH1
SC_TXEN
GPAD Sout
G.711
TXGAIN
_CH2
Linear PCM
Codec (CODEC_A)
Echo Canceller
AFF
STGAINA
Encoder
ACK0B/
GPIOA[4]
TX
Buffer1
CH2
FR1B
FR0B
DC_EN
RX2TX1
_GAIN
RX1TX2
_GAIN
ACK1B/
GPIOA[5]
TX
Buffer0
CH1 T
S
W
BPF
AMP
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10kΩ
AIN0N
PCMI
S/P
Speech Codec
WRB
Bus Control
Unit
RDB
CSB
D0-D15
10kΩ
Rout
RXGAINA
VFRO0
Rin
ATTr
RXGAIN_SC
LPF
CODECA_RXEN
AMP
RXGEN
RXGAIN
_CH2
RXDET
G.711
TIMER
Generator path
Detector path setting
DVDD2
DVDD1
TXDETB
FSK_DET
DTMF_REC
DVDD0
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
TGEN1_EXFLAG
CH2
POWER
TONE_DET0
MCK
CKGN
PLL
SYNC (8 kHz)
TONE_DET1
AGND
RXDET
AVDD
RXGEN
FSK_GEN
Control
Register
DP_DET
INT
FGEN_FLAG
TIMOVF
12.288 MHz
Unused
VGB
6
GPIOB
[5:0]
GPIOC
[7:0]
TST1
PDNB
TST0
XO
CLKOUT
8
XI
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
OSC
VREGOUT
GPIO2
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
RXGENB_EN
FGEN_FLAG
TONE1_DET
DPDET
RXGENA
RXGENB
(TONE A/ B)
TONE0_DET
Frame/DMA
Controller
TIMOVF
GPIO0
RXGENA_EN
TGEN0_EXFLAG
TONE_GEN0
DGND2
DPGEN
TXGEN
TONE_GEN1
(TONE C/ D)
DTMF_CODE[3:0]
DGND1
DGND0
RX
Buffer1
VREF
TXDETA
A0-A7
8b
DC_EN
RX_SIG
AVREF
16b
RX
Buffer0
T
CH1 S
W
Decoder
SC_RXEN
RXGENA
G.729.A
4
GPIOA
[3:0]
D/A0
RXGAIN
_CH1
This example shows the configuration for making three-way calling between analog telephones (A-TEL1,
A-TEL2, and A-TEL3) on the equipment with multiple analog telephone interface ports.
MCU
I/F
Speech
Codec
PCM
RX_SIG
A-TEL2
(CODEC_A)
Linear
PCM
Codec
(CODEC_B)
Linear
PCM
Codec
EC
EC
(CODEC_A)
Linear
PCM
Codec
(CODEC_B)
Linear
PCM
Codec
RX_SIG
RX_SIG
RX_SIG
RX_SIG
(CODEC_A)
EC
Linear
PCM
Codec
(CODEC_B)
Linear
PCM
Codec
I/F
PCM
Codec
Speech
Codec
PCM
Codec
Speech
Codec
PCM
Codec
RX_SIG
A-TEL3
ML7204
(configuration example 6)
MCU
I/F
PCM
I/F
ML7204
(configuration example 6)
MCU
I/F
PCM
I/F
ML7204
(configuration example 6)
A-TEL1
35/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 7 (CODEC-A-CODEC-B Loop Back Mode)
GSX1
TXGAIN_PCM1 PCM_TXEN1
TXDETB
10kΩ
AIN1N
A/D1
RX_SIG
BPF
TXGAINB
AMP1
PCM I/F
Encoder
G.711
LPEN0
CODECB_TXEN
TXGAIN_PCM0
P/S
PCM_TXEN0
PCMO
SYNC
Linear PCM
Codec (CODEC_B)
BCLK
TS
CONT
PCM Codec
STGAINB
CLKSEL
RXGAIN_ITS1
Decoder
10kΩ
RXGAINB
D/A1
VFRO1
CODECB_RXEN
G.711
LPEN1
LPF
AMP3
RXGAIN_ITS2
RXGENB
RXGAIN_PCM0
PCM_RXEN1
TXGEN
TXDETA
10kΩ
AIN0P
RXGAIN_PCM1
PCM_RXEN0
GSX0
G.729.A
TXGAIN_SC
AIN0N
A/D0
BPF
TXGAINA
AMP0
CODECA_TXEN
Sin
LPAD
+
- ATTs
Linear PCM
Codec (CODEC_A)
PCMI
S/P
TXGAIN
_CH1
SC_TXEN
GPAD Sout
Encoder
G.711
TXGAIN
_CH2
AFF
STGAINA
Center
Clip
Echo Canceller
RX2TX1
_GAIN
RX1TX2
_GAIN
ACK1B/
GPIOA[5]
TX
Buffer0
CH1 T
S
W
ACK0B/
GPIOA[4]
FR1B
TX
Buffer1
CH2
FR0B
DC_EN
WRB
Speech Codec
Bus Control
Unit
RDB
CSB
D0-D15
10kΩ
RXGAIN
Rout
Rin
ATTr
RXGAIN SC
LPF
CODECA_RXEN
SC_RXEN
RXGENA
RXGEN
Decode
RXGAIN
RXDET
CH2
G.711
DVDD2
DVDD1
TXDETB
FSK_DET
DTMF_REC
DVDD0
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF DET
DTMF_CODE[3:0]
DGND2
DGND1
DGND0
POWER
TONE_DET0
MCK
CKGN
PLL
SYNC (8 kHz)
RXDET
AGND
AVDD
VREGOUT
TIMER
Generator path
Detector path setting
TONE_DET1
TGEN1_EXFLAG
TONE_GEN1
(TONE C/ D)
TONE_GEN0
(TONE A/ B)
TONE0_DET
TONE1_DET
FGEN_FLAG
DPGEN
TXGEN
RXGENA_EN
TGEN0_EXFLAG
RX
Buffer1
CH2
VREF
TXDETA
DPDET
RXGENA
TIMOVF
Frame/DMA
Controller
GPIO2
Control
Register
GPIO0
DP_DET
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
RXGENB
RXGENB_EN
RXGEN
FSK_GEN
INT
FGEN_FLAG
TIMOVF
Unused
VGB
GPIOC
[7:0]
TST1
TST0
PDNB
XO
8
CLKOUT
INTB/
GPIOA[6]
FDET RQ
FDET_FER/FDET_OER
OSC
12.288 MHz
XI
A0-A7
8b
DC_EN
RX_SIG
AVREF
T
CH1 S
W
6
4
GPIOA
[3:0]
AMP2
_CH1
16b
RX
Buffer0
GPIOB
[5:0]
RXGAINA
D/A0
VFRO0
G.729.A
This example shows the configuration where CODEC_A and CODEC_B are connected in loopback mode
according to the internal path settings.
RX_SIG
B
Linear
PCM
Codec
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
(CODEC_B)
A
Linear
PCM
Codec
EC
(CODEC_A)
RX_SIG
ML7204 (Configuration example 7)
36/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
APPLICATION CIRCUITS
ML7204-001GA
1.4 V
50
51
52
Analog input
53
54
55
2.2uF
AIN0P
AIN0N
GSX0
GSX1
AIN1N
AVREF
0.1uF
56
Analog output
57
45
46
47
48
General-purpose
I/O pins
VFRO0
VFRO1
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
+3.3 V +3.3 V
43
3
4
500Ω
PCM
I/F
5
6
Power-down control
12.288 MHz
crystal
42
60
61
CLKSEL
PCMO
PCMI
BCLK
SYNC
PDNB
XI
XO
1MΩ
8pF
8pF
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
41
40
39
38
37
36
35
34
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MCU
I/F
+3.3 V
ACK0B
ACK1B
FR0B
FR1B
INTB
CSB
RDB
WRB
VBG
8
9
10
11
12
13
14
15
64
150pF
+3.3 V
7
33
62
49
10uF 0.1uF
16
44
59
58
DVDD0
DVDD1
DVDD2
AVDD
DGND0
DGND1
DGND2
AGND
VREGOUT
TST1
TST0
63
0.1uF 10uF
1
2
Conditions
• Frame mode
• SYNC and BCLK:
Configured to be
output
(CLKSEL = "1")
37/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
ML7204-001TB
1.4 V
78
79
80
Analog input
82
83
85
2.2 µF
AIN0P
AIN0N
GSX0
GSX1
AIN1N
AVREF
0.1 µF
86
Analog output
87
General-purpose
I/O pins A
General-purpose
I/O pins B
General-purpose
I/O pins C
VFRO0
VFRO1
70
71
74
75
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
62
63
65
66
68
69
GPIOB[0]
GPIOB[1]
GPIOB[2]
GPIOB[3]
GPIOB[4]
GPIOB[5]
4
5
10
11
13
14
17
18
GPIOC[0]
GPIOC[1]
GPIOC[2]
GPIOC[3]
GPIOC[4]
GPIOC[5]
GPIOC[6]
GPIOC[7]
+3.3 V +3.3 V
64
6
7
500Ω
PCM
I/F
8
9
92
94
12.288 MHz
crystal
CLKSEL
PCMO
PCMI
BCLK
SYNC
XI
XO
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MCU
I/F
ACK0B
ACK1B
FR0B
FR1B
INTB
CSB
RDB
WRB
VBG
VREGOUT
15
16
19
20
21
22
23
24
99
150 pF
98
0.1 µF 10 µF
8 pF
+3.3 V
12
52
95
76
10uF
49
48
46
45
43
42
40
39
37
36
34
33
31
30
28
27
+3.3 V
1 MΩ
8 pF
60
59
58
57
56
55
54
53
0.1uF
25
67
91
88
PDNB
DVDD0
DVDD1
DVDD2
AVDD
DGND0
DGND1
DGND2
AGND
CLKOUT
TST1
TST0
61
1
2
3
Power-down control
12.288 MHz
clock output
Conditions
• Frame mode
• SYNC and BCLK:
Configured to be
output
(CLKSEL = "1")
38/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method, temperature
and times).
39/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.55 TYP.
4/Oct. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method, temperature
and times).
40/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
REVISION HISTORY
Document No.
FEDL7204-001DIGEST-01
Date
Aug. 12, 2004
Page
Previous
Current
Edition
Edition
–
–
Description
Final edition 1
41/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2004 Oki Electric Industry Co., Ltd.
42/42