TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 2.25MHz 400mA/600mA Dual Step-Down Converter In Small 3x3mm QFN Package FEATURES DESCRIPTION • • • • • • The TPS6240x device series are synchronous dual step-down DC-DC converters optimized for battery powered portable applications. They provide two independent output voltage rails powered by 1-cell Li-Ion or 3-cell NiMH/NiCD batteries. The devices are also suitable to operate from a standard 3.3V or 5V voltage rail. • • • • • • • APPLICATIONS • • • • • • Cell Phones, Smart-phones PDAs, Pocket PCs OMAP™ and Low Power DSP Supply Portable Media Players Digital Radio Digital Cameras With an input voltage range of 2.5V to 6V the TPS62400 is ideal to power portable applications like smart phones, PDAs and other portable equipment. With the EasyScale™ serial interface the output voltages can be modified during operation. The fixed output voltage versions TPS62401 and TPS62403 support one pin controlled simple Dynamic Voltage Scaling for low power processors. The TPS6240x operates at 2.25MHz fixed switching frequency and enters the power save mode operation at light load currents to maintain high efficiency over the entire load current range. For low noise applications the devices can be forced into fixed frequency PWM mode by pulling the MODE/DATA pin high. In the shutdown mode, the current consumption is reduced to 1.2µA, typical. The devices allow the use of small inductors and capacitors to achieve a small solution size. The TPS62400 is available in a 10-pin leadless package (3×3mm QFN) 100 90 TPS62401 VIN 2.5 V – 6 V VIN 10 mF FB 1 80 2.2 mH Vout1: 1.575 V 400 mA SW1 DEF_1 10 mF EN_1 70 Efficiency • High Efficiency—Up to 95% VIN Range From 2.5 V to 6 V 2.25 MHz Fixed Frequency Operation Output Current 400 mA and 600 mA Adjustable Output Voltage From 0.6V to VIN EasyScale™ Optional One-Pin Serial Interface for Dynamic Output Voltage Adjustment TPS62401, TPS62403 Fixed Output Voltage Options Power Save Mode at Light Load Currents 180° Out of Phase Operation Output Voltage Accuracy in PWM Mode ±1% Typical 32-µA Quiescent Current for both Converters 100% Duty Cycle for Lowest Dropout One Pin Simple Dynamic Voltage Scaling Available in a 10-Pin QFN (3×3mm) VOUT2 = 1.8 V VIN = 3.6 V MODE/DATA = 0 60 50 VOUT1 = 1.575 V 40 30 EN_2 SW2 2.2 mH MODE/ DATA Vout2: 1.8 V 600 mA 20 10 ADJ2 GND 10 mF 0 0.01 0.1 1 10 100 1000 IOUT mA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EasyScale, OMAP, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 ORDERING INFORMATION TA PART NUMBER TPS62400 –40°C to 85°C TPS62401 DEFAULT OUTPUT VOLTAGE (1) OUT1 Adjustable OUT2 OUT1 Fixed default OUT2 OUT1 TPS62403 DEF_1 = Low 1.575V Fixed default 1.8V Fixed default OUT2 (1) (2) DEF_1 = High 1.1V DEF_1 = High 1.1V DEF_1 = Low 1.575V Fixed default 2.8V OUTPUT CURRENT 400mA 600mA 400mA QFN (2) PACKAGE ORDERING PACKAGE MARKING DRC TPS62400DRC BQE DRC TPS62401DRC BRN DRC TPS62403DRC BYI 600mA 400mA 600mA Contact TI for other fixed output voltage options. The DRC (QFN 10 PIN) package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Input voltage range on VIN (2) –0.3 to 7 V V ≤ 0.5 mA Voltage on SW1, SW2 –0.3 to 7 V Voltage on ADJ2, FB1 current into MODE/DATA ESD rating (3) –0.3 to VIN +0.3, ≤7 V HBM Human body model 2 kV Charge device model CDM 1 kV Machine model 200 V 150 °C Operating ambient temperature range –40 to 85 °C Storage temperature range –65 to 150 °C TJ(max) Maximum operating junction temperature TA Tstg (2) (3) UNIT –0.3 to VIN +0.3, ≤7 Voltage range on EN, MODE/DATA, DEF_1 (1) VALUE Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. DISSIPATION RATINGS PACKAGE RθJA POWER RATING FOR TA≤ 25°C DERATING FACTOR ABOVE TA = 25°C DRC 49°C/W 2050mW 21mW/°C RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VIN 2 NOM MAX UNIT Supply voltage 2.5 6 V Output voltage range for adjustable voltage 0.6 VIN V TA Operating ambient temperature -40 85 °C TJ Operating junction temperature -40 125 °C Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 ELECTRICAL CHARACTERISTICS VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2µH, COUT = 20µF, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage range IQ Operating quiescent current ISD Shutdown current VUVLO Undervoltage lockout threshold 6.0 V One converter, IOUT = 0mA. PFM mode enabled (Mode = 0) device not switching, EN1 = 1 OR EN2 = 1 2.5 19 29 µA Two converter, IOUT = 0mA. PFM mode enabled (Mode = 0) device not switching, EN1 = 1 AND EN2 = 1 32 48 µA IOUT = 0mA, MODE/DATA = GND, for one converter, VOUT 1.575V (1) 23 µA IOUT = 0mA, MODE/DATA = VIN, for one converter, VOUT 1.575V (1) 3.6 mA EN1, EN2 = GND, VIN = 3.6V (2) 1.2 3 EN1, EN2 = GND, VIN ramped from 0V to 3.6V (3) 0.1 1 Falling 1.5 2.35 Rising 2.4 µA V ENABLE EN1, EN2 VIH High-level input voltage, EN1, EN2 1.2 VIN V VIL Low-level input voltage, EN1, EN2 0 0.4 V IIN Input bias current, EN1, EN2 1.0 µA EN1, EN2 = GND or VIN 0.05 DEF_1 INPUT VDEF_1H DEF_1 high level input voltage DEF_1 pin is a digital input at TPS62401 fixed output voltage option 0.9 VIN V VDEF_1L DEF_1 low level input voltage DEF_1 pin is a digital input at TPS62401 fixed output voltage option 0 0.4 V IIN Input bias current DEF_1 DEF_1 GND or VIN 1.0 µA V 0.01 MODE/DATA VIH High-level input voltage, MODE/DATA 1.2 VIN VIL Low-level input voltage, MODE/DATA 0 0.4 V IIN Input bias current, MODE/DATA MODE/DATA = GND or VIN 1.0 µA VOH Acknowledge output voltage high Open drain, via external pullup resistor VIN V VOL Acknowledge output voltage low Open drain, sink current 500µA 0.4 V 0.01 0 INTERFACE TIMING tStart Start time tH_LB High time low bit, logic 0 detection Signal level on MODE/DATA pin is > 1.2V tL_LB Low time low bit, logic 0 detection Signal level on MODE/DATA pin < 0.4V µs 2 2 200 µs 2x 400 µs 2 200 µs 2x 400 µs tH_LB tL_HB Low time high bit, logic 1 detection Signal level on MODE/DATA pin < 0.4V tH_HB High time high bit, logic 1 detection Signal level on MODE/DATA pin is > 1.2V tL_HB TEOS End of Stream TEOS tACKN Duration of acknowledge condition (MODE/DATE line pulled low by the device) VIN 2.5V to 6V tvalACK Acknowledge valid time (1) (2) (3) µs 2 400 520 µs 2 µs Device is switching with no load on the output, L = 3.3µH, value includes losses of the coil These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage VIN has not powered down. These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid. Submit Documentation Feedback 3 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2µH, COUT = 20µF, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted) PARAMETER ttimeout TEST CONDITIONS Timeout for entering power save mode MIN TYP MAX UNIT 520 µs 620 mΩ 1 µA 200 450 mΩ 6 7.5 µA 0.68 0.8 0.92 0.85 1.0 1.15 MODE/DATA Pin changes from high to low POWER SWITCH RDS(ON) P-Channel MOSFET on-resistance, Converter 1,2 VIN = VGS = 3.6V ILK_PMOS P-Channel leakage current VDS = 6.0V RDS(ON) N-Channel MOSFET on-resistance Converter 1,2 VIN = VGS = 3.6V ILK_SW1/SW2 Leakage current into SW1/SW2 pin Includes N-Chanel leakage current, VIN = open, VSW = 6.0V, EN = GND (4) ILIMF Forward Current Limit OUTPUT 1 PMOS and NMOS OUTPUT 2 2.5V ≤ VIN≤ 6.0V Thermal shutdown Increasing junction temperature 150 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C TSD 280 A OSCILLATOR fSW 2.5V ≤ VIN ≤ 6.0V Oscillator frequency 2.0 2.25 2.5 MHz OUTPUT VOUT Adjustable output voltage range Vref Reference voltage 0.6 Voltage positioning active, MODE/DATA = GND, device operating in PFM mode, VIN = 2.5V to 5.0V (6) (7) VOUT (PFM) DC output voltage accuracy adjustable and fixed output voltage (5) VOUT(PWM) DC output voltage load regulation 2.5% MODE/DATA = GND; device operating in PWM Mode, VIN = 2.5V to 6.0V (7) –1% 0% 1% VIN = 2.5V to 6.0V, Mode/Data = VIN , Fixed PWM operation, 0mA < IOUT1 < 400mA ; 0mA < IOUT2 < 600mA (8) –1% 0% 1% 0.5 switching (9) Start-up time Activation time to start tRamp VOUT Ramp UP time Time to ramp from 5% to 95% of VOUT (7) (8) (9) 4 1.01 VOUT PWM operation mode V mV –1.5% tStart up (4) (5) (6) VIN 600 %/A 170 µs 750 µs On pins SW1 and SW2 an internal resistor of 1MΩ is connected to GND. Output voltage specification does not include tolerance of external voltage programming resistors Configuration L typ 2.2µH, COUT typ 20µF, see parameter measurement information, the output voltage ripple in PFM mode depends on the effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance. In Power Save Mode, PWM operation is typically entered at IPSM = VIN/32Ω. For VOUT > 2.0V, VIN min = VOUT +0.5V This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 =1) AND the other converter is already enabled (e.g., EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = low) to active mode (EN1 and/or EN2=1) a value of typ 80 µs for ramp up of internal circuits needs to be added. After tStart the converter starts switching and ramps VOUT. Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 PIN ASSIGNMENTS ADJ2 1 MODE/DATA 2 VIN 3 FB1 4 DEF_1 5 D PA r e w Po 10 SW2 9 EN2 8 GND 7 EN1 6 SW1 Top view DRC package TERMINAL FUNCTIONS TERMINAL NAME NO. (QFN) I/O ADJ2 1 I MODE/DATA 2 I/0 DESCRIPTION Input to adjust output voltage of converter 2. In adjustable version (TPS62400) connect a external resistor divider between VOUT2, this pin and GND to set output voltage between 0.6V and VIN. At fixed output voltage version (TPS62401) this pin MUST be directly connected to the output. If EasyScale Interface is used for converter 2, this pin must be directly connected to the output, too. This Pin has 2 functions: 1. Operation Mode selection: With low level, Power Save Mode is enabled where the device operates in PFM mode at light loads and enters automatically PWM mode at heavy loads. Pulling this PIN to high forces the device to operate in PWM mode over the whole load range. 2. EasyScale™ Interface function: One wire serial interface to change the output voltage of both converters. The pin has an open drain output to provide an acknowledge condition if requested. The current into the open drain output stage may not exceed 500µA. The interface is active if either EN1 or EN2 is high. VIN 3 FB1 4 I Supply voltage, connect to VBAT, 2.5V to 6V Direct feedback voltage sense input of converter 1, connect directly to Vout 1. An internal feed forward capacitor is connected between this pin and the error amplifier. In case of fixed output voltage versions or when the Interface is used, this pin is connected to an internal resistor divider network. DEF_1 5 I This pin defines the output voltage of converter 1. The pin acts either as analog input for output voltage setting via external resistors (TPS62400), or digital input to select between two fixed default output voltages (TPS62401). For the TPS62400, an external resistor network needs to be connected to this pin to adjust the default output voltage. Using the fixed output voltage device option TPS62401 this pin selects between two fixed default output voltages: High = 1.1V, Low = 1.575V. SW1 6 I/O EN1 7 I GND 8 EN2 9 I SW2 10 I/O PowerPAD™ Switch Pin of Converter1. Connect to Inductor Enable Input for Converter1, active high GND for both converters; connect this pin to the PowerPAD™ Enable Input for Converter 2, active high Switch Pin of Converter 2. Connect to Inductor. Connect to GND Submit Documentation Feedback 5 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 FUNCTIONAL BLOCK DIAGRAM VIN PMOS Current Limit Comparator Converter 1 VIN FB_VOUT Thermal Shutdown Softstart VREF +1% Skip Comp. EN1 FB_VOUT VREF- 1% Ext. res. network DEF1 Skip Comp. Low VREF Control Stage Error Amp. Internal FB VOUT1 compensated Int. Resistor Network PWM Comp. Cff 25pF SW1 MODE Register RI 1 Sawtooth Generator DEF1_High RI3 RI..N FB1 Gate Driver GND DEF1_Low Average Current Detector Skip Mode Entry Note 1 NMOS Current Limit Comparator CLK 0° Reference Mode/ DATA Easy Scale Interface ACK MOSFET Open drain Undervoltage Lockout PMOS Current Limit Comparator CLK 180° Converter 2 Int. Resistor Network Load Comparator 2.25MHz Oscillator VIN FB_VOUT VREF +1% Skip Comp. Register FB_VOUT DEF2 Note 2 Cff 25pF VREF- 1% Skip Comp. Low VREF Error Amp. RI 1 Internal compensated Control Stage Gate Driver PWM Comp. RI..N SW2 MODE FB_VOUT2 ADJ2 Thermal Shutdown Softstart Sawtooth Generator CLK 180° GND Average Current Detector Skip Mode Entry NMOS Current Limit Comparator EN2 Load Comparator GND 6 (1) In fixed output voltage version, the PIN DEF_1 is connected to an internal digital input and disconnected from the error amplifier (2) To set the output voltage of Converter 2 via EasyScale™ Interface, ADJ2 pin must be directly connected to VOUT2 Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION TPS62400 VIN 2.5 V – 6 V FB 1 VIN L1 CIN VOUT1 SW1 2.2 mH LSP4018 10 mF R11 COUT1 2x10 mF GRM21BR61A106K DEF_1 R12 EN_1 L2 EN_2 VOUT2 SW2 2.2 mH LSP4018 MODE/ DATA R21 C ff2 33 pF ADJ2 COUT2 2x10 mF GRM21BR61A106K R22 GND TYPICAL CHARACTERISTICS TABLE OF GRAPHS AND FIGURES FIGURE NO. Efficiency TPS62401 VOUT1 = 1.1V 1 Efficiency TPS62401 VOUT1 = 1.575V 2 Efficiency VOUT 2 = 1.8V 3 Efficiency TPS62400 VOUT2 = 3.3V 4 Efficiency vs VIN 5, 6 DC Output Accuracy VOUT1 = 1.1V 7 DC Output Accuracy VOUT2 = 3.3V 8 DC Output Accuracy VOUT2 = 1.8V 9 DC Output Accuracy VOUT1 1.575V, L = 2.2µH, COUT = 22µF 10 DC Output Accuracy VOUT1 1.575V, L = 3.3µH, COUT = 10µF 11 FOSC vs VIN 12 Iq for one converter 13 Iq for both converters, not switching 14 RDSON PMOS vs VIN 15 RDSON NMOS vs VIN 16 Light Load Output Voltage Ripple in Power Save Mode 17 Output Voltage Ripple in Forced PWM Mode 18 Output Voltage Ripple in PWM Mode 19 Forced PWM/ PFM Mode Transition 20 Load Transient Response PFM/PWM 21 Load Transient Response PWM Operation 22 Line Transient Response 23 Startup Timing One Converter 24 TPS62401 DEF1_pin Function for Output Voltage Selection 25 Typical Operation VIN = 3.6V, VOUT1 = 1.575V, VOUT2 = 1.8V 26 Submit Documentation Feedback 7 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) FIGURE NO. Typical Operation VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 3.0V 27 Typical Operation VIN = 3.6V, VOUT1 = 1.2V, VOUT2 = 1.2V 28 VOUT1 Change With EasyScale 29 Dynamic Voltage Positioning 30 Soft Start 31 EasyScale™ Protocol Overview 32 EasyScale Protocol Without Acknowledge 33 EasyScale Protocol Including Acknowledge 34 EasyScale – Bit Coding 35 MODE/DATA PIN: Mode Selection 36 MODE/DATA Pin: Power Save Mode / Interface Communication 37 Typical Application Circuit 1.5V / 2.85V Adjustable Outputs, low PFM voltage ripple optimized 38 Typical Application Circuit 1.5V / 2.85V Adjustable Outputs 39 TPS62401 Fixed 1.575V/1.8 V Outputs, low PFM voltage ripple optimized 40 TPS62401 Fixed 1.1V/1.8 V Outputs, low PFM voltage ripple optimized 41 TPS62401 Fixed 1.575V/1.8 V Outputs 42 Dynamic Voltage Scaling on Vout1 Controlled by DEF_1 pin 43 TPS62403 1.575V/2.8V Outputs 44 Layout Diagram 45 PCB Layout 46 EFFICIENCY TPS62401 VOUT1 = 1.1V 100 VOUT1 = 1.1 V 90 80 80 70 VIN = 2.7 V VIN = 2.7 V 60 VIN = 3.6 V 50 VIN = 3.6 V VIN = 5 V VIN = 5 V 40 30 Efficiency % Efficiency % VOUT1 = 1.575 V 90 70 Power Save Mode MODE/DATA = 0 Forced PWM Mode MODE/DATA = 1 10 10 1 10 100 1000 0 0.01 VIN = 3.6 V VIN = 5 V 40 30 VIN = 2.7 V VIN = 3.6 V 50 20 0.1 VIN = 2.7 V 60 20 0 0.01 8 EFFICIENCY TPS62401 VOUT1 = 1.575V 100 VIN = 5 V Power Save Mode MODE/DATA = 0 0.1 1 Forced PWM Mode MODE/DATA = 1 10 IOUT mA IOUT mA Figure 1. Figure 2. Submit Documentation Feedback 100 1000 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 EFFICIENCY VOUT 2 = 1.8V EFFICIENCY TPS62400 VOUT 2 = 3.3V 100 100 VOUT2 = 1.8 V 90 70 VIN = 2.7 V 70 VIN = 2.7 V Efficiency % 60 VIN = 3.6 V VIN = 3.6 V 50 VIN = 5 V VIN = 5 V 40 Power Save Mode MODE/DATA = 0 30 Forced PWM Mode MODE/DATA = 1 VIN = 5 V 50 40 20 10 1 10 100 0 0.01 1000 0.1 1 IOUT mA Efficiency - % EFFICIENCY vs VIN VOUT2 = 2.8 V VIN = 3.3 V VIN = 3.6 V MODE/DATA = low 70 60 30 IOUT = 10 mA 90 VOUT2 = 2.8 V VIN = 3.3 V VIN = 3.6 V MODE/DATA = high VOUT1 = 1.575 V VIN = 3.3 V VIN = 3.6 V MODE/DATA = low 85 TPS62403 Efficiency VOUT1/VOUT2, MODE/DATA = 0, DEF_1 = 0 VOUT1 = 1.575 V VIN = 3.3 V VIN = 3.6 V MODE/DATA = high 20 80 IOUT = 1 mA 75 IOUT = 200 mA 70 65 60 10 0 0.01 MODE/DATA = 0 VOUT = 1.575 V 95 50 40 1000 100 Efficiency % 80 100 Figure 4. EFFICIENCY TPS62403 VOUT1/VOUT2 90 10 IOUT mA Figure 3. 100 Forced PWM Mode MODE/DATA = 1 Power Save Mode MODE/DATA = 0 30 10 0.1 VIN = 5 V 60 20 0 0.01 VIN = 3.6 V VIN = 3.6 V 80 80 Efficiency % VOUT2 = 3.3 V 90 55 0.1 1 10 IOUT - mA 100 1000 50 2 3 4 5 6 VIN - V Figure 5. Figure 6. Submit Documentation Feedback 9 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 EFFICIENCY vs VIN 100 DC OUTPUT ACCURACY VOUT1 = 1.1V 1.150 MODE/DATA = 0 VOUT = 3.3 V IOUT = 100 mA VOUT1 = 1.1 V MODE/DATA = low, PFM Mode, voltage positioning active 90 VIN = 4.2 V 1.125 PWM Mode Operation VOUT DC - V Efficiency % IOUT = 10 mA IOUT = 1 mA 80 VIN = 2.7 V VIN = 3.6 V VIN = 2.7 V VIN = 3.6 V 1.100 VIN = 4.2 V MODE/DATA = high, forced PWM Mode 70 1.075 60 1.050 0.01 50 3 4 5 0.10 1 10 100 1000 IOUT - mA 6 VIN - V Figure 7. Figure 8. DC OUTPUT ACCURACY VOUT2 = 3.3V 3.400 DC OUTPUT ACCURACY VOUT2 = 1.8V 1.854 VOUT2 = 3.3V VOUT2 = 1.8 V MODE/DATA = low, PFM Mode, voltage positioning active 1.836 3.350 PWM Mode Operation PWM Mode Operation VIN = 3.6 V VIN = 4.2 V 3.300 VIN = 3.6 V VIN = 4.2 V VOUT DC - V VOUT DC - V MODE/DATA = low, PFM Mode, voltage positioning active VIN = 5 V VIN = 5 V MODE/DATA = high, forced PWM Mode 1.818 VIN = 5 V V = 4.2 V V = 3.6 V IN IN V IN = 2.7 V 1.800 VIN = 2.7 V VIN = 3.6 V VIN = 4.2 V VIN = 5 V MODE/DATA = high, forced PWM Mode 1.782 3.250 1.764 3.200 0.01 0.10 1 10 IOUT - mA 100 1000 1.746 0.01 1 10 IOUT - mA Figure 9. 10 0.10 Figure 10. Submit Documentation Feedback 100 1000 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 DC OUTPUT ACCURACY VOUT1 = 1.575V, L = 2.2µH, COUT = 22µF DC OUTPUT ACCURACY VOUT1 = 1.575V, L = 3.3µH, COUT = 10µF 1.650 1.650 VOUT1 = 1.575 V VOUT1 = 1.575 V MODE/DATA = low, PFM Mode, voltage positioning active MODE/DATA = low, PFM Mode, voltage positioning active 1.625 1.625 VIN = 4.2 V PWM Mode Operation 1.600 VOUT DC - V VOUT DC - V VIN = 4.2 V VIN = 3.6 V VIN = 2.7 V 1.575 VIN = 2.7 V 1.550 VIN = 3.6 V VIN = 4.2 V MODE/DATA = high, forced PWM Mode PWM Mode Operation 1.600 VIN = 2.7 V VIN = 2.7 V 1.550 1.525 VIN = 3.6 V 1.575 VIN = 3.6 V VIN = 4.2 V MODE/DATA = high, forced PWM Mode 1.525 1.500 0.01 0.10 100 1 10 IOUT - mA 1.500 0.01 1000 0.10 100 1 10 IOUT - mA Figure 11. 1000 Figure 12. FOSC vs VIN Iq FOR ONE CONVERTER, NOT SWITCHING 24 2.5 2.45 23 2.4 85°C 22 2.3 Iddq - mA Fosc - MHz 2.35 -40°C 2.25 2.2 25°C 21 20 25°C -40°C 2.15 2.1 19 85°C 18 2.05 2 2.5 3 3.5 4 4.5 VIN - V 5 5.5 6 17 2.5 Figure 13. 3 3.5 4 4.5 VIN - V 5 5.5 6 Figure 14. Submit Documentation Feedback 11 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 Iq FOR BOTH CONVERTERS, NOT SWITCHING RDSON PMOS vs VIN 42 0.55 40 0.5 0.45 38 0.4 RDSon - W Iddq - mA 85°C 36 25°C 34 32 -40°C 85°C 0.35 25°C 0.3 0.25 30 -40°C 0.2 0.15 2.5 28 2.5 3 3.5 4 4.5 5 5.5 6 3 3.5 4 4.5 VIN - V Figure 16. RDSON NMOS vs VIN LIGHT LOAD OUTPUT VOLTAGE RIPPLE IN POWER SAVE MODE Power Save Mode Mode/Data = low IOUT = 10mA RDSon - W 0.25 VOUT = 1.8V 20mV/Div 85°C 25°C Inductor current 100mA/Div 0.15 -40°C 0.1 0.05 2.5 3 3.5 4 4.5 5 5.5 6 VIN - V Time base - 10 ms/Div Figure 17. 12 5.5 Figure 15. 0.3 0.2 5 VIN - V Figure 18. Submit Documentation Feedback 6 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 OUTPUT VOLTAGE RIPPLE IN FORCED PWM MODE OUTPUT VOLTAGE RIPPLE IN PWM MODE Mode/Data = high, forced PWM MODE operation PWM MODE OPERATION VOUT = 1.8V IOUT = 400mA IOUT = 10mA VOUT ripple 20mV/Div VOUT = 1.8V 20mV/Div Inductor current 100mA/Div Inductor current 200mA/Div Time base - 400 ns/Div Time base - 200 ns/Div Figure 19. Figure 20. FORCED PWM/PFM MODE TRANSITION LOAD TRANSIENT RESPONSE PFM/PWM Forced PWM Mode VOUT = 1.575V 50mV/Div MODE/DATA 1V/Div MODE/DATA = low Enable Power Save Mode Entering PFM Mode Voltage positioning active Voltage positioning in PFM Mode reduces voltage drop during load step VOUT 20mV/Div IOUT 200mA/Div PWM Mode operation IOUT1 = 360mA VOUT = 1.8V IOUT = 20mA IOUT= 40mA Time base - 200 ms/Div Time base - 50 ms/Div Figure 21. Figure 22. Submit Documentation Feedback 13 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 LOAD TRANSIENT RESPONSE PWM OPERATION MODE/DATA = high PWM Mode operation VOUT = 1.575V 50mV/Div LINE TRANSIENT RESPONSE VIN 3.6V to 4.6V VIN 1V/Div MODE/DATA = high VOUT 1.575 IOUT 200mA IOUT 200mA/Div IOUT1 = 360mA VOUT 50mV/Div IOUT= 40mA Time base - 50 ms/Div Time base - 400 ms/Div Figure 23. Figure 24. STARTUP TIMING ONE CONVERTER TPS62401DEF1_PIN FUNCTION FOR OUTPUT VOLTAGE SELECTION DEF_1 pin 2V/Div EN1 / EN2 5V/Div VIN = 3.6V, MODE/DAT = low IOUT1 = 40mA VIN = 3.8V IOUT1 max = 400mA VOUT1 = 1.575V VOUT1 500mV/Div VOUT1 500mV/Div VOUT1 = 1.1V SW1 1V/Div Icoil 500mA/Div Icoil 500mA/Div Time base - 100 ms/Div Time base - 200 ms/Div Figure 25. 14 Figure 26. Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.575V, VOUT2 = 1.8V TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 3.0V SW1 5V/Div SW1 5V/Div I coil1 200mA/Div I coil1 200mA/Div SW2 5V/Div SW2 5V/Div Icoil2 200mA/Div Icoil2 200mA/Div VIN 3.6V, VOUT1 : 1.8V VOUT2 : 3.0V I OUT1 = I OUT2 = 200mA VIN 3.6V, VOUT1: 1.575V VOUT2: 1.8V I OUT1 = IOUT2 = 200mA Time base - 100 ns/Div Time base - 100 ns/Div Figure 27. Figure 28. TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.2V, VOUT2 = 1.2V VOUT1 CHANGE WITH EASYSCALE SW1 5V/Div MODE/DATA 2V/Div I coil1 200mA/Div SW2 5V/Div VOUT1 : 200mV/Div I coil2 200mA/Div VIN 3.6V, VOUT1 : 1.2V VOUT2 : 1.2V I OUT1 = I OUT2 = 200mA VOUT1: 1.1V Time base - 100 ns/Div VOUT1 : 1.5V VIN 3.8V ACKN = off IOUT1 = 150mA REG_DEF_1_Low Time base - 100 ms/Div Figure 29. Figure 30. DETAILED DESCRIPTION OPERATION The TPS62400 includes two synchronous step-down converters. The converters operate with typically 2.25MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If Power Safe Mode is enabled, the converters automatically enter Power Save Mode at light load currents and operate in PFM (Pulse Frequency Modulation). During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. Submit Documentation Feedback 15 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 DETAILED DESCRIPTION (continued) Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit. The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and converter 2 decreases the input RMS current. Converter 1 In the adjustable output voltage version TPS62400 the converter 1 default output voltage can be set via an external resistor network on PIN DEF_1, which operates as an analog input. In this case, the output voltage can be set in the range of 0.6V to VIN V. The FB1 Pin must be directly connected to the converter 1 output voltage VOUT1. It feeds back the output voltage directly to the regulation loop. The output voltage of converter 1 can also be changed by the EasyScale™ serial Interface. This makes the device very flexible for output voltage adjustment. In this case, the device uses an internal resistor network. In the fixed default output voltage version TPS62401, the DEF_1 Pin is configured as a digital input. The converter 1 defaults to 1.1V or 1.575V depending on the level of DEF_1 pin. If DEF_1 is low the default is 1.575V; if high, the default is 1.1V. With the EasyScale™ interface, the output voltage for each DEF_1 Pin condition (high or low) can be changed. Converter 2 In the adjustable output voltage version TPS62400, the converter 2 output voltage is set by an external resistor divider connected to ADJ2 Pin and uses an external feed forward capacitor of 33pF. In fixed output voltage version TPS62401, the default output voltage is fixed to 1.8V. In this case, the ADJ2 pin must be connected directly to the converter 2 output voltage VOUT2. It is also possible to change the output voltage of converter 2 via the EasyScale™ Interface. In this case, the ADJ2 Pin must be directly connected to converter 2 output voltage VOUT2 and no external resistors may be connected. POWER SAVE MODE The Power Save Mode is enabled with Mode/Data Pin set to low for both converters. If the load current of a converter decreases, this converter will enter Power Save Mode operation automatically. The transition to Power Save Mode of a converter is independent from the operating condition of the other converter. During Power Save Mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage in PFM mode to typically 1.01×VOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step. In order to optimize the converter efficiency at light load the average inductor current is monitored. The device changes from PWM Mode to Power Save Mode, if in PWM mode the inductor current falls below a certain threshold. The typical output current threshold depends on VIN and can be calculated according to Equation 1 for each converter. Equation 1: Average output current threshold to enter PFM Mode VINDCDC I OUT_PFM_enter + 32 W Equation 2: Average output current threshold to leave PFM Mode 16 Submit Documentation Feedback (1) TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 DETAILED DESCRIPTION (continued) I OUT_PFM_leave + VINDCDC 24 W (2) In order to keep the output voltage ripple in Power Save Mode low, the output voltage is monitored with a single threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip comp) of 1.01 x VOUTnominal, the corresponding converter starts switching for a minimum time period of typ. 1µs and provides current to the load and the output capacitor. Therefore the output voltage will increase and the device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied by the output capacitor until the output voltage has dropped below the threshold again. Hereupon the device starts switching again. The Power Save Mode is left and PWM Mode entered in case the output current exceeds the current IOUT_PFM_leave or if the output voltage falls below a second comparator threshold, called skip comparator low (Skip Comp Low) threshold. This skip comparator low threshold is set to -2% below nominal Vout, and enables a fast transition from Power Save Mode to PWM Mode during a load step. In Power Save Mode the quiescent current is reduced typically to 19µA for one converter and 32µA for both converters active. This single skip comparator threshold method in Power Save Mode results in a very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing output capacitor values will minimize the output ripple. The Power Save Mode can be disabled through the MODE/DATA pin set to high. Both converters will then operate in fixed PWM mode. Power Save Mode Enable/Disable applies to both converters. Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is activated in Power Save Mode operation. It provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. This improves load transient behavior. At light loads, in which the converter operates in PFM Mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch. Smooth increased load +1% PFM Mode light load Fast load transient PFM Mode light load VOUT_NOM PWM Mode medium/heavy load PWM Mode medium/heavy load PWM Mode medium/heavy load COMP_LOW threshold -2% Figure 31. Dynamic Voltage Positioning Soft Start The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 32. Submit Documentation Feedback 17 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 DETAILED DESCRIPTION (continued) EN 95% 5% VOUT t Startup tRAMP Figure 32. Soft Start 100% Duty Cycle Low Dropout Operation The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: Vin min + Vout max ) Iout max ǒRDSonmax ) R LǓ (3) with: Ioutmax = maximum output current plus inductor ripple current RDSonmax = maximum P-channel switch RDSon. RL = DC resistance of the inductor Voutmax = nominal output voltage plus maximum output voltage tolerance With decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current, maintaining high efficiency. Under-Voltage Lockout The under-voltage lockout circuit prevents the device from malfunctioning at low input voltages, and from excessive discharge of the battery, and disables the converters. The under-voltage lockout threshold is typically 1.5V; maximum of 2.35V. In case the default register values are overwritten by the Interface, the new values in the registers REG_DEF_1_High, REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall below the under-voltage lockout threshold, independent of whether the converters are disabled. MODE SELECTION The MODE/DATA pin allows mode selection between forced PWM Mode and Power Save Mode for both converters. Furthermore, this pin is a multipurpose pin and provides (besides Mode selection) a one-pin interface to receive serial data from a host to set the output voltage. This is described in the EasyScale™ Interface section. Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters operates in fixed-frequency PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads, maintaining high efficiency over a wide load current range. 18 Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 DETAILED DESCRIPTION (continued) Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode, even at light load currents. The advantage is that the converters operate with a fixed frequency, allowing simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. For additional flexibility, it is possible to switch from power save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements. In case the operation mode is changed from forced PWM mode (MODE/DATA = high) to Power Save Mode Enable (MODE/DATA = 0), the Power Save Mode is enabled after a delay time of ttimeout , which is max. 520µs. The forced PWM Mode operation is enabled immediately with Pin MODE/DATA set to 1. ENABLE The device has a separate EN pin for each converter to start up each converter independently. If EN1 and EN2 are set to high, the corresponding converter starts up with soft start as previously described. Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2µA. In this mode, the P and N-Channel MOSFETs are turned-off and the entire internal control circuitry is switched-off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating. DEF_1 PIN FUNCTION The DEF_1 pin is dedicated to converter 1 and makes the output voltage selection very flexible to support dynamic voltage management. Depending on the device version, this pin works either as: 1. Analog input for adjustable output voltage setting (TPS62400): – Connecting an external resistor network to this pin adjusts the default output voltage to any value starting from 0.6V to VIN 2. Digital input for fixed default output voltage selection (TPS62401): – In case this pin is tied to low level, the output voltage is set according to the value in register REG_DEF_1_Low. The default voltage will be 1.575V. If tied to high level, the output voltage is set according to the value in register REG_DEF_1_High. The default value in this case is 1.1V. Depending on the level of Pin DEF_1, it selects between the two registers REG_DEF_1_Low and REG_DEF_1_High for output voltage setting. Each register content (and therefore output voltage) can be changed individually via the EasyScale™ interface. This makes the device very flexible in terms of output voltage setting; see Table 4. 180° OUT-OF-PHASE OPERATION In PWM Mode the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths the input current. This feature reduces the surge current drawn from the supply. SHORT-CIRCUIT PROTECTION Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the PMOS switch reaches its current limit, it is turned off and the NMOS switch is turned on. The PMOS only turns on again, once the current in the NMOS decreases below the NMOS current limit. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis. EasyScale™: One-Pin Serial Interface for Dynamic Output Voltage Adjustment General EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DC Submit Documentation Feedback 19 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 DETAILED DESCRIPTION (continued) converters. The interface is based on a master – slave structure, where the master is typically a microcontroller or application processor. Figure 33 and Table 3. give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte consists of five bits for information, two address bits, and the RFA bit. RFA bit set to high indicates the Request For Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale™ compared to other one pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires no additional pin. Protocol All bits are transmitted MSB first and LSB last. Figure 34 shows the protocol without acknowledge request (bit RFA = 0), Figure 35 with acknowledge (bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the Mode/Data pin need be pulled high for at least tStart before the bit transmission starts with the falling edge. In case the Mode/Data line was already at high level (forced PWM Mode selection), no start condition need be applied prior the device address byte. The transmission of each byte needs to be closed with an End Of Stream condition for at least TEOS. Addressable Registers Three registers with a data content of 5 bits can be addressed. With 5 bit data content, 32 different values for each register are available. Table 1 shows the addressable registers to set the output voltage when DEF_1 pin works as digital input. In this case, converter 1 has a related register for each DEF_1 Pin condition, and one register for converter 2. With a high/low condition on pin DEF_1 (TPS62401) either the content of register REG_DEF_1_high/REG_DEF1_low is selected. The output voltage of converter 1 is set according to the values in Table 4. Table 2 shows the addressable registers if DEF_1 pin acts as analog input with external resistors connected. In this case one register is available for each converter. The output voltage of converter 1 is set according to the values in Table 5. For converter 2, the available voltages are shown in Table 6. To generate these output voltages a precise internal resistor divider network is used, making external resistors unnecessary (less board space), and provides higher output voltage accuracy. The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is high). After the startup-time tStart (170µs) the interface is ready for data reception. Table 1. Addressable Registers for default Fixed Output Voltage Options (PIN DEF_1 = digital input) DEVICE REGISTER DESCRIPTION TPS62401 REG_DEF_1_High Converter 1 output voltage setting for , DEF_1 = High condition. The content of TPS62402 the register is active with DEF1_ Pin high. , REG_DEF_1_Low Converter 1 output voltage setting for TPS62403 DEF_1 = Low condition. REG_DEF_2 Converter 2 output voltage DEF_1 PIN A1 A0 High 0 1 Output voltage setting, see Table 4 Low 0 0 Output voltage setting, see Table 4 Not applicable 1 0 Output voltage setting, see Table 6 1 1 Don’t use D4 D3 D2 D1 D0 Table 2. Addressable Registers for Adjustable Output Voltage Options (PIN DEF_1 = analog input) DEVICE REGISTER TPS62400 REG_DEF_1_High not available REG_DEF_1_Low REG_DEF_2 20 DESCRIPTION A1 A0 Converter 1 output voltage setting 0 0 see Table 5 Converter 2 output voltage 1 0 see Table 6 Don’t’ use 1 1 Submit Documentation Feedback D4 D3 D2 D1 D0 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 Bit Decoding The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can be simplified to: High Bit: tHigh > tLow, but with tHigh at least 2x tLow, see Figure 34 Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 34 The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge. Depending on the relation between tLow and tHigh a 0 or 1 is detected. Acknowledge The Acknowledge condition is only applied if: • Acknowledge is requested by a set RFA bit • The transmitted device address matches with the device address of the device • 16 bits were received correctly In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time tACKN, which is 520µs maximum . The Acknowledge condition is valid after an internal delay time tvalACK. This means the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master controller keeps the line low during this time. The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after tvalACK and read back a 0. In case of an invalid device address, or not-correctly-received protocol, no-acknowledge condition is applied; thus, the internal MOSFET is not turned on and the external pullup resistor pulls MODE/DATA pin high after tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends. NOTE: The acknowledge condition may only be requested in case the master device has an open drain output. In case of a push-pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit the current to 500 µA in case of an accidentally requested acknowledge, to protect the internal ACKN-MOSFET. MODE Selection Because the MODE/DATA pin is used for two functions, interface and a MODE selection, the device needs to determine when it has to decode the bit stream or to change the operation mode. The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level. The device also stays in forced PWM mode during the entire protocol reception time. With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at least ttimeout, the device gets an internal timeout and Power Save Mode operation is enabled. A protocol sent within this time is ignored because the falling edge for the Mode change is first interpreted as start of the first bit. In this case it is recommended to send the protocol first, and then change at the end of the protocol to Power Save Mode. DATA IN Start Start Device Address DA7 DA6 DA5 DA4 0 1 0 0 DATABYTE DA3 DA2 DA1 1 1 1 DA0 EOS Start RFA 0 A1 A0 D4 D3 D2 D1 D0 EOS DATA OUT ACK Figure 33. EasyScale™ Protocol Overview Submit Documentation Feedback 21 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 Table 3. EasyScale™ Bit Description BYTE BIT NUMBER NAME TRANSMISSION DIRECTION Device Address Byte 7 DA7 IN 0 MSB device address 6 DA6 IN 1 5 DA5 IN 0 4 DA4 IN 0 3 DA3 IN 1 2 DA2 IN 1 1 DA1 IN 1 0 DA0 IN 0 LSB device address 7(MSB) RFA IN Request For Acknowledge, if high, Acknowledge condition will applied by the device 6 A1 Address Bit 1 5 A0 Address Bit 0 4 D4 Data Bit 4 3 D3 Data Bit 3 2 D2 Data Bit 2 1 D1 Data Bit 1 0(LSB) D0 Data Bit 0 4Ehex Databyte ACK OUT DESCRIPTION Acknowledge condition active 0, this condition will only be applied in case RFA bit is set. Open drain output, Line needs to be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open drain output stage. In case of a push pull output stage Acknowledge condition may not be requested! tStart DATA IN tStart Address Byte DATA Byte Mode, Static High or Low Mode, Static High or Low DA7 0 DA0 0 RFA 0 TEOS D0 1 TEOS Figure 34. EasyScale™ Protocol Without Acknowledge tStart DATA IN DATA Byte Mode, Static High or Low Mode, Static High or Low DA7 0 DATA OUT tStart Address Byte DA0 0 T EOS RFA 1 D0 1 tvalACK Controller needs to Pullup Data Line via a resistor to detect ACKN Figure 35. EasyScale™ Protocol Including Acknowledge 22 Submit Documentation Feedback ACKN tACKN Acknowledge true, Data Line pulled down by device Acknowledge false, no pull down TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 t Low tHigh t Low t High Low Bit High Bit (Logic 0) (Logic 1) Figure 36. EasyScale™– Bit Coding MODE/DATA ttimeout Power Save Mode Forced PWM MODE Power Save Mode Figure 37. MODE/DATA PIN: Mode Selection tStart Address Byte tStart DATA Byte MODE/DATA TEOS TEOS t timeout Power Save Mode Forced PWM MODE Power Save Mode Figure 38. MODE/DATA Pin: Power Save Mode/Interface Communication Submit Documentation Feedback 23 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 Table 4. Selectable Output Voltages for Converter 1, With Pin DEF_1 as Digital Input (TPS62401) TPS62401 OUTPUT VOLTAGE [V] REGISTER REG_DEF_1_LOW 24 TPS62401 OUTPUT VOLTAGE [V] REGISTER REG_DEF_1_HIGH D4 D3 D2 D1 D0 0 0.8 0.9 0 0 0 0 0 1 0.825 0.925 0 0 0 0 1 2 0.85 0.95 0 0 0 1 0 3 0.875 0.975 0 0 0 1 1 4 0.9 1.0 0 0 1 0 0 5 0.925 1.025 0 0 1 0 1 6 0.95 1.050 0 0 1 1 0 7 0.975 1.075 0 0 1 1 1 8 1.0 1.1(default TPS62401, TPS62403) 0 1 0 0 0 9 1.025 1.125 0 1 0 0 1 10 1.050 1.150 0 1 0 1 0 11 1.075 1.175 0 1 0 1 1 12 1.1 1.2 0 1 1 0 0 13 1.125 1.225 0 1 1 0 1 14 1.150 1.25 0 1 1 1 0 15 1.175 1.275 0 1 1 1 1 16 1.2 1.3 1 0 0 0 0 17 1.225 1.325 1 0 0 0 1 18 1.25 1.350 1 0 0 1 0 19 1.275 1.375 1 0 0 1 1 20 1.3 1.4 1 0 1 0 0 21 1.325 1.425 1 0 1 0 1 22 1.350 1.450 1 0 1 1 0 23 1.375 1.475 1 0 1 1 1 24 1.4 1.5 1 1 0 0 0 25 1.425 1.525 1 1 0 0 1 26 1.450 1.55 1 1 0 1 0 27 1.475 1.575 1 1 0 1 1 28 1.5 1.6 1 1 1 0 0 29 1.525 1.7 1 1 1 0 1 30 1.55 1.8 1 1 1 1 0 31 1.575 (default TPS62401, TPS62403) 1.9 1 1 1 1 1 Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 Table 5. Selectable Output Voltages for Converter 1, With DEF1 Pin as Analog Input (Adjustable, TPS62400) 0 TPS62400 OUTPUT VOLTAGE [V] REGISTER REG_DEF_1_LOW D4 D3 D2 D1 D0 VOUT1 Adjustable with Resistor Network on DEF_1 Pin (default TPS62400) 0 0 0 0 0 0.6V with DEF_1 connected to VOUT1 (default TPS62400) 1 0.825 0 0 0 0 1 2 0.85 0 0 0 1 0 3 0.875 0 0 0 1 1 4 0.9 0 0 1 0 0 5 0.925 0 0 1 0 1 6 0.95 0 0 1 1 0 7 0.975 0 0 1 1 1 8 1.0 0 1 0 0 0 9 1.025 0 1 0 0 1 10 1.050 0 1 0 1 0 11 1.075 0 1 0 1 1 12 1.1 0 1 1 0 0 13 1.125 0 1 1 0 1 14 1.150 0 1 1 1 0 15 1.175 0 1 1 1 1 16 1.2 1 0 0 0 0 17 1.225 1 0 0 0 1 18 1.25 1 0 0 1 0 19 1.275 1 0 0 1 1 20 1.3 1 0 1 0 0 21 1.325 1 0 1 0 1 22 1.350 1 0 1 1 0 23 1.375 1 0 1 1 1 24 1.4 1 1 0 0 0 25 1.425 1 1 0 0 1 26 1.450 1 1 0 1 0 27 1.475 1 1 0 1 1 28 1.5 1 1 1 0 0 29 1.525 1 1 1 0 1 30 1.55 1 1 1 1 0 31 1.575 1 1 1 1 1 Submit Documentation Feedback 25 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 Table 6. Selectable Output Voltages for Converter 2, (ADJ2 Connected to VOUT) 0 OUTPUT VOLTAGE [V] FOR REGISTER REG_DEF_2 D4 D3 D2 D1 D0 VOUT2 Adjustable with resistor network and Cff on ADJ2 pin (default TPS62400) 0 0 0 0 0 0.6V with ADJ2 pin directly connected to VOUT2 (default TPS62400) 26 1 0.85 0 0 0 0 1 2 0.9 0 0 0 1 0 3 0.95 0 0 0 1 1 4 1.0 0 0 1 0 0 5 1.05 0 0 1 0 1 6 1.1 0 0 1 1 0 7 1.15 0 0 1 1 1 8 1.2 0 1 0 0 0 9 1.25 0 1 0 0 1 10 1.3 0 1 0 1 0 11 1.35 0 1 0 1 1 12 1.4 0 1 1 0 0 13 1.45 0 1 1 0 1 14 1.5 0 1 1 1 0 15 1.55 0 1 1 1 1 16 1.6 1 0 0 0 0 17 1.7 1 0 0 0 1 18 1.8 (default TPS62401) 1 0 0 1 0 19 1.85 1 0 0 1 1 20 2.0 1 0 1 0 0 21 2.1 1 0 1 0 1 22 2.2 1 0 1 1 0 23 2.3 1 0 1 1 1 24 2.4 1 1 0 0 0 25 2.5 1 1 0 0 1 26 2.6 1 1 0 1 0 27 2.7 1 1 0 1 1 28 2.8 (default TPS62403) 1 1 1 0 0 29 2.85 1 1 1 0 1 30 3.0 1 1 1 1 0 31 3.3 1 1 1 1 1 Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION OUTPUT VOLTAGE SETTING Converter1 Adjustable Default Output Voltage Setting: TPS62400 The output voltage can be calculated to: V OUT + VREF ǒ R 1 ) 11 R 12 Ǔ with an internal reference voltage VREF typical 0.6V (4) To keep the operating current to a minimum, it is recommended to select R12 within a range of 180kΩ to 360kΩ. The sum of R12 and R11 should not exceed ~1MΩ. For higher output voltages than 3.3V, it is recommended to choose lower values than 180kΩ for R12. Route the DEF_1 line away from noise sources, such as the inductor or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. A feedforward capacitor is not necessary. Converter1 Fixed Default Output Voltage Setting (TPS62401, TPS62403). The output voltage is selected with DEF_1 pin. A high level sets the output voltage to 1.1V, low level to 1.575V. Converter 2 Adjustable Default Output Voltage Setting TPS62400: The output voltage of converter 2 can be set by an external resistor network. For converter 2 the same recommendations apply as for converter1. In addition to that, a 33pF feedforward Capacitor Cff2 for good load transient response should be used. The output voltage can be calculated to: V OUT + VREF ǒ R 1 ) 21 R 22 Ǔ with an internal reference voltage VREF typical 0.6V (5) Converter 2 Fixed Default Output Voltage Setting ADJ2 pin must be directly connected with VOUT2 TPS62401, VOUT2 default = 1.8V TPS62403, VOUT2 default = 2.8V TPS62400 VIN 3.3 V – 6 V VIN FB 1 SW1 CIN 10 mF L1 2.2 mH VOUT1 = 1.5 V R11 270 kW DEF_1 R12 180 kW IOUT1 up to 400 mA COUT1 22 mF EN_1 EN_2 L2 VOUT2 = 2.85 V SW2 3.3 mH MODE/ DATA C ff2 R21 825 kW 33 pF ADJ2 R22 220 kW IOUT2 up to 600 mA COUT2 22 mF GND Figure 39. Typical Application Circuit 1.5V/2.85V Adjustable Outputs, low PFM Voltage Ripple Optimized Submit Documentation Feedback 27 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) TPS62400 VIN 3.3 V – 6 V FB 1 VIN L1 CIN SW1 10 mF 2.2 mH VOUT1 = 1.5 V IOUT1 up to 400 mA R11 270 kW COUT1 10 mF DEF_1 R12 180 kW EN_1 EN_2 L2 3.3 mH MODE/ DATA VOUT2 = 2.85 SW2 ADJ2 C ff2 R21 825 kW 33 pF IOUT2 up to 600 mA COUT2 10 mF R22 220 kW GND Figure 40. Typical Application Circuit 1.5V/2.85V Adjustable Outputs TPS62401 VIN 2.5 V – 6 V VIN FB 1 2.2 mH SW1 10 mF VOUT1 = 1.575 V 400 mA 22 mF DEF_1 EN_1 EN_2 2.2 mH SW2 MODE/ DATA VOUT2 = 1.8 V 600 mA 22 mF ADJ2 GND Figure 41. TPS62401 Fixed 1.575V/1.8V Outputs, low PFM Voltage Ripple Optimized 28 Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) TPS62401 VIN 2.5 V – 6 V FB 1 VIN 2.2 mH 10 mF VOUT1 = 1.1 V 400 mA SW1 DEF_1 22 mF EN_1 EN_2 2.2 mH SW2 MODE/ DATA VOUT2 = 1.8 V 600 mA 22 mF ADJ2 GND Figure 42. TPS62401 Fixed 1.1V/1.8V Outputs, low PFM Ripple Voltage Optimized TPS62401 VIN 2.5 V – 6 V VIN FB 1 2.2 mH SW1 10 mF VOUT1 = 1.575 V 400 mA 10 mF DEF_1 EN_1 EN_2 2.2 mH SW2 MODE/ DATA VOUT2 = 1.8 V 600 mA 10 mF ADJ2 GND Figure 43. TPS62401 Fixed 1.575V/1.8V Outputs Submit Documentation Feedback 29 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) TPS62401/03 VIN 2.5 V – 6 V VIN Processor FB 1 L1 Vout 1 400 mA: DEF _1 = 0: 1.575 V DEF _1 = 1: 1.1 V 10 µF SW 1 10 µF EN_1 DEF _1 V Core_Sel L2 EN_2 SW 2 MODE / DATA ADJ 2 V Core Vout 2 600 mA: TPS 62401 : 1.8 V TPS 62403 : 2.8 V V I/O 10 µF GND Figure 44. Dynamic Voltage Scaling on Vout1 Controlled by DEF_1 pin TPS62403 VIN 2.5 V – 6 V VIN FB 1 2.2 µH Vout 1 : 1.575 V 400 mA SW 1 10 m F 10 µF DEF _1 EN _1 3.3 µH EN _2 SW 2 MODE/ DATA ADJ 2 Vout 2: 2.8 V 600 mA 10 µF GND Figure 45. TPS62403 1.575V/2.8V Outputs OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) The converters are designed to operate with a minimum inductance of 1.75µH and minimum capacitance of 6µF. The device is optimized to operate with inductors of 2.2µH to 4.7µH and output capacitors of 10µF to 22µF. Inductor selection The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductor will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency. Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is recommended because during heavy load transient the inductor current rises above the calculated value. 30 Submit Documentation Feedback TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) DI L + Vout 1 * Vout Vin ƒ L I Lmax + I outmax ) (6) DI L 2 (7) with: f = Switching Frequency (2.25MHz typical) L = Inductor Value ∆IL = Peak-to-Peak inductor ripple current ILmax = Maximum Inductor current The highest inductor current occurs at maximum Vin. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Take into consideration that the core material from inductor to inductor differs and this difference has an impact on the efficiency. Refer to Table 7 and the typical application circuit examples for possible inductors. Table 7. List of Inductors DIMENSIONS [mm3] INDUCTOR TYPE SUPPLIER 3.2×2.6×1.0 MIPW3226 FDK 3×3×0.9 LPS3010 Coilcraft 2.8×2.6×1.0 VLF3010 TDK 2.8x2.6×1.4 VLF3014 TDK 3×3×1.4 LPS3015 Coilcraft 3.9×3.9×1.7 LPS4018 Coilcraft Output Capacitor Selection The advanced fast response voltage mode control scheme of the converters allows the use of tiny ceramic capacitors with a typical value of 10µF to 22µF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors with low ESR values results in lowest output voltage ripple, and are therefore recommended. The output capacitor requires either X7R or X5R dielectric. Y5V and Z5U dielectric capacitors are not recommended due to their wide variation in capacitance. If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. The RMS ripple current is calculated as: 1 * Vout 1 Vin I RMSCout + Vout ƒ L 2 Ǹ3 (8) At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging and discharging the output capacitor: DVout + Vout 1 * Vout Vin L ƒ ǒ8 1 Cout ƒ Ǔ ) ESR (9) Where the highest output voltage ripple occurs at the highest input voltage Vin. Submit Documentation Feedback 31 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. Higher output capacitors like 22µF values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM Mode. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interference with other circuits in the system. An input capacitor of 10µF is sufficient. LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low-inductance, impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold in Figure 46. The input capacitor should be placed as close as possible to the IC pins VIN and GND, the inductor and output capacitor as close as possible to the pins SW1 and GND. Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For each converter use a common Power GND node and a different node for the signal GND to minimize the effects of ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common path to the GND PIN, which returns the small signal components and the high current of the output capacitors, as short as possible to avoid ground noise. The output voltage sense lines (FB 1, DEF_1, ADJ2) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW1 and SW2 lines). If the EasyScale™ interface is operated with high transmission rates, the MODE/DATA trace must be routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling. TPS62400 VIN 3 V – 6 V VIN EN_1 CIN EN_2 10 mF MODE/ DATA FB 1 L2 SW2 COUT2 Cff2 33 pF SW1 3.3 mH R21 3.3 mH R11 ADJ2 DEF_1 R22 R12 PowerPAD GND Figure 46. Layout Diagram 32 L1 Submit Documentation Feedback COUT1 TPS62400,, TPS62401 TPS62403 www.ti.com SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 COUT1 CIN GND Pin connected with Power Pad COUT2 Figure 47. PCB Layout Submit Documentation Feedback 33 PACKAGE OPTION ADDENDUM www.ti.com 12-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS62400DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62400DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62400DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62400DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62401DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62401DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62401DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62401DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62403DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62403DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62403DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Dec-2006 to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated