TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 1-A Step-Down Converter in 2-mm × 2-mm QFN Package Check for Samples: TPS62590-Q1 FEATURES DESCRIPTION • • • • • • • The TPS62590-Q1 device is a high-efficiency synchronous step-down converter, optimized for battery-powered portable applications. It provides up to 1000-mA output current from batteries, such as single Li-Ion or other common-chemistry AA and AAA cells. 1 • Qualified for Automotive Applications Output Current up to 1000 mA Input Voltage Range from 2.5 V to 6 V Output Voltage Accuracy in PWM mode ±2.5% Typ. 15-μA Quiescent Current 100% Duty Cycle for Lowest Dropout Available in a 2-mm × 2-mm × 0,8-mm QFN Package For Improved Features Set, See TPS62290 With an input voltage range of 2.5 V to 6 V, the device is targeted to power a large variety of portable handheld equipment or POL applications. The TPS62590-Q1 family operates at a 2.25-MHz fixed switching frequency and enters a power-save mode at light load currents to maintain a high efficiency over the entire load current range. The power-save mode is optimized for low outputvoltage ripple. For low-noise applications, the device can be forced into fixed-frequency PWM mode by pulling the MODE pin high. In the shutdown mode, the current consumption is reduced to less than 1 µA. The TPS62590-Q1 allows the use of small inductors and capacitors to achieve a small solution size. The TPS62590-Q1 is available in a 2-mm × 2-mm 6pin QFN package. Empty para 2.5 V to 5.5 V 4 CIN 10mF 2 VIN SW 1 EN FB 3 GND 6 100 L 2.2 mH R1 C1 COUT R2 10mF VI = 5 V 80 0.75 V to VIN 22pF MODE PwrPAD 90 VOUT Efficiency - % TPS62590DRV 5 VI N VI = 4.2 V 70 60 VI = 3.8 V 50 40 30 VOUT = 3.3 V, MODE = GND, 20 10 Typical Application 0 0.0001 0.001 0.01 0.1 IO - Output Current - A 1 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (1) TA PACKAGE –40°C to 105°C (1) (2) QFN 2-mm × 2-mm (2) Reel of 3000 ORDERABLE PART NUMBER TOP-SIDE MARKING TPS62590TDRVRQ1 QWT The DRV (2-mm × 2-mm 6-terminal QFN) packages are available in tape on reel. For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Input voltage range (2) VI Voltage range at EN, MODE Voltage on SW Peak output current VALUE UNIT –0.3 to 7 V –0.3 to VIN +0.3, ≤ 7 V –0.3 to 7 V Internally limited A TJ Maximum operating junction temperature –40 to 125 °C Tstg Storage temperature range –65 to 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL INFORMATION TPS62590-Q1 THERMAL METRIC (1) DRV UNIT 6 PINS θJA Junction-to-ambient thermal resistance (2) 101.4 °C/W θJCtop Junction-to-case (top) thermal resistance (3) 80.9 °C/W θJB Junction-to-board thermal resistance (4) 71.3 °C/W (5) ψJT Junction-to-top characterization parameter 2.3 °C/W ψJB Junction-to-board characterization parameter (6) 71.6 °C/W θJCbot Junction-to-case (bottom) thermal resistance (7) 43.8 °C/W (1) (2) (3) (4) (5) (6) (7) 2 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 RECOMMENDED OPERATING CONDITIONS MIN VIN Supply voltage NOM MAX UNIT 2.5 6 Output voltage range for adjustable voltage 0.75 VIN V TA Operating ambient temperature –40 105 °C TJ Operating junction temperature –40 125 °C Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 V 3 TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6 V. External components CIN = 10 μF 0603, COUT = 10 μF 0603, L = 2.2 μH; see parameter measurement information. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VI Input voltage range IO Output current (1) IQ Operating quiescent current ISD Shutdown current UVLO Undervoltage lockout threshold 2.5 6 VIN 2.7 V to 6 V 1000 VIN 2.5 V to 2.7 V 600 V mA IO = 0 mA, PFM mode enabled (MODE = GND) device not switching, See (2) 15 μA IO = 0 mA, switching with no load (MODE = VIN) PWM mode, VO = 1.8 V, VIN = 3 V 3.8 mA 0.5 μA EN = GND Falling 1.85 Rising 1.95 V ENABLE, MODE VIH High-level input voltage, EN, MODE 2.5 V ≤ VIN ≤ 6 V 1 VIN VIL Low-level input voltage, EN, MODE 2.5 V ≤ VIN ≤ 6 V 0 0.4 II Input bias current, EN, MODE EN, MODE = GND or VIN 0.01 1 V V μA POWER SWITCH High-side MOSFET on-resistance rDS(on) Low-side MOSFET on-resistance ILIMF TSD 250 VIN = VGS = 3.6 V, TA = 25°C mΩ 190 Forward current limit MOSFET high-side and low-side VIN = VGS = 3.6 V, TA = 25°C Thermal shutdown Increasing junction temperature 140 Thermal shutdown hysteresis Decreasing junction temperature 20 1.19 1.4 1.78 A °C OSCILLATOR fSW Oscillator frequency 2.5 V ≤ VIN ≤ 6 V 2.25 MHz OUTPUT VO Adjustable output voltage range Vref Reference voltage 0.75 VI 600 VFB(PWM) Feedback voltage MODE = VIN, PWM mode, 2.5 V ≤ VIN ≤ 6 V, See (3) VFB(PFM) Feedback voltage, PFM mode MODE = GND, device in PFM mode, 1% voltage positioning active, See (2) Load regulation –2.5% 0% Start-up time tRamp VO ramp-up time Time to ramp from 5% to 95% of VO 250 Leakage current into SW pin VI = 3.6 V, VI = VO = VSW, EN = GND, See (4) 0.1 4 2.5% –1 tStart Up (1) (2) (3) (4) mV 1% Time from active EN to reach 95% of VO Ilkg V 500 %/A μs μs 1 μA Not production tested. In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref . See the parameter measurement information. For VIN = VO + 1 V In fixed output-voltage versions, the internal resistor divider network is disconnected from the FB pin. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 PIN ASSIGNMENTS DRV PACKAGE (TOP VIEW) SW MODE FB 1 2 3 D 6 PA 5 r we 4 Po GND VIN EN TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION VIN 5 PWR VIN power supply pin GND 6 PWR GND supply pin EN 4 I SW 1 OUT This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor between this terminal and the output capacitor. FB 3 I Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of fixed output-voltage option, connect this pin directly to the output capacitor. MODE 2 I MODE pin = high forces the device to operate in fixed-frequency PWM mode. Mode pin = low enables the power-save mode with automatic transition from PFM mode to fixed-frequency PWM mode. Thermal pad This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling this pin to high enables the device. This pin must be terminated. Must be soldered to achieve appropriate power dissipation. Should be connected to GND. FUNCTIONAL BLOCK DIAGRAM VIN EN Thermal Shutdown Current Limit Comparator Softstart VOUT RAMP CONTROL VIN High Side Reference 0.6 V VREF PFM Comp FB VREF MODE Undervoltage Lockout 1.8 V MODE Error Amp Control Stage Gate Driver Anti Shoot-Through SW VREF Integrator FB Zero-Pole AMP. PWM Comp . GND Low Side Sawtooth Generator 2.25 MHz Oscillator Current Limit Comparator Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 GND 5 TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION L 2.2 mH TPS62590DRV VIN VIN VOUT SW EN CIN 10mF R1 FB MODE C1 22pF COUT GND 10mF R2 PwPd Table 2. List of Components: COMPONENT REFERENCE PART NUMBER MANUFACTURER VALUE CIN GRM188R60J106M Murata 10-μF, 6.3-V. X5R ceramic COUT GRM188R60J106M Murata 10-μF, 6.3-V. X5R ceramic Murata 22-pF, ceramic Coilcraft 2.2 μH, 110mΩ C1 L1 LPS3015 R1, R2 Values depending on the programmed output voltage Spacer TYPICAL CHARACTERISTICS Table 3. Table Of Graphs FIGURE Efficiency Output Voltage Transient Behavior vs Output Current VOUT = 1.8 V (Power-Save Mode) Figure 1 vs Output Current VOUT = 1.8 V (Forced PWM Mode) Figure 2 vs Output Current VOUT = 3.3 V (Power-Save Mode) Figure 3 vs Output Current VOUT = 3.3 V (Forced PWM Mode) Figure 4 vs Output Current VOUT = 1.8 V (Forced PWM Mode) Figure 5 vs Output Current VOUT = 1.8 V (Power-Save Mode) Figure 6 vs Output Current VOUT = 3.3 V (Forced PWM Mode) Figure 7 vs Output Current VOUT = 3.3 V (Power-Save Mode) Figure 8 PFM Load Transient Figure 9 PFM Line Transient Figure 10 PWM Load Transient Figure 11 PWM Line Transient Figure 12 Typical Performance – PFM Mode Figure 13 Typical Performance – PWM Mode Figure 14 Shutdown Current into VIN vs. Input Voltage Figure 15 Quiescent Current vs Input Voltage Figure 16 Static Drain-Source On-State Resistance vs Input Voltage 6 Submit Documentation Feedback Figure 17 Figure 18 Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 VI = 2.7 V 90 90 VI = 3.6 V 80 60 80 VI = 3.3 V VI = 4.5 V 70 Efficiency - % Efficiency - % 70 VI = 5 V 50 40 30 10 0 0.0001 0.001 0.01 IO - Output Current - A 0.1 0 0.001 1 0.01 0.1 IO - Output Current - A Figure 1. Figure 2. EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 1 100 VI = 4.2 V 90 VI = 5 V 80 80 VI = 4.2 V 60 50 40 30 20 10 0.01 IO - Output Current - A 0.1 VI = 5 V 60 VI = 4.5 V 50 40 VOUT = 3.3 V, MODE = VIN, L = 2.2 mH 30 VOUT = 3.3 V, MODE = GND, L = 2.2 mH 0.001 VI = 3.8 V 70 VI = 3.8 V Efficiency - % Efficiency - % VOUT = 1.8 V, MODE = VIN, L = 2.2 mH 10 90 0 0.0001 VI = 4.5 V 40 20 100 70 VI = 5 V 50 30 VOUT = 1.8 V, MODE = GND, L = 2.2 mH 20 VI = 2.7 V 60 20 10 1 0 0.001 Figure 3. 0.01 0.1 IO - Output Current - A 1 Figure 4. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 7 TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 1.9 1.85 VO = 1.8 V, MODE = GND VO = 1.8 V, MODE = VI 1.88 VO - Output Voltage - V VO - Output Voltage - V 1.83 VI = 2.7 V, TA = 25°C 1.81 1.79 VI = 4.5 V, TA = 25°C VI = 3.6 V, TA = 25°C 1.77 1.86 PWM Mode PFM Mode, Voltage Positioning On 1.84 1.82 VI = 4.5 V, TA = 25°C VI = 3.6 V, TA = 25°C 1.8 VI = 2.7 V, TA = 25°C 1.75 0.00001 0.0001 0.001 0.01 IO - Output Current - A 0.1 1.78 0.00001 1 Figure 6. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 0.1 1 3.4 VO = 3.3 V, MODE = GND VO = 3.3 V, MODE = VI VI = 4.5 V, TA = 25°C 3.36 VO - Output Voltage - V 3.33 VI = 4.5 V, TA = 25°C 3.31 VI = 4.2 V, TA = 25°C VI = 3.7 V, TA = 25°C 3.29 VI = 5 V, TA = 25°C 3.25 0.00001 VI = 4.2 V, TA = 25°C 3.32 PFM Mode, Voltage Positioning On PWM Mode 3.28 3.24 3.27 0.0001 0.001 0.01 IO - Output Current - A 0.1 1 3.2 0.00001 Figure 7. 8 0.001 0.01 IO - Output Current - A Figure 5. 3.35 VO - Output Voltage - V 0.0001 0.0001 0.001 0.01 IO - Output Current - A 0.1 1 Figure 8. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 PFM LOAD TRANSIENT PFM LINE TRANSIENT VIN 3.6 V, VOUT 1.8 V, IOUT 300 mA to 800 mA, MODE = GND VOUT 100 mV/Div SW 2V/Div VOUT 50 mV/Div VIN 3.6 V, VOUT 1.8 V, IOUT 50 mA to 250 mA, 250 mA MODE = GND IOUT 500 mA/Div 800 mA 300 mA IOUT 200 mA/Div 50 mA Icoil 500 mA/Div Icoil 500 mA/Div Time Base - 20 ms/Div Time Base - 20 ms/Div Figure 9. Figure 10. PWM LOAD TRANSIENT PWM LINE TRANSIENT VIN 3.6 V to 4.2 V 500 mV/Div VIN 3.6 V to 4.2 V, 500 mV/Div VOUT = 1.8 V, 50 mV/Div, IOUT = 50 mA, MODE = GND VOUT = 1.8 V, 50 mV/Div, IOUT = 250 mA, MODE = GND Time Base - 100 ms/Div Time Base - 100 ms/Div Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 9 TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com TYPICAL PERFORMANCE – PFM MODE TYPICAL PERFORMANCE – PWM MODE VIN 3.6 V, VOUT 1.8 V, IOUT 150 mA, VOUT 20 mV/Div VOUT 10 mV/Div L 2.2 mH, COUT 10 mF 0603 VIN 3.6 V, VOUT 1.8 V, IOUT 10 mA, SW 2 V/Div L 2.2 mH, COUT 10 mF 0603 SW 2 V/Div Icoil 200 mA/Div Icoil 200 mA/Div Time Base - 10 ms/Div Time Base - 10 ms/Div Figure 13. Figure 14. SHUTDOWN CURRENT INTO VIN vs INPUT VOLTAGE QUIESCENT CURRENT vs INPUT VOLTAGE 0.8 20 0.7 18 0.6 IQ – Quiescent Current – mA ISD - Shutdown Current Into VIN − mA EN = GND o TA = 85 C 0.5 0.4 0.3 0.2 o TA = -40oC TA = 25 C MODE = GND, EN = VIN, Device Not Switching 16 o TA = 25 C 14 12 o TA = -40 C 10 0.1 0 2.5 3 3.5 4 4.5 5 5.5 8 2.5 VIN − Input Voltage − V 3 3.5 4 4.5 5 5.5 VIN − Input Voltage − V Figure 15. 10 o TA = 85 C Figure 16. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 0.8 High Side Switching 0.7 0.6 o TA = 85 C 0.5 o TA = 25 C 0.4 0.3 0.2 0.1 0 2.5 o TA = -40 C 3 3.5 4 VIN − Input Voltage − V 4.5 5 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE RDS(on) - Static Drain-Source On-State Resistance − W RDS(on) - Static Drain-Source On-State Resistance − W STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 0.4 Low Side Switching 0.35 0.3 o TA = 85 C 0.25 o TA = 25 C 0.2 0.15 0.1 o 0.05 TA = -40 C 0 2.5 Figure 17. 3 3.5 4 4.5 5 VIN − Input Voltage − V Figure 18. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 11 TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com DETAILED DESCRIPTION OPERATION The TPS62590-Q1 step-down converter operates with typically 2.25-MHz fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. At light load currents, the converter can automatically enter powersave mode and operates then in PFM mode. During PWM mode, the converter uses a unique fast-response voltage-mode controller scheme with inputvoltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is turned on. The current flows now from the input capacitor via the high-side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic turns off the switch. The current-limit comparator also turns off the switch if the current limit of the high-side MOSFET switch is exceeded. After a dead time preventing shoot-through current, the low-side MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the inductor to the output capacitor and to the load. It returns to the inductor through the low-side MOSFET rectifier. The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the high-side MOSFET switch. POWER-SAVE MODE The power-save mode is enabled with the MODE pin set to low level. If the load current decreases, the converter enters power-save mode automatically. During power-save mode, the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage 1% above the nominal output voltage typically. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the low-side MOSFET switch becomes zero, which indicates discontinuous-conduction mode. During the power-save mode, the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT nominal + 1%, the device starts a PFM current pulse. For this, the high-side MOSFET switch turns on and the inductor current ramps up. After the on-time expires, the switch is turned off and the low-side MOSFET switch is turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current, the output voltage rises. If the output voltage is equal to or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical 15-μA current consumption. If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses is generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold. With a fast single-threshold comparator, the output voltage ripple during PFM mode can be kept small. The PFM pulse is time-controlled, which allows modifying the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. Increasing output capacitor values and inductor values minimizes the output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode entered in case the output current can no longer be supported in PFM mode. The power-save mode can be disabled by setting the MODE pin to high. The converter then operates in fixed-frequency PWM mode. Dynamic Voltage Positioning This feature reduces the voltage under- and overshoots at load steps from light to heavy load and vice versa. It is active in power-save mode and regulates the output voltage 1% higher than the nominal value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. 12 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 Output voltage Voltage Positioning Vout +1% PFM Comparator threshold Light load PFM Mode Vout (PWM) moderate to heavy load PWM Mode Figure 19. Operation in Power-Save Mode 100% Duty-Cycle Low-Dropout Mode The device starts to enter 100% duty-cycle mode once the input voltage comes close the nominal output voltage. To maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN, the high-side MOSFET switch is turned on completely. In this case, the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: VINmin = VOmax + IOmax × rDS(on)max + RL) with: IOmax = maximum output current plus inductor ripple current rDS(on)max = maximum P-channel switch rDS(on). RL = dc resistance of the inductor VOmax = nominal output voltage plus maximum output-voltage tolerance Undervoltage Lockout The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the output stage of the converter. The undervoltage lockout threshold is typically 1.85 V with falling VIN. MODE SELECTION The MODE pin allows mode selection between forced PWM mode and power-save mode. Connecting this pin to GND enables the power-save mode with automatic transition between PWM and PFM modes. Pulling the MODE pin high forces the converter to operate in fixed-frequency PWM mode even at light load currents. This allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. The condition of the MODE pin can be changed during operation and allows efficient power management by adjusting the operation mode of the converter to the specific system requirements. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 13 TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com ENABLE The device is enabled setting EN pin to high. During start-up time tStart Up, the internal circuits are settled. Afterwards, the device activates the soft-start circuit. The EN input can be used to control power sequencing in a system with various dc/dc converters. The EN pin can be connected to the output of another converter, to drive the EN pin high and get a sequencing of supply rails. With EN = GND, the device enters shutdown mode. In this mode, all circuits are disabled. In fixed-output-voltage versions, the internal resistor divider network is disconnected from the FB pin. SOFT START The TPS62590-Q1 has an internal soft-start circuit that controls the ramp-up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within typically 250 μs. This limits the inrush current in the converter during ramp-up and prevents possible input voltage drops when a battery or high-impedance power source is used. The soft-start circuit is enabled within start-up time tStart Up. SHORT-CIRCUIT PROTECTION The high-side and low-side MOSFET switches are short-circuit protected with maximum switch current = ILIMF. The current in the switches is monitored by current-limit comparators. Once the current in the high-side MOSFET switch exceeds the threshold of its current-limit comparator, it turns off and the low-side MOSFET switch is activated to ramp down the current in the inductor and high-side MOSFET switch. The high-side MOSFET switch can only turn on again once the current in the low-side MOSFET switch has decreased below the threshold of its current-limit comparator. THERMAL SHUTDOWN As soon as the junction temperature TJ exceeds 140°C (typical) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis. 14 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 APPLICATION INFORMATION L 2.2 mH TPS62590DRV 5 VIN 2.5 V to 5.5 V 4 CIN 10mF 2 VIN EN 3 FB MODE VOUT =1.8V 1 SW R1 360kΩ Up to 1A C1 22pF R2 180kΩ 6 GND PwrPAD COUT 10mF Figure 20. TPS62590-Q1DRV Adjustable 1.8 V L 2.2 mH TPS62590DRV 5 VIN 3.3 V to 5.5 V 4 CIN 10mF 2 VIN SW EN FB MODE GND VOUT =3.3V 1 3 R1 820kΩ I OUT,max =1A C1 22pF 6 PwrPAD R2 182kΩ COUT 10mF Figure 21. TPS62590-Q1DRV Adjustable 3.3 V OUTPUT VOLTAGE SETTING The output voltage can be calculated to: æ R1ö÷ V OUT = VREF x çç1 + ÷ çè R2 ø÷ (1) with the internal reference voltage VREF = 0.6 V typically. To minimize the current through the feedback divider network, R2 should be 180 kΩ or 360 kΩ. The sum of R1 and R2 should not exceed approximately 1 MΩ, to keep the network robust against noise. An external feedforward capacitor C1 is required for optimum load-transient response. The value of C1 should be in the range between 22 pF and 33 pF. Route the FB line away from noise sources, such as the inductor or the SW line. OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) The TPS62590-Q1 is designed to operate with inductors in the range of 1.5 μH to 4.7 μH and with output capacitors in the range of 4.7 μF to 22 μF. The part is optimized for operation with a 2.2-μH inductor and 10-μF output capacitor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For stable operation, the L and C values of the output filter may not fall below 1-μH effective inductance and 3.5-μF effective capacitance. Inductor Selection The inductor value has a direct effect on the ripple current. The selected inductor must be rated for its dc resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO. The inductor selection also impacts the output-voltage ripple in PFM mode. Higher inductor values lead to lower output-voltage ripple and higher PFM frequency; lower inductor values lead to a higher output-voltage ripple but lower PFM frequency. Equation 2 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 3. This is recommended because during heavy load transients the inductor current rises above the calculated value. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 15 TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com V 1 * OUT V DI L + VOUT L I L max + I out max ) IN f DI L (2) 2 (3) with: f = Switching frequency (2.25 MHz, typical) L = Inductor Value ΔIL = Peak-to-peak inductor ripple current ILmax = Maximum inductor current A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Accepting larger values of ripple current allows the use of low inductance values, but results in higher output voltage ripple, greater core losses, and lower output-current capability. The total losses of the coil have a strong impact on the efficiency of the dc/dc conversion and consist of both the losses in the dc resistance (R(DC)) and the following frequency-dependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses Table 4. List of Inductors DIMENSIONS [mm] INDUCTOR TYPE SUPPLIER 3 × 3 × 1.5 LPS3015 Coilcraft 3 × 3 × 1.5 LQH3NPN2R2NM0 MURATA 3.2 × 2.6 × 1.2 MIPSA3226D2R2 FDK Output Capacitor Selection The advanced fast-response voltage-mode control scheme of the TPS62590-Q1 allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output-voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode, and the RMS ripple current is calculated as: V 1 * OUT V I RMSC OUT + VOUT L IN 1 f 2 Ǹ3 (4) The overall output voltage ripple under the same conditions is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: V 1 * OUT V DV OUT + VOUT L IN f ǒ8 1 Cout f Ǔ ) ESR (5) At light load currents, the converter operates in power-save mode, and the output-voltage ripple is dependent on the output capacitor and inductor values. Larger output capacitor and inductor values minimize the voltage ripple in PFM mode and tighten dc output accuracy in PFM mode. 16 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 TPS62590-Q1 www.ti.com SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 Input Capacitor Selection The buck converter has a natural pulsating input current; therefore, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications, a 10-μF ceramic capacitor is recommended. The input capacitor can be increased without any limit for better input voltage filtering. Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce ringing at the VIN pin. The ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings. Table 5. List of Capacitor CAPACITANCE TYPE SIZE SUPPLIER 10 μF GRM188R60J106M69D 0603 1.6 mm × 0.8 mm × 0.8 mm Murata LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues, and EMI problems. It is critical to provide a low-inductance, low-impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor, output capacitor, and inductor should be placed as close as possible to the IC pins. Connect the GND pin of the device to the thermal pad of the PCB and use this pad as a star point. Use a common power GND node and a different node for the signal GND to minimize the effects of ground noise. Connect these ground nodes together to the thermal pad (star point) underneath the IC. Keep the common path to the GND pin, which returns the small-signal components and the high current of the output capacitors, as short as possible to avoid ground noise. The FB line should be connected directly to the output capacitor and routed away from noisy components and traces (for example, the SW line). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 17 TPS62590-Q1 SLVSAO5A – DECEMBER 2010 – REVISED APRIL 2012 www.ti.com VOUT R2 GND C1 R1 COUT CIN VIN L G N D U Figure 22. Layout 18 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS62590-Q1 PACKAGE OPTION ADDENDUM www.ti.com 17-Apr-2012 PACKAGING INFORMATION Orderable Device TPS62590TDRVRQ1 Status (1) Package Type Package Drawing ACTIVE SON DRV Pins Package Qty 6 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF TPS62590-Q1 : • Catalog: TPS62590 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS62590TDRVRQ1 Package Package Pins Type Drawing SON DRV 6 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 179.0 8.4 Pack Materials-Page 1 2.2 B0 (mm) K0 (mm) P1 (mm) 2.2 1.2 4.0 W Pin1 (mm) Quadrant 8.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62590TDRVRQ1 SON DRV 6 3000 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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