TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 Low Input Voltage, Compact LCD Bias IC With VCOM Buffer FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 1.8-V to 6-V Input Voltage Range Integrated VCOM Buffer High Voltage Switch to Isolate VGH Gate Voltage Shaping of VGH 2-A Internal MOSFET Switch Main Output Vs up to 15 V With <1% Output Voltage Accuracy Virtual Synchronous Converter Technology Negative Regulated Charge Pump Driver VGL Positive Regulated Charge Pump Driver VGH Adjustable Power On Sequencing Adjustable Fault Detection Timing Gate Drive Signal for external isolation MOSFET Thermal Shutdown Available in TSSOP-24 Package Available in QFN-24 Package TFT LCD Displays for Notebooks TFT LCD Display for Monitor Car Navigation Display DESCRIPTION The TPS65150 offers a very compact and small power supply solution that provides all three voltages required by thin film transistor (TFT) LCD displays. With an input voltage range of 1.8 V to 6.0 V the device is ideal for notebooks powered by a 2.5-V or 3.3-V input rail or monitor applications with a 5-V input voltage rail. Additionally the TPS65150 provides an integrated high current buffer to provide the VCOM voltage for the TFT backplane. Two regulated adjustable charge pump driver provide the positive VGH and negative VGL bias voltages for the TFT. The device incorporates adjustable power on sequencing for VGL as well as for VGH. This avoids any additional external components to implement application specific sequencing. The device has an integrated high voltage switch to isolate VGH. TYPICAL APPLICATION R8 500 k C6 R7 500 k 1 nF L1 3.9 H Vin 5V VS 13.5 V/450 mA D1 C1 22 F R3 620 k C7 0.33 F IN VIN DRVN D3 R4 150 k C8 220 nF FB REF DRVP GND FBP TPS65150 PGND CPI PGND VGH CTRL VCOM ADJ C9 2.2 nF C10 22 pF C11 D4 C15 22 pF SUP FBN C12 10 nF 10 nF C16 C2 22 F D5 CPI 0.33 F C4 0.33 F CPI VGH 23 V/20 mA R5 1 M R6 56 k VCOM Output C13 100 nF R1 820 k R2 75 k GD COMP VGH Control Signal C14 1 F SW SW DLY2 C3 0.33 F D2 DLY1 −5 V/20 mA FDLY VGL C5 1 F VIN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The same internal circuit can also be used to provide a gate shaping signal of VGH for the LCD panel controlled by the signal applied to the CTRL input. For highest safety the TPS65150 has an integrated adjustable shutdown latch feature to allow application specific flexibility. The device monitors the outputs (Vs, VGL, VGH); and, as soon as one of the outputs falls below its power good threshold, the device enters shutdown latch, after its adjustable delay time has passed by. ORDERING INFORMATION (1) TA ORDERING NUMBER PACKAGE (2) PACKAGE MARKING TPS65150PWP TSSOP24 (PWP) TPS65150 TPS65150RGE QFN-24 (RGE) TPS65150 –40°C to 85°C (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. The PWP package is available taped and reeled. Add R suffix to the device type (TPS65150PWPR) to order quantities of 2000 and (TPS65150RGER) to order quantities of 3000 devices per reel. Without suffix the device is shipped in tubes. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Voltages on pin VIN (2) –0.3 V to 7 V Voltages on pin SUP –0.3 V to 15.5 V Voltage on pin SW 20 V Voltage on CTRL –0.3 V to 7 V Voltage on GD 15.5 V Voltage on CPI 32V Continuous power dissipation See Dissipation Rating Table Operating junction temperature range –40°C to 150°C Storage temperature range –65°C to 150°C Lead temperature (soldering, 10 sec) (1) (2) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 30.13 C°/W (PowerPad™ soldered) 3.3 W 1.83 W 1.32 W 30 C°/W (PowerPadTM soldered) 3.3 W 1.8 W 1.3 W PACKAGE θJA 24 pin TSSOP 24 pin QFN RECOMMENDED OPERATING CONDITIONS MIN VIN Input voltage range VS Output voltage range of the main boost converter VS L Inductor (1) TA Operating ambient temperature (1) 2 Refer to application section for further information. TYP 1.8 MAX 6.0 15 4.7 –40 UNIT V V µH 85 °C TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 RECOMMENDED OPERATING CONDITIONS (continued) MIN TJ Operating junction temperature TYP –40 MAX UNIT 125 °C MAX UNIT ELECTRICAL CHARACTERISTICS VIN = 3.3 V, Vs = 10 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SUPPLY CURRENT VIN Input voltage range 1.8 IQVIN No load quiescent current into Vin Device is not switching 14 25 µA IQSUP No load quiescent current into SUP Device is not switching 1.9 3 mA IQVCOM VCOM quiescent current into SUP 750 1500 µA VUVLO Undervoltage lockout threshold VIN falling 1.6 1.8 V Vhys Undervoltage lockout threshold VIN rising 1.7 1.9 Thermal shutdown Temperature rising 155 °C 10 °C Thermal shutdown hysteresis 6.0 V V LOGIC SIGNALS CTRL VIH High level input voltage VIL Low level input voltage II Input leakage current 1.6 CTRL=GND or VIN V 0.4 V 0.01 0.2 µA 15 V 1.146 1.154 V nA MAIN BOOST CONVERTER VS Output voltage range VFB Feedback regulation voltage IFB Feedback input bias current N-MOSFET on-resistance (Q1) RDS(on) P-MOSFET on-resistance (Q2) 1.136 10 100 Vs = 10 V; Isw = 500 mA 200 300 Vs = 5 V; Isw = 500 mA 305 450 Vs = 10 V; Isw = 500 mA 8 15 Vs = 5 V; Isw = 500 mA 12 22 IMAX Maximum P-MOSFET peak switch current 1 ILIM N-MOSFET switch current limit (Q1) Ileak Switch leakage current Vsw = 15 V Vovp Output overvoltage protection VOUT rising fOSC Oscilator frequency 2.0 Ω A 2.5 3.4 A 1 10 µA 1.2 1.38 16 1.02 mΩ 20 V MHz Line regulation Vin=1.8V to 5.0V, Iload=1mA 0.007 %/V Load regulation Vin=5V, Iload=0A to 400mA 0.16 %/A NEGATIVE CHARGE PUMP VGL VGL Output voltage range VREF Reference Voltage on pin REF VFB Feedback regulation voltage IFB Feedback input bias current RDS(on) Q4 P-Channel switch RDSon VDropN Current sink voltage drop (1) Load regulation –2 V 1.205 1.213 1.219 –36 0 36 mV 10 100 nA Ω IOUT = 20 mA 4.4 IDRN = 50 mA, VFBN = VFBNNominal– 5% 130 300 IDRN = 100 mA, VFBN = VFBNNominal– 5% 280 450 VGL=-5V, Iload=0mA to 20mA V 0.016 mV %/mA POSITIVE CHARGE PUMP OUTPUT VCPO (1) Output voltage range CTRL = GND, VGH = open 30 V The maximum charge pump output current is half the drive current of the internal current source or sink. 3 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) VIN = 3.3 V, Vs = 10 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1.187 1.214 1.238 V 10 100 nA VFB Feedback regulation voltage CTRL = GND, VGH = open IFB Feedback input bias current CTRL = GND, VGH = open RDS(on) Q3 P-Channel switch RDSon IOUT = 20 mA 1.1 IDRP = 50 mA, VFBP = VFBPNominal– 5% 420 650 IDRP= 100 mA, VFBP = VFBPNominal– 5% 900 1400 VGH=24V, Iload=0mA to 20mA 0.07 VDropN Current sink voltage drop (1) Load regulation UNIT Ω mV %/mA VGH ISOLATION SWITCH, GATE VOLTAGE FALL TIME CONTROL RDS(on) Q5 - Pass MOSFET RDSon IOUT = 20 mA Iadj Capacitor charge current Vadj = 20 V, CPI = 30 V Minimum output voltage Vadj = 0 V, IVGH = 10 mA IVGH Maximum output current 160 12 30 Ω 200 240 µA 2 V 20 mA TIMING CIRCUITS DLY1, DLY2, FDLY IDLY1 Drive current into delay capacitor DLY1 VDLY1 = 1.213 V 3 5 7 µA IDLY2 Drive current into delay capacitor DLY1 VDLY2 = 1.213 V 3 5 7 µA 250 450 650 kΩ RFDLY Fault time delay resistror (2) GATE DRIVE (GD) V(GD, Vs) Gate drive threshold (3) Vs rising VOL Gate drive output low voltage I(sink) = 500 µA ILKG Gate drive output leakage current VGD = 15 V –12% of Vs –4% of Vs 0.001 V 0.5 V 1 µA Vcom Buffer VCM Common mode input range Vos Input offset voltage DC load regulation IB VCOMIN Input bias current Ipeak Peak output current (2) (3) 4 2.25 (Vs) –2V IOUT = 0 mA –25 25 Io = ±25 mA –37 37 Io = ±50 mA –77 55 Io = ±100 mA –85 85 Io = ±150 mA –110 110 –300 Vs = 15 V 1.2 Vs = 10 V 0.65 Vs = 5 V 0.15 –30 300 V mV mV nA The fault time is calculated as: tF= C × R = C × 450 kΩ The GD signal is latched low when the main boost converter output Vs is within regulation. The GD signal is reset when the input voltage or enable of the boost converter is cycled low. A TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 PIN ASSIGNMENT TSSOP-24 Package Top View 9 18 17 16 10 15 11 14 12 13 CPI DRVP DRVN GND REF COMP 1 24 23 22 21 20 19 18 VGH GD 2 17 ADJ FDLY 3 16 CTRL FB 4 15 FBP DLY1 5 14 IN DLY2 6 Exposed Thermal Die* 7 8 9 13 10 11 12 VCOM SUP 8 20 19 PGND 7 21 PGND 5 6 SW 22 4 SW 3 FDLY GD COMP FBN REF GND DRVN DRVP CPI VGH ADJ CTRL FBN 24 23 VIN 1 2 Thermal PowerPAD* FB DLY1 DLY2 VIN SW SW PGND PGND SUP VCOM IN FBP QFN-24 Package Top View * The thermal die (PowerPADTM) is connected to GND. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION QFN TSSOP ADJ 17 14 I/O Gate voltage shaping circuit. Connecting a capacitor to this pin sets the fall time of the positive gate voltage (VGH). COMP 1 22 O This is the compensation pin for the main boost converter. A small capacitor and if required a series resistor is connected to this pin. CPI 19 16 I Input of the VGH isolation switch and gate voltage shaping circuit. CTRL 16 13 I Control signal for the gate voltage shaping signal. Apply the control signal for the gate voltage control. Usually the timing controller of the LCD panel generates this signal. If this function is not required, this pin needs to be connected to VIN. By doing this, the internal switch between CPI and VGH provides isolation for the positive charge pump output VGH. DLY2 sets the delay time for VGH to come up. DLY1 5 2 I/O Power-on sequencing adjust. Connecting a capacitor from this pin to GND allows to set the delay time between the boost converter output Vs and the negative charge pump VGL during startup. DLY2 6 3 I/O Power-on sequencing adjust. Connecting a capacitor from this pin to GND allows to set the delay time between the negative charge pump VGL and the positive charge pump during startup. Note that Q5 in the Gate Voltage Shaping block only turns on when the positive charge pump (FBP) is within regulation. (This provides input to output isolation of VGH). DRVN 21 18 I/O Charge pump driver to generate the negative voltage VGL. DRVP 20 17 I/O Charge pump driver to generate the positive output voltage VGH. FB 4 1 I Feedback of the main boost converter generating Vsource (Vs). FBN 24 21 I Feedback pin of the negative charge pump VGL. FBP 15 12 I Feedback pin of the positive charge pump. FDLY 3 24 I/O GD 2 23 I GND 22 19 Fault delay. Connecting a capacitor from this pin to Vin allows to set the delay time from the point when one of the outputs (VS, VGH, VGL) drops below its power good threshold until the devices enters the shutdown latch. To re-start the device the input voltage has to be cycled to GND. This feature can be disabled by connecting the FDLY pin to Vin. Active low open drain output. This output is latched low when the boost converter Vs is in regulation. This signal can be used to drive an external MOSFET to provide isolation for Vs. Analog ground 5 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 TERMINAL FUNCTIONS (continued) TERMINAL NAME IN PGND NO. I/O QFN TSSOP 14 11 I DESCRIPTION Input of the Vcom buffer. If this pin is connected to GND, the Vcom buffer is disabled. 10, 11 7, 8 REF 23 20 O Power ground Internal reference output typically 1.213 V SUP 12 9 I/O Supply pin of the positive, negative charge pump and Boost Converter Gate Drive Circuit. This pin needs to be connected to the output of the main boost converter and can’t be connected to any other voltage rail. SW 8, 9 5, 6 I Switch pin of the boost converter VGH 18 15 O Positive output voltage to drive the TFT gates with an adjustable falltime. This pin is internally connected with a MOSFET switch to the positive charge pump input CPI. VIN 7 4 I This is the input voltage pin of the device. VCOM 13 10 O VCOM buffer output. Typically a 1-µF output capacitor is required on this pin. NA NA PowerPADTM, exposed thermal die 6 The PowerPADTM needs to be soldered to GND TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURES Main Boost Converter η Efficiency vs Load current Vs=10 V 1 η Efficiency vs Load current Vs=13.5 V 2 η Efficiency vs Load current Vs=15 V 3 fSW Switching frequency vs Input voltage and temperature 4 PWM operation at nominal load current 5 PWM operation at light load current 6 Load transient response 7 Softstart boost converter 8 Power-on sequencing 9 Power-on sequencing External MOSFET in series to Vs 10 Gate voltage shaping of VGH 11 Adjustable Fault detection 12 Negative Charge Pump Driver VGL VGL vs load current 13 Positive Charge Pump Driver VGH VGH vs load current; Charge pump doubler stage 14 VGH VGH vs load current; Charge pump tripler stage 15 VCOM Buffer VCOM Buffer transconductance 16 EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100 100 VS = 10 V, VGH = VGL = No Load, Switching VS = 13.5 V, VGH = VGL = No Load, Switching 90 90 VIN = 5 V VIN = 5 V 80 Efficiency − % Efficiency − % 80 VIN = 3.3 V VIN = 2.5 V 70 VIN = 3.3 V 60 60 50 50 40 0 0.1 0.2 0.3 0.4 0.5 IO − Load Current − A Figure 1. 0.6 0.7 0.8 VIN = 2.5 V 70 40 0 0.1 0.2 0.3 0.4 0.5 0.6 IO − Load Current − A Figure 2. 7 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 EFFICIENCY vs LOAD CURRENT SWITCHING FREQUENCY vs TEMPERATURE 1.155 100 VS = 13.5 V VS = 15 V, VGH = VGL = No Load, Switching Efficiency − % f − Frequency − MHz VIN = 5 V VIN = 3.3 V 70 VIN = 3.6 V 1.150 90 80 VIN = 7 V VIN = 2.5 V 60 VIN = 1.8 V 1.145 1.140 1.135 1.130 50 40 0 1.125 0.05 0.1 0.15 0.2 0.25 0.3 IO − Load Current − A 0.35 0.4 1.120 −40 −20 0 20 40 60 Figure 3. Figure 4. PWM OPERATION NOMINAL LOAD CURRENT PWM OPERATION LIGHT LOAD CURRENT VSW 10 V/div VSW 10 V/div VO 50 mV/div VO 50 mV/div VIN = 5 V VO = 13.5 V/10 mA IL 1 A/div VIN = 5 V, VO = 13.5 V/300 mA 250 ns/div Figure 5. 8 80 TA − Free-Air Temperature − C IL 1 A/div 250 ns/div Figure 6. 100 120 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 LOAD TRANSIENT RESPONSE SOFT START BOOST CONVERTER VIN 5 V/div VO1 100 mV/div VIN = 3.3 V VS = 10 V, CO = 22 F VS 5 V/div IO 30 mA to 330 mA VIN = 5 V VO = 13.5 V Iout = 200 mA IIN 500 mA/div 100 s/div 2.5 ms/div Figure 7. Figure 8. POWER-ON SEQUENCING POWER-ON SEQUENCING WITH EXTERNAL ISOLATION MOSFET AT VS VS 5 V/div VS 5 V/div VGH 10 V/div VGH 10 V/div VGL 5 V/div VGL 5 V/div VCOM 2 V/div VIN = 5 V VO = 13.6 V/ 300 mA VCOM CIN = 1 nF 1 ms/div Figure 9. VCOM 5 V/div 2.5 ms/div Figure 10. 9 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 GATE VOLTAGE SHAPING VGH ADJUSTABLE FAULT DETECTION CTRL 2 V/div Fault Delay Time VS 5 V/div VGH 10 V/div VGH 10 V/div Fault (Heavy Load at VS) VGL 5 V/div CADJ = 68 pF VGH = No Load CFDLY = 100 nF 10 ms/div 2.5 s/div Figure 11. Figure 12. VGL– GATE VOLTAGE LOW vs LOAD CURRENT VGH– GATE VOLTAGE HIGH vs LOAD CURRENT –X2 STAGE −4.86 VS = 10 V VGL = –5 V 24.50 VGH − Gate Voltage High − V VGL − Gate Voltage Low − V −4.88 25 TA = 85C −4.90 −4.92 TA = 25C −4.94 −4.96 TA = −40C −4.98 24 VS = 15 V VGH = 24 V x2 Stage 23.50 23 TA = 85C 22.50 TA = 25C 22 21.50 TA = −40C 21 −5.00 −5.02 0 20.50 20 0.02 0.04 0.06 IO − Load Current − A Figure 13. 10 0.08 0.1 0 0.02 0.04 0.06 IO − Load Current − A Figure 14. 0.08 0.1 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 VGH– GATE VOLTAGE HIGH vs LOAD CURRENT – X3 STAGE VCOM BUFFER dVOUT vs LOAD CURRENT 25 0.08 0.06 VS = 10 V VVCOM = 5 V 24 0.04 23.50 VS = 10 V VGH = 24 V x3 Stage 23 VCOM Buffer − V VGH − Gate Voltage High − V 24.50 TA = −40C 22.50 TA = 25C 22 21.50 TA = 85C 0.02 0 −0.02 −0.04 21 −0.06 22.50 20 0 0.02 0.04 0.06 IO − Load Current − A Figure 15. 0.08 0.1 −0.08 −150 −100 −50 0 50 IO − Load Current − A 100 150 Figure 16. 11 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 FUNCTIONAL BLOCK DIAGRAM VIN SW SW Q2 Main boost converter Current Limit Bias Vref=1.213V Logic Control Block Shutdown Latch Timer Thermal Shutdown FDLY GND DL1 SUP and Soft Start 1.2 MHz Oscillator SUP Control Logic Gate Drive circuit DL2 Q1 COMP PGND GM Amplifier Sawtooth Generator FB Comparator PGND SUP VFB SUP (Vout) 1.154V Positive Charge Pump SUP I DRVP GM Amplifier Low Gain VFB 1.154 Current Control Softstart Vref 1.213V Vin DRVP Q3 IDLY1 Delay Between Vs and VGL Vref DL1 FBP DLY1 Vin VGH Q5 Gate Voltage Control Circuit IDLY2 Delay Between VGL and VGH Vref DL2 DLY2 SUP Negative Charge Pump Q4 Q7 Control CTRL,EN,FBP=high Q11=Q13=on, Q12=off CTRL=low Q11=Q13off, Q12=on Q6 Current Control Soft Start DRVN UVLO I DRVN I ADJ SUP CTRL Main Boost Soft Start Gate Drive Completed FBN Vref 1.213V Q11 Reference Output Q12 Vref 1.213V Disable IN 12 Vref 1.213V ADJ Soft Start REF CPI VCOM Buffer Main Boost Power Good ADJ VCOM ADJ GD TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION Main Boost Converter The main boost converter operates with pulse width modulation (PWM) and a fixed switching frequency of 1.2 MHz. The converter uses an unique fast response, voltage mode controller scheme with input voltage feedforward. This achieves excellent line and load regulation (0.16%/A load regulation typical) and allows the use of small external components. To add higher flexibility to the selection of external component values the device uses external loop compensation. Although the boost converter looks like a non-synchronous boost converter topology operating in discontinuous conduction mode at light load current the TPS65150 maintains continuous conduction even at light load currents. This is achieved by using the Virtual Synchronous Converter Technology having an external Schottky diode with an integrated MOSFET in parallel connected between SW pin and the SUP pin. See Functional Block Diagram. The intention of this MOSFET is to allow the current to go below ground which is the case at light load conditions. For this purpose a small integrated P-Channel MOSFET, with typically 10-Ω RDS(on), is sufficient. When the inductor current is positive the external Schottky diode with the lower forward voltage conducts the current. This causes the converter to operate with a fixed frequency in continuous conduction mode over the entire load current range. This avoids the ringing on the switch pin as seen with standard non-synchronous boost converter and allows a simpler compensation for the boost converter. Soft Start The main boost converter as well as the charge pump driver have an internal soft-start circuit. This avoids heavy voltage drops at the input voltage rail or at the output of the main boost converter Vs during startup caused by high inrush currents. As the main boost converter starts up the internal current limit threshold is increased in three steps. The device starts with the first step where the current limit is set to 2/5 of the typical current limit (2/5 of 2.3 A) for 2048 clock cycles then increased to 3/5 of the current limit for 2048 clock cycles and the 3rd step is the full current limit. This gives a typical start-up time around 5 ms. Adjustable Fault Delay The TPS65150 has an adjustable delay timer integrated shutting down the entire device in case of a fault at the outputs. The fault timer is also active during startup. Connecting a capacitor from the FDLY pin to Vin sets the delay time, from the point where one of the outputs (VS, VGH, VGL) drops below its power good threshold, until the device enters the shutdown latch. Since the fault delay timer is also active during startup, the device enters shutdown when the output voltage of the main boost converter, Vs, does not reach its power-good threshold after the fault delay time has passed. When an external isolation switch is used, shown in Figure 24, then the device provides short circuit protection even during start-up. To restart the device, the input voltage has to be cycled to GND. The shutdown function can be disabled by connecting FDLY to VIN. The fault delay time is calculated as: tF = C × R = C × 450 kΩ = 100 nF × 450 kΩ≈ 40 ms Positive Charge Pump The positive charge pump provides a regulated output voltage, set by the external resistor divider. Figure 17 shows an extract of the positive charge pump driver circuit out of the block diagram. The operation of the charge pump driver can be understood best by looking at Figure 17. During the first cycle Q3 is turned on and the flying capacitor, Cfly, is charged to the source voltage, Vs. During the next clock cycle Q3 is turned off, and the current source charges the drive pin, DRVP, up to the supply voltage, VSUP. Since the flying capacitor voltage sits on top of the drive pin voltage the maximum output voltage is VGH=Vsup + Vs - Vdrop. Vdrop is the voltage drop across the external diodes and internal charge pump MOSFETs. 13 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) SUP = VIN for VS > = 15 V SUP = VS for VS < = 15 V Vs I DRVP DRVP Current Control Soft Start Cfly VGH 23 V/50 mA Q3 R5 C13 0.47 F FBP R6 Figure 17. Extract of the Positive Charge Pump Driver If higher output voltages are required another charge pump stage can be added to the output, as shown in Figure 21 at the end of the data sheet. To minimize quiescent current a high impedance feedback divider should be used. The top feedback resistor should not be selected larger than 1MΩ. Setting the output voltage: V out 1.213 1 R5 R6 Vout V out R5 R6 1 R6 1 1.213 VFB (1) Negative Charge Pump The negative charge pump provides a regulated output voltage set by the external resistor divider. The negative charge pump operates very similar to the positive charge pump with the difference that the voltage on the supply pin SUP is inverted. The maximum output voltage for a single stage charge pump inverter is VGL = (–VSUP) + Vdrop. Vdrop is the voltage drop across the external diodes and internal charge pump MOSFETs. Setting the output voltage: V out V R3 1.213 V R3 REF R4 R4 Vout Vout R3 R4 R4 1.213 V REF (2) The lower feedback resistor value, R4, should range between 40 kΩ to 120 kΩ; or, the overall feedback resistance should be within 500 kΩ to 1 MΩ. Smaller values load the reference too heavily; and larger values may cause stability problems. The negative charge pump requires two external Schottky diodes. The peak current rating of the Schottky diode has to be twice the load current of the output. For a 20-mA output current, the BAT54 dual Schottky diode is a good choice. 14 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) Power-on Sequencing, DLY1, DLY2 As soon as the input voltage is applied, and rises above the undervoltage lockout (UVLO), the device starts with the main boost converter, Vs, coming up first. Then the negative voltage, VGL, comes up, set by the delay time DLY1; and then the positive charge pump, VGH, set by the delay time DLY2. Finally, the VCOM buffer starts up. The delay times, DLY1 and DLY2, are set by the capacitor value connected to these pins. An internal current source charges the capacitor with a constant current of typically 5 µA until the voltage reaches the internal comparator trip point of Vref = 1.213 V. VIN DLY2 VGH, with CTRL=high Fall Time of VS, VGL and VGH Depends on Load Current and Feedback Resistor Impedance Vs DLY1 VGL GD Figure 18. Power on Sequencing With CTRL = High Setting the Delay Times DLY1, DLY2 Connecting an external capacitor to the DLY1 and DLY2 pins sets the delay time. If no delay time is required, these pins can be left open. To set the delay time, the external capacitor connected to DLY1 and DLY2 is charged with a constant current source of typically 5 µA . The delay time is terminated when the capacitor voltage has reached the internal reference voltage of Vref = 1.213 V. The external delay capacitor is calculated: 5 A td 5 A td C with td Desired delay time dly V REF 1.213 V (3) Gate Drive, GD The gate drive pin can be used to drive an external MOSFET, providing isolation for the main boost converter Vs. The gate drive is an open drain output capable of sinking typically 500 µA. The gate drive is latched low as soon as the main boost converter, Vs, reaches its power-good threshold. The gate drive signal goes high impedance when the input voltage falls below the undervoltage lockout (UVLO) or the device enters shutdown latch triggered by the fault delay. VGH Switch / Gate Voltage Shaping, CPI – VGH The gate voltage shaping circuit is used to reduce crosstalk between the LCD pixels by adjusting the fall time of the positive gate voltage, VGH. The CTRL pin needs to be connected to Vin if the gate voltage shaping function is not used. This function is implemented by adjusting the fall time of the gate voltage signal, VGH, generated by the positive charge pump. The fall time can be adjusted with the external capacitor, Cadj connected to the ADJ pin. The corresponding timing diagram is shown in Figure 20. 15 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) Q5 CPI VGH Q7 Control CTRL, UVOL, FPB = High Q5 = Q7 = ON, Q6 = OFF CTRL = Low Q5 = Q7 = OFF, Q6 = Turns ON Q6 FBP ADJ UVLO I ADJ Vref 1.213 V Cadj 47 pF CTRL Figure 19. Implementation of the Gate voltage shaping Control Signal (Pin CTRL) VCPI VGH V VL toff ton Iadj x toff Cadj V Figure 20. Timing Diagram of the Gate voltage shaping The control signal applied to CTRL sets the timing of VGH. When CTRL is high, Q5 is turned on and the positive charge pump voltage applied on CPI is present on VGH. At the same time, the capacitor connected to ADJ is charged up by Q7 to VGH, while Q6 is turned off. When CTRL is taken low, Q5 and Q7 turn off, and Q6 is slowly turned on as the capacitor on ADJ is discharged by the discharge current IADJ, typically 200 µA. The capacitor value on CADJ determines the fall time of VGH. For a given off time (toff), external capacitor Cadj determines the desired voltage drop, ∆V. Iadj toff Cadj with ladj 200 A V (4) When the input voltage falls below the undervoltage threshold (UVLO) or the device enters shutdown latch triggered by the fault delay timer, then VGH is disconnected from CPI by Q5 and is high impedance. 16 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) Thermal Shutdown A thermal shutdown is implemented to prevent damage because of excessive heat and power dissipation. Typically, the thermal shutdown threshold is 155°C . When this threshold is reached, the device enters shutdown. The device can be enabled again by cycling the input voltage to GND. Vcom Buffer The VCOM Buffer is a transconductance amplifier designed to drive capacitive loads. The IN pin is the input of the VCOM buffer. If the VCOM buffer is not required for certain applications, it is possible to shut down the VCOM buffer by connecting IN to ground, reducing the overall quiescent current. The VCOM buffer features a soft start, avoiding a large voltage drop at Vs during startup. The VCOM buffer input, IN, cannot be pulled dynamically to ground during operation. Boost Converter Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the boost converter supports the specific application requirements. A simple approach is to estimate the converter efficiency, by taking the efficiency numbers from the provided efficiency curves, or use a worst case assumption for the expected efficiency, e.g. 75%. Vin 1. Duty Cycle : D 1 Vout (5) (6) Vin D 2 ƒs L 1 D (7) 2. Maximum output current : I out Isw Vin D (1 D) 2 ƒs L 3. Peak switch current : I I out swpeak With Isw = Converter switch current (minimum switch current limit = 2.0 A) fs = Converter switching frequency (typical 1.2 MHz) L = Selected inductor value η = Estimated converter efficiency (use the number from the efficiency plots, or 0.75 as an estimation) The peak switch current is the steady-state peak switch current that the integrated switch, inductor, and external Schottky diode has to be able to handle. The calculation must be done for the minimum input voltage where the peak switch current is highest. For the calculation of the maximum current delivered by the boost converter it needs to be considered that the positive and negative charge pumps as well as the VCOM buffer run from the output of the boost converter as well. Inductor Selection Several inductors work with the TPS65150. Especially with external compensation, the performance can be adjusted to the specific application requirements. The main parameter for the inductor selection is the inductor saturation current, which should be higher than the peak switch current as calculated previously with additional margin to cover for heavy load transients. The alternative, more conservative approach, is to choose the inductor with a saturation current at least as high as the typical switch current limit of 2.5 A. The second important parameter is the inductor DC resistance. Usually the lower the DC resistance the higher the efficiency. It is important to note that the inductor DC resistance is not the only parameter determining the efficiency. For a boost converter, where the inductor is the energy storage element, the type and material of the inductor influences the efficiency as well. Especially at high switching frequencies of 1.2 MHz, inductor core losses, proximity effects, and skin effects become more important. Usually an inductor with a larger form factor gives higher efficiency. The efficiency difference between different inductors can vary between 2% to 10%. For the TPS65150, inductor values between 3.3 µH and 6.8 µH are a good choice, but other values can be used as well. Possible inductors are shown in Table 1. 17 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) Table 1. Inductor Selection INDUCTOR VALUE COMPONENT SUPPLIER DIMENSIONS IN mm Isat – DC Resistance 4.7 µH Coilcraft DO1813P-472HC 8,89 × 6,1 × 5,0 2.6 A – 54 mΩ 4.2 µH Sumida CDRH5D28 4R2 5,7 × 5,7 × 3 2.2 A – 23 mΩ 4.7 µH Sumida CDC5D23 4R7 6 × 6 × 2,5 1.6 A – 48 mΩ 4.2 µH Sumida CDRH6D12 4R2 6,5 × 6,5 × 1,5 1.8 A – 60 mΩ 3.9 µH Sumida CDRH6D28 3R9 7,0 × 7,0 × 3,0 2.6A – 20 mΩ 3.3 µH Sumida CDRH6D12 4R2 6,5 × 6,5 × 1,5 1.9 A – 50 mΩ Output Capacitor Selection For best output voltage filtering, a low ESR output capacitor is recommended. Ceramic capacitors have a low ESR value, but tantalum capacitors can be used as well, depending on the application. A 22-µF ceramic output capacitor works for most applications. Higher capacitor values can be used to improve the load transient regulation. See Table 2 for the selection of the output capacitor. Input Capacitor Selection For good input voltage filtering, low ESR ceramic capacitors are recommended. A 22-µF ceramic input capacitor is sufficient for most applications. For better input voltage filtering, this value can be increased. See Table 2, and Typical Applications for input capacitor recommendations. Table 2. Input and Output Capacitor Selection CAPACITOR VOLTAGE RATING COMPONENT SUPPLIER COMMENTS 22 µF/1206 16 V Taiyo Yuden EMK325BY226MM Cout 22 µF/1206 6.3 V Taiyo Yuden JMK316BJ226 Cin Rectifier Diode Selection To achieve high efficiency, a Schottky diode should be used. The reverse voltage rating should be higher than the maximum output voltage of the converter. The required average rectified forward current rating of the Schottky diode is calculated as the off time of the converter times the maximum switch current of the TPS65150: D 1 Vin Vout (8) Vin I avg (1 D) Isw 2.0 A with lsw minimum switch current Vout of the TPS65150 (2.0 A) (9) Usually, a Schottky diode with 1-A maximum average rectified forward current rating is sufficient for most of the applications. Secondly, the Schottky rectifier has to be able to dissipate the power. The dissipated power is the average rectified forward current times the diode forward voltage. PD = Iavg × VF = Isw × (1 – D) × VF with lsw = minimum switch current of the TPS65150 (2.0 A). Typically, the diode should be able to dissipate 270 mW maximum depending on the load current and forward voltage. In terms of efficiency, the main parameters of the diode are the forward voltage and the reverse leakage current of the diode; both should be as low as possible. Table 3. Rectifier Diode Selection 18 CURRENT RATING Iavg Vr Vforward COMPONENT SUPPLIER 2A 20 V 0.44 V at 2 A SL22, Vishay Semiconductor 2A 20 V 0.5 V at 2 A SS22, Fairchild Semiconductor 1A 30 V 0.44 V at 2 A MBRS130L, Fairchild Semiconductor 1A 20 V 0.45 V at 1 A UPS120, Microsemi 1A 20 V 0.45 V at 1 A MBRM120, ON Semiconductor TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 Setting the Output Voltage The output voltage is set by the external resistor divider and is calculated as: V out 1.146 V 1 R1 R2 (10) To minimize quiescent current high impedance feedback resistors should be used. The upper feedback resistor R1 should not be larger than 1MΩ. Across the upper resistor, a bypass capacitor is required to speed up the circuit during load transients. The capacitor value is selected according to Table 4 and the formula (12) as shown in the next section. Compensation (COMP) and feedforward capacitor The regulator loop can be compensated by adjusting the external components connected to the COMP pin. The COMP pin is the output of the internal transconductance error amplifier. The compensation capacitor adjusts the low-frequency gain. Adding a resistor in series to it will increase the high frequency gain. Since the converter gain changes with the input voltage different compensation capacitors are required. Lower input voltages require a higher gain, and therefore a smaller compensation capacitor value. Table 4. Compensation Components for different VIN Voltages VIN CCOMP RCOMP fZ 2.5 V 470 pF 68 kΩ 8.8 kHz 3.3 V 470 pF 33 kΩ 7.8 kHz 5.0 V 2.2 nF 0 kΩ 11.2 kHz The feedforward capacitor across the feedback resistor devider of the boost converter sets an additional zero at the frequency fz to compensate the loop. Typical values for fz are shown in Table 4 giving a feedforward capacitor value as calculated below. 1 1 C FF 2 ƒz R1 2 8.8 kHz R1 (11) Please refer to the typical application circuits at the end of the datasheet for detailed circuit configurations and values. Layout Consideration 1. 2. 3. 4. 5. 6. 7. 8. 9. The PCB layout is an important step in the power supply design. An incorrect layout could cause converter instability, load regulation problems, noise, and EMI issues. Especially with a switching dc-dc converter at high load currents, too-thin PCB traces can cause significant voltage spikes. Good grounding becomes important as well. If possible, a common ground plane to minimize ground shifts between analog (GND) and power ground (PGND) is recommended. Additionally, the following PCB design layout guidelines are recommended for the TPS65150: Boost converter output capacitor, input capacitor and Power ground (PGND) should form a star ground or should be directly connected together on a common power ground plane. Place the input capacitor directly from the input pin (VIN) to ground. Use a bold PCB trace to connect SUP to the output Vs. Place a small baypass capacitor from the SUP pin to ground. Use short traces for the charge-pump drive pins (DRVN, DRVP) of VGH and VGL because these traces carry switching currents. Place the charge pump flying capacitors as close as possible to the DRVP and DRVN pin, avoiding a high voltage spikes at these pins. Place the Schottky diodes as close as possible to the IC, respectively to the flying capacitors connected to DRVP and DRVN. Carfully route the chare pump traces to avoid interference with other circuits since they carry high voltage switching currents . Place the output capacitor of the VCOM buffer as close as possible to the output pin (VCOM). 19 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 10. The power pad of the TSSOP package needs to be soldered to the PCB for imroved thermal performance. 11. The thermal pad of the QFN package needs to be soldered to the PCB for reliability and thermal performance reasons. 20 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 APPLICATION INFORMATION R8 500 k C6 R7 500 k 1 nF IN VIN DRVN D3 R3 620 k REF DRVP GND R4 150 k PGND FBP CPI PGND VGH CTRL VCOM TPS65150 COMP VGH Contol Signal C9 470 pF R9 33 k DLY1 C8 220 nF FB ADJ C3 0.33 F SW SW SUP FBN C10 C11 22 pF 10 nF 10 nF R2 430 k C2 22 F R2 56 k C16 D5 D6 D7 CPI CPI 0.33 F C17 C18 0.33 F 0.33 F SW C4 0.33 F R5 1 M R6 56 k VGH 23 V/20 mA GD VCOM Output C13 C12 C15 33 pF C14 1 F FDLY 0.33 F DLY2 VGL −5 V/20 mA C7 D4 3.9 H C1 22 F D2 Vs 10 V/400 mA D1 L1 Vin 3.3 V C5 1 F 100 nF VIN Figure 21. Notebook LCD Supply powered from a 3.3V rail R8 500 k C6 R7 500 k 1 nF IN VIN DRVN 0.33 F D3 R3 620 k R4 150 k C8 220 nF FB REF DRVP GND PGND FBP CPI PGND VGH CTRL VCOM TPS65150 COMP VGH Contol Signal R9 68 k C9 470 pF C10 ADJ C3 0.33 F SW SW SUP FBN C11 C12 22 pF 10 nF 10 nF C15 47 pF C14 1 F R2 430 k C2 22 F R2 56 k C16 D5 D6 D7 CPI CPI 0.33 F C17 C18 0.33 F 0.33 F SW VGH 23 V/20 mA GD FDLY VGL −5 V/20 mA C7 DLY1 D2 D4 3.9 H C1 22 F DLY2 Vin 2.5 V Vs 10 V/280 mA D1 L1 C4 0.33 F R5 1 M R6 56 k VCOM Output C13 C5 1 F 100 nF VIN Figure 22. Notebook LCD Supply powered from a 2.5V rail 21 TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 APPLICATION INFORMATION (continued) R8 500 k C6 R7 500 k 1 nF D3 R3 620 k FB REF DRVP VGH CPI PGND VGH CTRL VCOM COMP GD C16 D5 CPI 0.33 F C4 0.33 F CPI C11 C12 22 pF 10 nF 10 nF R5 1 M R6 56 k VGH 23 V/20 mA VCOM Output C13 C10 C2 22 F R2 75 k FBP PGND C9 2.2 nF Contol Signal TPS65150 ADJ C8 220 nF SUP FBN GND R4 150 k SW R1 820 k C15 22 pF C14 1 F FDLY 0.33 F SW DLY1 C3 0.33 F C7 IN VIN DRVN DLY2 VGL −5 V/20 mA D4 3.9 H C1 22 F D2 Vs 13.5 V/450 mA D1 L1 Vin 5V C5 1 F 100 nF VIN Figure 23. Monitor LCD Supply powered from a 5V rail R7 500 kW R8 500 kW C6 1 nF L1 3.9 mH Vin 5V C17 220 nF D1 C1 22 mF VGL -5 V/20 mA C7 0.33 mF D2 IN SW VIN DRVN SW R3 620 kW D3 TPS65150 R4 150 kW C8 220 nF PGND VGH VCOM COMP VGH Contol Signal C9 2.2 nF ADJ C10 22 pF CPI CPI CPI CTRL C16 0.33 mF C4 0.33 mF VGH 23 V/20 mA GD DLY1 C11 11 nF R8 100 kW D5 FBP PGND C13 1 mF 22 mF DRVP GND R7 510 kW R2 75 kW FB REF R1 820 kW Vs 13.5 V/450 mA C2 SUP FBN C3 0.33 mF C 15 22 pF D4 C14 1 mF SI2343 Q1 GD R5 1M R6 56k V COM Output DLY2 F D L Y C13 C12 10 nF 100 nF C5 1 mF VIN Figure 24. Typical Isolation and Short-Circuit Protection Switch for Vs using Q1 and Gate Drive Signal (GD) 22 PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS65150PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65150PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65150PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65150PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65150RGER ACTIVE QFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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