TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 WLED DRIVER FOR NOTEBOOK DISPLAY FEATURES 1 • • • • • • • • • • • • 5 V to 24 V Input Voltage Integrated 1.5 A 40 V MOSFET 1.0 MHz/1.3 MHz Switching Frequency Boost Output Auto-Adaptive to WLED Voltages Small External Components Integrated Loop Compensation Six Current Sink of 25 mA Up to 10 WLED in Series Less Than 3% Current Matching and Accuracy 100:1 PWM Brightness Dimming Range Minimized Output Ripple Under PWM Dimming Driver for Input/Output Isolation PFET • • • • • True Shutdown Over Voltage Protection WLED Open/Short Protection Built-in Soft Start 16L 3 mm×3 mm QFN APPLICATIONS • • • Notebook LCD Display Backlight UMPC LCD Display Backlight Backlight for Media Form Factor LCD display DESCRIPTION The TPS61180/1/2 ICs provide highly integrated solutions for media size LCD backlight. These devices have a built-in high efficiency boost regulator with integrated 1.5A/40V power MOSFET. The six current sink regulators provide high precision current regulation and matching. In total, the device can support up to 60 WLED. In addition, the boost output automatically adjusts its voltage to the WLED forward voltage to improve efficiency. The devices support pulse width modulation (PWM) brightness dimming. During dimming, the WLED current is turned on/off at the duty cycle and frequency determined by the PWM signal input on the DCRTL pin. One potential issue of PWM dimming is audible noises from the output ceramic capacitors. The TPS61180/1/2 family is designed to minimize this output AC ripple across a wide dimming duty cycle and frequency range; and, therefore reduce the audible noise. The TPS61180/1/2 ICs provide a driver output for an external PFET connected between the input and inductor. During short circuit or over-current conditions, the ICs turn off the external PFET and disconnect the battery from the WLEDs. The PFET is also turned off during IC shutdown (true shutdown) to prevent any leakage current of the battery. The device also integrates over-voltage protection, soft-start and thermal shutdown. The TPS61180 IC requires external 3.3V IC supply, while TPS61181 and TPS61182 ICs have a built-in linear regulator for the IC supply. All the devices are in a 3×3 mm QFN package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. L1 10 mH Optional 5 V to 24 V C1 4.7 mF Q1 R2 51Ω R3 100 kW SW VBAT VO TPS61181/2 EN IFB6 DCTRL PWM Dimming IFB1 IFB2 IFB3 IFB4 IFB5 Cin C4 0.1 mF EN C2 4.7 mF 10 WLED in series,120 mA total D2 Fault C3 1 mF D1 ISET PGND GND R1 62 kW Figure 1. TPS61181/2 TYPICAL APPLICATION ORDERING INFORMATION (1) PACKAGE IC SUPPLY SWITCHING FREQUENCY (TYP) PACKAGE MARKING TPS61180RTE External 3.3 V 1.0 MHz CCG TPS61181RTE Built-in LDO 1.0 MHz CCH TPS61182RTE Built-in LDO 1.3 MHz CCI (1) 2 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 PINOUT Fault EN IFB6 IFB5 QFN PACKAGE 16 Pin 3x3 (TOP VIEW) 16 15 14 13 12 2 11 DCTRL VBAT 3 10 GND VO 4 9 IFB3 6 7 IFB4 8 IFB2 5 IFB1 SW Cin 1 ISET PGND TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NO. NAME 1 PGND I Power ground of the IC. Internally, it connects to the source of the PWM switch. 2 SW I This pin connects to the drain of the internal PWM switch, external Schottky diode and inductor. 3 VBAT I This pin is connected to the battery supply. It provides the pull-up voltage for the Fault pin and battery voltage signal. For TPS61181/2, this is also the input to the internal LDO. 4 VO O This pin monitors the output of the boost regulator. Connect this pin to the anode of the WLED strings. 5 ISET I The resistor on this pin programs the WLED output current. 6 Cin I Supply voltage of the IC. For TPS61181/2, it is the output of the internal LDO. Connect 0.1 µF bypass capacitor to this pin. For TPS61180, connect an external 3.3 V supply to power the IC. I Current sink regulation inputs. They are connected to the cathode of WLEDs. The PWM loop regulates the lowest VIFB to 400 mV. Each channel is limited to 25 mA current. 7, 8, 9 IFB1-IFB3 12, 13, 14 IFB4-IFB6 10 GND I Signal ground of the IC. 11 DCTRL I Dimming control logic input. The dimming frequency range is 100 Hz to 1 kHz. 15 EN I The enable pin to the IC. For TPS61181/2, a logic high signal turns on the internal LDO and enables the IC. Therefore, do not connect the EN pin to the Cin pin. 16 Fault I Gate driver output for an external PFET used for fault protection. It can also be used as signal output for system fault report. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 3 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 FUNCTIONAL BLOCK DIAGRAM L1 10 mH Optional 5 V to 24 V Q1 R3 100 kW R3 51 W C1 4.7 mF VBAT C2 4.7 mF SW Fault Protection C3 1 mF Cin VO Current Mode IFB 1... IFB 6 PWM Control Internal Regulator (TPS61181/2 only) Dimming Control GND EN EN Current Regulator DCTRL PWM Dimming 10 WLED in series,120 mA total D2 Fault C4 0.1 mF D1 PGND IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 ISET R1 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Voltages on pin VBAT and Fault (2) –0.3 to 24 V Voltage on pin Cin (2) –0.3 to 3.6 V –0.3 to 40 V –0.3 to 20 V –0.3 to 7 V Voltage on pin SW and VO (2) Voltage on pin IFB1 to IFB6 (2) Voltage on all other pins (2) Continuous power dissipation See Dissipation Rating Table Operating junction temperature range –40 to 150 °C Storage temperature range –65 to 150 °C 260 °C Lead temperature (soldering, 10 sec) (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS RθJA TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING TPS61180/1/2RTE (1) 270°C/W 370 mW 204 mW 148 mW TPS61180/1/2RTE (2) 48.7°C/W 2.05 W 1.13 W 821 mW PACKAGE (1) (2) 4 The JEDEC low-K (1s) board used to derive this data was a 3in×3in, two-layer board with 2-ounce copper traces on top of the board. The JEDEC high-K (2s2p) board used to derive this data was a 3in×3in, multilayer board with 1-ounce internal power and ground. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Vbat Battery input voltage range 5.0 24 V Cin IC supply voltage range 2.7 3.6 V VO Output voltage range Vin 38 V L Inductor 4.7 10 µH CI Input capacitor CO Output capacitor FPWM PWM dimming frequency TA Operating ambient temperature TJ Operating junction temperature –40 µF 1 10 µF 0.1 1 kHz –40 85 °C 125 °C 2.2 ELECTRICAL CHARACTERISTICS VBAT = 10.8 V, 0.1 µF at Cin, EN = Logic High, IFB current = 15m A, IFB voltage = 500 mV, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VBAT Battery input voltage range 5.0 24 V Vcc IC supply voltage range TPS61180 only 2.7 Vcin Cin pin output voltage TPS61181/TPS61182 only 2.7 3.15 3.6 V 3.15 3.6 Iq_bat Operating quiescent current into VBAT Device enable, switching no load, Vin = 24 V Iq_Vcc Operating quiescent current into Cin pin TPS61180 only IQ_sw Operating quiescent current into VO VO = 35V ISD Shutdown current EN=GND Vcc_UVLO Cin pin under-voltage lockout threshold TPS61180 only Vbat_UVLO VBAT under-voltage lockout threshold When Vin ramp down 4.2 4.5 Vbat_hys VBAT under-voltage lockout hysteresis When Vin ramp up 300 TPS61180 1 TPS61181/2 3 V mA 2 mA 50 µA 2 18 µA 2.2 2.4 V V mV EN AND DCTRL VH Logic high voltage VL Logic low voltage RPD Pull down resistor on both pins TSD EN pulse width to shutdown 1.2 V 0.4 400 EN high to low 800 V 1600 kΩ TPS61180/1 27 37 ms TPS61182 21 28 CURRENT REGULATION VISET ISET pin voltage 1.204 1.229 1.253 KISET Current multiple Iout/ISET ISET current = 15 µA and 25 µA 970 1000 1030 IFB Current accuracy Riset = 62K 19.4 20 20.6 Km (Imax–Imin)/IAVG ISET current = 15 µA and 25 µA 1 2.5 % Ileak IFB pin leakage current IFB voltage = 20 V on all pins 3 µA IIFB_MAX Current sink max output current IFB = 425 mV 25 V mA mA BOOST OUTPUT REGULATION VIFB_L VO dial up threshold Measured on VIFB(min) 400 mV VIFB_H VO dial down threshold Measured on VIFB(min) 700 mV Vreg_L Min Vout regulation voltage Vo_step VO stepping voltage 16 V 100 150 mV 0.2 0.45 Ω 300 Ω POWER SWITCH RPWM_SW PWM FET on-resistance Rstart Start up charging resistance VO = 0 V 100 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 5 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) VBAT = 10.8 V, 0.1 µF at Cin, EN = Logic High, IFB current = 15m A, IFB voltage = 500 mV, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS Vstart_r Isolation FET start up threshold VIN–VO, VO ramp up ILN_NFET PWM FET leakage current VSW = 35 V, TA = 25°C MIN TYP MAX 1.2 2 UNIT V 1 µA OSCILLATOR fS Oscillator frequency Dmax Maximum duty cycle Dmin Minimum duty cycle TPS61182 1.2 1.3 1.5 TPS61180/1 0.9 1.0 1.2 IFB = 0 V 85 94 MHz % 7 % OS, SC, OVP AND SS ILIM N-Channel MOSFET current limit D = Dmax 1.5 3 A Vovp VO overvoltage threshold Measured on the VO pin 38 39 40 V Vovp_IFB IFB overvoltage threshold Measured on the IFBx pin 15 17 20 V Vsc Short circuit detection threshold VIN-VO, VO ramp down 1.7 2.5 Vsc_dly Short circuit detection delay during start up VIFB_nouse IFB no use detection threshold TPS61180 Only V 32 ms 0.6 V Fault OUTPUT Vfault_high Fault high voltage Measured as Vbat–VFault Vfault_low Fault low voltage Measured as Vbat–VFault, sink 0.1mA, Vin = 15 V 0.1 6 8 V 10 V THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold Thysteresis Thermal shutdown threshold hysteresis 6 Submit Documentation Feedback 160 °C 15 °C Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS Table of Graphs Figure Load Efficiency TPS61181 Vbat= 11V; VO=28.8V, 23.2V and 17.6V; L=4.7uH Figure 2 Load Efficiency TPS61181 Vbat= 11V; VO=36.2V and 31.6V; L=4.7uH Figure 3 Load Efficiency TPS61181 Vbat= 11V; VO=28.8V; L=4.7uH, L=10uH Figure 4 Load Efficiency TPS61181 Vbat= 7V, 11V and 19V; VO=28.8V; L=4.7uH Figure 5 PWM Dimming Efficiency Vbat= 7V, 11V and 19V; VO=28.8V; Iset= 20µA; PWM Freq = 200Hz Figure 6 PWM Dimming Efficiency Vbat= 7V, 11V and 19V; VO=36.2V; Iset= 20µA; PWM Freq = 200Hz Figure 7 Dimming Linearity Vbat= 11V; VO=28.8V; Iset= 20µA; PWM Freq = 1kHz Figure 8 Dimming Linearity Vbat= 11V; VO=28.8V; Iset= 20µA; PWM Freq = 200Hz Figure 9 Output Ripple VO=28.8V; Iset= 20µA; PWM Freq = 200Hz; Duty = 50% Figure 10 Switching Waveform Vbat= 11V; Iset= 20µA Figure 11 Output Ripple at PWM Dimming Vbat= 11V; Iset= 20µA; PWM Freq = 200Hz; Duty = 50%; CO=4.7µF Figure 12 Short Circuit Protection Vbat= 11V; Iset= 20µA Figure 13 Open WLED Protection Vbat= 11V; Iset= 20µA Figure 14 Startup Waveform Vbat= 11V; Iset= 20µA Figure 15 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 98 Vbat = 11 V Vbat = 11 V 96 98 VO = 17.6 V 96 VO = 23.2 V Efficiency - % Efficiency - % 92 90 VO = 28.8 V 88 92 90 86 84 84 82 82 80 25 50 100 75 IO - Output Current - mA 125 150 VO = 36.2 V 88 86 80 0 VO = 31.6 V 94 94 0 Figure 2. 25 50 100 75 IO - Output Current - mA 125 150 Figure 3. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 7 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 Vbat = 11 V 98 98 Vbat = 19 V 96 96 10 mH 94 Efficiency - % Efficiency - % 94 92 4.7 mH 90 88 92 90 Vbat = 7 V 88 86 86 84 84 VO = 28.8 V, TPS61181 82 80 0 25 50 100 75 IO - Output Current - mA 80 150 125 VO = 28.8 V, TPS61181 82 0 25 Figure 5. EFFICIENCY vs DIMMING DUTY CYCLE EFFICIENCY vs DIMMING DUTY CYCLE 100 90 Vbat = 11 V Efficiency - % Efficiency - % 90 150 125 Vbat = 19 V Vbat = 19 V Vbat = 7 V 80 70 VO = 28.8 V, TPS61181 60 Vbat = 11 V 80 Vbat = 7 V 70 60 VO = 36.2 V - TPS61181 ISET = 20 mA, Dimming Frequency = 200 Hz 8 50 100 75 IO - Output Current - mA Figure 4. 100 50 Vbat = 11 V 0 10 20 30 40 50 60 70 80 PWM Dimming Duty Cycle - % Figure 6. 90 100 ISET = 20 mA Dimming Frequency = 200 Hz 50 0 10 Submit Documentation Feedback 20 30 40 50 60 70 80 PWM Dimming Duty Cycle - % 90 100 Figure 7. Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 PWM DIMMING LINEARITY 200Hz 140 120 120 IO - Output Current - mA IO - Output Current - mA PWM DIMMING linearity 1kHz 140 100 80 60 40 80 60 40 TPS61181 ISET = 20 mA, Dimming Frequency = 1 kHz 20 0 0 100 10 20 30 40 50 60 70 80 PWM Dimming Duty Cycle - % 90 TPS61181 ISET = 20 mA, Dimming Frequency = 200 Hz 20 0 100 0 10 20 30 40 50 60 70 80 PWM Dimming Duty Cycle - % Figure 8. 90 100 Figure 9. PWM DIMMING OUTPUT RIPPLE CO=4.7µF vs INPUT VOLTAGE 350 Output Ripple Peak to Peak - mV 300 L = 4.7 mH 250 200 L = 10 mH 150 VO = 28.8 V, TPS61181 100 ISET = 20 mA, Dimming Frequency = 200 Hz 50 5 7.5 10 12.5 Vbat - V 15 17.5 20.0 Figure 10. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 9 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 SWITCHING WAVEFORM OUTPUT RIPPLE AT PWM DIMMING CO=4.7µF Vbat 100 mV/div, AC DCTRL 5 V/div, DC SW 20 V/div, DC VO 100 mV/div, AC VO 100 mV/div, AC Inductor Current 1 A/div, DC Inductor Current 1 A/div, DC t - Time - 1 ms/div t - Time - 2 ms/div Figure 11. Figure 12. OUTPUT SHORT PROTECTION OPEN WLED PROTECTION Fault 5 V/div, DC Fault 5 V/div, DC VO 20 V/div, DC VO 20 V/div, DC Inductor Current 5 A/div, DC Inductor Current 1 A/div, DC t - Time - 1 s/div t - Time - 100 ms/div Figure 13. Figure 14. STARTUP WAVEFORM EN 5 V/div, DC VO 10 V/div, DC Inductor Current 1 A/div, DC WLED Current 20 mA/div, DC t - Time - 10 ms/div Figure 15. 10 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 DETAILED DESCRIPTION Recently, WLEDs have gained popularity as an alternative to CCFL for backlighting media size LCD displays. The advantages of WLEDs are power efficiency and low profile design. Due to the large number of WLEDs, they are often arranged in series and parallel, and powered by a boost regulator with multiple current sink regulators. Having more WLEDs in series reduces the number of parallel strings and therefore improves overall current matching. However, the efficiency of the boost regulator declines due to the need for high output voltage. Also, there have to be enough WLEDs in series to ensure the output voltage stays above the input voltage range. Otherwise, a buck-boost (for example, SEPIC) power converter has to be adopted which could be more expensive and complicated. The TPS61180/1/2 family of ICs have integrated all the key function blocks to power and control up to 60 WLEDs. The devices include a 40V/1.5A boost regulator, six 25mA current sink regulators and protection circuit for over-current, over-voltage and short circuit failures. The key advantages of the devices are small solution size, low output AC ripple during PWM dimming control, and the capability to isolate the input and output during fault conditions. SUPPLY VOLTAGE The TPS61181/2 ICs have built-in LDO linear regulator to supply the IC analog and logic circuit. The LDO is powered up when the EN pin is high. The output of the LDO is connected to the Cin pin. A 0.1µF bypass capacitor is required for LDO’s stable operation. Do not connect the Cin pin to the EN pin because this prevents the IC from starting up. In addition, avoid connecting the Cin pin to any other circuit as this could introduce noise into the IC supply voltage. The TPS61180 has no built-in LDO linear regulator, and therefore requires an external supply voltage in the range of 2.7V to 3.6V connected to the Cin pin. The benefit of using external supply is to reduce the power losses incurred by the LDO as it provides the IC supply current. This loss could become a significant percentage of total output power under light load condition. The Cin pin has 2.2V (typical) under-voltage lock out which turns off the IC when the Cin pin voltage is below this threshold. The voltage on the VBAT pin is the reference for the pull-up circuit of the Fault pin. In addition, it also serves as the input signal to the short circuit protection. For TPS61181/2 ICs, the VBAT connects to the input of the internal LDO, and powers the IC. There is an under-voltage lockout on the VBAT pin which disables the IC when its voltage reduces to 4.2V (Typical). The IC restarts when the VBAT pin voltage recovers by 300mV. BOOST REGULATOR The boost regulator is controlled by current mode PWM, and loop compensation is integrated inside the IC. The internal compensation ensures stable output over the full input and output voltage range. The TPS61180/1 switches at 1.0MHz, and the TPS61182 switches at 1.3MHz. The switching frequencies of the two devices, including their tolerance, due not over-lap. Therefore, in the unlikely event that one device creates electromagnetic inference to the system; the other device, switching at a different frequency, can provide an alternative solution. The output voltage of the boost regulator is automatically set by the IC to minimize the voltage drop across the IFB pins. The IC automatically regulates the lowest IFB pin to 400mV, and consistently adjusts the boost output voltage to account for any changes of the LED forward voltages. When the output voltage is too close to the input, the boost regulator may not be able to regulate the output due to the limitation of minimum duty cycle. In this case, increase the number of WLED in series or include series ballast resistors in order to provide enough headroom for the boost operation. The TPS61180/1/2 boost regulators cannot regulate their outputs to voltages below 15V. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 11 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 CURRENT PROGRAM AND PWM DIMMING The six current sink regulators can each provide maximum 25mA. The IFB current must be programmed to highest WLED current expected using the ISET pin resistor and the following Equation 1. V I FB + KISET ISET R ISET (1) Where KISET = Current multiple (1000 typical) VISET = ISET pin voltage (1.229 V typical) RISET = ISET pin resistor The TPS61180/1/2 ICs have built-in precise current sink regulator. The current matching among 6 current sinks is below 2.5%. This means the differential value between the maximum and minimum current of the six current sinks divided by the average current of the six is less than 2.5%. The WLED brightness is controlled by the PWM signal on the DCTRL pin. The frequency and duty cycle of the DCTRL signal is replicated on the IFB pin current. Keep the dimming frequency in the range of 100Hz to 1kHz to avoid screen flickering and maintain dimming linearity. Screen flickering may occur if the dimming frequency is below the range. The TPS61180/1/2 ICs are designed to minimize the AC ripple on the output capacitor during PWM dimming. Careful passive component selection is also critical to minimize AC ripple on the output capacitor. See APPLICATION INFORMATION for more information. ENABLE AND START UP A logic high signal on the EN pin turns on the IC. For the TPS61181/2 ICs, taking EN high turns on the internal LDO linear regulator which provides supply IC current. For all devices, an internal resistor Rstart (start up charging resistor) is connected between the VBAT pin and VO pin to charge the output capacitor toward Vin. The Fault pin outputs high during this time, and thus the external isolation PFET is turned off. Once the VO pin voltage is within 2 V (isolation FET start up threshold) of the VBAT pin voltage, Rstart is open, and the Fault pin pulls down the gate of the PFET and connects the VBAT voltage to the boost regulator. This operation is to prevent the in-rush current due to charging the output capacitor. Once the isolation FET is turned on, the IC starts the PWM switching to raise the output voltage above VBAT. Soft-start is implemented by gradually ramping up the reference voltage of the error amplifier to prevent voltage over-shoot and in-rush current. See the start-up waveform of a typical example, Figure 15. Pulling the EN pin low for 32ms (typical) shuts down the IC, resulting in the IC consuming less than 50µA in the shutdown mode. OVER-CURRENT, OVER-VOLTAGE AND SHORT-CIRCUIT PROTECTION The TPS61180/1/2 family has pulse by pulse over-current limit of 1.5A (min). The PWM switch turns off when the inductor current reaches this current threshold. The PWM switch remains off until the beginning of the next switching cycle. This protects the IC and external component under over-load conditions. When there is sustained over-current condition for more than 16ms ( under 100% dimming duty cycle), the IC turns off and requires PER or the EN pin toggling to restart. Under severe over-load and/or short circuit conditions, the VO pin can be pulled below the input (VBAT pin). Under this condition, the current can follow directly from input to output through the inductor and Schottky diode. Turning off the PWM switch alone does not limit current anymore. In this case, the TPS61180/1/2 ICs detect the output voltage is 1V (short circuit detection threshold) below the input voltage, turns off the isolation FET, and shuts down the IC. The IC restarts after input power-on reset (VBAT POR) or EN pin logic toggling. During the IC start up, if there is short circuit condition on the boost converter output, the output capacitor will not be charged to within 2V of VBAT through Rstart. After 32ms (short circuit detection delay during start up), the IC shuts down and does not restart until there is VBAT POR or EN pin toggling. The isolation FET is never turned on under the condition. 12 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 For the TPS61181/2 ICs, if one of the WLED strings is open, the boost output rises to over-voltage threshold (39V typical). The IC detects the open WLED string by sensing no current in the corresponding IFB pin. As a result, the IC removes the open IFB pin from the voltage feedback loop. Subsequently, the output voltage drops down and is regulated to a voltage for the connected WLED strings. The IFB current of the connected WLED string keeps in regulation during the whole transition. The IC only shuts down if it detects that all of the WLED strings are open. For the TPS61180, if the IC detects any open WLED string, the IC shuts down and remains off until there is VBAT POR or EN pin toggling. For all the devices, if the over-voltage threshold is reached, but the current sensed on the IFB pin is below the regulation target, the IC regulates the boost output at the over-voltage threshold. This operation could occur when the WLED is turned on under cold temperature, and the forward voltages of the WLEDs exceed the over-voltage threshold. Maintaining the WLED current allows the WLED to warm up and their forward voltages to drop below the over-voltage threshold. For the TPS61181/2 ICs, if any IFB pin voltage exceeds IFB over-voltage threshold (17V typical), the IC turns off the corresponding current sink and removes this IFB pin from VO regulation loop. The remaining IFB pins’ current regulation is not affected. This condition often occurs when there are several shorted WLEDs in one string. WLED mismatch typically does not create such large voltage difference among WLED strings. For the TPS61180 IC, if any IFB pin voltage exceeds IFB over-voltage threshold, the IC shuts down and remains off until there is VBAT POR or EN pin toggling. IFB PIN UNUSED If the application requires less than 6 WLED strings, one can easily disable unused IFB pins. The TPS61181/2 ICs simply require leaving the unused IFB pin open or shorting it to ground. If the IFB pin is open, the boost output voltage ramps up to VO over-voltage threshold during start up. The IC then detects the zero current string, and removes it from the feedback loop. If the IFB pin is shorted to ground, the IC detects the short immediately after IC enable, and the boost output voltage does not go up to VO over-voltage threshold. Instead, it ramps to the regulation voltage after soft start. For the TPS61180, connect a 10 kΩ resistor from the unused IFB pin to ground. After the device is enabled, the IC detects the resistor and disables the IFB pin from the feedback loop. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 13 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 APPLICATION INFORMATION INDUCTOR SELECTION Because the selection of the inductor affects power supply’s steady state operation, transient behavior and loop stability, the inductor is the most important component in switching power regulator design. There are three specifications most important to the performance of the inductor, inductor value, DC resistance and saturation current. The TPS61180/1/2 ICs are designed to work with inductor values between 4.7µH and 10µH. A 4.7µH inductor could be available in a smaller or lower profile package, while 10µH may produce higher efficiency due to lower inductor ripple. If the boost output current is limited by the over-current protection of the IC, using a 10µH inductor can offer higher output current. The internal loop compensation for the PWM control is optimized for the recommended component values, including typical tolerances. Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20 to 35% from the 0A value depending on how the inductor vendor defines saturation In a boost regulator, the inductor DC current can be calculated as V IO I dc + O V in h (2) Where VO = boost output voltage Io = boost output current Vin = boost input voltage η = power conversion efficiency, use 90% for TPS61180/1/2 applications The inductor current peak to peak ripple can be calculated as 1 I + pp L ǒ V 1 V * O bat ) 1 V Ǔ bat FS (3) Where Ipp = inductor peak to peak ripple L = inductor value Fs= Switching frequency Vbat= boost input voltage Therefore, the peak current seen by the inductor is I pp I p + I dc ) 2 (4) Select the inductor with saturation current over the calculated peak current. To calculate the worse case inductor peak current, use minimum input voltage, maximum output voltage and maximum load current. Regulator efficiency is dependent on the resistance of its high current path, switching losses associated with the PWM switch and power diode. Although the TPS61180/1/2 ICs have optimized the internal switch resistance, the overall efficiency still relies on the DC resistance (DCR) of the inductor; lower DCR improves efficiency. However, there is a trade off between DCR and inductor footprint. Furthermore, shielded inductors typically have a higher DCR than unshielded ones. Table 1 lists recommended inductor models. 14 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 Table 1. Recommended Inductor for TPS61180/1/2 L (µH) DCR Typ (mΩ) Isat (A) Size (LXWXH mm) A915AY-4R7M 4.7 38 1.87 5.2x5.2x3.0 A915AY-100M 10 75 1.24 5.2x5.2x3.0 SLF6028T-4R7M1R6 4.7 28.4 1.6 6.0x6.0x2.8 SLF6028T-100M1R3 10 53.2 1.3 6.0x6.0x2.8 TOKO TDK OUTPUT CAPACITOR SELECTION During PWM brightness dimming, the load transient causes voltage ripple on the output capacitor. Since the PWM dimming frequency is in the audible frequency range, the ripple can produce audible noises on the output ceramic capacitor. There are two ways to reduce or eliminate this audible noise. The first option is to select PWM dimming frequency outside the audible range. This means the dimming frequency needs be to lower than 200Hz or higher than 30KHz. The potential issue with low dimming frequency is that WLED on/off can become visible and thus cause a flickering effect on the display. On the other hand, high dimming frequency can compromise the dimming range since the LED current accuracy and current match are difficult to maintain at low dimming duty cycle. The TPS61180/1/2 ICs can support minimum 1% dimming duty cycle up to 1KHz dimming frequency. The second option is to reduce the amount of the output ripple, and therefore minimize the audible noise. The TPS61180/1/2 ICs adopt a patented technology to limit output ripple even with small output capacitance. In a typical application, the output ripple is less than 200mV during PWM dimming with 4.7µF output capacitor, and the audible noise is not noticeable. The devices are designed to be stable with output capacitor down to 1.0µF. However, the output ripple can increase with lower output capacitor. Care must be taken when evaluating a ceramic capacitor’s derating due to applied dc voltage, aging and over frequency. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the switching frequency range of the TPS61180/1/2. So the effective capacitance is significantly lower. Therefore, it may be necessary to use small capacitors in parallel instead of one large capacitor. ISOLATION MOSFET SELECTION The TPS61180/1/2 ICs provide a gate driver to an external P channel MOSFET which can be turned off during device shutdown or fault condition. This MOSFET can provide a true shutdown function, and also protect the battery from output short circuit conditions. The source of the PMOS should be connected to the input, and a pull up resistor is required between the source and gate of the FET to keep the FET off during IC shutdown. To turn on the isolation FET, the Fault pin is pulled low, and clamped at 8 V below the VBAT pin voltage. During device shutdown or fault condition, the isolation FET is turned off, and the input voltage is applied on the isolation MOSFET. During short circuit condition, the catch diode (D2 in typical application circuit) is forward biased when the isolation FET is turned off. The drain of the isolation FET swings below ground. The voltage cross the isolation FET can be momentarily greater than the input voltage. Therefore, select 30V PMOS for 24V maximum input. The on resistor of the FET has large impact on power conversion efficiency since the FET carries the input voltage. Select a MOSFET with Rds(on) less than 100mΩ to limit the power losses. AUDIBLE NOISE REDUCTION Ceramic capacitors can produce audible noise if the frequency of its AC voltage ripple is in the audible frequency range. In TPS61180/1/2 applications, both input and output capacitors are subject to AC voltage ripple during PWM brightness dimming. The ICs integrate a patented technology to minimize the ripple voltage, and thus audible noises. To further reduce the audible noise, one effective way is to use two or three small size capacitors in parallel instead of one large capacitor. The application circuit in Figure 16 uses two 2.2-µF/25V ceramic capacitors at the input and two 1-µF/50V ceramic capacitors at the output. All of the capacitors are in 0805 package. Although the output ripple during PWM dimming is higher than one 4.7µF in a 1206 package, the overall audible noise is lower. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 15 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 In addition, connecting a 10-nF/50V ceramic capacitor between the VO pin and IFB1 pin can further reduce the output AC ripple during the PWM dimming. Since this capacitor is subject to large AC ripple, choose a small package such as 0402 to prevent it from producing noise. LAYOUT CONSIDERATION As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C3 in the typical application circuit, needs not only to be close to the VBAT pin, but also to the GND pin in order to reduce the input ripple seen by the IC. The input capacitor, C1 in the typical application circuit, should be placed close to the inductor. The SW pin carries high current with fast rising and falling edges. Therefore, the connection between the pin to the inductor and Schottky should be kept as short and wide as possible. It is also beneficial to have the ground of the output capacitor C2 close to the PGND pin since there is large ground return current flowing between them. When laying out signal ground, it is recommended to use short traces separated from power ground traces, and connect them together at a single point, for example on the thermal pad. Thermal pad needs to be soldered on to the PCB and connected to the GND pin of the IC. Additional thermal via can significantly improve power dissipation of the IC. ADDITIONAL APPLICATION CIRCUITS Optional 5 V to 24 V C1 2.2 mF Q1 C1a R2 51Ω R3 100 kW L1 10 mH D1 C2 C2a 1 mF 1 mF 10 WLED in series, 120 mA total D2 2.2 mF Fault SW V BAT C3 1 mF VO TPS61181/2 Cin C4 0.1 mF PWM Dimming IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 EN EN C5 10 nF DCTRL ISET PGND GND R1 C1, C1a: Murata GRM219R61E225K C2, C2a: Murata GRM21BR71H105K C3: Murata GRM21BR71H105K C4: Murata GRM185R61A105K C5: Murata GRM155R71H103K L1: TOKO A915AY-100M D1: VISHAY SS2P5-E3/84A Figure 16. Audible Noise Reduction Circuit 16 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 L1 10 mH Optional 5 V to 24 V Q1 C1 4.7 mF R3 100 kW R2 51Ω D2 Fault SW V BAT VO C3 1 mF TPS61181/2 IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 Cin C4 0.1 mF EN/PWM C2 4.7 mF 10 WLED in series,120 mA total D1 EN DCTRL PGND GND ISET R1 62 kW Figure 17. Single Input Control Circuit Optional 5 V to 24 V C1 4.7 mF Q1 R2 51Ω R3 100 kW L1 10 mH SW V BAT C3 1 mF VO TPS61180 Cin C4 0.1uF EN EN DCTRL PWM Dimming C2 4.7 mF 10 WLED in series , 120 mA total D2 Fault 3.3 V D1 ISET IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 PGND GND R1 62 kW Figure 18. TPS61180 Typical Application Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 17 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 Optional 5 V to 24 V C1 4.7 mF L1 10 mH Q1 R2 51 W R3 100 kW C2 4.7 mF D2 Fault SW VBAT C3 1 mF VO TPS61181/2 Cin C4 0.1 mF EN EN PWM 10 WLEDs in Series 20 mA Each String D1 IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 PGND GND DCTRL ISET R1 62 kW S0333-01 Figure 19. TSP61181/2 for Three Strings of LEDs Optional 5 V to 24 V C1 4.7 mF L1 10 mH R2 51 W R3 100 kW C2 4.7 mF D2 Fault C3 1 mF EN VO TPS61181/2 Cin EN PWM SW VBAT C4 0.1 mF DCTRL ISET 10 WLEDs in Series 40 mA Each String D1 Q1 IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 PGND GND R1 62 kW S0334-01 Figure 20. TSP61181/2 for Three Strings of LEDs with Double Current 18 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 TPS61180/1/2 www.ti.com SLVS801A – DECEMBER 2007 – REVISED MARCH 2008 5 V to 24 V C1 4.7 mF L1 10 mH Q1 R2 51 W R3 100 kW C2 4.7 mF D2 Fault SW VBAT C3 1 mF VO TPS61181/2 Cin C4 0.1 mF EN EN PWM 10 WLEDs in Series 72 mA Each String D1 High-Brightness LED Optional IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 PGND GND DCTRL ISET R1 51 kW S0335-01 Figure 21. TSP61181/2 for Two Strings High Brightness LEDs Application C1 4.7 mF L1 10 mH D1 Q1 R2 51 W R3 100 kW C2 4.7 mF D2 Fault C3 1 mF EN VO TPS61181/2 Cin EN PWM SW VBAT C4 0.1 mF DCTRL ISET 10 WLEDs 120 mA High-Brightness LED Optional 5 V to 24 V IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 PGND GND R1 62 kW S0336-01 Figure 22. TSP61181/2 for One String High Brightness LEDs Application Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS61180/1/2 19 PACKAGE OPTION ADDENDUM www.ti.com 20-Mar-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS61180RTER ACTIVE QFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61180RTERG4 ACTIVE QFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61180RTET ACTIVE QFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61180RTETG4 ACTIVE QFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61181RTER ACTIVE QFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61181RTERG4 ACTIVE QFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61181RTET ACTIVE QFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61181RTETG4 ACTIVE QFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61182RTER ACTIVE QFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61182RTERG4 ACTIVE QFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61182RTET ACTIVE QFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61182RTETG4 ACTIVE QFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 20-Mar-2008 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS61180RTER QFN RTE 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q2 TPS61180RTET QFN RTE 16 250 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q2 TPS61181RTER QFN RTE 16 3000 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q2 TPS61181RTET QFN RTE 16 250 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q2 TPS61182RTER QFN RTE 16 3000 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q2 TPS61182RTET QFN RTE 16 250 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS61180RTER QFN RTE 16 3000 340.5 338.1 20.6 TPS61180RTET QFN RTE 16 250 340.5 338.1 20.6 TPS61181RTER QFN RTE 16 3000 340.5 338.1 20.6 TPS61181RTET QFN RTE 16 250 340.5 338.1 20.6 TPS61182RTER QFN RTE 16 3000 340.5 338.1 20.6 TPS61182RTET QFN RTE 16 250 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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