TPS53114 www.ti.com ..................................................................................................................................................................................................... SLVS887 – APRIL 2009 SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS FEATURES APPLICATIONS • High Efficiency, Low-Power Consumption • D-CAP2™ Mode Enables Fast Transient Response • No external parts required for loop compensation • Allows Ceramic Output Capacitor • Integrated Enable Pin to Select POSCAP or Ceramic Capacitor (MLCC) Use • High Initial Reference Accuracy • Low Output Ripple • Wide Input Voltage Range: 4.5V to 24V • Output Voltage Range: 0.76V to 5.5V • Low-Side RDS(on) Loss-less Current Sensing • Adaptive Gate Drivers with Integrated Boost Diode • Adjustable Soft Start • Pre-Biased Soft Start • Selectable Switching frequency 350kHz/700kHz • Built-In 5V Linear Regulator • 1 2 Point-of-load regulation in low power systems for wide range of applications – Digital TV Power Supply – Networking Home Terminal – Digital Set Top Box (STB) – DVD player / recorder – Gaming consoles and other DESCRIPTION The TPS53114 is a single, adaptive on-time D-CAP2™ mode synchronous buck controller. The part enables system designers to cost effectively complete the suite of various end equipment's power bus regulators with a low external component count and low standby consumption. The main control loop for the TPS53114 uses the D-CAP2™ mode topology which provides a very fast transient response with no external components. The TPS53114 also has a PROPRIETARY circuit that enables the device to adapt to not only low equivalent series resistance (ESR) output capacitors such as POSCAP/SP-CAP, but also ceramic using the CER pin. The part provides convenient and efficient operation with conversion voltages from 4.5V to 24V and output voltage from 0.76V to 5.5V. The TPS53114 is available in the 16 pin TSSOP package, and is specified from –40°C to 85°C temperature range. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2 is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS53114 SLVS887 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION CIRCUIT VIN VO 1 R1 VBST 16 DRVH 15 SW 14 DRVL 13 PGND 12 TRIP 11 VREG5 10 TPS53114PWP R2 2 VFB 3 SS 4 GND C7 C3 C2 0.1 mF Q1 10 mFx2 VO (TSSOP16) 5 CER 6 FSEL 7 THERMAL PAD EN V5FILT Q2 C1 R3 C5 C6 8 L1 VIN PGND 4.7 mF VIN 9 C4 1 mF PGND SGND ORDERING INFORMATION TA –40°C to 85°C PACKAGE ORDERING PART NUMBER HTSSOP（Thermal Pad） TPS53114PWPR PINS 16 TPS53114PWP OUTPUT SUPPLY ECO PLAN Tape-and-Reel Green (RoHS & no Sb/Br) Tube ABSOLUTE MAXIMUM RATINGS Operating under free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range Output voltage range VIN, EN –0.3 to 26 VBST –0.3 to 32 VBST(wrt SW) –0.3 to 6 V5FILT, VFB, TRIP, VO, FSEL, CER –0.3 to 6 SW –2 to 26 DRVH –1 to 32 DRVH (wrt SW) –0.3 to 6 DRVL, VREG5, SS –0.3 to 6 PGND Operating ambient temperature range –40 to 85 TSTG Storage temperature range –55 to 150 TJ Junction temperature range –40 to 150 2 V V –0.3 to 0.3 TA (1) UNIT °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 TPS53114 www.ti.com ..................................................................................................................................................................................................... SLVS887 – APRIL 2009 DISSIPATION RATING TABLE (2 oz. trace and copper pad with solder) PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING 16 pin HTSSOP(PWP) 2.73W 16.4mW/°C 1.09W RECOMMENDED OPERATING CONDITIONS MIN Supply input voltage range Input voltage range Output Voltage range MAX VIN 4.5 24 V5FILT 4.5 5.5 VBST –0.1 30 VBST (wrt SW) –0.1 5.5 VFB, VO, FSEL, CER –0.1 5.5 TRIP –0.1 0.3 EN –0.1 24 SW -1.8 24 DRVH –0.1 30 VBST (wrt SW) –0.1 5.5 DRVL, VREG5, SS –0.1 5.5 PGND –0.1 0.1 TA Operating free-air temperature –40 85 TJ Operating junction temperature –40 125 UNIT V V V °C ELECTRICAL CHARACTERISTICS over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT VIN current, TA = 25°C, VREG5 tied to V5FLT, EN = 5V, VFB = 0.8V, SW = 0.5V 350 600 µA VIN current, TA = 25°C, No Load , EN = 0V, VREG5 = ON 28 60 µA 1.0 % 765 775 SUPPLY CURRENT IIN VIN supply current IVINSDN VIN shutdown current VFB VOLTAGE and DISCHARGE RESISTANCE VBG Bandgap Initial regulation accuracy TA = 25°C –1.0 TA = 25°C , FSEL = 0 V, CER = V5FILT 755 TA = –40°C to 85°C, FSEL = 0V, CER = V5FILT 752 TA = 25°C , FSEL = CER = V5FILT 748 TA = –40°C to 85°C, FSEL = CER = V5FILT 745 VVFBTHL VFB threshold voltage VVFBTHH VFB threshold voltage IVFB VFB Input Current VFB = 0.8V, TA = 25°C RDischg Vo Discharge Resistance EN = 0V, VO = 0.5V, TA = 25°C 778 758 768 771 mV mV –0.01 ±0.1 µA 40 80 Ω 5.0 5.2 V VREG5 OUTPUT VVREG5 VREG5 Output Voltage TA=25°C, 5.5V < VIN < 24V, 0 < IVREG5 < 10mA 4.8 VLN5 Line regulation 5.5V < VIN < 24V, IVREG5 = 10mA 20 mV VLD5 Load regulation 1mA < IVREG5 < 10mA 40 mV IVREG5 Output current VIN = 5.5V, VVREG5 = 4.0V, TA = 25°C 170 mA OUTPUT: N-CHANNEL MOSFET GATE DRIVERS RDRVH DRVH resistance RDRVL DRVL resistance Source, IDRVH = –100mA 5.5 11 Sink, IDRVH = 100mA 2.5 5 Source, IDRVL = –100mA 4 8 Sink, IDRVL = 100mA 2 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 Ω Ω 3 TPS53114 SLVS887 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER TD Dead time MIN TYP MAX DRVH-low to DRVL-on CONDITIONS 20 50 80 DRVL-low to DRVH-on 20 40 80 0.7 UNIT ns INTERNAL BST DIODE VFBST Forward Voltage VVREG5-VBST, IF = 10mA, TA = 25°C 0.8 0.9 V IVBSTLK VBST Leakage Current VBST = 29V, SW = 24V, TA = 25°C 0.1 1 µA ON-TIME TIMER CONTROL TONL On Time SW = 12V, VO = 1.8V, FSEL = 0V 390 ns TONH On Time SW = 12V, VO = 1.8V, FSEL = V5FILT 139 ns TOFFL Min off time SW = 0.7V, TA = 25°C, VFB = 0.7V, FSEL = 0V 285 ns TOFFH Min off time SW = 0.7V, TA = 25°C, VFB = 0.7V, FSEL = V5FILT 216 ns SOFT START Issc SS charge current VSS = 0V , SOURCE CURRENT 1.4 2.0 2.6 Issd SS discharge current VSS = 0.5V , SINK CURRRENT 0.1 0.15 Wake up 3.7 4.0 4.3 Hysteresis 0.2 0.3 0.4 2.0 µA mA UVLO VUV5VFILT V5FILT UVLO threshold V LOGIC THRESHOLD VENH EN H-level input voltage EN VENL EN L-level input voltage EN V 0.3 V CURRENT SENSE ITRIP TRIP source current VTRIP = 0.1V, TA = 25°C TCITRIP ITRIP temperature coefficient on the basis of 25°C VOCLoff VRtrip OCP compensation offset Current limit threshold setting range 8.5 10 11.5 4000 (VTRIP-GND-VPGND-SW) voltage, VTRIP-GND = 60mV, TA = 25°C –10 (VTRIP-GND-VPGND-SW) voltage, VTRIP-GND = 60mV –15 15 30 200 mV 120 % VTRIP-GND voltage 0 µA ppm/°C 10 mV mV OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold TOVPDEL Output OVP prop delay VUVP Output UVP trip threshold OVP detect 110 UVP detect 65 Output UVP delay TUVPEN Output UVP enable delay µs 1.5 Hysteresis (recovery <20µs) TUVPDEL 115 UVP enable delay / softstart time 70 75 % µs 10 % 17 30 40 X1.4 X1.7 X2.0 THERMAL SHUTDOWN TSDN Thermal shutdown threshold Shutdown temperature (1) Hysteresis (1) 4 (1) 150 °C 20 Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 TPS53114 www.ti.com ..................................................................................................................................................................................................... SLVS887 – APRIL 2009 PIN ASSIGNMENT (TOP VIEW) VO 1 16 VBST 15 DRVH 14 SW 13 DRVL 12 PGND 11 TRIP VREG5 2 GND 4 CER FSEL 5 EN 7 10 V5FILT 8 9 TPS 531 14 VFB SS 3 6 VIN PIN FUNCTIONS PIN I/O NAME NO. VBST 16 EN SS DESCRIPTION I Supply input for high-side NFET driver (Boost Terminal). Connect capacitor from this pin to SW terminal. An internal PN diode is connected between VREG5 and VBST. User can add external schottky diode if forward drop is critical to drive the NFET. 7 I High level enable pin. 3 O Connect Capacitor from SS pin to GND. VO 1 I Connect to output of converter. This terminal is used for On-Time Adjustment and Output Discharge. VFB 2 I Converter feedback input. Connect with feedback resistor divider. GND 4 I Signal ground pin. DRVH 15 O High-side NFET driver output. SW referenced floating driver. The gate drive voltage is defined by the voltage across VBST to SW node capacitor. SW 14 I/O Switch node connections for high-side driver. Also serves as input to current comparator. DRVL 13 O Synchronous NFET driver output. PGND referenced driver. The gate drive voltage is defined by VREG5 voltage. PGND 12 TRIP 11 I Over current trip point set input. Connect resistor from this pin to GND to set threshold for synchronous FET RDS(on) sense. Voltage across this pin and GND is compared to voltage across PGND and SW by over current comparator. VIN 9 I Supply Input for 5V linear regulator. V5FILT 8 I 5V supply input for the entire control circuit except the NFET driver. Connect Capacitor (typical 1uF) from GND to V5FILT. V5FILT is connected to VREG5 via internal resistor. VREG5 10 O 5V power supply output. VREG5 is connected to V5FILT via internal resistor. CER 5 I Connect to GND for ceramic output capacitors. Connect to V5FILT for polymer electrolyte output capacitors (SP-CAP, POS-CAP, PXE). FSEL 6 I Switching frequency selection pin. Connect to GND for low switching frequency or connect to V5FILT for high switching frequency. I/O Ground return for DRVL. Also serves as input of current comparator. Connect PGND and GND together near the IC. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 5 TPS53114 SLVS887 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN -30% FSELECT UV VREG5 VBST 16 Control Logic 0.1 mF 15 VO OV 1 XCON 15% 14 13 PGND Ref SS 12 PWM 10 mA VFB 2 SW VO DRVL PGND GND TRIP OCP EN 10x2 mF DRVH EN Logic 7 SS Logic 11 LL PGND VIN VIN SS 9 3 UV GND OV 4 UVLO VREG5 Protection 5VREG 10 Logic 4.7 mF TSD CER Ref 5 REF V5FILT TEST 8 TEST BLOCK FSEL 6 FSELECT PowerGood UVLO 1 mF DETAILED DESCRIPTION PWM OPERATION The main control loop of the switching mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2TM Mode. D-CAP2TM mode uses internal compensation circuit and it is suitable for low external component count configuration with appropriate amount of equivalent series resistance (ESR) at the output capacitor(s) and/or ceramic output capacitors. D-CAP2 mode topology integrates a ripple injection circuit to allow use of ceramic output capacitors without external components. It can be stable even if ripple voltage at the output, VO(ripple), is virtually zero. The output ripple valley voltage is monitored at a feedback point voltage. At the beginning of each cycle, the synchronous high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. The one shot timer is determined by the converter’s input voltage, VIN, and the output voltage, VO, to keep frequency fairly constant over the input voltage range, hence it is called adaptive on-time control. The high-side MOSFET is turned on again when the feedback information indicates insufficient output voltage. Repeating the MOSFET operation in this manner, the controller regulates the output voltage. LOW-SIDE DRIVER The low-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). The drive capability is represented by its internal resistance. To prevent shoot through, a dead time is internally generated between high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. 5V bias voltage is delivered from the internal regulator VREG5 output. The instantaneous drive current is supplied by a capacitor connected between VREG5 and GND. The average drive current is equal to the gate charge at Vgs=5V times switching frequency. This gate drive current as well as the high-side gate drive current times 5V approximates the driving power which is dissipated in the TPS53114 package. 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 TPS53114 www.ti.com ..................................................................................................................................................................................................... SLVS887 – APRIL 2009 HIGH-SIDE DRIVER The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as a floating driver, a 5V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by the gate charge at Vgs=5V times switching frequency. The instantaneous drive current is supplied by the capacitor between VBST and SW pins. The drive capability is represented by its internal resistance. PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL The TPS53114 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator; however, the device runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The on-time control is inversely proportional to the input voltage and proportional to the output voltage; therefore, the duty ratio is VO/VIN and has the same cycle time. SOFT START AND PRE-BIASED SOFTSTART The TPS53114 has an adjustable soft-start. When the EN pin becomes high, 2.0µA current begins charging the capacitor which is connected from SS pin to GND. Smooth control of the output voltage is maintained during start up. The TPS53114 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [VFB]), the controller slowly activates synchronous rectification by starting the first DRVL pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensures that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation. SWITCHING FREQUENCY SELECTION Connect FSEL pin to GND for a switching frequency (fSW) is 350kHz. Connect FSEL pin to V5FILT for a switching frequency (fSW) is 700kHz. OUTPUT DISCHARGE CONTROL The TPS53114 discharges the outputs when EN is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-Ω MOSFET which is connected to VO and PGND. The external low-side MOSFET is not turned on during the output discharge operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that, on start, the regulated voltage always initializes from zero volts. CURRENT PROTECTION The TPS53114 has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller retains the OFF state when the inductor current is larger than the over current trip level. In order to provide both accuracy and cost effective solution, the device supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor, Rtrip. The TRIP terminal provides 10µA (Itrip) of current at the ambient temperature and the trip level is set to the OCL trip voltage (Vtrip) as follows. Vtrip (mV) = R trip (kW) ´ 10(mA) (1) The trip level is in the range of 30mV to 200mV over all operational temperatures. The inductor current is monitored by the voltage between PGND pin and SW pin. Itrip has 4000ppm/°C temperature slope to compensate the temperature dependency of RDS(on). PGND is used as the positive current sensing node so that PGND is connected to the source terminal of the bottom MOSFET. As the comparison is done during the OFF state, Vtrip sets the valley level of the inductor current; therefore, the load current at over current threshold, Iocp, can be calculated as follows: Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 7 TPS53114 SLVS887 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Vtrip 1 Iocp = Vtrip RDS(on) + IL1(ripple ) 2 = + RDS(on) 2 ´ L1 ´ ¦ sw ´ (VIN - VO ) ´ VO VIN (2) In an over current condition, the current to the load exceeds the current to the output capacitor; thus, the output voltage tends to fall off. Eventually, it will cross the under voltage protection threshold and shutdown. OVER/UNDER VOLTAGE PROTECTION The TPS53114 monitors a resistor divided feedback voltage to detect over and under voltages. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches the high-side MOSFET driver turns off and the low-side MOSFET driver turns on. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After 30us, the TPS53114 latches off both top and bottom MOSFET drivers. This function is enabled approximately 2.0ms after power-on. The latch off is reset when EN pin goes low. UVLO PROTECTION The TPS53114 has under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin. When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. The UVLO protection is a non-latch protection. THERMAL SHUTDOWN If the temperature exceeds the threshold value (typically 150°C), the drivers will be shut off both DRVH and DRVL are set low, the output discharge function is enabled and the device is shut off. Thermal shutdown is a non-latch protection. TYPICAL CHARACTERISTICS 600 45 f = 350 kHz VO = 1.05 V VREG5 = ON 40 IO(sd) − Shutdown Current − µA ICC − Supply Current − µA 500 400 300 200 FSEL = V5FILT 35 30 FSEL = GND 25 20 15 10 100 5 0 −50 0 50 100 150 TJ − Junction Temperature − °C Figure 1. VIN SUPPLY CURRENT vs. JUNCTION TEMPERATURE 8 0 −50 0 50 100 TJ − Junction Temperature − °C G001 150 G002 Figure 2. VIN SHUTDOWN CURRENT vs. JUNCTION TEMPERATURE Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 TPS53114 www.ti.com ..................................................................................................................................................................................................... SLVS887 – APRIL 2009 TYPICAL CHARACTERISTICS (continued) 500 16 4200ppm/°C for RDS(ON) Compensation 14 FSEL = GND f = 350 kHz f(SW) − Swithing Frequency − kHz I(TRIP) − Source Current − µA 450 12 10 8 6 4 400 VO = 5 V VO = 3.3 V VO = 1.8 V 350 300 VO = 1.05 V VO = 1.2 V 250 2 0 −50 200 0 50 100 150 TJ − Junction Temperature − °C 0 G003 600 500 VO = 1.05 V VO = 1.8 V 25 G004 500 VO = 3.3 V 400 300 VO = 1.05 V VO = 1.2 V FSEL = V5FILT 300 5 20 FSEL = GND VI = 12 V f(SW) − Swithing Frequency − kHz f(SW) − Swithing Frequency − kHz VO = 3.3 V 700 0 15 Figure 4. SWITCHING FREQUENCY (IO = 1 A) vs. INPUT VOLTAGE 600 800 400 10 VI − Input Voltage − V Figure 3. TRIP SOURCE CURRENT vs. JUNCTION TEMPERATURE VO = 5 V 5 10 15 VI − Input Voltage − V 20 25 200 0.0 0.5 1.5 2.0 2.5 3.0 3.5 4.0 IO − Output Current − A G005 Figure 5. SWITCHING FREQUENCY vs. INPUT VOLTAGE 1.0 G006 Figure 6. SWITCHING FREQUENCY vs. OUTPUT CURRENT Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 9 TPS53114 SLVS887 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) 800 1.10 VI = 12 V 1.09 1.08 VO = 3.3 V VO − Output Voltage − V f(SW) − Swithing Frequency − kHz 700 600 500 VO = 1.05 V 400 1.07 FSEL = GND 1.06 1.05 1.04 FSEL = V5FILT 1.03 1.02 300 FSEL = V5FILT VI = 12 V 200 0.0 0.5 1.0 1.01 1.5 2.0 2.5 3.0 3.5 4.0 IO − Output Current − A 1.00 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 IO − Output Current − A G007 Figure 7. SWITCHING FREQUENCY vs. OUTPUT CURRENT 0.5 G008 Figure 8. 1.05-V OUTPUT VOLTAGE vs. OUTPUT CURRENT 1.10 IO = 3 A 1.09 VO − Output Voltage − V 1.08 VO (50mV/div) FSEL = V5FILT 1.07 1.06 FSEL = GND (350 kHz Selection) 1.05 1.04 FSEL = GND 1.03 Iout1 (2A/div) 1.02 1.01 1.00 0 5 10 15 VI − Input Voltage − V 20 25 Figure 9. 1.05-V OUTPUT VOLTAGE vs. INPUT VOLTAGE 10 t − Time − 20 µs/div G009 G010 Figure 10. 1.05-V LOAD TRANSIENT RESPONSE Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 TPS53114 www.ti.com ..................................................................................................................................................................................................... SLVS887 – APRIL 2009 TYPICAL CHARACTERISTICS (continued) EN VO (50mV/div) SS FSEL = V5FILT (700 kHz Selection) VO = 1.05 V Iout2 (2A/div) CSS = 4700 pF t − Time − 20 µs/div t − Time − 2 ms/div G011 G012 Figure 12. STARTUP WAVEFORM 100 100 90 90 80 80 70 70 η − Efficiency − % η − Efficiency − % Figure 11. 1.05-V LOAD TRANSIENT RESPONSE 60 50 40 30 60 50 40 30 20 20 FSEL = GND 350 kHz Selection VI = 12 V 10 0 0.0 0.5 1.0 1.5 2.0 2.5 IO − Output Current − A 3.0 3.5 FSEL = V5FILT 700 kHz Selection VI = 12 V 10 4.0 0 0.0 1.0 1.5 2.0 2.5 3.0 3.5 IO − Output Current − A G013 Figure 13. 1.05-V EFFICIENCY vs. OUTPUT CURRENT 0.5 4.0 G014 Figure 14. 1.05-V EFFICIENCY vs. OUTPUT CURRENT Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 11 TPS53114 SLVS887 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION CHOOSE INDUCTOR The inductance value should be determined, using Equation 3, to give the ripple current a value of approximately 1/4 to of the maximum output current. Large ripple current increases output ripple voltage, improves S/N ratio, and contributes to a stable operation. L1 = 1 IL1(ripple) ´ ¦ sw ´ (VIN(max) - VO )´ VO = VIN(max) 3 IO (max) ´ ¦ sw ´ (VIN(max) - VO )´ VO VIN(max) (3) The inductor must have low DCR to achieve ideal efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated using the following (Equation 4). Vtrip (VIN(max) - VO) × VO 1 IL1(peak) = + × RDS(on) L1 × ƒ sw VIN(max) (4) CHOOSE OUTPUT CAPACITOR The capacitor value and ESR determines the amount of output voltage ripple. A ceramic output capacitor is recommended. C1= ñ RESR á (VIN(max) - VO) ´ VO 1 ´ VO(ripple) 8 ´ ¦ sw - RESR IL1(ripple) (5) VO(ripple) IL1(ripple) IC1(rms) = (6) VO ´ (VIN - VO) 12 ´ VIN ´ L1 ´ ¦ sw (7) CHOOSE INPUT CAPACITOR The TPS53114 requires an input decoupling capacitor and may require a bulk capacitor depending on the application. A ceramic capacitor over 10µF is recommended for the decoupling capacitor. The capacitor voltage rating must be greater than the maximum input voltage. CHOOSE BOOTSTRAP CAPACITOR 0.1µF ceramic capacitor must be connected between the VBST and SW pins for proper operation. CHOOSE VREG5 AND V5FILT CAPACITOR A 4.7µF ceramic capacitor must be connected between the VREG5 and GND for proper operation. A 1µF ceramic capacitor must be connected between the V5FILT and GND for proper operation. CHOOSE OUTPUT VOLTAGE RESISTOR The output voltage is set with a resistor divider from output node to the VFB pin. The use of 1% tolerance or better divider resistors are recommended. Start with a 10kΩ for the Rl resistor and use the Equation 8 and Equation 9 to calculate output voltage. 12 æ R1 ö Vout = 0.765 ´ ç 1+ ÷ è R2 ø (FSEL=GND) æ R1 ö Vout = 0.758 × ç 1+ ÷ è R2 ø (FSEL=V5FILT) (8) (9) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 TPS53114 www.ti.com ..................................................................................................................................................................................................... SLVS887 – APRIL 2009 CHOOSE SOFTSTART CAPACITOR Softstart timing equations are as follows: Css × 0.765 Tss = (s) (FSEL=GND) 2e - 6 Css ´ 0.758 Tss = (s) (FSEL=V5FILT) 2e - 6 (10) (11) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53114 13 PACKAGE OPTION ADDENDUM www.ti.com 13-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS53114PWP ACTIVE HTSSOP PWP 16 TPS53114PWPR ACTIVE HTSSOP PWP 16 90 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS53114PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel Diameter Width (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 7.0 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53114PWPR HTSSOP PWP 16 2000 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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