ALSC AS80SSTVF16859-56KT

August 2003
Advance Information
PulseC re AS80SSTVF16859
Š
DDR 13-Bit to 26-Bit Registered Buffer
Features
Recommended Applications
•
•
•
•
•
Differential clock signals
Meets SSTL_2 class II specifications on outputs
Low voltage operation – VDD = 2.3 V to 2.7 V
Available in 64-pin TSSOP and 56-pin VFQFN
packages (MLF2)
•
Pin Configurations
CLK
CLKB
D1
VREF
R
CLK
Q1A
D1
Q1B
To 12 other channels
56 Q8A
VDDQ
Q9A
Q10A
Q11A
Q12A
Q13A
VDDQ
GND
D13
D12
VDD
VDDQ
43 D11
RESETB
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
42 D10
VDDQ
D9
Q12B
D8
Q11B
D7
RESETB Q10B
Q9B
GND
Q8B
CLKB
Q7B
CLK
Q6B
VDDQ
VDD
GND
VREF
VDDQ
D6
Q5B
D5
Q4B
29 D4
Q3B
Q2B
Q1B
AS80SSTVF16859
Q7B 15
Q6B
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
VDDQ
D1
D2
VDD
VDDQ
D3 28
Q7A 1
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B 14
56-Pin VFQFN (MLF2)
8/6/03; v.0.10
Alliance Semiconductor
1
64
2
63
3
62
61
4
5
60
59
6
58
7
57
8
56
9
55
10
54
11
53
12
13
52
51
14
15
50
49
16
48
17
47
18
46
19
20
45
44
21
43
22
42
23
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
64-Pin TSSOP
AS80SSTVF16859
Block Diagram
•
DDR memory modules: PC1600, PC2100,
PC2700, AND PC3200
Provides complete DDR DIMM logic solution with
PCV857
SSTL_2-compatible data registers
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESETB
GND
CLKB
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
6.10 mm body, 0.50 mm pitch
P. 1 of 13
&RS\ULJKW‹$OOLDQFH6HPLFRQGXFWRU$OOULJKWVUHVHUYHG
AS80SSTVF16859
Š
Truth Table1
Inputs
Q outputs
RESETB
CLK
CLKB
D
Q
L
X or floating
X or floating
X or floating
L
H
↑
↓
H
H
H
↑
↓
L
L
H
L or H
L or H
X
Q 02
1 H = high signal level, L = low signal level, ↑ = transition low to high, ↓ = transition high to low, X = don’t care.
2 Output level before the indicated steady state input conditions were established.
Description
The 13-bit to 26-bit PC16859 is a universal bus driver designed for 2.3 V to 2.7 V VDD operation and SSTL_2 I/O
levels, except for the LVCMOS RESETB input.
Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficient noise margins,
whereas RESETB, an LVCMOS asynchronous signal, is intended for use only at power-up. PC16859 supports
low-power standby operation. A logic level low at RESETB assures that all internal registers and outputs (Q) are
reset to the logic low state, and that all input receivers, data (D), and clock (CLK/CLKB) are switched off. Note that
RESETB must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable
during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held
at a logic low level during power-up.
In the DDR DIMM application, RESETB is specified to be completely asynchronous with respect to CLK and
CLKB, therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power
standby state, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the
time to disable the differential input receivers. This ensures there are no glitches on the output. When coming out
of low power standby state, however, the register will become active quickly relative to the time to enable the
differential input receivers. When the data inputs are at a logic level low and the clock is stable during the low-tohigh transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will
remain at a logic low level.
8/6/03, v.0.10
Alliance Semiconductor
P. 2 of 13
AS80SSTVF16859
Š
Pin Configuration (64-Pin TSSOP)
Pin number
1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 20,
21, 22, 23, 24, 25, 28, 29, 30, 31, 32
7, 15, 26, 34, 39, 43, 50, 54, 58, 63
Pin name
Type
Q(13:1)
Output
GND
PWR
6, 18, 27, 33, 38, 47, 59, 64
VDDQ
PWR
35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57, 61, 62
48
49
37, 46, 60
51
D(13:1)
CLK
CLKB
VDD
RESETB
Input
Input
Input
PWR
Input
45
VREF
Input
Pin number
1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 18, 19,
20, 21, 22, 50, 51, 52, 53, 54, 56
37, 48
Pin name
Type
Q(13:1)
Output
GND
PWR
9, 17, 23, 27, 34, 44, 49, 55
VDDQ
PWR
24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47
35
36
26, 33, 45
38
D(13:1)
CLK
CLKB
VDD
RESETB
Input
Input
Input
PWR
Input
32
VREF
Input
–
Center
pad
PWR
Description
Data output
Ground
Output supply voltage, 2.5 V
nominal
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5 V nominal
Reset (active low)
Input reference voltage, 1.25 V
nominal
Pin Configuration (56-Pin MLF2)
8/6/03, v.0.10
Alliance Semiconductor
Description
Data output
Ground
Output supply voltage, 2.5 V
nominal
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5 V nominal
Reset (active low)
Input reference voltage, 1.25 V
nominal
Ground (VFQFN package only)
P. 3 of 13
AS80SSTVF16859
Š
Absolute Maximum Ratings
Storage temperature
- 65° C to +150° C
Supply voltage
-0.5 to 3.6 V
1
Input voltage
Output
-0.5 to VDD + 0.5
voltage1,2
-0.5 to VDD + 0.5
Input clamp current
± 50 mA
Output clamp current
± 50 mA
Continuous output current
± 50 mA
VDD, VDDQ, or GND current/pin
Package thermal impedance
± 100 mA
3
55° C/W
1 The input and output negative voltage ratings may be excluded if the input and output clamp ratings are
observed.
2 This current will flow only when the output is in the high state level V0 > VDDQ.
3 The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only, and functional operation of the device at these or any other conditions
above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions - DDRI / DDR333 (PC1600, PC2100, PC2700)
Guaranteed by design. Not 100% tested in production.
Parameter
VDD
Description
Min
Typ
Max
Units
Supply voltage
2.3
2.5
2.7
V
VDDQ
I/O supply voltage
2.3
2.5
2.7
V
VREF
Reference voltage
1.15
1.25
1.35
V
VTT
Termination voltage
VREF - 0.04
VREF
VREF + 0.04
V
VDD
V
VI
Input voltage
VIH(DC)
DC input high voltage
VIH(AC)
AC input high voltage
VIL(DC)
DC input low voltage
VIL(AC)
AC input low voltage
VIH
Input high voltage level
VIL
Input low voltage level
VICR
0
Data
inputs
RESETB
VID
Common mode input range CLK.
CLKB
Differential input voltage
VIX
Cross-point voltage of differential clock
pair
IOH
VREF + 0.15
V
VREF + 0.31
V
VREF - 0.15
V
VREF - 0.31
V
1.7
0.97
V
0.7
V
1.53
V
0.36
(VDDQ/2) - 0.2
V
(VDDQ/2) + 0.2
V
High-level output current
-20
mA
IOL
Low-level output current
20
mA
TA
Operating free-air temperature
70
°C
8/6/03, v.0.10
0
Alliance Semiconductor
P. 4 of 13
AS80SSTVF16859
Š
Recommended Operation Conditions - DDRI-400 (PC3200)
Guarenteed by design, not 100% tested in production.
Parameter
Min
Typ
Max
Units
Supply Voltage
2.5
2.6
2.7
V
VDDQ
I/O supply voltage
2.5
2.6
2.7
V
VREF
Reference voltage
1.25
1.3
1.35
V
VTT
Termination voltage
VREF - 0.04
VREF
VREF + 0.04
V
VDDQ
V
VDD
VI
Description
Input voltage
VIH(DC)
DC input high voltage
VIH(AC)
AC input high voltage
VIL(DC)
DC input low voltage
VIL(AC)
AC input low voltage
VIH
Input high voltage level
VIL
Input low voltage level
0
VREF + 0.15
Data
Inputs
RESETB
V
VREF + 0.31
V
VREF - 0.15
V
VREF - 0.31
V
1.7
V
0.7
V
1.53
V
VICR
Common mode input range
VID
Differential input voltage
VIX
Cross-point voltage of differential
clock pair
IOH
High-level output current
-16
mA
IOL
Low-level output current
16
mA
TA
Operating free-air temperature
70
°C
8/6/03, v.0.10
CLK,
CLKB
0.97
0.36
(VDDQ/2) - 0.2
0
Alliance Semiconductor
V
(VDDQ/2) + 0.2
V
P. 5 of 13
AS80SSTVF16859
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DC Electrical Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
TA = 0° C to 70° C, VDD = 2.5 ± 0.2 V, and VDDQ = 2.5 ± 0.2 V (unless otherwise stated)
Guaranteed by design. Not 100% tested in production..
Symbol
Parameters
VIK
VOH
VOL
II
IDD
All inputs
Test conditions
VDD
Min
Typ
Max
Units
-1.2
V
II = -18 mA
2.3 V
IOH = -100 µA
2.3 V to
2.7 V
VDD 0.2
V
IOH = -16 mA
2.3 V
1.95
V
IOL = 100 µA
2.3 V to
2.7 V
0.2
V
IOL = 16 mA
2.3 V
0.35
V
VI = VDD or GND
2.7 V
±5
µA
Standby (static)
RESETB = GND
2.7 V
0.01
µA
Operating
(static)
VI = VIH(AC) or VIL(AC),
RESETB = VDD
2.7 V
25
mA
Dynamic
operating (clock
only)
RESETB = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLKB switching
50% duty cycle
2.7 V
IDDD
Dynamic
operating (per
each data input)
RESETB = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLKB = switching
50% duty cycle
30
µA/
clock
MHz
10
µΑ/
clock
MHz/
data
input
IO = 0
2.7 V
One data input switching at
half clock frequency, 50% duty
cycle
rOH
Output high
IOH = -20 mA
2.3 V to
2.7 V
7
20
Ω
rOL
Output low
IOL = 20 mA
2.3 V to
2.7 V
7
20
Ω
rO(D)
|rOH - rOL| each
separate bit
IO = 20 mA, TA = 25° C
2.5 V
4
Ω
VI = VREF ± 310 mV,
VICR = 1.25 V,
VI(PP) = 360 mV
2.5 V
2.5
3.5
pF
2.5 V
2.5
3.5
pF
2.5V
2.5
3.5
pF
Data inputs
Ci
CLK and CLKB
RESETB
8/6/03, v.0.10
VI = VDD or GND
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AS80SSTVF16859
Š
DC Electrical Characteristics - DDRI-400 (PC3200)
TA = 0° C to 70° C, VDD = 2.6 ± 0.1 V, and VDDQ = 2.6 ± 0.1 V (unless otherwise stated)
Guaranteed by design. Not 100% tested in production..
Symbol
Parameters
VIK
VOH
VOL
II
IDD
All inputs
Test conditions
VDD
Min
Typ
Max
Units
-1.2
V
II = -18 mA
2.5 V
IOH = -100 µA
2.5 V to
2.7 V
VDD 0.2
V
IOH = -8 mA
2.5 V
1.95
V
IOL = 100 µA
2.5 V to
2.7 V
0.2
V
IOL = 8 mA
2.5 V
0.35
V
VI = VDD or GND
2.7 V
±5
µA
Standby (static)
RESETB = GND
2.7 V
0.01
µA
Operating
(static)
VI = VIH(AC) or VIL(AC),
RESETB = VDD
2.7 V
25
mA
Dynamic
operating (clock
only)
RESETB = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLKB switching
50% duty cycle
2.7 V
IDDD
Dynamic
operating (per
each data input)
RESETB = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLKB = switching
50% duty cycle
30
µA/
clock
MHz
10
µΑ/
clock
MHz/
data
input
IO = 0
2.7 V
One data input switching at
half clock frequency, 50% duty
cycle
rOH
Output high
IOH = -16 mA
2.5 V to
2.7 V
7
20
Ω
rOL
Output low
IOL = 16 mA
2.5 V to
2.7 V
7
20
Ω
rO(D)
|rOH - rOL| each
separate bit
IO = 20 mA, TA = 25° C
2.6 V
4
Ω
VI = VREF ± 310 mV,
VICR = 1.25 V,
VI(PP) = 360 mV
2.6 V
2.5
3.5
pF
2.6 V
2.5
3.5
pF
2.6V
2.5
3.5
pF
Data inputs
Ci
CLK and CLKB
RESETB
8/6/03, v.0.10
VI = VDD or GND
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P. 7 of 13
AS80SSTVF16859
Š
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted.)
Guaranteed by design. Not 100% tested in production
* This parameter is not necessarily production tested..
VDDQ = 2.5V±0.2V
Symbol
fCLOCK
tW
tACT*
tINACT*
tS
th
Parameters
Min
Max
Clock frequency
Min
Differential inputs active time
Differential inputs inactive
Setup time, slow slew rate
4,5
rate3,5
Hold time, slow slew
2.5
rate4,5
MHz
ns
22
time2
Setup time, fast slew rate3,5
270
2.5
1
Units
Max
200
Pulse duration, CK, CKLB high or low
Hold time, fast slew
VDDQ = 2.6V±0.1V
22
22
ns
22
ns
Data before CLK↑,
CLKB↓
0.75
0.4
ns
0.9
0.6
ns
Data after CLK↑,
CLKB↓
0.75
0.4
ns
0.9
0.6
ns
1 Data inputs must be low a minimum time of tACT max, after RESETB is taken high
2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESETB is taken low
3 For data signal input slew rate > 1 V/ns
4 For data signal input slew rte > 0.5 V/ns and < 1 V/ns
5 CLK, CLKB signals iput slew rates are > 1 V/ns
Switching Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
(Over recommended operating free-air temperature range unless otherwise noted.)
VDD = 2.5 V ± 0.2 V
Symbol
From (input)
To (output)
fmax
tPD
Min
Typ
Max
Units
200
–
–
MHz
CLK, CLKB (TSSOP)
Q
1.1
2.8
ns
CLK, CLKB (VFQFN[MLF2])
Q
1.1
2.8
ns
RESETB
Q
–
5.0
ns
tphl
–
Switching Characteristics - DDRI-400 (PC3200)
(Over recommended operating free-air temperature range unless otherwise noted.)
VDD = 2.6 V ± 0.1 V
Symbol
From (input)
To (output)
fmax
tPD
Min
Typ
Max
210
MHz
Q
tPDSS
CLK, CLKB (VFQFN[MLF2])
Simultaneous switching
Q
2.48
ns
tphl
RESETB
Q
3.5
ns
8/6/03, v.0.10
1.1
Units
Alliance Semiconductor
2.2
ns
P. 8 of 13
AS80SSTVF16859
Š
Parameter Measurement Information (VDD = 2.5 V ± 0.2 V)
VTT
RL = 50 Ω
From output under test
Test point
CL = 30 pF1
Load circuit
1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified).
The outputs are measured one at a time with one transition per measurement.
VTT = VREF = VDDQ/2.
VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
tPLH and tPHL are the same as tpd.
Input active and inactive times
LVCMOS RESETB
VDD/2
Input
IDD
VDD
VDD/2
0V
tinact
1
tact
IDDH
90%
10%
1
IDDL
IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Pulse duration
tw
VREF
Input
VREF
VIH
VIL
Setup and hold times
VI(pp)
VICR
Timing input
ts
Input
8/6/03, v.0.10
VREF
th
VREF
Alliance Semiconductor
VIH
VIL
P. 9 of 13
AS80SSTVF16859
Š
Propagation delay times
VI(pp)
VICR
Timing input
Output
VICR
tPLH
tPHL
VTT
VTT
LVCMOS RESETB
Input
VOH
VOL
VIH
VDD/2
VIL
tPHL
Output
VOH
VTT
VOL
HIGH-TO-LOW SLEW-RATE MEASUREMENT
LOW-TO-HIGH SLEW RATE MEASUREMENT
VOH
dt_r
dV_r
80%
VOH
Output
80%
20%
Output
20%
VOL
dV_f
VOL
dt_f
Output slew rates over recommended operating free-air temperature range (unless otherwise noted)
VCC= 2.5 V + 0.2V *
VCC = 2.6 V + 0.1 V *
Parameter
From
To
Min
Max
Min
Max
Unit
dV/dt_r
20%
80%
1
4
1
4
V/ns
dV/dt_f
80%
20%
1
4
1
4
V/ns
1
V/ns
dV/dt_∆
∗∗
20% or 80% 80% or 20%
1
*For this test condition, VDDQ is always equal to VDD
**Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
8/6/03, v.0.10
Alliance Semiconductor
P. 10 of 13
AS80SSTVF16859
Š
Package Dimensions (64- Pin TSSOP)
Millimeters
c
N
L
E1
E
Index area
Symbol
Min
Max
Min
Max
A
–
1.20
–
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.32
0.041
b
0.17
0.27
0,007
0.011
c
0.09
0.20
0.0035
0.008
D
E
12
D
α
A2
e
b
A1
6.10 mm (240 mil) body,
0.50 mm (0.020 mil) pitch TSSOP
E1
e
A
Seating plane
L
aaa C
N
See variations below
8.10 basic
6.00
6.20
0.50 basic
0.45
0.75
0.319 basic
0.236
0.244
0.020 basic
0.018
0.030
See variations below
α
0°
8°
0°
8°
aaa
–
0.10
–
0.004
Variations:
D (mm)
8/6/03, v.0.10
Inches
D (inch)
N
Min
Max
Min
Max
64
16.90
17.10
0.665
0.673
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AS80SSTVF16859
Š
Package Dimensions (56-Pin MLF2)
0.25 C A
D
Common dimensions
A
D/2
A2
A1
A3
D1
D1/2
0.25 C B
0.18 Dia.
E1
E
E1/2 E/2
Typ
Max
0.85
1.00
0.01
0.05
A2
0.65
0.80
A3
0.20 BSC
D
8.00 BSC
D1
7.75 BSC
E
8.00 BSC
E1
7.75 BSC
A1
θ
Seating plane
P
R
Top view
D2
D2/2
Pin ID
4x P
0.35
(Ne - 1) X e
E2
0.00
12
0.24
0.42
0.60
0.13
0.17
0.23
Pitch variation D
Side view
0.25 C A B
4x P
Min
A
θ
0.20 C B
0.20 C A
Symbol
e
0.50 BSC
N
56
Nd
14
Ne
14
L
0.30
0.40
0.50
b
0.18
0.23
0.30
Q
0.00
0.20
0.45
D2
4.35
4.50
4.65
E2
5.05
5.20
5.35
E2/2
L
e
(Nd - 1) X e
Bottom view
b
A1
Terminal tip
For odd terminal/side
8/6/03, v.0.10
For even terminal/side
Alliance Semiconductor
Cross section
P. 12 of 13
AS80SSTVF16859
Š
Ordering Information
Ordering Number
Marking
Package
AS80SSTVF16859-64TT
AS80SSTVF16859T
64-Pin TSSOP, Tube
AS80SSTVF16859-64TR
AS80SSTVF16859T
64-Pin TSSOP,
Tape & Reel
AS80SSTVF16859-56KT
AS80SSTVF16859K
56-pin MLF2, Tube
AS80SSTVF16859-56KR
AS80SSTVF16859K
56-pin MLF2,
Tape & Reel
8/6/03; v.0.10
Alliance Semiconductor
Qty per Reel Temperature
0°C to 70°C
2500
0°C to 70°C
0°C to 70°C
2500
0°C to 70°C
P. 13 of 13
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