ALSC ASM4SSTVF16859

August 2004
ASM4SSTVF16859
rev 2.0
DDR 13-Bit to 26-Bit Registered Buffer
off. Note that RESETB should be supported with a
Features
LVCMOS level at a valid state since VREF may not be

Differential clock signals.

Meets SSTL_2 class II specifications on
stable during power-up.
outputs.
To ensure that outputs are at a defined logic state before a

Low voltage operation: VDD = 2.3V to 2.7V.
stable clock has been supplied, RESETB must be held at a

Available in 64-pin TSSOP, 64-pin TVSOP,
logic low level during power-up.
and 56-pin VFQFN packages.
In the JEDEC defined Registered DDR DIMM application,
Product Description
RESETB is specified to be asynchronous with respect to
The ASM4SSTVF16859 is a universal 13/26 bit
CLK/CLKB; therefore, no timing relationship can be
register
(D F/F based), designed for 2.3V to 2.7V
guaranteed between the two signals. When entering a
VDD operation. The device supports SSTL_2 I/O
low-power standby state, the register will be cleared and
levels, and is fully compliant with the JEDEC JC40,
the outputs will be driven to a logic low level quickly
JC42.5 DDR I specifications covering PC1600, PC
relative to the time to disable the differential input
2100, PC2700, and PC3200 operational ranges ( DDR
receivers. This ensures there are no “glitches” on any
400 – 200 MHz ). 13/26 bits refers to 2Q outputs for
output. However, when coming out of low power standby
each D input - designed for use in Stacked Registered
mode, the register will become active quickly relative to the
(stacked
time taken to enable the differential input receivers. When
Memory
Devices),
Buffered
DIMM
applications.
the data inputs are at a logic level low and the clock is
stable during the low-to-high transition of RESETB until the
Data flow from D to Q is controlled by the differential
input receivers are fully enabled, the design ensures that
clock (CLK/CLKB) and a control signal (RESETB).
the outputs will remain at a logic low level.
The positive edge of CLK is used to trigger the data
transfer, and CLKB is used to maintain sufficient noise
Applications
margins, whereas RESETB input is designed and
•
intended for use at power-up.
The ASM4SSTVF16859 supports a low power standby
JEDEC and Non-JEDEC DDR Memory Modules
•
Stacked or Planar configurations.
•
Supports PC1600 - PC2100 - PC2700 - PC3200
•
DDR 400 compliant (200MHz+).
mode of operation. A logic level low at RESETB,
•
SSTL_2 I/O.
assures that all internal registers and outputs (Q) are
•
Provides a complete support solution for JEDEC
reset to a logic low state, and that all input receivers,
JC42.5 DIMMs’ when used with the ASM5CVF857
data (D) buffers, and clock (CLK/CLKB) are switched
Zero Delay Buffer.
Alliance Semiconductor
2575, Augustine Drive  Santa Clara, CA  Tel: 408.855.4900  Fax: 408.855.4999  www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004
ASM4SSTVF16859
rev 2.0
Block Diagram
ASM4SSTVF16859
CLK
CLKB
RESETB
D1
VREF
R
CLK
D1
Q1A
Q1B
To 12 other channels
DDR 13-Bit to 26-Bit Registered Buffer
1 of 16
August 2004
ASM4SSTVF16859
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESETB
GND
CLKB
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ASM4SSTVF16859
42
41
40
39
38
37
36
35
34
33
32
31
30
29
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
ASM4SSTVF16859
rev 2.0
Pin Configurations
56-pin VFQFN (MLF2)
64-pin TSSOP
6.10 mm body, 0.50 mm pitch
DDR 13-Bit to 26-Bit Registered Buffer
2 of 16
August 2004
ASM4SSTVF16859
rev 2.0
Pin Descriptions
64-pin TSSOP
Pin #
Pin Name
Type
Description
1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16,
Q (13:1)
O
Data output.
7, 15, 26, 34, 39, 43, 50, 54, 58, 63
GND
P
Ground to entire chip.
6, 18, 27, 33, 38, 47, 59, 64
VDDQ
P
Output supply voltage, 2.5V nominal.
35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57,
D(13:1)
I
Data input.
48
CLK
I
Positive master clock input.
49
CLKB
I
Negative master clock input.
37, 46, 60
VDD
P
Core supply voltage, 2.5V nominal.
51
RESETB
I
Rest Active low.
45
VREF
I
Input reference voltage, 1.25V nominal.
17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
31, 32
61, 62
56-pin MLF2
Pin #
Pin Name
Type
Description
1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16,
Q (13:1)
O
Data output.
37, 48
GND
P
Ground to entire chip.
9, 17, 23, 27, 34, 44, 49, 55
VDDQ
P
Output supply voltage, 2.5V nominal.
24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47
D(13:1)
I
Data input.
35
CLK
I
Positive master clock input.
36
CLKB
I
Negative master clock input.
26, 33, 45
VDD
P
Core supply voltage, 2.5V nominal.
38
RESETB
I
Rest Active low.
32
VREF
I
Input reference voltage, 1.25V nominal.
-
Center Pad
P
Ground (VFQFN package only)
18, 19, 20, 21, 22, 50, 51, 52, 53, 54, 56
DDR 13-Bit to 26-Bit Registered Buffer
3 of 16
August 2004
ASM4SSTVF16859
rev 2.0
Truth Table
Inputs
Q Outputs
RESETB
CLK
CLKB
D
Q
L
X or floating
X or floating
X or floating
L
H
H
H
H
L
L
X
Q 02
H
L or H
L or H
Note:
1. H=High signal level, L=Low signal level,
= transition from low to high,
= transition from high to low, X = don’t care
2. Output level before the indicated steady state input conditions were established.
1
Absolute Maximum Ratings
Min
Max
Unit
Storage Temperature
Parameter
-65
+150
°C
Supply Voltage
-0.5
3.6
V
-0.5
VDD + 0.5
V
-0.5
VDD + 0.5
V
1
Input Voltage
1,2
Output Voltage
Input Clamp Current
± 50
mA
Output Clamp Current
±50
mA
Continuous Output Current
±50
mA
100
mA
55
°C/W
VDD, VDDQ or GND current/pin
3
Package Thermal Impedance
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0 > VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods
can affect device reliability.
DDR 13-Bit to 26-Bit Registered Buffer
4 of 16
August 2004
ASM4SSTVF16859
rev 2.0
Recomended Operating Conditions - DDRI / DDR333 (PC1600, PC2100, PC2700)*
Parameter
Description
Min
Typ
Max
Unit
VDD
Supply voltage
2.3
2.5
2.7
V
VDDQ
I/O supply voltage
2.3
2.5
2.7
V
VREF
Reference voltage
1.15
1.25
1.35
V
VTT
Termination voltage
VREF - 0.04
VREF
VREF + 0.004
V
VI
Input voltage
VDD
V
0
VIH(DC)
DC input high voltage
VREF + 0.15
V
VIH(AC)
AC input high voltage
VREF + 0.31
V
VIL(DC)
DC input low voltage
VIL(AC)
AC input low voltage
Data Inputs
VIH
Input high voltage level
VIL
Input low voltage level
VICR
Common mode input range
VID
Differential input voltage
VIX
Cross-point voltage of differential clock pair
IOH
VREF - 0.15
V
VREF - 0.31
V
1.7
RESETB
V
CLK
0.97
CLKB
0.36
0.7
V
1.53
V
V
(VDDQ/2) - 0.2
(VDDQ/2) +0.2
V
High-level output current
-20
mA
IOl
Low-level output current
20
mA
TA
Operating free-air temperature
70
°C
0
Recomended Operating Conditions - DDRI-400 (PC3200)*
Parameter
Description
Min
Typ
Max
Units
VDD
Supply Voltage
2.5
2.6
2.7
V
VDDQ
I/O supply voltage
2.5
2.6
2.7
V
VREF
Reference voltage
1.25
1.3
1.35
V
VTT
Termination voltage
VREF - 0.04
VREF
VREF + 0.04
V
VI
Input voltage
VDDQ
V
VIH(DC)
DC input high voltage
VIH(AC)
AC input high voltage
VIL(DC)
DC input low voltage
VIL(AC)
AC input low voltage
0
Data Inputs
VIH
Input high voltage level
VIL
Input low voltage level
VICR
Common mode input range
VID
Differential input voltage
VIX
Cross-point voltage of differential clock pair
IOH
RESETB
CLK, CLKB
VREF + 0.15
V
VREF + 0.31
V
VREF - 0.15
V
VREF - 0.31
V
1.7
0.97
V
0.7
V
1.53
V
0.36
(VDDQ/2) - 0.2
V
(VDDQ/2) + 0.2
V
High-level output current
-16
mA
IOL
Low-level output current
16
mA
TA
Operating free-air temperature
70
C
0
DDR 13-Bit to 26-Bit Registered Buffer
5 of 16
August 2004
ASM4SSTVF16859
rev 2.0
* Guaranteed by design. Not 100% production tested.
DC Electrical Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
TA = 0°C to 70°C, VDD = 2.5 ± 0.2V, and VDDQ = 2.5 ± 0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
Symbol
Parameters
Test conditions
VDD
Min
Typ
Units
-1.2
V
VIK
II = -18 mA
VOH
IOH = -100 A
2.3 V to 2.7 V
VDD - 0.2
V
IOH = -16 mA
2.3 V
1.95
V
IOL = 100 A
2.3 V to 2.7 V
0.2
V
IOL = 16 mA
2.3 V
0.35
V
VI = VDD or GND
2.7 V
±5
A
Standby (static) RESETB = GND
2.7 V
0.01
A
2.7 V
25
mA
VOL
II
IDD
All inputs
Operating
(static)
IDDD
Dynamic
2.3 V
Max
VI = VIH(AC) or VIL(AC),
RESETB = VDD
RESETB = VDD, VI = VIH(AC) or
2.7 V
30
A/clock
operating (clock VIL(AC), CLK and CLKB switching
only)
Dynamic
50% duty cycle
MHz
IO = 0
RESETB = VDD, VI = VIH(AC) or
2.7 V
10
/clock
operating (per VIL(AC), CLK and CLKB =
each data
input)
MHz/data
switching 50% duty cycle
input
One data input switching at half
clock frequency, 50% duty cycle
rOH
Output high
IOH = -20 mA
2.3 V to 2.7 V
7
20
W
rOL
Output low
IOL = 20 mA
2.3 V to 2.7 V
7
20
W
rO(D)
|rOH - rOL| each
4
W
separate bit
Ci
Data inputs
IO = 20 mA, TA = 25 C
VI = VREF ± 310 mV, VICR = 1.25 V,
2.5 V
2.5 V
2.5
3.5
pF
2.5 V
2.5
3.5
pF
2.5V
2.5
3.5
pF
VI(PP) = 360 mV
CLK and CLKB
RESETB
VI = VDD or GND
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004
ASM4SSTVF16859
rev 2.0
DC Electrical Characteristics - DDRI - 400 (PC3200)
TA = 0°C to 70°C, VDD = 2.6 ± 0.2V, and VDDQ = 2.6 ± 0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
Symbol
Parameters
Test conditions
VIK
II = -18 mA
VOH
IOH = -100 A
VOL
II
All inputs
IDD
Standby
(static)
Operating
(static)
IDDD
Typ
2.5 V
Max
Units
-1.2
V
2.5 V to 2.7 V
VDD - 0.2
V
2.5 V
1.95
V
IOL = 100 A
2.5 V to 2.7 V
0.2
V
IOL = 8 mA
2.5 V
0.35
V
VI = VDD or GND
2.7 V
±5
A
2.7 V
0.01
A
2.7 V
25
mA
RESETB = GND
VI = VIH(AC) or VIL(AC),
RESETB = VDD
RESETB = VDD, VI = VIH(AC) or
operating
VIL(AC), CLK and CLKB switching
Dynamic
Min
IOH = -8 mA
Dynamic
(clock only)
VDD
50% duty cycle
2.7 V
30
A/clock
MHz
IO = 0
RESETB = VDD, VI = VIH(AC) or
2.7 V
10
/clock
operating (per VIL(AC), CLK and CLKB = switching
each data
input)
MHz/data
50% duty cycle; One data input
input
switching at half clock frequency,
50% duty cycle
rOH
Output high IOH = -16 mA
2.5 V to 2.7 V
7
20
W
rOL
Output low
2.5 V to 2.7 V
7
20
W
rO(D)
|rOH - rOL| each
4
W
separate bit
Data inputs
Ci
IOL = 16 mA
IO = 20 mA, TA = 25 C
VI = VREF ± 310 mV, VICR = 1.25 V,
CLK and CLKB VI(PP) = 360 mV
RESETB
VI = VDD or GND
2.6 V
2.6 V
2.5
3.5
pF
2.6 V
2.5
3.5
pF
2.6V
2.5
3.5
pF
DDR 13-Bit to 26-Bit Registered Buffer
7 of 16
August 2004
ASM4SSTVF16859
rev 2.0
Timing Requirements**
Guaranteed by design. Not 100% production tested.
Symbol
Parameters
VDDQ = 2.5V±0.2V
Min
fCLOCK
tW
tACT*
tINACT*
tS
Max
Clock frequency
Min
Pulse duration, CK, CKLB high or low
270
2.5
Units
Max
200
MHz
2.5
ns
Differential inputs active time
22
22
ns
Differential inputs inactive time
22
22
ns
Data before CLK, CLKB
Setup time, fast slew rate
0.75
0.4
0.9
0.6
0.75
0.4
0.9
0.6
ns
Setup time, slow slew rate
th
VDDQ = 2.6V±0.1V
Hold time, fast slew rate
Data after CLK, CLKB
Hold time, slow slew rate
ns
Note:
1. Data inputs must be low for a minimum time of tACT max, after which RESETB is taken high.
2. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tINACTmax after which RESETB is taken low.
3. For data signal input slew rate >=V/ns
4. For data signal input slew rate >=0.5 V/ns and < 1V/ns
5. CLK,CLKB signals input slew rates are >=1V/ns
Switching Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)**
Symbol
From (input)
To (output)
fmax
tPD
tphl
VDD = 2.5 V ± 0.2 V
Units
Min
Typ
Max
200
–
–
MHz
CLK, CLKB (TSSOP)
Q
1.1
2.8
ns
CLK, CLKB (VFQFN[MLF2])
Q
1.1
2.8
ns
RESETB
Q
–
5.0
ns
–
Switching Characteristics - DDRI-400 (PC3200)**
Symbol
From (input)
To (output)
VDD = 2.6 V ± 0.1 V
Min
fmax
tPD
Typ
Max
210
CLK, CLKB (VFQFN[MLF2])
Q
1.1
Units
MHz
2.2
ns
Q
2.48
ns
Q
3.5
ns
Simultaneous switching
tPDSS
tphl
RESETB
*this parameter is not necessarily production tested.
**Over recommended operating free-air temperature range unless otherwise noted.
DDR 13-Bit to 26-Bit Registered Buffer
8 of 16
August 2004
ASM4SSTVF16859
rev 2.0
Parameter Measurement Information (VDD = 2.5 V ± 0.2 V)
VTT
RL = 50 
From output under test
Test point
1
CL = 30 pF
Load circuit
1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Zo = 50 , input slew rate = 1 V/ns ± 20% (unless otherwise specified).
The outputs are measured one at a time with one transition per measurement.
VTT = VREF = VDDQ/2.
VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
tPLH and tPHL are the same as tpd.
Input active and inactive times
LVCMOS RESETB
VDD /2
Input
IDD
tinact
1
VDD
VDD /2
0V
tact
IDDH
90%
10%
1
IDDL
IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Pulse duration
tw
Input
VREF
VREF
VIH
VIL
Setup and hold times
DDR 13-Bit to 26-Bit Registered Buffer
9 of 16
August 2004
ASM4SSTVF16859
rev 2.0
VI(pp)
VICR
Timing input
ts
Input
th
VREF
VREF
VIH
VIL
Propagation delay times
VI(pp)
Timing input
VICR
Output
VICR
tPLH
tPHL
VTT
VTT
VOH
VOL
LVCMOS RESETB
Input
VIH
VDD /2
VIL
tPHL
Output
VOH
VTT
VOL
Output slew rates over recommended operating free-air temperature range (unless otherwise noted)
Parameter
From
To
VCC= 2.5 V + 0.2V *
VCC = 2.6 V + 0.1 V *
Min
Max
Min
Max
Unit
dV/dt_r
20%
80%
1
4
1
4
V/ns
dV/dt_f
80%
20%
1
4
1
4
V/ns
20% or 80%
80% or 20%
1
V/ns

dV/dt_
1
*For this test condition, VDDQ is always equal to VDD
**Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
DDR 13-Bit to 26-Bit Registered Buffer
10 of 16
August 2004
ASM4SSTVF16859
rev 2.0
DDR 13-Bit to 26-Bit Registered Buffer
11 of 16
August 2004
ASM4SSTVF16859
rev 2.0
Package Dimensions (64- Pin TSSOP)
c
N
Millimeters
L
E1
E
Index area
1 2
D

A2
Seating plane
e
b
A1
Min
Max
Min
Max
A
–
1.20
–
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.32
0.041
b
0.17
0.27
0,007
0.011
c
0.09
0.20
0.0035
0.008
D
A
aaa C
E
E1
e
6.10 mm (240 mil) body,
0.50 mm (0.020 mil) pitch TSSOP
Inches
Symbol
L
See variations below
8.10 basic
6.00
6.20
0.50 basic
0.45
N
0.75
0.319 basic
0.236
0.244
0.020 basic
0.018
0.030
See variations below
a
0
8
0
8
aaa
–
0.10
–
0.004
Variations:
D (mm)
D (inch)
N
64
Min
Max
Min
Max
16.90
17.10
0.665
0.673
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004
ASM4SSTVF16859
rev 2.0
Package Dimensions (56-Pin MLF2)
0.25 C A
D
A
D/2
A2
A1
A3
D1
D1/2
0.25 C B
0.18 Dia.
E1
Symbol
E
Common dimensions
Min
Typ
Max
0.85
1.00
0.01
0.05
A2
0.65
0.80
A3
0.20 BSC
D
8.00 BSC
D1
7.75 BSC
E
8.00 BSC
E1
7.75 BSC
A
E1/2 E/2
A1

0.20 C B
Seating plane
0.20 C A
Top view
Side view
0.00
q
0.25 C A B
4x P
D2
D2/2
Pin ID
12
P
0.24
0.42
0.60
R
0.13
0.17
0.23
4x P
Pitch variation D
0.35
(Ne - 1) X e
E2
E2/2
L
e
(Nd - 1) X e
e
0.50 BSC
N
56
Nd
14
Ne
14
L
0.30
0.40
0.50
b
0.18
0.23
0.30
Q
0.00
0.20
0.45
D2
4.35
4.50
4.65
E2
5.05 b 5.20
5.35
Bottom view
A1
Terminal tip
For odd terminal/side
For even terminal/side
DDR 13-Bit to 26-Bit Registered Buffer
Cross section
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August 2004
ASM4SSTVF16859
rev 2.0
Ordering Information
Ordering Number
Marking
Package
ASM4SSTVF16859-64TT
AS4SSTVF16859T
64-Pin TSSOP, Tube
ASM4SSTVF16859-64TR
AS4SSTVF16859T
64-Pin TSSOP, Tape & Reel
ASM4SSTVF16859-56QT
AS4SSTVF16859Q
56-pin MLF2 - VQFN, Tube
ASM4SSTVF16859-56QR
AS4SSTVF16859Q
56-pin MLF2 - VQFN, Tape &
Qty per Reel
Temperature
0C to 70C
2500
0C to 70C
0C to 70C
2500
0C to 70C
Reel
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August 2004
ASM4SSTVF16859
rev 2.0
Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright ÿ Alliance Semiconductor
All Rights Reserved
Advance Information
Part Number: ASM4SSTVF16859
Document Version: v2.0
© Copyright 2004 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and
Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance.
Alliance reserves the right to change or correct this data at any time, without notice. If the product described
herein is under development, significant changes to these specifications are possible. The information in this
product data sheet is intended to be general descriptive information for potential customers and users, and is
not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not
assume any responsibility or liability arising out of the application or use of any product described herein, and
disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability
or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available
from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and
Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights,
copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties.
Alliance does not authorize its products for use as critical components in life-supporting systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use
and agrees to indemnify Alliance against all claims arising from such use.
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