ALSC ASM4ISSTVF32852

August 2004
ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
Features
To ensure that outputs are at a defined logic state
before a stable clock has been supplied, RESETB must

Differential clock signals.
be held at a logic “Low” level during power-up.

Supports SSTL_2 class II specifications on
inputs and outputs.
In the DDR DIMM application, RESETB is specified to
be asynchronous with respect to CLK/CLKB. Therefore,

Low voltage operation.


no timing relationship can be guaranteed between the
VDD = 2.3V to 2.7V.
Available in 114 ball BGA package.
Industrial temperature range also available.
two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be
driven to a logic “Low” level quickly relative to the time
to disable the differential input receivers. This ensures
there are no “glitches” on any output. However, when
coming out of low power standby state, the register will
Product Description
The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal
bus driver designed for 2.3V to 2.7V VDD operation and
SSTL_2 I/O levels except for the LVCMOS RESETB
input.
become active quickly relative to the time taken to
enable the differential input receivers. When the data
inputs are at a logic level “Low” and the clock is stable
during the “Low-to-High” transition of RESETB until the
input receivers are fully enabled, the design ensures
Data flow from D to Q is controlled by the differential
clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow,
and CLKB is used to maintain sufficient noise margins,
whereas the RESETB, an LVCMOS asynchronous
that the outputs will remain at a logic “Low” level.
Applications

DDR Memory Modules.

Provides complete DDR DIMM logic solution
with ASM5CVF857, ASM4SSTVF16857 and
ASM4SSTVF16859.

SSTL_2 compatible data registers.
signal is intended for use at the time of power-up only.
The ASM4SSTVF32852 supports a low power standby
mode of operation. A logic “Low” level at RESETB,
assures that all internal registers and outputs (Q) are
reset to a logic “Low” state, and that all input receivers,
data (D) buffers, and clock (CLK/CLKB) are switched
off. Please note that RESETB must always be
supported with a LVCMOS levels at a valid logic state
since VREF may not be stable during power-up.
Alliance Semiconductor
2575, Augustine Drive  Santa Clara, CA  Tel: 408.855.4900  Fax: 408.855.4999  www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004
ASM4SSTVF32852
rev 2.0
Block Diagram
CLK
CLKB
Q1A
R
RESETB
CLK
D1
VREF
Q1B
D1
To 23 Other Channels
Pin Configurations
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
114-Pin Ball BGA
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004
ASM4SSTVF32852
rev 2.0
Pin Description
Pin #
Pin Name
Type
Description
R1, P1, N1, N2, M1, L2, L1, K1, K2, J2, J1, H1,
G1, G2, F1, F2, E1, D1, D2, C1, C2, B1, A1, A2
Q (24:1)A
O
Data output.
R6, P6, N6,N5,M6, L5, L6, K6, K5, J5, J6, H6, G6,
G5, F6, F5, E6, D6, D5, C6, C5, B6, A6, A5
Q (24:1)B
O
Data output.
E2, B3, D3, G3, J3, L3, M3, P3, B4, D4, G4, J4,
L4, M4, P4, E5
GND
P
Ground.
B2, M2, P2, C3, E3, F3, H3, K3, N3, C4, E4, F4,
H4, K4, N4, B5, M5, P5
VDDQ
P
Output supply voltage, 2,5V nominal.
W4, V4, U4, W5, W6, V5, T4, V6, U6, U5, T6, T5,
W3, V3, U3, W2, W1, V2, T3, V1, U1, U2, T1, T2
D(24:1)
I
Data input.
A3
CLK
I
Positive master clock input.
A4
CLKB
I
Negative master clock input.
H2, H5, R2, R5
VDD
P
Core supply voltage, 2.5V nominal.
R3
RESETB
I
Reset (Active Low).
R4
VREF
I
Input reference, 1.25V nominal.
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004
ASM4SSTVF32852
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Pin Configuration Assignments
1
2
3
4
5
6
A
Q2A
Q1A
CLK
CLKB
Q1B
Q2B
B
Q3A
VDDQ
GND
GND
VDDQ
Q3B
C
Q5A
Q4A
VDDQ
VDDQ
Q4B
Q5B
D
Q7A
Q6A
GND
GND
Q6B
Q7B
E
Q8A
GND
VDDQ
VDDQ
GND
Q8B
F
Q10A
Q9A
VDDQ
VDDQ
Q9B
Q10B
G
Q12A
Q11A
GND
GND
Q11B
Q12B
H
Q13A
VDD
VDDQ
VDDQ
VDD
Q13B
J
Q14A
Q15A
GND
GND
Q15B
Q14B
K
Q17A
Q16A
VDDQ
VDDQ
Q16B
Q17B
L
Q18A
Q19A
GND
GND
Q19B
Q18B
M
Q20A
VDDQ
GND
GND
VDDQ
Q20B
N
Q22A
Q21A
VDDQ
VDDQ
Q21B
Q22B
P
Q23A
VDDQ
GND
GND
VDDQ
Q23B
R
Q24A
VDD
RESETB
VREF
VDD
Q24B
T
D2
D1
D6
D18
D13
D14
U
D4
D3
D10
D22
D15
D16
V
D5
D7
D11
D23
D19
D17
W
D8
D9
D12
D24
D21
D20
DDR 24-Bit to 48-Bit Registered Buffer
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rev 2.0
Truth Table1
Inputs
Q Outputs
RESET#
CLK
CLK#
D
Q
L
X or floating
X or floating
X or floating
L
H
↑
↓
H
H
H
↑
↓
L
L
H
L or H
L or H
X
Q0
2
Note: 1. H=High signal level, L=Low signal level, ↑= transition from low to high, ↓= transition from high to low, X = don’t care 2.
Output level before the indicated steady state input conditions were established.
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Storage Temperature
-65
+150
°C
Supply Voltage
-0.5
3.6
V
Input Voltage1
-0.5
VDD + 0.5
V
Output Voltage1,2
-0.5
VDD + 0.5
V
Input Clamp Current
± 50
mA
Output Clamp Current
±50
mA
Continuous Output Current
±50
mA
VDD, VDDQ or GND current/pin
100
mA
Package Thermal Impedance3
55
°C/W
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0 > VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged
periods can affect device reliability.
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004
ASM4SSTVF32852
rev 2.0
Recommended Operating Conditions
Guaranteed by design. Not 100% tested in production.
Parameter
Description
Min
Typ
Max
Unit
VDD
Supply voltage
2.3
2.5
2.7
V
VDDQ
Output supply voltage
2.3
2.5
2.7
V
VREF
Reference voltage
1.15
1.25
1.35
V
VTT
Termination voltage
VREF - 0.04
VREF
VREF + 0.04
V
VDDQ
V
VI
Input voltage
0
VIH(DC)
DC input high voltage
VIH(AC)
AC input high voltage
VIL(DC)
DC input low voltage
VREF - 0.15
V
VIL(AC)
AC input low voltage
VREF - 0.31
V
VIH
Data
Inputs
Input high voltage level
VREF + 0.15
V
VREF + 0.31
V
1.7
V
RESETB
VIL
Input low voltage level
VICR
Common mode input range
VID
Differential input voltage
VIX
Cross-point voltage of differential clock pair
IOH
CLK
0.97
CLKB
0.36
(VDDQ/2) - 0.2
0.7
V
1.53
V
V
(VDDQ/2) +0.2
V
High-level output current
-19
mA
IOl
Low-level output current
19
mA
TA
Operating free-air temperature
70
°C
0
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004
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rev 2.0
DC Electrical Characteristics
TA = 0°C to 70°C, VDD = 2.5 ± 0.2V, and VDDQ = 2.5±0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
Symbol
Parameter
VIK
Test conditions
VDDQ
II = -18 mA
Min
Typ
2.3 V
Max
Units
-1.2
V
IOH = -100 A
2.3 V to 2.7 V
VDD - 0.2
V
IOH = -16 mA
2.3 V
2.05
V
IOL = 100 A
2.3 V to 2.7 V
0.2
V
IOL = 16 mA
2.3 V
0.20
V
VI = VDD or GND
2.7 V
±5
A
0.01
A
VOH
VOL
II
All inputs
Standby
(static)
RESETB = GND
IDD
Operating
(static)
Dynamic
operating
(clock only)
VI = VIH(AC) or VIL(AC) ,
40
RESETB = VDD
mA
RESETB = VDD,
VI = VIH(AC) or VIL(AC) ,
IO = 0
2.5V
A/clock
35
CLK and CLKB switching
MHz
50% duty cycle
IDDD
Dynamic
operating
(per each
data input)
RESETB = VDD, VI = VIH(AC) or
VIL(AC), CLK and CLKB =
/clock
switching 50% duty cycle;
7
MHz/data
One data input switching at half
input
clock frequency, 50% duty cycle
rOH
Output high
IOH = -20 mA
2.3 V to 2.7 V
12

rOL
Output low
IOL = 20 mA
2.3 V to 2.7 V
10

|rOH - rOL|
rO(D)
each
IO = 20 mA, T A = 25 C
2.5 V
VI = VREF ± 350 mV, VICR = 1.25 V,
2.5 V
2.5 V
4

2.5
3.5
pF
2.5
3.5
pF
separate bit
Data inputs
Ci
VI(PP) = 360 mV
CLK & CLKB
DDR 24-Bit to 48-Bit Registered Buffer
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rev 2.0
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted).
Symbol
VDD = 2.5V±0.2V
Parameters
Min
fCLOCK
Clock to output time
TRST
Reset to output time
tS
1.9
Setup time, fast slew rate 2,4
Hold time, fast slew rate 2,4
MHz
2.7
ns
4.5
ns
ns
ns
0.7
0.3
Data after CLK, CLKB
Hold time, slow slew rate 3,4
tSL
200
0.5
Data before CLK, CLKB
Setup time, slow slew rate 3,4
th
Max
Clock frequency
TPD
Unit
ns
ns
0.5
Output slew rate
1
4
V/ns
Note:
1. Guaranteed by design, not 100% tested in production.
2. For data signal input slew rate >= 1V/ns
3. For data signal input slew rate >= 0.5 V/ns and < 1V/ns
4. CLK,CLKB signals input slew rates are >=1V/ns
Switching Characteristics
(Over recommended operating free-air temperature range unless otherwise noted.)
Symbol
From (input)
VDD = 2.5 V ± 0.2 V
To (output)
fmax
Units
Min
Typ
Max
200
–
–
MHz
2.7
ns
4.5
ns
tPD
CLK, CLKB
Q
1.9
tphl
RESETB
Q
–
–
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rev 2.0
Parameter Measurement Information (VDD = 2.5 V ± 0.2V)
VTT
RL = 50 
From output under test
Test point
CL = 30 pF1
Load circuit
1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics:

PRR  10 MHz, Zo = 50 , input slew rate = 1 V/ns ± 20% (unless otherwise specified).

The outputs are measured one at a time with one transition per measurement.

VTT = VREF = VDDQ/2.

VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.

VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.

tPLH and tPHL are the same as tpd.
Input active and inactive times
LVCMOS RESETB
VDD/2
Input
IDD
VDD
VDD /2
0V
tinact
1
tact
90%
10%
1
IDDH
IDDL
IDD tested with clock and data inputs held at V
DD
or GND, and I O = 0 mA.
Pulse duration
tw
Input
VREF
VIH
VREF
VIL
Setup and hold times
VI(pp)
VICR
Timing input
ts
Input
VREF
th
VREF
VIH
VIL
DDR 24-Bit to 48-Bit Registered Buffer
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rev 2.0
Propagation delay times
VI(pp)
Timing input
Output
VICR
VICR
tPLH
tPHL
VTT
VTT
LVCMOS RESETB
Input
VOH
VOL
VIH
VDD/2
VIL
tPHL
Output
VTT
VOH
VOL
DDR 24-Bit to 48-Bit Registered Buffer
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ASM4SSTVF32852
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Package Dimensions
114-Pin Ball BGA
Numeric Designations for
Horizontal Grid
C
T
A1
4
3
2
1
b (REF)
A
B
C
D
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
are not used)
d (TYP)
D
-e-
E
h (TYP)
-e-
c (REF)
D
E
16.00
5.50
BSC
BSC
T Min/Max
1.30/1.50
TYP
e
0.80
BSC
BALL GRID
HORIZ
VERT
TOTAL
6
19
114
DDR 24-Bit to 48-Bit Registered Buffer
TYP
d
h Min/Max
0.46
0.31/0.41
REF. DIMENSIONS
b
c
0.80
0.75
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ASM4SSTVF32852
rev 2.0
Ordering Codes
Ordering Number
Marking
Package Type
ASM4SSTVF32852-114BT
AS4SSTVF32852B
114-pin Ball, BGA, tray/tube
ASM4SSTVF32852-114BR
AS4SSTVF32852B
114-pin Ball, BGA, tape and reel
ASM4ISSTVF32852-114BT
AS4ISSTVF32852B
114-pin Ball, BGA, tray/tube
ASM4ISSTVF32852-114BR
AS4ISSTVF32852B
114-pin Ball, BGA, tape and reel
DDR 24-Bit to 48-Bit Registered Buffer
Quantity
per reel
Temperature
0C to 70C
2500
0C to 70C
-40°C to +85°C
2500
-40°C to +85°C
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August 2004
ASM4SSTVF32852
rev 2.0
Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright ÿ Alliance Semiconductor
All Rights Reserved
Advance Information
Part Number: ASM4SSTVF32852
Document Version: v1.1
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and
Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance.
Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is
under development, significant changes to these specifications are possible. The information in this product data
sheet is intended to be general descriptive information for potential customers and users, and is not intended to
operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any
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intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
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manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
DDR 24-Bit to 48-Bit Registered Buffer
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