TI TPS3606

SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
features
typical applications
D Supply Current of 40 µA (Max)
D Precision 3.3-V Supply Voltage Monitor
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Other Voltage Options on Request
Watchdog Timer With 800-ms Time-Out
Backup-Battery Voltage Can Exceed VDD
Power-On Reset Generator With Fixed
100-ms Reset Delay Time
Voltage Monitor for Power-Fail or
Low-Battery Monitoring
Manual Switchover to Battery-Backup
Mode
Manual Reset
Battery Freshness Seal
10-Pin MSOP Package
Temperature Range . . . −40°C to 85°C
Fax Machines
Set-Top Boxes
Advanced Voice Mail Systems
Portable Battery Powered Equipment
Computer Equipment
Advanced Modems
Automotive Systems
Portable Long-Time Monitoring Equipment
Point-of-Sale Equipment
MSOP (DGS) Package
(TOP VIEW)
VOUT
VDD
GND
MSWITCH
PFI
VBAT
RESET
WDI
MR
PFO
description
The TPS3606-33 supervisory circuit monitors and
controls the processor activity. In case of powerfail or brownout conditions, the backup-battery
switchover function of the TPS3606-33 allows a
low-power processor and its peripherals to run
from the installed backup battery without
asserting a reset beforehand.
ACTUAL SIZE
3,05 mm x 4,98 mm
typical operating circuit
Power
Supply
0.1 µF
External
Source
Rx
VDD
VBAT
TPS3606
PFI
Backup
Battery
uC
RESET
RESET
Ry
WDI
I/O
PFO
I/O
MR
Manual
Reset
MSWITCH V
OUT
GND
Switchover
Capacitor
0.1 µF
VCC
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2000−2007, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
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1
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
description (continued)
During power on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1 V.
Thereafter, the supply voltage supervisor monitors VOUT and keeps the RESET output active as long as VOUT
remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state
(high) to ensure proper system reset. The delay time starts after VOUT has risen above VIT. When the supply
voltage drops below VIT, the output becomes active (low) again.
The TPS3606-33 is available in a 10-pin MSOP package and is characterized for operation over a temperature
range of −40_C to 85_C.
PACKAGE INFORMATION
TA
−40°C to 85°C
DEVICE NAME
TPS3606−33DGSR†
MARKING
AKE
† The DGSR passive indicates tape and reel of 2500 parts.
ordering information application specific versions (see Note)
TPS360 6
− 33 DGS
R
Reel
Package
Nominal Supply Voltage
Functionality
Family
NOMINAL VOLTAGE}, VNOM
DEVICE NAME
TPS3606−33 DGS
3.3 V
‡ For other threshold voltages, contact the local TI sales office for
availability and lead-time.
FUNCTION TABLES TPS3606
VDD > VSW
0
VOUT > VIT
0
VDD > VBAT
0
VOUT
VBAT
RESET
0
0
1
0
0
1
0
VDD
VBAT
0
1
1
1
0
VDD
VDD
1
1
1
1
1
VDD
1
PFI > VPFI
PFO
0
0
1
1
CONDITION.: VOUT > VDD(min)
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2
0
1
1
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
functional schematic
TPS3606
MR
MSWITCH
VBAT
+
_
Switch
Control
VOUT
VDD
Reference
Voltage
or 1.15 V
R1
_
+
R2
RESET
Logic
and
Timer
RESET
_
PFO
+
PFI
Oscillator
WDI
Transition
Detector
Watchdog
Logic
and
Control
40 kΩ
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3
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
timing diagram
VBAT
V(BOK)
V(SWP)
V(SWN)
V(IT)
VDD
t
VOUT
V(SWN)
t
RESET
VBAT
VDD
VBAT
VDD
VBAT
NOTES: A. MSWITCH = 0, MR = 1
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GND
3
I
Ground
MR
7
I
Manual reset input
MSWITCH
4
I
Manual switch to force device into battery-backup mode
PFI
5
I
Power-fail comparator input
PFO
6
O
Power-fail comparator output
RESET
9
O
Active-low reset output
VBAT
VDD
10
I
Backup-battery input
2
I
Input supply voltage
VOUT
WDI
1
O
Supply output
8
I
Watchdog timer input
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4
t
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
detailed description
battery freshness seal
The battery freshness seal of the TPS3606 family disconnects the backup battery from the internal circuitry until
it is needed. This ensures that the backup battery connected to VBAT is fresh when the final product is put to
use. The following steps explain how to enable the freshness seal mode:
1. Connect VBAT (VBAT > VBAT(min))
2. Ground PFO
3. Connect PFI to VDD or PFI > V(PFI)
4. Connect VDD to power supply (VDD > VIT)
5. Ground MR
6. Power down VDD
7. The freshness seal mode is entered and pins PFO and MR can be disconnected.
The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied.
power-fail comparator (PFI and PFO)
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail
input (PFI) is compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail
threshold (V(PFI)) of 1.15 V typical, the power-fail output (PFO) goes low. If it goes above V(PFI) plus about 12-mV
hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any
voltages above V(PFI). The sum of both resistors should be about 1 MΩ, to minimize power consumption and
also to ensure that the current in the PFI pin can be neglected compared with the current through the resistor
network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of
sensed voltage.
If the power-fail comparator is unused, connect PFI to ground and leave PFO unconnected.
backup-battery switchover
In the event of a brownout or power failure, it may be necessary to keep a processor running. If a backup battery
is installed at VBAT, the devices automatically connect the processor to backup power when VDD fails. In order
to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, this family of supervisors
does not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 2-Ω
switch) when VOUT falls below V(SWN) and VBAT is greater than VDD. When VDD recovers, switchover is deferred
either until VDD crosses VBAT, or when VDD rises above the threshold (V(SWP).
VDD > VBAT
1
VDD > V(SWN)
1
VOUT
VDD
1
0
0
1
VDD
VDD
0
0
VBAT
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5
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
detailed description (continued)
manual switchover (MSWITCH)
While operating in the normal mode from VDD, the device can be manually forced to operate in the
battery-backup mode by connecting MSWITCH to VDD. The table below shows the different switchover modes.
MSWITCH
GND
VDD mode
Battery-backup mode
VDD
GND
VDD
Status
VDD mode
Switch to battery-backup mode
Battery-backup mode
Battery-backup mode
If the manual switchover feature is not used, MSWITCH must be connected to ground.
watchdog
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also
important to ensure the correct program execution. The task of a watchdog is to ensure that the program is not
stalled in an indefinite loop. The microprocessor, microcontroller, or the DSP has to toggle the watchdog input
within typically 0.8 s to avoid a time-out from occurring. Either a low-to-high or a high-to-low transition resets
the internal watchdog timer. If the input is unconnected, the watchdog is disabled and is retriggered internally.
saving current while using the watchdog
The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily
pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power
consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once
within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead, WDI is externally driven high
for the majority of the time-out period, a current of e.g. 5 V/40 kΩ ≈ 125 µA can flow into WDI.
VOUT
VIT
WDI
t(tout)
RESET
td
td
Undefined
Figure 1. Watchdog Timing
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6
td
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage: VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
MR, WDI, and PFI pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VDD + 0.3 V)
Continuous output current at VOUT: IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA
All other pins, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGS
424 mW
3.4 mW/°C
271 mW
220 mW
recommended operating conditions at specified temperature range
MIN
Supply voltage, VDD
Battery supply voltage, VBAT
Input voltage, VI
High-level input voltage, VIH
MAX
UNIT
1.65
5.5
V
1.5
5.5
V
0
VO + 0.3
V
0.7 x VO
Low-level input voltage, all other pins, VIL
V
0.3 x VO
V
Continuous output current at VOUT, IO
200
mA
Input transition rise and fall rate at WDI, MSWITCH, ∆t/∆V
100
ns/V
34
mV/µs
85
°C
Slew rate at VDD or VBAT
Operating free-air temperature range, TA
−40
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7
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RESET
VOH
High-level output voltage
VOUT = 2 V, IOH = −400 µA
VOUT = 3.3 V IOH = −2 mA
VOUT = 5 V, IOH = −3 mA
VOUT = 1.8 V, IOH = −20 µA
MIN
VOUT = 3.3 V,
VOUT = 5 V,
VBAT > 1.1 V
VDD > 1.4 V,
IO = 5 mA,
IOL = 2 mA
IOL = 3 mA
or
IOL = 20 µA
VDD = 1.8 V
IO = 75 mA,
IO = 150 mA,
VDD = 3.3 V
VDD = 5 V
VDD − 50 mV
VDD − 150 mV
VDD − 250 mV
Battery-backup mode
IO = 4 mA,
IO = 75 mA,
VBAT = 1.5 V
VBAT = 3.3 V
VBAT − 50 mV
VBAT − 150 mV
rds(on)
VDD to VOUT on-resistance
VBAT to VOUT on-resistance
VDD = 3.3 V
VBAT = 3.3 V
VIT
Negative-going input
threshold voltage
(see Notes 3 and 4)
TPS3606x33
V(PFI)
Power-fail input
threshold voltage
PFI
V(SWN)
Battery switch threshold voltage
negative-going VOUT
RESET
PFO
Low-level output voltage
Vres
Power-up reset voltage (see Note 2)
Normal mode
VOUT
NOTES: 2.
3.
4.
5.
V
VOUT − 0.4 V
0.2
0.4
0.4
V
V
V
1
2
1
2
2.87
2.93
2.99
1.13
1.15
1.17
VIT + 1%
VIT + 2%
VIT + 3.2%
Ω
V
V
The lowest supply voltage at which RESET becomes active. tr(VDD) ≥ 15 µs/V.
To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal.
Voltage is sensed at VOUT
For details on how to optimize current consumption when using WDI refer to section detailed description.
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8
UNIT
VOUT − 0.3 V
IOH = −80 µA
IOH = −120 µA
IOL = 400 µA
VOL
MAX
VOUT − 0.4 V
VOUT = 3.3 V,
VOUT = 5 V,
VOUT = 2 V,
PFO
TYP
VOUT − 0.2 V
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
electrical characteristics over recommended operating conditions (unless otherwise noted)
(continued)
PARAMETER
TEST CONDITIONS
VIT
Vhys
MIN
TYP
1.65 V < VIT < 2.5 V
20
2.5 V < VIT < 3.5 V
40
3.5 V < VIT < 5.5 V
50
VPFI
Hysteresis
V(SWN)
MAX
UNIT
12
1.65 V < V(SWN) < 2.5 V
85
2.5 V < V(SWN) < 3.5 V
100
3.5 V < V(SWN) < 5.5 V
110
mV
WDI
WDI = VDD = 5.5 V
MR
MR = 0.7 × VDD, VDD = 5 V
WDI
WDI = 0 V,
MR
MR = 0 V,
Input current
PFI, MSWITCH
VI < VDD
PFO = 0 V,
PFO
PFO = 0 V,
VDD = 1.8 V
VDD = 3.3 V
−0.3
Short-circuit current
PFO = 0 V,
VDD = 5 V
−2.4
IIH
High-level input current
IIL
Low-level input current
II
IOS
150
VDD = 5 V
VDD = 5 V
IDD
VDD supply current
VOUT = VDD
VOUT = VBAT
I(BAT)
VBAT supply current
VOUT = VDD
VOUT = VBAT
Ci
Input capacitance
VI = 0 V to 5 V
−33
µA
−76
−150
−110
−255
−25
25
−1.1
40
8
−0.1
0.1
40
5
nA
mA
µA
µA
A
pF
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = −40°C to 85°C
PARAMETER
tw
TEST CONDITIONS
VDD
MR
Pulse width
WDI
MIN
VIH = VIT + 0.2 V, VIL = VIT − 0.2 V
VDD > VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD
TYP
MAX
UNIT
5
µs
100
ns
switching characteristics at RL= 1 MΩ, CL = 50 pF, TA = −40°C to 85°C
PARAMETER
td
Delay time
t(tout)
Watchdog time-out
tPHL
Propagation (delay) time,
high-to-low-level output
TEST CONDITIONS
VDD to RESET
PFI to PFO
MR to RESET
Transition time
VDD to VBAT
VDD ≥ VIT + 0.2 V,
See timing diagram
MR ≥ 0.7 x VDD,
VDD > VIT + 0.2 V,
VIL = VIT − 0.2 V,
See timing diagram
VIH = VIT + 0.2 V
VIH = V(PFI) + 0.2 V
VIL = V(PFI) − 0.2 V,
VDD ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
VIL = V(BAT) − 0.2 V, VIH = V(BAT) + 0.2 V,
V(BAT) < VIT
MIN
TYP
MAX
UNIT
60
100
140
ms
0.48
0.8
1.12
s
2
5
µs
3
5
µs
0.1
1
µs
3
µs
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9
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
rDS(on)
Static drain-source on-state resistance (VDD to VOUT)
vs Output current
2
Static drain-source on-state resistance (VBAT to VOUT)
vs Output current
3
IDD
Supply current
VIT
Input threshold voltage at RESET
vs Supply voltage
4
vs Battery supply
5
vs Free-air temperature
6
High-level output voltage at RESET
7, 8
VOH
High-level output voltage at PFO
vs High-level output current
VOL
Low-level output voltage at RESET
vs Low-level output current
Minimum pulse duration at VDD
vs Threshold voltage overdrive at VDD
13
Minimum pulse duration at PFI
vs Threshold voltage overdrive at PFI
14
rDS(on) − Static Drain Source On-State Resistance
(V BAT to VOUT) − Ω
rDS(on) − Static Drain Source On-State Resistance
(V DD to VOUT) − Ω
TA = 85°C
1.4
1.3
TA = 25°C
1.2
TA = 0°C
1.1
1
TA = −40°C
VDD = 3.3 V
VBAT = GND
MSWITCH = GND
0.9
0.8
50
75
100
125
150
IO − Output Current − mA
175
200
Figure 2
1.6
VBAT = 3.3 V
MSWITCH = VDD
1.5
TA = 85°C
1.4
1.3
TA = 25°C
1.2
TA = 0°C
1.1
TA = −40°C
1
0.9
50
75
100
125
150
IO − Output Current − mA
Figure 3
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10
11, 12
STATIC DRAIN SOURCE ON-STATE RESISTANCE
(VBAT TO VOUT)
vs
OUTPUT CURRENT
STATIC DRAIN SOURCE ON-STATE RESISTANCE
(VDD TO VOUT)
vs
OUTPUT CURRENT
1.5
9, 10
175
200
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
BATTERY SUPPLY
7
30
VBAT Mode
VBAT = 5 V
MSWITCH = GND
5
TA = −40°C
TA = 0°C
4
TA = 25°C
3
25
I DD(BAT) − Supply Current − µ A
I DD − Supply Current − µ A
6
2
TA = 85°C
20
1
1.5
2 2.5 3 3.5 4
VDD − Supply Voltage − V
4.5
TA = 85°C
TA = −40°C
5
0
5
0
1
2
3
4
V(BAT) − Battery Supply − V
Figure 4
5
6
Figure 5
INPUT THRESHOLD VOLTAGE AT RESET
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
6
VOH − High-Level Output Voltage at RESET − V
1.001
VIT − Input Threshold Voltage at RESET − V
TA = 0°C
10
0
0.5
VDD Mode
VBAT = GND
MSWITCH = GND
TA = 25°C
15
1
0
VBAT Mode
VDD = GND
or
MSWITCH = GND
1
0.999
0.998
0.997
0.996
0.995
−40 −30 −20 −10 0 10 20 30 40 50 60 70 80
TA − Free-Air Temperature − °C
Figure 6
5
VDD = 5 V
VBAT = GND
MSWITCH = GND
TA = −40°C
4
TA = 25°C
TA = 0°C
3
2
TA = 85°C
1
0
−35
−30
−25
−20
−15
−10
−5
IOH − High-Level Output Current − mA
0
Figure 7
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11
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE AT PFO
vs
HIGH-LEVEL OUTPUT CURRENT
6
VOH − High-Level Output Voltage at PFO − V
VOH − High-Level Output Voltage at RESET − V
5.1
Expanded View
5
TA = −40°C
4.9
TA = 25°C
TA = 0°C
4.8
4.7
TA = 85°C
VDD = 5 V
VBAT = GND
MSWITCH = GND
4.6
4.5
−5 −4.5 −4 −3.5
−3 −2.5 −2 −1.5 −1 −0.5
5
TA = −40°C
TA = 25°C
4
TA = 0°C
3
TA = 85°C
2
0
−2.5
0
IOH − High-Level Output Current − mA
Figure 8
VOL − Low-Level Output Voltage at RESET − V
VOH − High-Level Output Voltage at PFO − V
Expanded View
5.50
TA = −40°C
TA = 25°C
TA = 0°C
5.35
5.30
5.25
TA = 85°C
VDD = 5.5 V
PFI = 1.4 V
VBAT = GND
MSWITCH = GND
5.20
5.15
5.10
−200 −180 −160 −140 −120 −100 −80 −60 −40 −20
3.5
VDD = 3.3 V
VBAT = GND
MSWITCH = GND
3
2.5
TA = 0°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = −40°C
0.5
0
0
0
IOH − High-Level Output Current − µA
5
10
15
20
IOL − Low-Level Output Current − mA
Figure 11
Figure 10
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12
0
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
5.55
5.40
−2
−1.5
−1
−0.5
IOH − High-Level Output Current − mA
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE AT PFO
vs
HIGH-LEVEL OUTPUT CURRENT
5.45
VDD = 5.5 V
PFI = 1.4 V
VBAT = GND
MSWITCH = GND
1
25
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
MINIMUM PULSE DURATION AT VDD
vs
THRESHOLD VOLTAGE OVERDRIVE AT VDD
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
10
TA = 85°C
VDD = 3.3 V
VBAT = GND
MSWITCH = GND
400
Minimum Pulse Duration at VDD − µ s
Expanded View
TA = 25°C
300
TA = 0°C
200
TA = −40°C
100
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
IOL − Low-Level Output Current − mA
0
0
5
0.1
0.2
0.3
0.4 0.5
0.6 0.7 0.8 0.9
1
VT(O) − Threshold Voltage Overdrive at VDD − V
Figure 13
Figure 12
MINIMUM PULSE DURATION AT PFI
vs
THRESHOLD VOLTAGE OVERDRIVE AT PFI
5
Minimum Pulse Duration at PFI − µ s
VOL − Low-Level Output Voltage at RESET − mV
500
4.6
VDD = 1.65 V
4.2
3.8
3.4
3
2.6
2.2
1.8
1.4
1
0.6
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VT(O) − Threshold Voltage Overdrive at PFI − V
Figure 14
www.ti.com
13
PACKAGE OPTION ADDENDUM
www.ti.com
29-Nov-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS3606-33DGS
ACTIVE
MSOP
DGS
10
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3606-33DGSG4
ACTIVE
MSOP
DGS
10
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3606-33DGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3606-33DGSRG4
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
TPS3606-33DGSR
11-Jun-2007
Package Pins
DGS
10
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
HNT
330
12
5.3
3.4
1.4
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TPS3606-33DGSR
DGS
10
HNT
358.0
335.0
35.0
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
12
NONE
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