TI TPS3617-50

SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
D Supply Current of 40 µA (Max)
D Battery Supply Current of 100 nA (Max)
D Precision 5-V Supply Voltage Monitor,
D
D
D
D
D
D
D
typical applications
D
D
D
D
D
D
D
D
D
Other Voltage Options on Request
Backup-Battery Voltage Can Exceed VDD
Watchdog Timer With 800-ms Time-Out
Power-On Reset Generator With Fixed
100-ms Reset Delay Time
Voltage Monitor for Power-Fail or
Low-Battery Monitoring
Battery Freshness Seal
8-Pin MSOP Package
Temperature Range . . . –40°C to 85°C
Fax Machines
Set-Top Boxes
Advanced Voice Mail Systems
Portable Battery Powered Equipment
Computer Equipment
Advanced Modems
Automotive Systems
Portable Long-Time Monitoring Equipment
Point of Sale Equipment
MSOP (DGK) Package
(TOP VIEW)
description
The TPS3617-50 supervisory circuit monitors and
controls processor activity by providing backupbattery switchover for data retention of CMOS
RAM.
VOUT
VDD
GND
PFI
VBAT
RESET
WDI
PFO
ACTUAL SIZE
3,05 mm x 4,98 mm
During power on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1 V.
Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains
below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high)
to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage (VIT).
typical operating circuit
Power
Supply
0.1 µF
External
Source
Rx
Ry
VDD
VBAT
TPS3617
PFI
Backup
Battery
uC
RESET
RESET
WDI
I/O
PFO
I/O
Switchover
Capacitor
VOUT
GND
0.1 µF
VCC
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
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1
SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
description (continued)
When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again.
The product spectrum is designed for supply voltages of 5.0 V. The TPS3617-50 is available in a 8-pin MSOP
package and is characterized for operation over a temperature range of –40°C to 85°C.
PACKAGE INFORMATION
TA
–40°C to 85°C
DEVICE NAME
TPS3617–50DGKR†
MARKING
ASD
† The DGKR passive indicates tape and reel of 2500 parts.
ordering information application specific versions
TPS361
7 – 50
DGK
R
NOMINAL VOLTAGE‡, VNOM
DEVICE NAME
Reel
TPS3617–50 DGK
Package
5V
‡ For other threshold voltages, contact the local TI sales office
for availability and lead-time.
Nominal Supply Voltage
Functionality
Family
FUNCTION TABLE
VDD > VIT
0
VDD > VBAT
0
VOUT
VBAT
RESET
0
1
0
1
0
VDD
VDD
1
1
VDD
1
PFI > VPFI
PFO
0
0
1
1
CONDITION: VDD > VDD(min)
2
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0
1
SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
functional schematic
TPS3617
VBAT
+
_
Switch
Control
VOUT
VDD
Reference
Voltage
or 1.15 V
+
_
RESET
Logic
+
Timer
RESET
GND
Oscillator
–
WDI
PFO
+
PFI
Transition
Detector
Watchdog
Logic
+
Control
40 kΩ
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3
SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
timing diagram
VBAT
VDD
VIT
t
VOUT
t
RESET
td
td
t
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GND
3
I
Ground
PFI
4
I
Power-fail comparator input
PFO
5
O
Power-fail comparator output
RESET
7
O
Active-low reset output
VBAT
8
I
Backup-battery input
VDD
VOUT
2
I
Input supply voltage
1
O
Supply output
WDI
6
I
Watchdog input
4
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SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
detailed description
battery freshness seal
The battery freshness seal of the TPS3617 family disconnects the backup battery from the internal circuitry until
it is needed. This ensures that the backup battery connected to VBAT should be fresh when the final product is
put to use. The following steps explain how to enable the freshness seal mode:
1.
2.
3.
4.
Connect VBAT (VBAT > VBAT(min)
Ground PFO
Connect PFI to VDD (PFI = VDD)
Connect VDD to power supply (VDD > VIT) and keep connected for 5 ms < t < 35 ms
The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied.
power-fail comparator (PFI and PFO)
An additional comparator monitors voltages other than the nominal supply voltage. The power-fail-input (PFI)
can be compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail
threshold (V(PFI)) of 1.15 V typical, the power-fail output (PFO) goes low. If it goes above V(PFI) plus about 12-mV
hysteresis, the output returns to high. By connecting two external resistors it is possible to supervise any
voltages above V(PFI). The sum of both resistors should be about 1 MΩ, to minimize power consumption and
also to ensure that the current in the PFI pin can be neglected compared with the current through the resistor
network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of the
sensed voltage. If the power-fail comparator is unused, connect PFI to ground and leave the PFO unconnected.
watchdog
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also
important to ensure correct program execution. The task of a watchdog is to ensure that the program is not
stalled in an indefinite loop. The microprocessor, microcontroller, or DSP has to toggle the watchdog input within
0.8 s typically, to avoid a time out from occurring. Either a low-to-high or a high-to-low transition resets the
internal watchdog timer. If the input is unconnected, the watchdog is disabled and should be retriggered
internally.
saving current while using the watchdog
The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily
pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power
consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once
within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead, WDI is externally driven high
for the majority of the time-out period, a current of e.g. 5.0 V/40 kΩ ≈ 125 µA can flow into WDI.
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SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
detailed description (continued)
VOUT
VIT
WDI
t(tout)
RESET
td
td
td
Undefined
Figure 1. Watchdog Timing
backup-battery switchover
In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery
is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In
order to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, these supervisors
should not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ω
switch) when VDD falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred
either until VDD crosses VBAT, or until VDD rises above the reset threshold VIT. VOUT connects to VDD through
a 1-Ω (max) PMOS switch when VDD crosses the reset threshold.
6
VDD > VBAT
1
VDD > VIT
1
VOUT
VDD
1
0
0
1
VDD
VDD
0
0
VBAT
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SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
VDD – Normal Supply Voltage
backup-battery switchover (continued)
VDD – Mode
VIT Hysteresis
VBAT – Mode
VBSW Hysteresis
Undefined
VBAT – Backup-Battery Supply Voltage
Figure 2. VDD – VBAT Switchover
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage: VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
PFI pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V)
Continuous output current at VOUT: IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
All other pins, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGK
470 mW
3.76 mW/°C
301 mW
241 mW
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SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
recommended operating conditions
Supply voltage, VDD
Battery supply voltage, VBAT
Input voltage, VI
MIN
MAX
UNIT
1.65
5.5
V
1.5
5.5
V
VDD + 0.3
V
0
High-level input voltage, VIH
0.7 x VDD
Low-level input voltage, VIL
V
0.3 x VDD
V
Continuous output current at VOUT, IO
300
mA
Input transition rise and fall rate at MR, ∆t/∆V, WDI
100
ns/V
1
V/µs
85
°C
Slew rate at VDD or VBAT
Operating free-air temperature range, TA
–40
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RESET
VOH
High level output voltage
High-level
PFO
RESET
PFO
VOL
Low-level output voltage
Vres
Power-up reset voltage (see Note 2)
Normal mode
VDD = 1.8 V, IOH = –400 µA
VDD = 3.3 V, IOH = –2 mA
VDD = 5 V,
IOH = –3 mA
VDD = 1.8 V, IOH = –20 µA
VDD = 3.3 V, IOH = –80 µA
VDD = 5 V,
IOH = –120 µA
VDD = 1.8 V, IOL = 400 µA
VDD = 3.3 V, IOL = 2 mA
VDD = 5 V,
IOL = 3 mA
VBAT > 1.1 V, or
VDD > 1.1 V, IOL = 20 µA
IO = 8.5 mA,
VDD = 1.8 V, VBAT = 0 V
IO = 125 mA,
VDD = 3.3 V, VBAT = 0 V
IO = 200 mA,
VDD = 5 V,
VBAT = 0 V
IO = 0.5 mA,
VBAT = 1.5 V, VDD = 0 V
Batter back p mode
Battery-backup
IO = 7.5 mA,
VBAT = 3.3 V, VDD = 0 V
NOTE 2: The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.
VOUT
8
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MIN
TYP
MAX
UNIT
VDD – 0.2 V
VDD – 0.4 V
V
VDD – 0.3 V
VDD – 0.4 V
0.2
0.4
0.4
V
V
VDD – 50 mV
VDD – 150 mV
VDD – 200 mV
VBAT – 20 mV
VBAT – 113 mV
V
SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RDS(on)
DS( )
VDD to VOUT on-resistance
VBAT to VOUT on-resistance
VIT
VPFI
Negative-going
input
Negative
going in
ut threshold voltage
(see Note 3)
TPS3617–50
40°C to 85°C
TA = –40°C
PFI
VIT
Vhys
MIN
VDD = 5 V
VBAT = 3.3 V
Hysteresis
1
8
15
4.46
4.55
4.64
1.13
1.15
1.17
1.65 V < VIT < 2.5 V
20
2.5 V < VIT < 3.5 V
40
3.5 V < VIT < 5..5 V
60
II
Input current
IOS
WDI (see Note 5)
Low-level input current
IDD
VDD supply current
IBAT
VBAT supply current
VDD = 1.8 V
WDI = VDD = 5 V
Ω
V
mV
PFO
55
150
WDI = 0 V, VDD = 5 V
VI < VDD
PFO = 0 V, VDD = 1.8 V
PFI
Short-circuit
Short
circuit current
UNIT
12
VBSW (see Note 4)
High-level input current
MAX
0.6
PFI
IIH
IIL
TYP
–150
–25
25
nA
–0.3
PFO = 0 V, VDD = 3.3 V
–1.1
PFO = 0 V, VDD = 5 V
–2.4
VOUT = VDD
VOUT = VBAT
VOUT = VDD
µA
40
40
–0.1
0.1
VOUT = VBAT
VI = 0 V to 5 V
0.5
mA
µA
µA
Ci
Input capacitance
5
pF
NOTES: 3. To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply
terminals.
4. For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT.
5. For details on how to optimize current consumption when using WDI, refer to detailed watchdog description.
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 85°C
PARAMETER
tw
Pulse width
VDD
WDI
TEST CONDITIONS
VIH = VIT + 0.2 V,
VDD > VIT + 0.2 V
MIN
VIL = VIT – 0.2 V
VIL = 0.3 x VDD, VIH = 0.7 x VDD
TYP
MAX
UNIT
6
µs
100
ns
switching characteristics at RL = 1 MΩ, CL= 50 pF, TA = –40 °C to 85 °C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
td
Delay time
VDD ≥ VIT + 0.2 V,
See timing diagram
60
100
140
t(tout)
Watchdog time-out
VDD > VIT + 0.2 V,
See timing diagram
0.48
0.8
1.12
tPHL
VDD to RESET
VIL = VIT – 0.2 V,
VIH = VIT + 0.2 V
2
5
PFI to PFO
VIL = VPFI – 0.2 V,
VIH = VPFI + 0.2 V
3
5
time high
to low level output
Propagation (delay) time,
high-to-low-level
Transition time
VDD to VBAT
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UNIT
ms
s
µs
3
9
SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
rDS(on)
IDD
VIT
Static drain-source on-state resistance (VDD to VOUT)
vs Output current
3
Static drain-source on-state resistance (VBAT to VOUT)
vs Output current
4
Supply current
vs Supply voltage
5
Input threshold voltage at RESET
vs Free-air temperature
6
7, 8
High-level output voltage at PFO
vss High-level
High le el output
o tp t current
c rrent
VOL
Low-level output voltage at RESET
vs Low-level output current
Minimum pulse duration at VDD
vs Threshold voltage overdrive at VDD
13
Minimum pulse duration at PFI
vs Threshold voltage overdrive at PFI
14
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VDD to VOUT)
vs
OUTPUT CURRENT
1000
VDD = 3.3 V
VBAT = GND
900
TA = 85°C
800
TA = 25°C
700
TA = 0°C
TA = –40°C
600
500
50
75
100
125
150
175
200
– Static Drain-Source On-State Resistance – Ω
VOH
rDS(on)
rDS(on)
– Static Drain-Source On-State Resistance – mΩ
High-level output voltage at RESET
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VBAT to VOUT)
vs
OUTPUT CURRENT
20
VBAT = 3.3 V
17.5
15
TA = 85°C
12.5
TA = 25°C
TA = 0°C
10
7.5
5
2.5
TA = –40°C
4.5
IO – Output Current – mA
6.5
8.5
10.5
12.5
IO – Output Current – mA
Figure 4
Figure 3
10
9, 10
11, 12
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14.5
SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
INPUT THRESHOLD VOLTAGE AT RESET
vs
FREE-AIR TEMPERATURE
30
20
or
TA = 25°C
TA = 0°C
TA = 85°C
15
TA = –40°C
10
5
0
0
1
2
3
4
VDD – Supply Voltage – V
5
1
0.999
0.998
0.997
0.996
0.995
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
6
TA – Free-Air Temperature – °C
Figure 5
Figure 6
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
6
VOH – High-Level Output Voltage at RESET – V
I DD – Supply Current – µ A
25
1.001
VDD Mode
VBAT = GND
VIT – Input Threshold Voltage at RESET – V
VBAT Mode
VBAT = 2.6 V
VDD = 5 V
VBAT = GND
5
TA = –40°C
TA = 25°C
4
TA = 0°C
3
TA = 85°C
2
1
0
–35
–30
–25
–20
–15
–10
–5
0
IOH – High-Level Output Current – mA
Figure 7
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SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE AT PFO
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
6
VOH – High-Level Output Voltage at PFO – V
VOH – High-Level Output Voltage at RESET – V
5.1
Expanded View
5
TA = –40°C
4.9
TA = 25°C
TA = 0°C
4.8
4.7
TA = 85°C
4.6
VDD = 5 V
VBAT = GND
4.5
–5 –4.5 –4 –3.5 –3 –2.5 –2 –1.5 –1 –0.5
5
TA = –40°C
TA = 25°C
4
TA = 0°C
3
TA = 85°C
2
VDD = 5.5 V
PFI = 1.4 V
VBAT = GND
1
0
–2.5
0
–2
–1.5
–1
–0.5
IOH – High-Level Output Current – mA
IOH – High-Level Output Current – mA
Figure 8
Figure 9
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE AT PFO
vs
HIGH-LEVEL OUTPUT CURRENT
VOL – Low-Level Output Voltage at RESET – V
VOH – High-Level Output Voltage at PFO – V
5.55
Expanded View
5.50
TA = –40°C
5.45
5.40
TA = 25°C
TA = 0°C
5.35
5.30
5.25
TA = 85°C
5.20
VDD = 5.5 V
PFI = 1.4 V
VBAT = GND
5.15
5.10
–200 –180 –160 –140 –120 –100 –80 –60 –40 –20
3.5
VDD = 3.3 V
VBAT = GND
3
2.5
TA = 0°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = –40°C
0.5
0
0
IOH – High-Level Output Current – µA
0
5
10
15
20
IOL – Low-Level Output Current – mA
Figure 10
12
0
Figure 11
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25
SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
MINIMUM PULSE DURATION AT VDD
vs
THRESHOLD VOLTAGE OVERDRIVE AT VDD
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
10
Expanded View
Minimum Pulse Duration at VDD – µ s
400
9
TA = 85°C
VDD = 3.3 V
VBAT = GND
TA = 25°C
300
TA = 0°C
200
TA = –40°C
100
8
7
6
5
4
3
2
1
0
0
1
2
3
4
IOL – Low-Level Output Current – mA
0
0
5
0.1
0.2
0.3
0.4 0.5
0.6 0.7 0.8 0.9
1
Threshold Voltage Overdrive at VDD – V
Figure 12
Figure 13
MINIMUM PULSE DURATION AT PFI
vs
THRESHOLD VOLTAGE OVERDRIVE AT PFI
5
4.6
Minimum Pulse Duration at PFI – µ s
VOL – Low-Level Output Voltage at RESET – mV
500
VDD = 1.65 V
4.2
3.8
3.4
3
2.6
2.2
1.8
1.4
1
0.6
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Threshold Voltage Overdrive at PFI – V
1
Figure 14
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13
SLVS339B – DECEMBER 2000 – REVISED DECEMBER 2002
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°–ā6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073329/B 04/98
NOTES: A.
B.
C.
D.
14
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-187
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
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