CDC328A 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995 D D D D D D D D D OR DB PACKAGE (TOP VIEW) Low Output Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Six Clock Outputs Polarity Control Selects True or Complementary Outputs Distributed VCC and GND Pins Reduce Switching Noise High-Drive Outputs (– 48-mA IOH, 48-mA IOL) State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages GND 1Y2 2Y1 GND 2Y2 3Y GND 4Y 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1Y1 1T/C VCC 2T/C A VCC 3T/C 4T/C description The CDC328A contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control inputs (T/C), various combinations of true and complementary outputs can be obtained. The CDC328A is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS T/C A OUTPUT Y L L L L H H H L H H H L logic symbol † A 1T/C 2T/C 3T/C 4T/C 12 1 15 1 N1 13 N2 10 9 2 2 N3 3 N4 4 16 2 3 5 6 8 1Y1 1Y2 2Y1 2Y2 3Y 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC328A 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995 logic diagram (positive logic) 1T/C 15 16 2 2T/C 1Y1 1Y2 13 3 2Y1 12 A 5 3T/C 4T/C 10 9 6 8 2Y2 3Y 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . 0.77 W DB package . . . . . . . . . . . . . . . . . . 0.6 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC328A 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995 recommended operating conditions (see Note 3) MIN NOM MAX UNIT 4.75 5 5.25 V VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC – 48 mA Low-level output current 48 mA ∆t / ∆v Input transition rise or fall rate fclock TA Input clock frequency High-level input voltage 2 V 0.8 Input voltage 0 Operating free-air temperature – 40 V V 5 ns / V 100 MHz 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CDC328A 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = –18 mA IOH = – 48 mA VOL II IO‡ VCC = 4.75 V, VCC = 5.25 V, IOL = 48 mA VI = VCC or GND VCC = 5.25 V, VO = 2.5 V ICC VCC = 5.25 V,, VI = VCC or GND IO = 0,, MIN TYP† MAX UNIT –1.2 V 2 V –15 0.5 V ±1 µA –100 mA Outputs high 10 Outputs low 40 Ci VI = 2.5 V or 0.5 V † All typical values are at VCC = 5 V, TA = 25°C ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 3 mA pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Any Y tPLH tPHL T/C Any Y tsk(o) k( ) A tsk(p) A tr tf 4 POST OFFICE BOX 655303 Any Y (same phase) MIN MAX 1.7 5 1.5 5 1.5 5 1.4 5 0.5 UNIT ns ns ns Any Y (any phase) 1 Any Y 1 ns Any Y 1.5 ns Any Y 1.5 ns • DALLAS, TEXAS 75265 CDC328A 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) 500 Ω LOAD CIRCUIT FOR OUTPUTS 3V Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH Output 1.5 V 0.8 V 2V tr 1.5 V 0.8 V VOH VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDC328A 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION A 1T/C 1Y1 tPLH1 tPHL1 tPLH5 tPHL5 tPLH2 tPHL2 tPLH6 tPHL6 tPLH3 tPHL3 tPHL7 tPLH7 tPLH4 tPHL4 tPHL8 tPLH8 1Y2 2T/C 2Y1 2Y2 NOTES: A. Output skew, tsk(o), from A to any Y (same phase), can be measured only between outputs for which the respective polarity-control inputs (T/C) are at the same logic level. It is calculated as the greater of: – The difference between the fastest and slowest of tPLH from A↑ to any Y (e.g., tPLHn, n = 1 to 4; or tPLHn, n = 5 to 6) – The difference between the fastest and slowest of tPHL from A↓ to any Y (e.g., tPHLn, n = 1 to 4; or tPHLn, n = 5 to 6) – The difference between the fastest and slowest of tPLH from A↓ to any Y (e.g., tPLHn, n = 7 to 8) – The difference between the fastest and slowest of tPHL from A↑ to any Y (e.g., tPHLn, n = 7 to 8) B. Output skew, tsk(o), from A to any Y (any phase), can be measured between outputs for which the respective polarity-control inputs (T/C) are at the same or different logic levels. It is calculated as the greater of: – The difference between the fastest and slowest of tPLH from A↑ to any Y or tPHL from A↑ to any Y (e.g., tPLHn, n = 1 to 4; or tPLHn, n = 5 to 6, and tPHLn, n = 7 to 8) – The difference between the fastest and slowest of tPHL from A↓ to any Y or tPLH from A↓ to any Y (e.g., tPHLn, n = 1 to 4; or tPHLn, n = 5 to 6, and tPLHn, n = 7 to 8) C. Pulse skew, tsk(p), is calculated as the greater of tPLHn - tPHLn(n = 1, 2, 3, 4, 5, 6 ,7, 8). Figure 2. Waveforms for Calculation of tsk(o), tsk(p) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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