AMICC A428316S-35

A428316 Series
Preliminary
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
History
Issue Date
Remark
0.0
Initial issue
June 13, 2001
Preliminary
0.1
Modify AC data
April 26, 2002
0.2
Modify DC data and all parts guarantee self-refresh mode
June 10, 2002
0.3
Delete -30,-40 grade and add -25 grade
August 20, 2002
Rev. No.
PRELIMINARY
(August, 2002, Version 0.3)
AMIC Technology, Inc.
A428316 Series
Preliminary
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
n Organization: 262,144 words X 16 bits
n Part Identification
- A428316 (512 Ref.)
n Single 5.0V power supply/built-in VBB generator
n Low power consumption
- Operating: 110mA (-25 max)
- Standby: 2.5mA (TTL), 1.0mA (CMOS)
1.0mA (Self-refresh current)
n High speed
- 25/35 ns RAS access time
- 12/17 ns column address access time
- 8/10 ns CAS access time
- 12/16 ns EDO Page Mode Cycle Time
n Industrial operating temperature range: -40°C to 85°C
for -U
n Fast Page Mode with Extended Data Out
n Separate CAS ( UCAS , LCAS ) for byte selection
n 512 Refresh Cycle in 8ms
n Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 400mil, 40-pin SOJ
- 400mil, 40/44 TSOP type II package
This allow random access of up to 512 words within a row
at a 83/62 MHz EDO cycle, making the A428316 ideally
suited for graphics, digital signal processing and high
performance computing systems.
General Description
The A428316 is a new generation randomly accessed
memory for graphics, organized in a 262,144-word by 16bit configuration. This product can execute Byte Write
and Byte Read operation via two CAS pins.
The A428316 offers an accelerated Fast Page Mode
Pin Descriptions
Pin Configuration
Symbol
nSOJ
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
NC
NC
WE
RAS
NC
A0
A1
A2
13
14
15
16
17
18
19
20
21
22
A3
VCC
A428316V
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A428316S
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
n TSOP
Description
A0 – A8
Address Inputs
I/O0 - I/O15
Data Input/Output
RAS
Row Address Strobe
LCAS
Column Address Strobe for Lower Byte
44
43
42
41
40
39
38
37
36
35
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
32
31
30
29
28
27
26
25
NC
WE
Write Enable
LCAS
UCAS
OE
Output Enable
VCC
5.0V Power Supply
VSS
Ground
NC
No Connection
24
23
A4
VSS
(I/O0 – I/O7)
UCAS
Column Address Strobe for Upper Byte
(I/O8 – I/O15)
OE
A8
A7
A6
A5
cycle with a feature called Extended Data Out (EDO).
PRELIMINARY
(August, 2002, Version 0.3)
1
AMIC Technology, Inc.
A428316 Series
Selection Guide
Symbol
Description
-25
-35
Unit
tRAC
Maximum RAS Access Time
25
35
ns
tAA
Maximum Column Address Access Time
12
17
ns
tCAC
Maximum CAS Access Time
8
10
ns
tOEA
Maximum Output Enable ( OE ) Access Time
8
10
ns
tRC
Minimum Read or Write Cycle Time
44
62
ns
tPC
Minimum EDO Cycle Time
12
16
ns
Functional Description
The A428316 reads and writes data by multiplexing an 18bit address into a 9-bit row and 9-bit column address.
RAS and CAS are used to strobe the row address and the
column address, respectively.
The A428316 offers an accelerated Fast Page Mode cycle
through a feature called Extended Data Out, which keeps
the output drivers on during the CAS precharge time (tcp).
Since data can be output after CAS goes high, the user is
not required to wait for valid data to appear before starting
the next access cycle. Data-out will remain valid as long as
RAS and OE are low, and WE is high; this is the only
characteristic which differentiates Extended Data Out
operation from a standard Read or Fast Page Read.
The A428316 has two CAS inputs: LCAS controls I/O0I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS
function in an identical manner to CAS in that either will
generate an internal CAS signal. The CAS function and
timing are determined by the first CAS ( UCAS or
LCAS ) to transition low and by the last to transition high.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 512 combinations of
the 9-bit row addresses, regardless of sequence, at least
once every 8ms through any RAS cycle (Read, Write) or
RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR
Refresh cycle automatically controls the row addresses by
invoking the refresh counter and controller.
Byte Read and Byte Write are controlled by using LCAS
and UCAS separately.
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 16 common I/O pins, with RAS , CAS ,
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
WE and OE controlling the in direction.
EDO Page Mode operation all 512 columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
PRELIMINARY
(August, 2002, Version 0.3)
It is recommended that RAS and CAS track with VCC or
be held at a valid VIH during Power-On to avoid current
surges.
2
AMIC Technology, Inc.
A428316 Series
Block Diagram
OE
WE
OE Clock
Generator
WE Clock
Generator
UCAS
CAS Clock
Generator
LCAS
I/O0
Data I/O
Buffers
AY0 - AY8
Column
Address
Buffers
Column Decoders
to
I/O15
Sense Amplifiers
A0 - A8
. .
Row
Address
Buffers
AX0 - AX8
ROW DECODER
Refresh
Counter &
Controller
.
.
.
512
.
.
.
512 x 16 .
.
Memory Array
512 x 512 x 16
VCC
RAS Clock
Generator
RAS
VSS
Recommended Operating Conditions
Symbol
Description
(Ta = 0°C to +70°C or -40°C to +85°C)
Min.
Typ.
Max.
Unit
Notes
VCC
Power Supply
4.5
5.0
5.5
V
1
VSS
Input High Voltage
0.0
0.0
0.0
V
1
VIH
Input High Voltage
2.4
-
VCC + 1.0
V
1
VIL
Input Low Voltage
-0.5
-
0.8
V
1
PRELIMINARY
(August, 2002, Version 0.3)
3
AMIC Technology, Inc.
A428316 Series
Truth Table
Function
RAS
UCAS
LCAS
Standby
H
H
Read: Word
L
L
Read: Lower Byte
L
Read: Upper Byte
L
Write: Word
Write: Lower Byte
Address
I/Os
Notes
WE
OE
H
X
X
X
High-Z
L
H
L
Row/Col.
Data Out
H
L
H
L
Row/Col.
I/O0-7 = Data Out
I/O8-15 = High-Z
L
H
H
L
Row/Col.
I/O0-7 = High-Z
I/O8-15 = Data Out
L
L
L
L
H
Row/Col.
Data In
L
H
L
L
H
Row/Col.
I/O0-7 = Data In
I/O8-15 = X
Write: Upper Byte
L
L
H
L
H
Row/Col.
I/O0-7 = X
I/O8-15 = Data In
Read-Write
L
L
L
H→L
L→H
Row/Col.
Data Out → Data In
1,2
EDO-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles
L
L
H→L
H→L
H→L
H→L
H→L
H
H
H→L
Row/Col.
Col.
Data Out
Data Out
2
2
EDO-Page-Mode Write
-First cycle
-Subsequent Cycles
L
L
H→L
H→L
H→L
H→L
L
L
H
H
Row/Col.
Col.
Data In
Data In
1
1
EDO-Page-Mode Read-Write
-First cycle
-Subsequent Cycles
L
L
H→L
H→L
H→L
L→H
Data Out → Data In
H→L
H→L
H→L
L→H
Row/Col.
Col.
Data Out → Data In
1, 2
1, 2
Hidden Refresh Read
L→H→L
L
L
H
L
Row/Col.
Data Out
2
Hidden Refresh Write
L→H→L
L
L
L
X
Row/Col.
Data In → High-Z
1
L
H
H
X
X
Row
High-Z
CBR Refresh
H→L
L
L
X
X
X
High-Z
Self Refresh
H→L
L
L
H
X
X
High-Z
RAS -Only Refresh
Note:
3
1. Byte Write may be executed with either UCAS or LCAS active.
2. Byte Read may be executed with either UCAS or LCAS active.
3. Only one CAS signal ( UCAS or LCAS ) must be active.
PRELIMINARY
(August, 2002, Version 0.3)
4
AMIC Technology, Inc.
A428316 Series
Absolute Maximum Ratings*
*Comments
Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Output Voltage (Vout) . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Power Supply Voltage (VCC) . . . . . . . . . . . -1.0V to +7.0V
Operating Temperature (TOPR) . . . . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Symbol
Parameter
-25
-35
Unit
Min.
Max.
Min.
Max.
Test Conditions
IIL
Input Leakage Current
-5
+5
-5
+5
µA
0V ≤ Vin ≤ VCC
Pins not under
Test = 0V
IOL
Output Leakage Current
-5
+5
-5
+5
µA
DOUT disabled,
0V ≤ Vout ≤ VCC
ICC1
Operating Power Supply
Current
-
115
-
105
mA
RAS , UCAS , LCAS and
Address cycling;
tRC = min.
ICC2
TTL Supply Current Supply
Current
-
2.5
-
2.5
mA
RAS = UCAS = LCAS = VIH
ICC3
Average Power Supply
Current, RAS Refresh
Mode
-
115
-
105
mA
RAS and Address cycling,
UCAS = LCAS = VIH,
tRC = min.
ICC4
EDO Page Mode Average
Power Supply Current
-
115
-
105
mA
RAS and address = VIL,
UCAS , LCAS and
Address cycling;
tPC = min.
ICC5
CAS -before- RAS Refresh
Power Supply Current
-
115
-
105
mA
RAS and UCAS or
LCAS cycling;
tRC = min.
ICC6
CMOS Standby Power
Supply Current
-
1.0
-
1.0
mA
RAS = UCAS = LCAS =
VCC - 0.2V
ICC7
Self Refresh Mode Current
-
1.0
-
1.0
mA
RAS = CAS ≤VSS+0.2V
All other input high levels
are VCC-0.2V or input low
levels are VSS +0.2V
2.4
-
2.4
-
V
IOUT = -5.0mA
-
0.4
-
0.4
V
IOUT = 4.2mA
VOH
VOL
Output Voltage
PRELIMINARY
(August, 2002, Version 0.3)
5
Notes
1, 2
1
1, 2
1
AMIC Technology, Inc.
A428316 Series
AC Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
#
Std
Symbol
-25
-35
Parameter
Min.
Max.
Min.
Max.
Unit
Notes
4, 5
tT
Transition Time (Rise and Fall)
1
50
1
50
ns
1
tRC
Random Read or Write Cycle Time
44
-
62
-
ns
2
tRP
RAS Precharge Time
15
-
23
-
ns
3
tRAS
RAS Pulse Width
25
10K
35
10K
ns
4
tCAS
CAS Pulse Width
4
10K
6
10K
ns
5
tRCD
RAS to CAS Delay Time
10
21
10
25
ns
6
6
tRAD
RAS to Column Address Delay Time
8
14
8
18
ns
7
7
tRSH
CAS to RAS Hold Time
5
-
6
-
ns
8
tCSH
CAS Hold Time
25
-
31
-
ns
9
tCRP
CAS to RAS Precharge Time
5
-
5
-
ns
10
tASR
Row Address Setup Time
0
-
0
-
ns
11
tRAH
Row Address Hold Time
5
-
6
-
ns
12
tCLZ
CAS to Output in Low Z
3
-
3
-
ns
8
13
tRAC
Access Time from RAS
-
25
-
35
ns
6,7
14
tCAC
Access Time from CAS
-
8
-
10
ns
6, 13
15
tAA
Access Time from Column Address
-
12
-
17
ns
7, 13
16
tOEA
OE Access Time
-
8
-
10
ns
17
tAR
Column Address Hold Time from RAS
22
-
31
-
ns
18
tRCS
Read Command Setup Time
0
-
0
-
ns
19
tRCH
Read Command Hold Time
0
-
0
-
ns
PRELIMINARY
(August, 2002, Version 0.3)
6
9
AMIC Technology, Inc.
A428316 Series
AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
#
-25
Std
Symbol
-35
Parameter
Min.
Max.
Min.
Max.
Unit
Notes
9
20
tRRH
Read Command Hold Time Reference to RAS
0
-
0
-
ns
21
tRAL
Column Address to RAS Lead Time
12
-
17
-
ns
22
tCOH
Output Hold After CAS Low
3
-
3
-
ns
23
tOFF
Output Buffer Turn-Off Delay Time
-
3
-
3
ns
24
tASC
Column Address Setup Time
0
-
0
-
ns
25
tCAH
Column Address Hold Time
5
-
6
-
ns
26
tOES
OE Low to CAS High Set Up
5
-
7
-
ns
27
tWCS
Write Command Setup Time
0
-
0
-
ns
11
28
tWCH
Write Command Hold Time
5
-
6
-
ns
11
29
tWCR
Write Command Hold Time to RAS
22
-
31
-
ns
30
tWP
Write Command Pulse Width
5
-
6
-
ns
31
tRWL
Write Command to RAS Lead Time
7
-
10
-
ns
32
tCWL
Write Command to CAS Lead Time
5
-
7
-
ns
33
tDS
Data-in setup Time
0
-
0
-
ns
12
34
tDH
Data-in Hold Time
5
-
6
-
ns
12
35
tDHR
Data-in Hold Time to RAS
22
-
31
-
ns
36
tRWC
Read-Modify-Write Cycle Time
62
-
85
-
ns
37
tRWD
RAS to WE Delay Time (Read-Modify-Write)
34
-
46
-
ns
11
38
tCWD
CAS to WE Delay Time (Read-Modify-Write)
17
-
21
-
ns
11
PRELIMINARY
(August, 2002, Version 0.3)
7
8, 10
AMIC Technology, Inc.
A428316 Series
AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
#
Std
Symbol
-30
-35
Parameter
Min.
Max.
Min.
Max.
Unit
Notes
11
39
tAWD
Column Address to WE Delay Time
(Read-Modify-Write)
21
-
28
-
ns
40
tOEH
OE Hold Time from WE
5
-
6
-
ns
41
tOEP
OE High Pulse Width
5
-
5
-
ns
42
tPC
Read or Write Cycle Time (EDO Page)
12
-
16
-
ns
14
43
tCPA
Access Time from CAS Precharge (EDO Page)
-
14
-
18
ns
13
44
tCP
CAS Precharge Time
4
-
6
-
ns
45
tPCM
EDO Page Mode RMW Cycle Time
32
-
40
-
ns
46
tCRW
EDO Page Mode CAS Pulse Width (RMW)
24
-
30
-
ns
47
tRASP
RAS Pulse Width (EDO Page)
30
200K
35
200K
ns
48
tCSR
CAS Setup Time ( CAS -before- RAS )
5
-
5
-
ns
3
49
tCHR
CAS Hold Time ( CAS -before- RAS )
7
-
10
-
ns
3
50
tRPC
RAS to CAS Precharge Time
10
-
10
-
ns
3
51
tOEZ
Output Buffer Turn-off Delay from OE
-
3
-
3
ns
8
52
tRASS
RAS pulse width ( C -B- R self refresh)
100
-
100
-
µs
53
tRPS
RAS precharge time ( C -B- R self refresh)
44
-
62
-
ns
54
tCHS
CAS hold time ( C -B- R self refresh)
-50
-
-50
-
ns
PRELIMINARY
(August, 2002, Version 0.3)
8
AMIC Technology, Inc.
A428316 Series
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.
4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and
50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥
tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. These parameters are referenced to UCAS and LCAS leading edge in early write cycles and to WE leading edge in
read-modify-write cycles.
13. Access time is determined by the longer of tAA or tCAC or tCPA.
14. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.
PRELIMINARY
(August, 2002, Version 0.3)
9
AMIC Technology, Inc.
A428316 Series
Word Read Cycle
tRC(1)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
tCRP(9)
tCAS(4)
UCAS
LCAS
tRAD(6)
tASR(10)
A0~A8
tRAL(21)
tRAH(11)
tASC(24)
Row Address
tCAH(25)
Column Address
tAR(17)
tRCH(19)
tRCS(18)
tRRH(20)
WE
tOEA(16)
OE
tCAC(14)
tAA(15)
tRAC(13)
I/O 0 ~
I/O 15
tOFF(23)
tOEZ(51)
High-Z
Valid Data-out
tCLZ(12)
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
10
AMIC Technology, Inc.
A428316 Series
Word Write Cycle (Early Write)
tRC(1)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
UCAS
tCRP(9)
tCAS(4)
LCAS
tAR(17)
tRAD(6)
tASR(10)
tRAL(21)
tRAH(11)
tCAH(25)
tASC(24)
A0~A8
Row Address
Column Address
tWCR(29)
tCWL(32)
tRWL(31)
tWP(30)
WE
tWCS(27)
tWCH(28)
OE
tDHR(35)
tDS(33)
I/O 0 ~
I/O 15
tDH(34)
Valid Data-in
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
11
AMIC Technology, Inc.
A428316 Series
Word Write Cycle (Late Write)
tRC(1)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
UCAS
tCRP(9)
tCAS(4)
LCAS
tAR(17)
tRAD(6)
tASR(10)
tRAL(21)
tRAH(11)
tCAH(25)
tASC(24)
A0~A8
Row Address
Column Address
tCWL(32)
tRWL(31)
tWCR(29)
tWP(30)
WE
tOEH(40)
OE
tDHR(35)
tDS(33)
I/O 0 ~
I/O 15
tDH(34)
High-Z
Vaild Data-in
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
12
AMIC Technology, Inc.
A428316 Series
Word Read-Modify-Write Cycle
tRWC(36)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
tCRP(9)
UCAS
LCAS
tAR(17)
tRAD(6)
tASR(10)
A0~A8
tRAH(11)
Row Address
tASC(24)
tCAH(25)
Column Address
tAWD(39)
tCWL(32)
tCWD(38)
tRCS(18)
tRWD(37)
tRWL(31)
WE
tWP(30)
tOEA(16)
tOEZ(51)
OE
tOEH(40)
tCAC(14)
tAA(15)
tDS(33)
tDH(34)
tRAC(13)
I/O 0 ~
I/O 15
High-Z
Data-out
Data-in
tCLZ(12)
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
13
AMIC Technology, Inc.
A428316 Series
EDO Page Mode Word Read Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tPC(42)
tRSH(7)
tCRP(9)
tRCD(5)
tCP(44)
tCAS(4)
tCAS(4)
tCAS(4)
UCAS
LCAS
tCSH(8)
tAR(16)
tRAL(21)
tCAH(25)
tRAD(6)
tASR(10)
A0~A8
tCAH(25)
tRAH(11)
tASC(24)
tASC(24)
Row
Column
Column
tCAH(25)
Column
tRCS(18)
tRCS(18)
tRCH(19)
tRCH(25)
tRCS(18)
WE
tAA(15)
tAA(15)
tRRH(20)
tCPA(43)
tOEA(16)
tOEA(16)
tOES(26)
OE
tCAC(14)
tRAC(13)
tCAC(14)
tOEP(41)
tCOH(22)
tCLZ(12)
I/O 0 ~
I/O 15
Data-out
tOFF(23)
tCAC(14)
tOEZ(51)
tOEZ(51)
Data-out
Data-out
tCLZ(12)
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
14
AMIC Technology, Inc.
A428316 Series
EDO Page Mode Early Word Write Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8)
tPC(42)
tRSH(7)
tCRP(9)
tCRP(9)
tRCD(5)
tCAS(4)
tCP(44)
tCAS(4)
tCP(44)
tCAS(4)
UCAS
LCAS
tRAL(21)
tRAD(6)
tASR(10)
A0~A8
tCAH(25)
tRAH(11)
tASC(24)
Row
tCAH(25)
tASC(24)
tCAH(25)
tASC(24)
Column
Column
tCWL(32)
tCWL(32)
Column
tCWL(32)
tRWL(31)
tWCS(27)
tWCS(27)
tWCS(27)
tWCH(28)
tWCH(28)
tWCH(28)
WE
tWP(30)
tWP(30)
tWP(30)
OE
tDH(34)
tDS(33)
I/O 0 ~
I/O 15
tDH(34)
tDS(33)
Data-in
tDH(34)
tDS(33)
Data-in
Data-in
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
15
AMIC Technology, Inc.
A428316 Series
EDO Page Mode Word Read-Modify-Write Cycle
tRP(2)
tRASP(47)
RAS
tCSH(8)
tCRP(9)
tPCM(45)
tRSH(7)
tCRP(9)
tRCD(5)
tCRW(46)
tCP(44)
tCP(44)
tCRW(46)
tCRW(46)
UCAS
LCAS
tRAL(21)
tRAD(6)
tASR(10)
tCAH(25)
tRAH(11)
A0~A8
Row
tCAH(25)
tCAH(25)
tASC(24)
tASC(24)
Column
tASC(24)
Column
Column
tCWL(32)
tCWL(32)
tCWL(32)
tRWD(37)
tRWL(31)
tRCS(18)
tCWD(38)
tCWD(38)
tCWD(38)
WE
tWP(30)
tAWD(39)
tWP(30)
tAWD(39)
tOEA(16)
tWP(30)
tAWD(39)
tOEA(16)
tOEA(16)
OE
tOEH(40)
tCAC(14)
tCPA(43)
tAA(15)
tOEZ(51)
tAA(15)
tOEZ(51)
tDH(34)
tRAC(13)
tOEZ(51)
tDH(34)
tDH(34)
tDS(33)
tDS(33)
tDS(33)
I/O 0 ~
I/O 15
tCPA(43)
tAA(15)
High-Z
tCLZ(12)
tCLZ(12)
tCLZ(12)
Data-in
Data-out
Data-in
Data-out
Data-in
Data-out
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
16
AMIC Technology, Inc.
A428316 Series
RAS Only Refresh Cycle
tRC(1)
tRAS(3)
tRP(2)
RAS
tRPC(50)
tCRP(9)
UCAS
LCAS
tASR(10)
tRAH(11)
Row
A0~A8
Note: WE, OE = Don't care.
: High or Low
CAS Before RAS Refresh Cycle
tRC(1)
tRP(2)
tRAS(3)
tRP(2)
RAS
tRPC(50)
tCHR(49)
tCSR(48)
tCP(44)
UCAS
LCAS
tOFF(23)
High-Z
I/O 0 ~
I/O 15
Note: WE, OE, Address = Don't care.
PRELIMINARY
(August, 2002, Version 0.3)
: High or Low
17
AMIC Technology, Inc.
A428316 Series
Hidden Refresh Cycle (Word Read)
tRC(1)
tRC(1)
tRAS(3)
tRP(2)
tRAS(3)
tRP(2)
RAS
tAR(17)
tCRP(9)
tRSH(7)
tRCD(5)
tCHR(49)
tCRP(9)
UCAS
LCAS
tRAD(6)
tASR(10)
tRAL(21)
tCAH(25)
tRAH(11)
tASC(24)
A0~A8
Row
Column
tRCS(18)
tRRH(20)
WE
tAA(15)
tOEZ(51)
tOEA(16)
OE
tCAC(14)
tOFF(23)
tCLZ(12)
tRAC(13)
I/O0 ~
I/O 15
High-Z
Valid Data-out
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
18
AMIC Technology, Inc.
A428316 Series
Hidden Refresh Cycle (Early Word Write)
tRC(1)
tRC(1)
tRAS(3)
tRP(2)
tRAS(3)
tRP(2)
RAS
tAR(17)
tCRP(9)
tRSH(7)
tRCD(5)
tCHR(49)
tCRP(9)
UCAS
LCAS
tRAD(6)
tASR(10)
tRAH(11)
tRAL(21)
tCAH(25)
tASC(24)
A0~A8
Row
Column
tWCS(27)
tWCH(28)
tWP(30)
WE
OE
tDS(33)
I/O 0 ~
I/O 15
tDH(34)
Valid Data-in
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
19
AMIC Technology, Inc.
A428316 Series
EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
tRP(2)
tRASP(47)
RAS
tCSH(8)
tPC(42)
tRCD(5)
tCRP(9)
tCAS(4)
tPC(42)
tCP(44)
tCAS(4)
tRSH(7)
tCP(44)
tCAS(4)
tCPR(9)
UCAS
LCAS
tRAL(21)
tRAD(6)
tASR(10)
A0~A8
tASC(24)
tRAH(11) tASC(24)
Row
tCAH(25)
tASC(24)
tCAH(25)
Column
Column
tCAH(25)
Column
tRCH(19)
tRCS(18)
tWCS(27)
WE
tWCH(28)
tAA(15)
tAA(15)
tCAP(43)
tDS(33)
tDH(34)
tRAC(13)
tCAC(14)
tCAC(14)
tOEA(16)
OE
tCOH(22)
I/O 0 ~
I/O 15
Data-out
Data-out
Data-in
: High or Low
PRELIMINARY
(August, 2002, Version 0.3)
20
AMIC Technology, Inc.
A428316 Series
Self Refresh Mode
tRP(2)
tRASS(52)
tRPS(53)
RAS
tCHS(54)
tCSR(48)
tRPC(50)
tCRP(9)
UCAS
LCAS
tCP(44)
tASR(10)
ROW
A0~A8
COL
tOFF(23)
High-Z
I/O 0 ~
I/O 15
: High or Low
Note: WE, OE = Don't care.
n Self Refresh Mode.
a. Entering the Self Refresh Mode:
The A428316 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal “low”
longer than 100µs.
b. Continuing the Self Refresh Mode:
The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode.
It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode.
c. Exiting the Self Refresh Mode:
The A428316 exits the Self Refresh Mode when the RAS signal is brought “high”.
PRELIMINARY
(August, 2002, Version 0.3)
21
AMIC Technology, Inc.
A428316 Series
Capacitance (f = 1MHz, Ta = Room Temperature, VCC = 5.0V ± 10%)
Symbol
Signals
CIN1
A0 - A8
CIN2
RAS , UCAS ,
Parameter
Max.
Unit
Test Conditions
5
pF
Vin = 0V
Input Capacitance
7
pF
Vin = 0V
I/O Capacitance
7
pF
Vin = Vout = 0V
LCAS , WE ,
OE
CI/O
I/O0 - I/O15
Ordering Codes
Package RAS Access Time
25ns
35ns
Self-Refresh
SOJ 40L (400mil)
A428316S-25
A428316S-35
Yes
TSOP 40/44 L type II (400mil)
A428316V-25
A428316V-35
Yes
TSOP 40/44 L type II (400mil)
A428316V-25U
A428316V-35U
Yes
Note: -U is for industrial operating temperature range.
PRELIMINARY
(August, 2002, Version 0.3)
22
AMIC Technology, Inc.
A428316 Series
Package Information
SOJ 40L (400mil) Outline Dimensions
21
1
20
E
40
HE
unit: inches/mm
L
A
A2
C
D
b
b1
A1
e
D
S
Seating Plane
Symbol
e1
y
θ
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.144
-
-
3.66
A1
0.025
-
-
0.64
-
-
A2
0.105
0.110
0.115
2.67
2.79
2.92
b1
0.026
0.028
0.032
0.66
0.71
0.81
b
0.016
0.018
0.022
0.41
0.46
0.56
C
0.008
0.010
0.014
0.20
0.25
0.36
D
1.020
1.025
1.030
25.91
26.04
26.16
E
0.395
0.400
0.405
10.03
10.16
10.29
e
0.044
0.050
0.056
1.12
1.27
1.42
e1
0.355
0.366
0.376
9.114
9.383
9.652
HE
0.430
0.440
0.450
10.92
11.18
11.43
L
0.081
0.093
0.105
2.083
2.39
2.70
S
-
-
0.050
-
-
1.27
y
-
-
0.004
-
-
0.10
θ
0°
-
10°
0°
-
10°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY
(August, 2002, Version 0.3)
23
AMIC Technology, Inc.
A428316 Series
Package Information
TSOP 40/44L (Type II) (400mil) Outline Dimensions
unit: inches/mm
HE
E
44
θ
L
L1
1
B
e
D
S
A
A1
A2
c
D
y
L
Dimensions in inches
Symbol
Min
Nom
Max
L1
Dimensions in mm
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.041
0.95
1.00
1.05
B
0.013
0.015
0.017
0.32
0.37
0.42
c
0.003
0.005
0.009
0.08
0.13
0.23
D
0.720
0.725
0.730
18.28
18.41
18.54
E
0.395
0.400
0.405
10.03
10.16
10.29
e
0.031 BSC
0.80 BSC
HE
0.455
0.463
0.471
11.56
11.76
11.96
L
0.016
0.020
0.024
0.40
0.50
0.60
L1
-
0.031
-
-
0.80
-
S
-
-
0.035
-
-
0.90
y
-
-
0.004
-
-
0.10
θ
1°
3°
5°
1°
3°
5°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(August, 2002, Version 0.3)
24
AMIC Technology, Inc.