E2G0026-17-41 ¡ Semiconductor MSM514260C/CSL ¡ Semiconductor This MSM514260C/CSL version: Jan. 1998 Previous version: May 1997 262,144-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514260C/CSL is a 262,144-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514260C/CSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514260C/CSL is available in a 40-pin plastic SOJ or 44/ 40-pin plastic TSOP. The MSM514260CSL (the self-refresh version) is specially designed for lowerpower applications. FEATURES • 262,144-word ¥ 16-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 512 cycles/8 ms, 512 cycles/128 ms (SL version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM514260C/CSL-xxJS) 44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM514260C/CSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Power Dissipation Cycle Time (Min.) Operating (Max.) Standby (Max.) MSM514260C/CSL-50 50 ns 25 ns 15 ns 15 ns 90 ns 935 mW MSM514260C/CSL-60 60 ns 30 ns 15 ns 15 ns 110 ns 825 mW MSM514260C/CSL-70 70 ns 35 ns 20 ns 20 ns 130 ns 770 mW 5.5 mW/ 1.1 mW (SL version) 1/16 ¡ Semiconductor MSM514260C/CSL PIN CONFIGURATION (TOP VIEW) VCC 1 40 VSS VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 A2 18 NC NC 30 NC WE 29 LCAS RAS 28 UCAS NC 27 OE A0 26 A8 A1 A2 25 A7 A3 24 A6 VCC 23 A5 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS A3 19 22 A4 VCC 20 21 VSS DQ1 2 39 DQ16 DQ2 3 38 DQ15 DQ3 4 37 DQ14 DQ4 5 36 DQ13 VCC 6 35 VSS DQ5 7 34 DQ12 DQ6 8 33 DQ11 DQ7 9 32 DQ10 DQ8 10 31 DQ9 NC 11 NC 12 WE 13 RAS 14 NC 15 A0 16 A1 17 44/40-Pin Plastic TSOP (K Type) 40-Pin Plastic SOJ Pin Name A0 - A8 RAS Function Address Input Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS Upper Byte Column Address Strobe DQ1 - DQ16 Data Input / Data Output OE Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MSM514260C/CSL BLOCK DIAGRAM RAS WE Timing Generator OE I/O Controller LCAS UCAS 8 I/O Controller Column Address Buffers 9 9 Internal Address Counter A0 - A8 Refresh Control Clock Row Address 9 Buffers 9 Row Decoders Output Buffers 8 DQ1 - DQ8 Column Decoders Sense Amplifiers 16 I/O Selector 8 Input Buffers 8 8 Input Buffers 8 16 Memory Cells Word Drivers DQ9 - DQ16 8 Output Buffers 8 VCC On Chip VBB Generator VSS FUNCTION TABLE Input Pin RAS LCAS DQ Pin UCAS WE OE DQ1 - DQ8 DQ9 - DQ16 Function Mode H * * Standby H * * High-Z H * * High-Z L High-Z High-Z Refresh L L H H L High-Z Lower Byte Read L H L H L DOUT High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don't Care Lower Byte Write L H L L H Don't Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z — *: "H" or "L" 3/16 ¡ Semiconductor MSM514260C/CSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VT –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A8) CIN1 — 7 pF Input Capacitance (RAS, LCAS, UCAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ16) CI/O — 10 pF Parameter 4/16 ¡ Semiconductor MSM514260C/CSL DC Characteristics (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter Symbol Condition MSM514260 MSM514260 MSM514260 C/CSL-60 C/CSL-50 C/CSL-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2 mA 0 0.4 0 0.4 0 0.4 V –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 170 — 150 — 140 mA 1, 2 — 2 — 2 — 2 — 1 — 1 — 1 — 200 — 200 — — 170 — 150 — 5 — — 170 — 0 V £ VI £ 6.5 V; Input Leakage Current ILI All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) DQ disable 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V mA 1 200 mA 1, 5 — 140 mA 1, 2 5 — 5 — 150 — 140 mA 1, 2 170 — 150 — 140 mA 1, 3 — 300 — 300 — 300 mA — 200 — 200 — 200 mA RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, 1 DQ = enable Average Power ICC6 Supply Current mA (CAS before RAS Refresh) RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tPC = Min. Average Power tRC = 125 ms, ICC10 CAS before RAS, Supply Current tRAS £ 1 ms (Battery Backup) 1, 4, 5 Average Power Supply Current (CAS before RAS ICCS RAS £ 0.2 V, CAS £ 0.2 V 1, 5 Self-Refresh) Notes: 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. SL version. 5/16 ¡ Semiconductor MSM514260C/CSL AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Symbol MSM514260 MSM514260 MSM514260 C/CSL-60 C/CSL-50 C/CSL-70 Unit Note Min. Max. Min. Max. Min. Max. tRC 90 150 — — 130 130 — — 110 tRWC 180 — — tPC 35 — 40 — 45 — ns ns tPRWC 75 — 80 — 95 — ns ns tRAC — 50 — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC — 15 — 15 — 20 ns 4, 5 Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 25 30 — — 30 35 — — 35 40 ns ns 4, 6 4, 12 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 15 — — 0 15 — — 0 20 — ns ns 4 4 CAS to Data Output Buffer Turn-off Delay Time tOFF 15 50 8 128 0 0 3 — — 15 15 50 8 128 0 0 3 — — 15 tOEZ tT tREF tREF 0 0 3 — — 15 OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (SL version) 15 50 8 128 ns ns ns ms ms 7 7 3 RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time RAS Hold Time referenced to OE tRSH tROH 15 10 — — 15 15 — — 20 20 — — ns ns CAS Precharge Time (Fast Page Mode) tCP 10 — 10 — 10 — ns CAS Pulse Width tCAS 15 10,000 15 10,000 20 10,000 ns CAS Hold Time tCSH ns — 70 10 — — 60 10 — tCRP 50 10 — CAS to RAS Precharge Time — ns 12 30 20 15 — 35 25 35 20 15 — 45 30 40 20 15 — 50 35 ns ns ns 12 5 6 15 14 RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time RAS to Column Address Delay Time tRCD Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 10 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns 11 Column Address Hold Time tCAH tAR 10 40 — — 10 50 — — 15 55 — — ns ns 11 Column Address Hold Time from RAS Column Address to RAS Lead Time tRAL 25 — 30 — 35 — ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns 11 Read Command Hold Time tRCH 0 — 0 — 0 — ns 8, 11 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 tRAD 6/16 ¡ Semiconductor MSM514260C/CSL AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM514260 MSM514260 MSM514260 C/CSL-50 C/CSL-60 C/CSL-70 Unit Note Min. Max. Min. Max. Min. Max. Write Command Set-up Time tWCS 0 — 0 — 0 — ns 9, 11 Write Command Hold Time tWCH 10 — 15 — 15 — ns 11 Write Command Hold Time from RAS tWCR 40 — 45 — 50 — ns Write Command Pulse Width tWP 10 — 15 — 15 — ns OE Command Hold Time tOEH 15 — 15 — 20 — ns Write Command to RAS Lead Time tRWL 15 — 15 — 20 — ns Write Command to CAS Lead Time tCWL 15 — 15 — 20 — ns 13 Data-in Set-up Time tDS 0 — 0 — 0 — ns 10, 11 10, 11 Data-in Hold Time tDH 10 — 10 — 15 — ns Data-in Hold Time from RAS tDHR 40 — 50 — 55 — ns OE to Data-in Delay Time tOED 15 — 15 — 15 — ns CAS to WE Delay Time tCWD 35 — 35 — 45 — ns 9 Column Address to WE Delay Time tAWD 45 — 50 — 60 — ns 9 RAS to WE Delay Time tRWD 70 — 80 — 95 — ns 9 CAS Precharge WE Delay Time tCPWD 50 — 55 — 65 — ns 9 CAS Active Delay Time from RAS Precharge tRPC 10 — 10 — 10 — ns 11 RAS to CAS Set-up Time (CAS before RAS) tCSR 10 — 10 — 10 — ns 11 RAS to CAS Hold Time (CAS before RAS) RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) tCHR 15 — 20 — 15 — ns 12 tRASS 100 — 100 — 100 — ms 15 tRPS 90 — 110 — 130 — ns 15 tCHS –30 — –40 — –50 — ns 15 CAS Hold Time (CAS before RAS Self-Refresh) 7/16 ¡ Semiconductor Notes: MSM514260C/CSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 13. tCWL should be satisfied by both UCAS and LCAS. 14. tCP is determined by the time both UCAS and LCAS are high. 15. Only SL version. 8/16 E2G0096-17-41I , ,, , ,,,, ¡ Semiconductor MSM514260C/CSL TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tAR tCSH tCRP CAS tRCD VIH – VIL – VIH – VIL – tRSH tCAS tRAD tASR Address tCRP tRAH tASC tRAL tCAH Column Row tRCS WE VIH – VIL – tAA tROH tOEA VIH – OE VIL – tCAC tRAC DQ tRCH tRRH VOH – tOEZ Open VOL – tOFF Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tAR tCRP VIH – CAS VIL – WE VIH – VIL – tCSH tRCD tRSH tCAS tRAD tRAH tASR Address tCRP tASC Row tCAH Column tWCS tWCH VIH – tRWL VIH – VIL – tDS DQ tCWL tWP VIL – tWCR OE tRAL VIH – VIL – tDHR tDH Valid Data-in Open "H" or "L" 9/16 , ,, ¡ Semiconductor MSM514260C/CSL Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tRP tAR tCRP tCSH tCRP tRCD tRSH tCAS VIH – CAS VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH– VI/OL– tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/16 ,, , , ,, , ¡ Semiconductor MSM514260C/CSL Fast Page Mode Read Cycle tRASP VIH – RAS V – IL VIH – CAS VIL – Address WE VIH – VIL – tAR tCRP tRHCP tPC tRCD tRAD tASR tRAH tASC tCP tCAS tCSH tCAH tASC Column Row VIH – VIL – Column tRCS tRCH tCAC tOEZ tRRH tCPA tOEA tOFF tRCH tAA tAA tCAC tOEA tOFF tCAC tOEZ tCLZ Valid Data-out tCLZ tRCS tCPA tOEA VOH – VOL – tRAL tCAH tASC Column tAA tRAC tCAS tCAH tRCH tRCS tCRP tRSH tCP tCAS VIH – OE VIL – DQ tRP tCLZ tOFF tOEZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tAR VIH – RAS V – IL tCRP VIH – CAS VIL – Address VIH – VIL – tRCD tRAH tASC Row tWCS WE VIH – VIL – tDS VIH – DQ VIL – tCSH tCAH Column tCWL tWCH tWP tRAD tRHCP tRSH tCAS tASR tRP tPC tWCR tDH Valid Data-in tDHR tCP tCRP tCP tCAS tASC tCAH tASC Column tCWL tWCS tWCH tWP tDS tDH Valid Data-in tCAS tCAH tRAL Column tRWL tCWL tWCS tWCH tWP tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/16 ¡ Semiconductor MSM514260C/CSL ,,, , ,, , Fast Page Mode Read Modify Write Cycle tRASP VIH – RAS VIL – tAR tRP tCSH tPRWC tRCD VIH – CAS VIL – tASC tCAH tRAH VIH – VIL – tCRP tCAS tASC tCAH tCAH Column Column tASC Column Row tRCS tCPWD tCWD tRWD tCWD tRCS V WE IH – VIL – tCWL tAWD tCWL tWP tDH VI/OH– VI/OL – Out tCLZ tOEA tOED tOEZ tCAC In tDH tDS tOEA tOEZ tCAC tWP tCPA tAA tOED VIH – OE V – IL tCWL tROH tWP tDH tDS tOEA tRWL tAWD tCPA tAA tAA tRAL tRCS tCPWD tCWD tAWD tDS tRAC DQ tCP tCAS tRAD tASR Address tCP tCAS tRSH Out tOED In tCLZ tOEZ tCAC Out In tCLZ "H" or "L" RAS-Only Refresh Cycle tRC RAS VIL – CAS Address VIH – VIL – VIH – VIL – tRP tRAS VIH – tCRP tASR tRPC tRAH Row tOFF DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" 12/16 ,, , ,, ¡ Semiconductor MSM514260C/CSL CAS before RAS Refresh Cycle tRC tRP RAS VIH – VIL – DQ tRP tRPC tRPC tCSR tCP CAS tRAS VIH – VIL – tCHR tOFF VOH – VOL – Open Note: WE, OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRAS RAS VIH – tRP tAR VIH – VIL – VIH – VIL – tRSH tRCD tRAD tASC tRAH tASR Address tRAS tRP VIL – tCRP CAS tRC Row tCHR tCAH Column tRCS tRAL VIH – WE V IL – tRRH tAA tROH tOEA VIH – OE V IL – tRAC DQ VOH – VOL – tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" 13/16 ¡ Semiconductor MSM514260C/CSL ,,, , Hidden Refresh Write Cycle tRC tRAS VIH – RAS VIL – CAS tCRP tRCD tCHR tRSH tRAD tASC tASR tCAH tRAH tRAL Column Row tRWL tWCH tWCS WE tRP tAR VIH – VIL – V Address IH – VIL – tRC tRAS tRP VIH – VIL – tWP tWCR VIH – OE VIL – tDS DQ VIH – VIL – tDH Valid Data-in tDHR "H" or "L" CAS before RAS Self-Refresh Cycle tRASS tRP VIH – RAS VIL – tRPC tCP CAS tRPS tRPC tCHS tCSR VIH – VIL – tOFF DQ VOH – VOL – Open Note: WE, OE, Address = "H" or "L" Only SL version "H" or "L" 14/16 ¡ Semiconductor MSM514260C/CSL PACKAGE DIMENSIONS (Unit : mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM514260C/CSL (Unit : mm) TSOPII44/40-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16