A64S06162A Preliminary Document Title 16M(1M x 16bit) Normal mode & Page mode with Deep Power Down Static Random Access Memory Revision history Rev. No. 0.0 (May, 2005, Version 0.0) History Issue Date Remark Initial issue May 24, 2005 Preliminary 1 AMIC Technology, Corp. A64S06162A Preliminary MEMORY 16M(1M x 16bit) Normal mode & Page mode with Deep Power Down Static Random Access Memory DESCRIPTION The A64S06162A is a 16Mb high speed, low power Static Random Access Memory(SRAM) organized as 1,048,576 words by 16 bits and supports Deep Power Down and Page Mode. The A64S06162A is a Pseudo SRAM based on successfully proven DRAM CELL SRAM which was specifically developed for cost sensitive, low power computing and communication applications such as mobile cellular phone handsets, personal digital assistants and other battery-operated consumer products. FEATURES • Standard Asynchronous SRAM Interface with Deep Power Down and Page Mode • Organization : 1M x 16Bit • Power Supply Voltage : 2.7 ~ 3.3 V • Page Size : 4 words • Page Mode Access (tPAA) : 35ns • Data Retention Voltage : 2.4V • Deep Power Down : 5uA • Tri-state Output and TTL Compatible PRODUCT FAMILY Product Family Operating Temperature Voltage Speed ISB1 (Max) IccDR (Max) ICC1 (Max) Mode A64S06162A -40 ~ 85 ℃ 2.7 ~ 3.3 V 70 100uA 100uA 2.0mA Page 2 3 4 5 6 A /LB /OE A0 A1 A2 /PD B IO8 /UB A3 A4 /CS IO0 C IO9 IO10 A5 A6 IO1 IO2 D VSS IO11 A17 A7 IO3 VCC FUNCTIONAL BLOCK DIAGRAM VCC IO12 VSS A16 IO4 VSS F IO14 IO13 A14 A15 IO5 IO6 G IO15 A19 A12 A13 /WE IO7 H A18 A8 A9 A10 A11 NC Column Address Row Decoder Sense Amp. DC Generator Circuit Memory Array 8192 rows 128 x 16 columns Add. Input Buffer E Row Address Add. Input Buffer Ref. Cont. IO0 Data I/O Buffer 1 Write Driver PIN DESCRIPTION IO7 IO8 IO15 Column Decoder Control Logic /CS /PD /OE /WE /UB /LB Note : E3 pin ( VSS) can be remain as a NC Name /CS /OE /WE A0∼A19 IO0∼IO15 (May, 2005, Version 0.0) Function Chip Select Input Output Enable Input Write Enable Input Address Input Data Input / Output 2 Name VCC VSS /UB /LB /PD Function Power Ground Upper Byte (IO8∼15) Lower Byte (IO0∼7) Deep Power Down AMIC Technology, Corp. A64S06162A Preliminary PRODUCT LIST Part Name Function A64S06162A-70U 16M, 48-FBGA , 70 ns, 3.0V, -40℃∼85℃ ABSOLUTE MAXIMUM RATING Item Symbol Ratings Unit VIN, VOUT -0.2 to VCC+0.3 V V Voltage on Vcc supply relative to Vss VCC -0.2 to 3.6 V Power Dissipation PD 1.0 W TSTG -55 to 150 ℃ TA -40 ~ 85 ℃ Voltage on any pin relative to Vss Storage temperature Operating Temperature (Extended) Note : Stresses greater than those listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TABLE /CS /PD /OE /WE /LB /UB I/O 0~7 I/O 8~15 MODE Power X L X X X X High-Z High-Z Deselected Deep Power Down H H X X X X High-Z High-Z Deselected Standby X H X X H H High-Z High-Z Deselected Standby L H H H L X High-Z High-Z Output Disabled Active L H H H X L High-Z High-Z Output Disabled Active L H L H L H Data Out High-Z Lower Byte Read Active L H L H H L High-Z Data Out Upper Byte Read Active L H L H L L Data Out Data Out Word Read Active L H X L L H Data In High-Z Lower Byte Write Active L H X L H L High-Z Data In Upper Byte Write Active L H X L L L Data In Data In Word Write Active (May, 2005, Version 0.0) 3 AMIC Technology, Corp. A64S06162A Preliminary RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Symbol Min Typ Max Unit Supply Voltage (5) Vcc 2.7 3.0 3.3 V Ground Vss 0 0 0 V Input High Voltage VIH 0.8*Vcc - Vcc+0.2 2) V Input Low Voltage VIL -0.2 3) - 0.4 V Note : 1.TA = -40℃ to 85℃, otherwise specified. 2. Overshoot : Vcc + 1.0V in case of pulse width ≤ 20 ns. 3. Undershoot : -1.0V in case of pulse width ≤ 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested. 5. Stable power supply required 100 us before device operation. CAPACITANCE (TA = 25 ℃, f = 1.0MHz) Symbol Parameter Condition Max. Unit CIN Input Capacitance VIN =0V 8 pF COUT Output Capacitance VIO =0V 10 pF Note : This parameter is sampled and not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Condition Min Typ Max Unit Input Leakage Current ILI VIN = Vss to Vcc -1 1 uA Output Leakage Current ILO /CS = VIH, /UB=/LB= VIH or /OE=VIH or /WE=VIL, VIO=Vss to Vcc -1 1 uA Icc1 Cycle Time = 1 us, 100%duty, IIO=0mA, /CS ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ Vcc-0.2V 2.0 mA Icc2 Cycle time=Min, IIO=0mA, 100% duty /CS = VIL,VIN=VIL or VIH 20 mA Iccp /CS1 = VIL, CS2=VIH,Tpwc = min Page address cycling 10 mA Output Low Voltage VOL IOL = 2 mA 0.4 V Output High Voltage VOH IOH = -1 mA Standby Current(TTL) ISB /CS=VIH, /UB=/LB= VIH, Other inputs = VIH or VIL 0.3 mA Standby Current(CMOS) ISB1 /CS ≥ Vcc-0.2V, /UB=/LB ≥ Vcc-0.2V (/UB,/LB Controlled) Other inputs = 0 or Vcc 100 uA Deep Power Down Current ISB2 /PD ≤ Vss+0.2V 5 uA (May, 2005, Version 0.0) 2.2 4 V AMIC Technology, Corp. A64S06162A Preliminary Data Retention Electric Characteristic TA = -40℃ to 85℃ (Normal), unless otherwise specified Item Symbol Test Condition Voltage for Data Retention VDR /CS=/PD=VIH＞Vcc-0.2V or /UB,/LB≥Vcc-0.2V, VIN≥VCC-0.2V or VIN≤VSS + 0.2V Data Retention Current IccDR Vcc=2.4V, /CS=/PD=VIH＞Vcc-0.2V or /UB,/LB≥Vcc-0.2V, VIN≥VCC-0.2V or VIN≤VSS + 0.2V Chip Deselect to Data Retention Time tCDR Operating Recovery Time tR Refer to data retention wave form Min Typ. (1) 2.4 Max Unit 3.3 V 100 uA 0 - - ns tRC - - ns (1) Vcc = 2.4V, TA = 25℃ Data Retention Wave Form Data Retention Mode VCC 2.7V tCDR tR VIH VDR /CS ≥ Vcc-0.2V /CS VSS (May, 2005, Version 0.0) 5 AMIC Technology, Corp. A64S06162A Preliminary AC TEST CONDITIONS TA = -40℃ to 85℃ (Normal), unless otherwise specified PARAMETER Value Input Pulse Level 0.4V to 2.2V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load CL = 30pF + 1TTL Load AC TEST LOADS TTL CL(1) Note : (1) Including jig and scope capacitance POWER UP TIME At starting, maintain stable power for a minimum 100us with /CS = /PD = high. (May, 2005, Version 0.0) 6 AMIC Technology, Corp. A64S06162A Preliminary AC CHARACTERISTICS (Vcc = 2.7 ~ 3.3V, TA = -40 to 85℃) 70ns Parameter List Symbol Unit Min R E A D Read Cycle Time tRC 70 ns Address Set-up Time tAS 0 ns Address Access Time tAA 70 ns Chip Select to Output tCO 70 ns Output Enable to Valid Output tOE 35 ns /UB,/LB Access Time tBA 70 ns Chip select to Low-Z Output tLZ 10 ns /UB, /LB Enable to Low-Z Output tBLZ 10 ns Output Enable to Low-Z Output tOLZ 5 ns Chip Disable to High-Z Output tHZ 0 25 ns /UB, /LB Disable to High-Z Output tBHZ 0 25 ns Output Disable to High-Z Output tOHZ 0 25 ns tOH 10 ns tP 10 ns Page Read Cycle Time tPRC 35 ns Page Read Address Access Time tPAA Write Cycle Time tWC 70 ns Chip Select to End of Write tCW 60 ns Address Valid to End of Write tAW 60 ns /UB, /LB Valid to End of Write tBW 60 ns Write Pulse Width tWP 50 ns Write Recovery Time tWR 0 ns tWHZ 0 Output Hold from Address Change Page Read Precharge Time W R I Max Write to Output High-Z 35 20 ns ns T Data to Write Time Overlap tDW 40 ns E Data Hold from Write Time tDH 0 ns End of Write to Output Low-Z tOW 5 ns Page Write Precharge Time tP 10 ns Page Write Cycle Time tPWC 35 ns Page Write Data to Write Time overlap tPDW 20 ns Page Write Data Hold from Write Time tPDH 0 ns (May, 2005, Version 0.0) 7 AMIC Technology, Corp. A64S06162A Preliminary TIMING DIAGRAMS READ CYCLE (/PD = /WE = VIH) tRC Address(A2 – A19) Page Address(A0 – A1) tAA tCO /CS tAS /UB,/LB tP tLZ(2) tBA tOE /OE tHZ(1,2) tOHZ(1) DATA OUT Note (READ CYCLE) : 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. 3. /WE is high for the read cycle. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. (May, 2005, Version 0.0) 8 AMIC Technology, Corp. A64S06162A Preliminary PAGE READ CYCLE (/PD = /WE = VIH) tRC Address (A2-A19) tPRC Page Corresponding (A0-A1) Addresses tAA tP(5) tPAA tCO /CS tAS /UB,/LB /OE tLZ(2) tBA tOE tHZ(1,2) tOHZ(1) DATA OUT Note (PAGE MODE READ CYCLE) : 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. 3. /WE is high for the read cycle. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. 5. tP (precharge time) should be guaranteed for new Address. 6. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page (May, 2005, Version 0.0) 9 AMIC Technology, Corp. A64S06162A Preliminary WRITE CYCLE 1 (/CS Controlled, /PD = VIH) tWC ADDR tAS tWR tCW /CS tAW tP tBW /UB,/LB tWP /WE tDW Data In High-Z tDH High-Z Data Valid High-Z Data Out WRITE CYCLE 2 (/UB /LB Controlled, /PD = VIH tWC ADDR tWR(4) tCW(2) /CS tP tAW tBW /UB,/LB tAS(3) tWP /WE tDW Data In Data Out tDH Data Valid High-Z Notes (WRITE CYCLE) : 1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among /CS going low and /WE going low: A write end at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS. 5. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. (May, 2005, Version 0.0) 10 AMIC Technology, Corp. A64S06162A Preliminary PAGE MODE WRITE CYCLE (/PD = VIH) tWC Address(A2 – A19) tPWC Page Address(A0 – A1) tP /CS /UB,/LB tCW(3) tAS(1) tBW tWP(1) /WE tDW tDH tPDW tPDH tPDW tPDH DATA IN DATA OUT High-Z Notes (PAGE MODE WRITE CYCLE) : 1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among /CS going low in initial page mode . A write end at the earliest transition among /CS going high and Page Address transition. tWP is measured from the beginning of write to the end of write in initial page access. 2. tPWC is measured from Page Address trasition (After initial page access) to Page Address transition or /CS going high. 2. tCW is measured from the later of /CS going low to the end of write in initial page access. 3. tAS is measured from the address valid to the beginning of write. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. 5. tP (precharge time) should be guaranteed for new Page Address. 6. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page (May, 2005, Version 0.0) 11 AMIC Technology, Corp. A64S06162A Preliminary Deep Power Down Mode 100us 1us /PD Wake Up Normal Operation Deep Power Down Mode Normal Operation Mode /CS (May, 2005, Version 0.0) 12 AMIC Technology, Corp. A64S06162A Preliminary Ordering Information Part No. Access Time (ns) Operating Current Max. (mA) Power Down Mode Standby Current Max. (µA) A64S06162AG-70 70 20 5 A64S06162AG-70F 70 20 5 A64S06162AG-70U 70 20 5 A64S06162AG-70UF 70 20 5 Package 48B Mini BGA 48B Pb-Free Mini BGA 48B Mini BGA 48B Pb-Free Mini BGA •Note : -U is for -40c ~ 85c temperature grade (May, 2005, Version 0.0) 13 AMIC Technology, Corp. A64S06162A Preliminary PACKAGE DIMENSION FOR BGA TYPE Unit: millimeters 48 BALL FINE PITCH 6mm x 8mm BGA(0.75mm ball pitch) Bottom View Top View B B A1 INDEX MARK B1 5 4 3 2 1 B A 6 C H G F C1 / 2 E C C1 D C #A1 B/2 Side View E2 D 0.25/Typ. E1 E A Y Min Typical Max A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E - - 1.20 E1 - - 0.90 E2 0.20 0.25 0.30 Y - - 0.10 (May, 2005, Version 0.0) 0.90/Typ. C 14 AMIC Technology, Corp.