SD60C31/P, SD60C51/P Semiconductor CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER Description The AUK 60C31/P 60C51/P is a high-performance micro controller fabricated with AUK high-density CMOS technology. The AUK CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS. The 60C51 contains a 4K x 8 ROM, a 128 x 8 RAM, 32 I/O lines, two 16-bit counter/timers, a five-source, two-priority level nested interrupt structure, a serial I/O port for either multiprocessor communication, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device has two software selectable modes of power reduction idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Features • • • • • • • 8-bit CPU optimized for control applications. • Power control modes. Pin-to-pin compatible with intel's 80C51/80C31. 60C51 low power mask programmable ROM • 60C31 low power CPU only 64K Program Memory Space, Data Memory space 32K programmable I/O lines. • Two 16bit timer/counters High performance CMOS process. • 5 interrupt sources. 2 Level programmable serial port • 3.5 to 12MHz @ 5V ± 20% Ordering Information Type NO. Marking Package Code Type NO. Marking Package Code SD60C31 SD60C31 PLCC44 SD60C31P SD60C31 DIP40 SD60C51 SD60C51 PLCC44 SD60C51P SD60C51 DIP40 unit : mm 1 20 13.4 ±0.2 o 0.656 (16.662) 0.650 (16.510) 0.048 (1.219) 0.2 5 21 1 5.24 40 (1 7.6 53 ) (1 7.3 99 ) (1 6.6 62 ) (1 6.5 10 ) 0.042(1.067) 45 0.695 (17.653) 0.685 (17.399) 0 .6 95 0 .6 85 0 .6 56 0 .6 50 15 MA X Outline Dimensions 50.7 ±0. 2 1 .2 2T YP 2 .5 4 PLCC44 1. 4±0. 1 4. 5± 0.3 3.5 ± 0.3 0.5 MIN BASE PLANE SEATING PLANE 0.180 (4.572) 0.165 (4.191) 0.120 (3.048) 0.090 (2.286) 0 .6 30 (16 .0 02 ) 0 .5 90 (14 .9 06 ) MIN 0.020 (0.508) ± 0 .0 50 (1 .27 0) 0. 5±0. 1 DIP40 KSI-W001-000 1 SD60C31/P SD60C51/P Absolute Maximum Ratings Characteristic Rating Unit 0 ~+70 °C -65 ~ +150 °C Voltage on any pin to Vss -0.5~Vcc + 0.5 V Maximum IOL per I/O pin 15 ㎃ 1 Watt Ambient temperature under bias Storage temperature Power dissipation Block Diagram External Interrupts Interrupt Control 4K ROM Timer 1 128 RAM SFR Timer 0 Counter Input CPU Osc Bus Control Serial Port Four I/O Ports TxD P0 P2 P1 RxD P3 Address/Data - F Figure ig u r e D M C 6 0 C 5 1Block B lo c kDiagram D ia g ra m 60C51L Description The AUK 60C31/P 60C51/P is a high-performance micro controller fabricated with AUK high-density CMOS technology. The AUK CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS. The 60C51 contains a 4K×8 ROM, a 128×8 RAM, 32I/O lines, two 16-bit counter/times, a five-source, two-priority level nested interrupt structure, a serial I/O port for either multiprocessor communication, I/O expansion or full duplex UART, and on-chip oscillator and clock circuists. In addition, the device has tow software selectable modes of power reduction idle mode and powerdown mode. The idle mode freezes the CPU while allowing the RAM, times, serial port, and interrupt system to continue functioning. KSI-W001-000 2 SD60C31/P SD60C51/P P0.2/AD2 P1.4 5 36 P0.3/AD3 P1.5 6 35 P0.4/AD4 P1.6 7 34 P0.5/AD5 P1.7 8 33 P0.6/AD6 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 INT1/P3.3 32 P0.7/AD7 31 EA/VP P 30 ALE/PROG 12 29 PSEN 13 28 P2.7/A15 39 8 38 9 37 10 36 11 35 44PLCC PLCC44 12 13 34 33 14 32 15 31 16 30 17 29 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/V PP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 28 P2.4/A12 27 25 26 16 25 WR/P3.6 24 P2.5/A13 23 26 22 15 21 T1/P3.5 27 20 14 19 T0/P3.4 18 P2.6/A14 7 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 40DIP DIP40 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 40 37 41 4 42 P0.1/AD1 P1.3 43 38 1 3 44 P0.0/AD0 P1.2 2 T2EX/P1.1 3 VCC 39 4 40 2 5 1 6 T2/P1.0 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC V CC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 Pin Configuration Pin Description VCC : PIN 40 (DIP40), PIN 44 (PLCC44) Supply voltage during normal, Idle and power down operations. VSS : PIN 20 (DIP40), PIN 22 (PLCC44) Circuit ground. Port 0 : PIN 32~39 (DIP40), PIN 36~43 (PLCC44) Port 0 is an 8bit open drain bi-directional I/O port. Port 0 pins that have 1's written to the them float, and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullups when emitting 1's. KSI-W001-000 3 SD60C31/P SD60C51/P Pin Description(continued) Port 1 : PIN 1~8 (DIP40), PIN 2~9 (PLCC44) Port 1 is an 8-bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pullups. Port 2 : PIN 21~28 (DIP40), PIN 24~31 (PLCC44) Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1's. During accesses to external data memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register Port 3 : PIN 10~17 (DIP40), PIN 13~19 (PLCC44) Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the pullups. Port 3 also serves the function of various special feature of the MCS-51 Family, as listed below : RST Port PIN PIN NO. Alternate Function P3.0 10 RxD (Serial input port) P3.1 11 TxD (Serial output port) P3.2 12 INT0 (external interrupt 0) P3.3 13 INT1 (external interrupt 1) P3.4 14 T0 (Timer 0 external input) P3.5 15 T1 (Timer 1 external input) P3.6 16 WR (external data memory write strobe) P3.7 17 RD (external data memory read strobe) : PIN 9 (DIP40), PIN 10 (PLCC44) Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits Power-On reset using only an external capacitor to VCC. KSI-W001-000 4 SD60C31/P SD60C51/P Pin Description(continued) ALE : PIN 30 (DIP40), PIN 33 (PLCC44) Address latch enable output pulse for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing of clocking purposes. Note : However, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX instruction. Otherwise, the pin is weakly pulled high. PSEN : PIN 29 (DIP40), PIN 32 (PLCC44) Program store enable is the read strobe to external program memory. When the 60C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA : PIN 31 (DIP40), PIN 35 (PLCC44) External access enable. EA must be strapped to VSS in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. If EA is strapped to VCC the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. XTAL1 : PIN 19 (DIP40), PIN 21 (PLCC44) Input to the inverting oscillator amplifier and input to the internal clock generator circuits. NC : PIN1, 12, 23, 34 (PLCC44) Non connection pins. XTAL2 : PIN 18 (DIP40), PIN 20(PLCC44) Output from the inverting oscillator amplifier KSI-W001-000 5 SD60C31/P SD60C51/P Pin Description(continued) • Crystal oscillator XTAL2 30pF 30pF XTAL1 VSS Idle Mode In the Idle mode, the CPU puts itself to sleep while all the on chip peripherals stay active. The instruction that invokes the Idle mode is the last instruction executed in the normal operating mode before Idle mode is activated. The content of the on-chip RAM and all the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt, at which time the process is picked up at the interrupt service routine and continued, or by a hardware reset which starts the processor the same as a power on reset. Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and special function register retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. change the on-chip RAM. Reset redefines the SFRs but does not The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The control bits for the reduced power modes are in the special function register PCON. Table Status of the external pins during Idle and power down modes. Mode Program memory ALE PSEN PORT 0 PORT 1 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 Float Data Data Data KSI-W001-000 PORT 2 PORT 3 6 SD60C31/P SD60C51/P Electrical Characteristics(DC) (TA = 0℃ ~ 70℃ or -40℃ ~ 85℃, VCC = 5V ± 20%, VSS=0V) SYMBOL PARAMETER VIL Input low voltage, except EA VILI Input low voltage to EA Input high voltage, except XTAL1,RST Input high voltage to XTAL1, RST Output low voltage to ports 1,2,3 Output low voltage to ports 0, ALE, PSEN VIH VIHI VOL VOLI VOH Output high voltage to ports 1,2,3,ALE,PSEN VOHI Output high voltage (port 0 in external bus mode) Logical 0 input current to ports 1,2,3 Logical 1 to 0 transition current to port 1,2,3 Input leakage current to port 0, EA Power supply current Active mode @ 12MHz Idle mode @ 12MHz Power-down mode Internal reset pull-down resistor Pin capacitance IIL ITL ILI ICC RRST C10 Note : 1. TEST CONDITIONS MIN LIMITS TYP. MAX 0.2VCC0.1 0.2VCC0.3 -0.5 0 UNIT V V 0.2VCC+ 0.9 VCC+0.5 V 0.7 VCC VCC+0.5 V IOL=1.6 ㎃ 0.45 V IOL=3.2 ㎃ 0.45 V IOH=-60 ㎂ IOH=-25 ㎂ IOH=-10 ㎂ IOH=-800 ㎂ IOH=-300 ㎂ IOH=-80 ㎂ 2.4 0.75VCC 0.9VCC V 2.4 0.75VCC 0.9VCC V VIN=0.45V -50 µA VIN=2V -650 µA 0.45<VIN< VCC ±10 µA 20 5 50 mA mA µA 150 kohm 10 pF See note1 11 1.7 5 50 See figure 8 through 11 for ICC test conditions. Minimum VCC for power down is 2V. KSI-W001-000 7 SD60C31/P SD60C51/P Electrical AC Characteristics(AC) (TA = 0℃ or -40℃ ~ 85℃, VCC = 5V ± 20%, VSS=0V) SYM FIGU -BOL RE PARAMETER tLHLL 1 Oscillator frequency versions 60C31/60C51 ALE pulse width tAVLL 1 tLLAX 1/tCLC L 12MHz CLOCK MIN MAX : Speed VARIABLE CLOCK MIN MAX 3.5 12 UNIT MHz 127 2tCLCL-40 ns Address valid to ALE low 28 tCLCL-55 ns 1 Address hold after ALE low 48 tCLCL-35 ns tLLIV 1 ALE low to valid instruction in tLLPL 1 ALE low to PSEN low tPLPH 1 PSEN pulse width tPLIV 1 PSEN low to valid instruction in tPXIX 1 Input instruction hold after PSEN tPXIZ 1 Input instruction float after PSEN tAVIV 1 Address to valid instruction in tPLAZ 1 PSEN low to address float 234 4tCLCL-100 ns 43 tCLCL-40 ns 205 3tCLCL-45 ns 145 0 3CLCL-105 0 ns ns 59 tCLCL-25 ns 312 5tCLCL-105 ns 10 10 ns Data Memory tRLRH 2.3 RD pulse width 400 6tCLCL-100 ns tWLWH 2.3 WR pulse width 400 6tCLCL-100 ns tRLDV 2.3 RD low to valid data in tRHDX 2.3 Data hold after RD tRHDZ 2.3 Data float after RD tLLDV 2.3 tAVDV 252 0 5tCLCL-165 0 ns ns 97 2tCLCL-70 ns ALE low to valid data in 517 8tCLCL-150 ns 2.3 Address to valid data in 585 9tCLCL-165 ns tLLWL 2.3 ALE low to RD or WR low 200 3tCLCL+50 ns tAVWL 2.3 Address valid to WR low or RD low 203 4tCLCL-130 ns tQVWX 2.3 Data valid to WR transition 23 tCLCL-60 ns tWHQZ 2.3 Data hold after WR 33 tCLCL-50 ns tRLAZ 2.3 RD low to address float tWHLH 2.3 RD or WR high to ALE high 43 300 3tCLCL-50 0 123 tCLCL-40 0 ns tCLCL+40 ns External Clock tCHCX 4 High time 20 20 ns tCLCX 4 Low time 20 20 ns tCLCH 4 Rise time 20 20 ns tCHCL 4 Fall time 20 20 ns KSI-W001-000 8 SD60C31/P SD60C51/P Timing Diagram tLHLL ALE tAVLL tLLPL tPLPH tLLIV PSEN tPLIV tLLAX PORT0 tPXIZ tPLAZ tPXIX A0 - A7 INSTR IN A0 - A7 tAVIV PORT2 A0 - A15 A8 - A15 Figure 1. External Program Memory Read Cycle ALE tWHLH tLLDV PSEN tLLWL tRLRH RD tAVLL tLLAX tRLDV tRLAX PORT0 A0 - A7 FROM RI OR DPL tRHDZ tRHDX DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT2 P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A15 FROM PCH Figure 2. External Data Memory Read Cycle KSI-W001-000 9 SD60C31/P SD60C51/P Timing Diagram(Continued) ALE tWHLH PSEN tLLWL tWLWH WR tLLAX tAVLL PORT0 tQVWX tWHQX A0 - A7 FROM RI OR DPL DATA OUT A0 - A7 FROM PCL INSTR IN tAVWL PORT2 P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A15 FROM PCH Figure 3. External Data Memory Write Cycle - 0.5 VCC 0.7VCC -0.1 0.45V t CHCX 0.2VSS t CHCL t CLCX t CLCH tCLCL Figure 4. Ex ternal Clock Drive + 0.1V -0.5 VCC V LOAD+ +0.9 VLOAD 0.2VCC 0.45V - 0.1V VLOAD 0.2VCC-0.1 NOTE : AC Inputs during testing are driv en at V CC-0.5 for a logic '1' and 0.45V for a logic '0'. Timing measurements are made at V IH min for a logic '1' and V IL for a logic '0' - 0.1V TIMING REFERENCE POINTS VOH + 0.1V VOL NOTE : For timing purposes, a port is no longer floating when a 100mV change from load v oltage occurs, and begings to float when a 100mV change from the loaded V OH /V OL lev el occurs. IOH/IOL ≥± 20mA Figure 5. AC T es ting Input/ Output Figure 6. Float Waveform KSI-W001-000 10 SD60C31/P SD60C51/P Timing Diagram(Continued) 45 40 35 30 MAX ACTIVE MODE 25 I CC ㎃ 20 TYP ACTIVE MODE 15 10 MAX IDLE MODE 5 TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz FREQ AT XTAL1 Figure 7. Icc vs. FREQ Valid only within frequency specifications of the device under test VCC VCC ICC ICC RST VCC RST VCC P0 P0 EA (NC) CLOCK SIGNAL VCC VCC EA (NC) XTAL2 XTAL1 CLOCK SIGNAL XTAL2 XTAL1 VSS VSS Figure 8. I CC Test Condition, Active Mode All other pins are disconnected Figure 9. I CC Test Condition, Idle Mode All other pins are disconnected KSI-W001-000 11 SD60C31/P SD60C51/P Timing Diagram(Continued) - 0.5 VCC 0.7VCC 0.45V - 0.1 0.2VSS t CHCL t CHCX tCLCH tCLCX t CLCL Figure 10. Clock Signal Waveform for Icc Tests in Active and Idle Modes t CLCH = tCHCL = 5㎱ V CC I CC RST VCC V CC P0 EA (NC) XTAL2 XTAL1 V SS Figure 11. Icc Test Condition, Power down Mode All other pins are disconnected, Vcc = 2V to 5.5V KSI-W001-000 12