Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 DESCRIPTION PIN CONFIGURATIONS The OM5202 8-Bit ROMless Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The OM5202 has the same instruction set as the 80C51. See also: – OM5232 — 8K bytes mask programmable ROM – OM5234 — 16k bytes mask programmable ROM – OM5238 — 32K bytes mask programmable ROM This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The OM5202 contains no read-only program memory, a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a multi-source, two-priority-level, nested interrupt structure, UART and on-chip oscillator and timing circuits. The OM5202 can be expanded with standard TTL compatible memories and logic. P1.0 1 40 V DD P1.1 2 39 P0.0/AD0 P1.2 3 38 P0.1/AD1 P1.3 4 37 P0.2/AD2 P1.4 5 36 P0.3/AD3 P1.5 6 35 P0.4/AD4 P1.6 7 34 P0.5/AD5 P1.7 8 33 P0.6/AD6 RST 9 32 P0.7/AD7 DIP RxD/P3.0 10 30 ALE TxD/P3.1 11 The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 16MHz crystal, 58% of the instructions are executed in 0.75µs and 40% in 1.5µs. Multiply and divide instructions require 3µs. INT0/P3.2 12 29 PSEN INT1/P3.3 13 28 P2.7/A15 T0/P3.4 14 27 P2.6/A14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 16 25 P2.4/A12 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 FEATURES • 80C51 central processing unit • no internal ROM, externally up to 64k bytes • 256 × 8 RAM, expandable externally to 64k bytes • Two standard 16-bit timer/counters • Four 8-bit I/O ports • Two open drain I/O’s (P1.6, P1.7) • Full-duplex UART facilities • Power control modes 31 EA 34 44 1 33 QFP (SOT307–2) 11 23 – Idle mode – Power-down mode 12 • Operating frequency range: 1.2 to 16 MHz • Operating ambient temperature range: 0 to +70°C 22 SEE PAGE 2 FOR QFP PIN FUNCTIONS. PART NUMBER SELECTION PHILIPS PART ORDER NUMBER PART MARKING PACKAGE NUMBER OM5202/FBP SOT129 OM5202/FBB SOT307–2 TEMPERATURE RANGE °C, PACKAGE FREQUENCY MHz 0 to +70, Plastic Dual In–line Package, 40 leads 1.2 to 16 0 to +70, Plastic Quad Flat Pack, 44 leads 1.2 to 16 EQUIVALENT TYPES Details are as specified by the data sheet for the equivalent type: OM5202 = P80C652 without I2C function. OM5232 = P83C652 without I2C function. OM5234 = P83C654 without I2C function. OM5238 = P83C528 without I2C function. December 1994 1 Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 QFP PIN FUNCTIONS LOGIC SYMBOL 34 33 XTAL1 XTAL2 EA PSEN QFP (SOT307–2) Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS1 NC P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE VSS2 EA/VPP P0.7/AD7 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD VSS3 P1.0 P1.1 P1.2 P1.3 P1.4 PORT 1 RxD TxD INT0 INT1 T0 T1 WR RD NOTE: 1. Due to EMC improvements, all VSS pins (6, 16, 28, 39) must be connected to VSS. BLOCK DIAGRAM FREQUENCY REFERENCE XTAL2 COUNTERS XTAL1 T0 OSCILLATOR AND TIMING DATA MEMORY (256 x 8 RAM) T1 TWO 16-BIT TIMER/EVENT COUNTERS CPU INTERNAL INTERRUPTS INT0 INT1 64K BYTE BUS EXPANSION CONTRTOL CONTROL PROGRAMMABLE I/O PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS EXTERNAL INTERRUPTS December 1994 2 PROG SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT SERIAL IN SERIAL OUT SHARED WITH PORT 3 PORT 2 Function P1.5 P1.6 P1.7 RST P3.0/RxD VSS4 P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 22 PORT 3 12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ALE 23 ALTERNATE FUNCTIONS 11 PORT 0 RST 1 ADDRESS AND DATA BUS VDDVSS ADDRESS BUS 44 Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 PIN DESCRIPTIONS PIN NUMBER MNEMONIC DIP QFP TYPE VSS 20 6, 16, 28, 39 I Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be connected. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. VDD NAME AND FUNCTION 40 38 I 39–32 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1–6 40–44, 1 I/O 7 8 2 3 I/O I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions include: open drain output open drain output P2.0–P2.7 21–28 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0–P3.7 10–17 5, 7–13 I/O 10 11 12 13 14 15 16 17 5 7 8 9 10 11 12 13 I O I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe RST 9 4 I ALE 30 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 26 O Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is activated twice each machine cycle during fetches from the external program memory. When executing out of external program memory two activations of PSEN are skipped during each access to external data memory. PSEN is not activated (remains HIGH) during no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS inputs without external pull–ups. EA 31 29 I External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the internal program memory ROM provided the Program Counter is less than 16384. If during a RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is not allowed to float. XTAL1 19 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 14 O Crystal 2: Output from the inverting oscillator amplifier. P0.0–0.7 P1.0–P1.5 P1.6 P1.7 Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS – 0.5V, respectively. December 1994 3 Philips Semiconductors Product specification ROMless 8-bit microcontroller Table 1. OM5202 Special Function Registers SYMBOL DESCRIPTION DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H B* B Register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPTR: Data Pointer (2 bytes) Data Pointer High Data Pointer Low 83H 82H IE*# Interrupt Enable A8H IP*# Interrupt Priority B8H – 87 86 85 84 83 82 81 80 P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 P1*# Port 1 90H SDA SCL A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H A15 A14 A13 A12 A11 A10 A9 A8 B7 B6 B5 B4 B3 B2 B1 B0 DPH DPL 00H 00H AF AE EA BF BE AD AC AB AA A9 A8 ES1 ES0 ET1 EX1 ET0 EX0 BD BC BB BA B9 B8 PS1 PS0 PT1 PX1 PT0 PX0 0x000000B xx000000B FFH FFH FFH P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD FFH PCON Power Control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B 9F 9E 9D 9C 9B 9A 99 98 S0CON*# Serial 0 Port Control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI S0BUF# Serial 0 Data Buffer 99H D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV F1 P PSW* 00H xxxxxxxxB Program Status Word D0H reserved (Note 1) DAH 00H Stack Pointer 81H 07H reserved (Note 1) DBH 00H reserved (Note 1) D9H F8H reserved (Note 1) D8H 00000000B TCON* Timer Control 88H TH1 Timer High 1 8DH 00H TH0 Timer High 0 8CH 00H TL1 Timer Low 1 8BH 00H TL0 Timer Low 0 8AH 00H TMOD Timer Mode 89H SP * OM5202 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 GATE C/T M1 SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. NOTE 1. Reserved for I2C; not supported in OM5202 December 1994 4 M0 GATE C/T M1 M0 00H 00H 00H Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 milliseconds) plus two machine cycles. At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up. ROM CODE EXTERNAL (OM5202) The MOVC instructions are the only instructions that have access to program code in the external program memory. The EA input is latched during RESET. Idle Mode In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol, page 2. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. Power-Down Mode In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 2 shows the state of the I/O ports during low current operating modes. Reset A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few Table 2. External Pin Status During Idle and Power-Down Mode PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle External 1 1 Float Data Address Data Power-down External 0 0 Float Data Data Data MODE Serial Control Register (S1CON) – See Table 3 S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0 Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation. Table 3. Serial Clock Rates BIT FREQUENCY (kHz) AT fOSC CR2 CR1 CR0 6MHz 12MHz 16MHz fOSC DIVIDED BY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 23 27 31.25 37 6.25 50 100 0.24 < 62.5 0 to 255 47 54 62.5 75 12.5 100 200 0.49 < 62.5 0 to 254 62.5 71 83.3 100 17 133 267 0.65 < 55.6 0 to 253 256 224 192 160 960 120 60 December 1994 5 96 × (256 – (reload value Timer 1)) reload value range Timer 1 (in mode 2) Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 ABSOLUTE MAXIMUM RATINGS1, 2, 3 RATING UNIT Storage temperature range –65 to +150 °C Voltage on any other pin to VSS –0.5 to + 6.5 V Input, output current on any single pin ±5 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1 W PARAMETER NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 40 IDD (mA) 30 (1) 20 10 (2) 0 0 4 8 12 16 fXTAL1 (MHz) (1) MAXIMUM OPERATING MODE: VDD = VDDmax (2) MAXIMUM IDLE MODE: VDD = VDDmax These values are valid within the specified frequency range. Figure 1. IDD vs. Frequency December 1994 6 Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 DC ELECTRICAL CHARACTERISTICS VSS = 0V, VDD = 5.0V ±10%. Operating temperature range 0 to 70°C. TEST SYMBOL PARAMETER LIMITS CONDITIONS MIN. MAX. UNIT VIL Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V VIL1 Input low voltage to EA –0.5 0.2VDD–0.3 V VIL2 Input low voltage to P1.6, P1.7 –0.5 0.3VDD V VIH Input high voltage, except XTAL1, RST, P1.6, P1.7 0.2VDD+0.9 VDD+0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VDD VDD+0.5 V VIH2 Input high voltage, P1.6, P1.7 VOL Output low voltage, ports 1, 2, 3, except P1.6, P1.7 VOL1 Output low voltage, port 0, ALE, PSEN VOL2 Output low voltage, P1.6, P1.7 6.0 V IOL = 1.6mA 7), 8) 0.7VDD 0.45 V 7), 8) 0.45 V 0.4 V IOL = 3.2mA IOL = 3.0mA 9) VOH Output high voltage, ports 1, 2, 3, ALE, PSEN VOH1 Output high voltage; port 0 in external bus mode IIL Logical 0 input current, ports 1, 2, 3, except P1.6, P1.7 VIN = 0.45V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6, P1.7 See note 6) –650 µA IL1 Input leakage current, port 0, EA 0.45V < VI < VDD ±10 µA IL2 Input leakage current, P1.6, P1.7 0V < VI < 6.0V 0V < VDD < 6.0V ±10 µA IDD Power supply current: Active mode @ 16MHz 2), 10) Idle mode @ 16MHz 3), 10) Power down mode 4), 5) See note 1) VDD=6.0V 26.5 6 50 mA mA µA 150 kΩ 10 pF RRST Internal reset pull-down resistor CIO Pin capacitance IOH = –60µA IOH = –25µA IOH = –10µA 2.4 0.75VDD 0.9VDD V V V IOH = –800µA IOH = –300µA IOH = –80µA 2.4 0.75VDD 0.9VDD V V V 50 Freq.=1MHz NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. See Figures 9 through 11 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V; VIH = VDD –0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD. See Figure 9. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V; VIH = VDD –0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 10. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 11. 5. 2V ≤ VPD ≤ VDDmax. 6. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum IOL = 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 10. IDDMAX for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. IDDMAX is given in mA. December 1994 7 Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 AC ELECTRICAL CHARACTERISTICS1, 2 16MHz CLOCK SYMBOL FIGURE PARAMETER MIN VARIABLE CLOCK MAX MIN MAX UNIT 1.2 16 MHz 1/tCLCL 2 Oscillator frequency tLHLL 2 ALE pulse width 85 2tCLCL–40 ns tAVLL 2 Address valid to ALE low 8 tCLCL–55 ns tLLAX 2 Address hold after ALE low 28 tCLCL–35 ns tLLIV 2 ALE low to valid instruction in tLLPL 2 ALE low to PSEN low 23 tCLCL–40 ns tPLPH 2 PSEN pulse width 143 3tCLCL–45 ns tPLIV 2 PSEN low to valid instruction in tPXIX 2 Input instruction hold after PSEN tPXIZ 2 Input instruction float after PSEN 38 tCLCL–25 ns tAVIV 2 Address to valid instruction in 208 5tCLCL–105 ns tPLAZ 2 PSEN low to address float 10 10 ns 150 4tCLCL–100 83 3tCLCL–105 0 0 ns ns ns Data Memory tRLRH 3, 4 RD pulse width 275 6tCLCL–100 ns tWLWH 3, 4 WR pulse width 275 tRLDV 3, 4 RD low to valid data in tRHDX 3, 4 Data hold after RD tRHDZ 3, 4 Data float after RD 55 2tCLCL–70 ns tLLDV 3, 4 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 3, 4 Address to valid data in 398 9tCLCL–165 ns tLLWL 3, 4 ALE low to RD or WR low 138 3tCLCL+50 ns tAVWL 3, 4 Address valid to WR low or RD low 120 4tCLCL–130 ns tQVWX 3, 4 Data valid to WR transition 3 tCLCL–60 ns tDW 3, 4 Data setup time before WR 288 7tCLCL–150 ns tWHQX 3, 4 Data hold after WR 13 tCLCL–50 ns tRLAZ 3, 4 RD low to address float tWHLH 3, 4 RD or WR high to ALE high 23 tXLXL 5 Serial port clock cycle time3 0.75 12tCLCL µs tQVXH 5 Output data setup to clock rising edge3 492 10tCLCL–133 ns 80 2tCLCL–117 ns 6tCLCL–100 148 ns 5tCLCL–165 0 0 238 3tCLCL–50 0 103 tCLCL–40 ns ns 0 ns tCLCL+40 ns Shift Register tXHQX 5 Output data hold after clock rising edge3 edge3 tXHDX 5 Input data hold after clock rising tXHDV 5 Clock rising edge to input data valid3 0 tCHCX 6 High time3 20 tCLCX 6 Low time3 20 tCLCH 6 Rise time3 0 492 ns 10tCLCL–133 ns 20 tCLCL – tCLCX ns 20 tCLCL – tCHCX ns 20 20 ns 20 20 ns External Clock tCHCL 6 Fall time3 NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. These values are characterized but not 100% production tested. December 1994 8 Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. tLHLL ALE tPLPH tLLPL tAVLL tLLIV PSEN tPLIV tLLAX INSTR IN A0–A7 PORT 0 tPXIZ tPLAZ tPXIX A0–A7 tAVIV PORT 2 A8–A15 A8–A15 Figure 2. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tLLAX tAVLL tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0–A7 FROM RI OR DPL DATA IN A0–A7 FROM PCL tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH Figure 3. External Data Memory Read Cycle December 1994 9 A8–A15 FROM PCH INSTR IN Philips Semiconductors Product specification ROMless 8-bit microcontroller OM5202 ALE tWHLH PSEN tWLWH tLLWL WR tLLAX tAVLL tWHQX tQVWX tDW A0–A7 FROM RI OR DPL PORT 0 DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH Figure 4. External Data Memory Write Cycle INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH OUTPUT DATA WRITE TO SBUF tXHDX tXHDV SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI Figure 5. Shift Register Mode Timing VIH1 0.8V tCHCL tCHCX tCLCH tCLCX tCLCL Figure 6. External Clock Drive at XTAL1 December 1994 10 Philips Semiconductors Product specification ROMless 8-bit microcontroller VDD–0.5 OM5202 VLOAD+0.1V 0.2VDD+0.9 0.2VDD–0.1 0.45V VOH–0.1V TIMING REFERENCE POINTS VLOAD VLOAD–0.1V VOL+0.1V NOTE: FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A 100mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL > + 20mA. NOTE: AC INPUTS DURING TESTING ARE DRIVEN AT VDD–0.5 FOR A LOGIC ’1’ AND 0.45V FOR A LOGIC ’0’. TIMING MEASUREMENTS ARE MADE AT VIH MIN FOR A LOGIC ’1’ AND VIL MAX FOR A LOGIC ’0’. Figure 7. AC Testing Input/Output Figure 8. Float Waveform VDD VDD IDD IDD VDD VDD VDD VDD RST VDD RST EA P0 P0 EA (NC) XTAL2 P1.6 * * P1.7 CLOCK SIGNAL XTAL1 (NC) XTAL2 CLOCK SIGNAL P1.6 * P1.7 * XTAL1 VSS VSS Figure 9. IDD Test Condition, Active Mode All other pins are disconnected Figure 10. IDD Test Condition, Idle Mode All other pins are disconnected VDD IDD VDD VDD RST EA P0 (NC) P1.6 XTAL2 P1.7 XTAL1 * * VSS Figure 11. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V NOTE: * Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not exceed the IOL1 specification. December 1994 11