SBAS318 − JUNE 2004 FEATURES D 16-Bit Resolution D 14-Bit Linearity D ±250mV Input Range with Single +5V Supply D 1% Internal Reference Voltage D 1% Gain Error D Flexible Serial Interface with Four Different DESCRIPTION The ADS1203 is a delta-sigma (∆Σ) modulator with a 95dB dynamic range, operating from a single +5V supply. The differential inputs are ideal for direct connection to transducers or low-level signals. With the appropriate digital filter and modulator rate, the device can be used to achieve 16-bit analog-to-digital (A/D) conversion with no missing codes. An effective resolution of 14 bits or SNR of 85dB (typical) can be maintained with a digital filter bandwidth of 40kHz at a modulator rate of 10MHz. The ADS1203 is designed for use in medium- to high-resolution measurement applications including current measurements, smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. It is available in an 8-lead TSSOP package. A 16-pin QFN (3x3) package will be available soon. Modes D Implemented Twinned Binary Coding as D Split-Phase or Manchester Coding for One-Line Interfacing Operating Temperature Range: −40°C to +85°C APPLICATIONS D Motor Control D Current Measurement D Industrial Process Control D Instrumentation D Smart Transmitters D Portable Instruments D Weight Scales D Pressure Transducers VIN+ VIN− MDAT 2nd−Order ∆Σ Modulator MCLK RC Oscillator 20MHz VDD Interface Circuit M0 M1 GND Buffer Reference Voltage 2.5V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2004, Texas Instruments Incorporated !"# ! $ % $ &'% ( % %$ &%$% & ) $ !* " + ,( % &% % , % $ & ( www.ti.com www.ti.com SBAS318 − JUNE 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) MAXIMUM GAIN ERROR (%) PACKAGELEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS1203(2) ±3 ±1 TSSOP-8 PW −40°C to +85°C AZ1203 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS1203IPWT Tape and Reel, 250 ADS1203IPWR Tape and Reel, 2000 (1) For the most current specification and package information, refer to our web site at www.ti.com. (2) 16-pin QFN (3x3) package available soon. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1203 UNIT −0.3 to +6 V GND − 0.4 to VDD + 0.3 GND − 0.3 to VDD + 0.3 V 0.25 W Operating Virtual Junction Temperature Range, TJ −40 to +150 °C Operating Free-Air Temperature Range, TA −40 to +85 °C Storage Temperature Range, TSTG −65 to +150 °C Supply voltage, GND to VDD Analog input voltage range Digital input voltage range Power Dissipation V Lead Temperature (1.6mm or 1/16″ from case for 10s) +260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX UNIT Supply Voltage, VDD 4.5 5.0 5.5 V Analog Input Voltage −250 +250 mV 0 +5 V 24 MHz +105 °C Operating Common-Mode Signal External Clock(1) 16 20 Operating Junction Temperature Range −40 (1) With reduced accuracy, clock can go from 1MHz up to 32MHz; see Typical Characteristic curves. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C(1) TA = 70°C POWER RATING TA = 85°C POWER RATING TSSOP-8 483.6mW 3.868mW/°C 309.5mW 251.4W (1) This is the inverse of the traditional junction-to-ambient thermal resistance (Rq JA). Thermal resistances are not production tested and are for informational purposes only. 2 www.ti.com SBAS318 − JUNE 2004 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at −40°C to +85°C, VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, Mode 3, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. PARAMETER TEST CONDITIONS Resolution MIN ADS1203IPW TYP(1) MAX 16 UNITS Bits DC Accuracy INL Integral linearity error(2) DNL Differential nonlinearity(3) VOS Input offset TCVOS Input offset drift GERR Gain error(4) TCGERR Gain error drift PSRR Power-supply rejection ratio ±1 ±3 0.001 0.005 ±1 −220 4.75V < VDD < 5.25V ±1000 LSB % LSB µV 3.5 8 µV/°C −0.2 ±1 % 20 ppm/°C 80 dB Analog Input FSR Full-scale differential range Input capacitance ±320 (VIN+) − (VIN−) Operating common-mode signal(3) −0.1 Common-mode 5 3 Differential input resistance Equivalent Differential input capacitance At DC CMRR Common-mode rejection ratio VIN = 0V to 5V at 50kHz V pF ±1 Input leakage current mV nA 28 kΩ 5 pF 92 dB 105 dB Internal Voltage Reference VOUT Reference voltage output Scale to 320mV Accuracy Scale to 320mV 2.475 2.5 2.525 V ±1 % dVOUT/dT Reference temperature drift ±20 ppm/°C PSRR Power-supply rejection ratio 80 dB 0.1 ms Startup time to 0.1% at CL = 0 Internal Clock for Modes 0, 1, and 2 Clock frequency 9 10 11 MHz 16 20 24 MHz External Clock for Mode 3 Clock frequency(5) AC Accuracy SINAD Signal-to-noise + distortion VIN = ±250mVPP at 5kHz 82.5 85 dB SNR Signal-to-noise ratio VIN = ±250mVPP at 5kHz 83 85 dB THD Total harmonic distortion VIN = ±250mVPP at 5kHz SFDR Spurious-free dynamic range VIN = ±250mVPP at 5kHz −95 90 95 −88 dB dB (1) All typical values are at TA = +25°C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for VIN+ = −250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) With reduced accuracy, minimum clock can go from 1MHz up to 32MHz. 3 www.ti.com SBAS318 − JUNE 2004 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at −40°C to +85°C, VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, Mode 3, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. PARAMETER TEST CONDITIONS MIN ADS1203IPW TYP(1) MAX UNITS Digital Input Logic family CMOS with Schmitt Trigger VIH High-level input voltage VIL Low-level input voltage IIH High-level Input current VI = VDD or GND IIL Low-level Input current VI = VDD or GND CI Input capacitance 0.7 × VDD VDD + 0.3 −0.3 0.3×VDD V 50 nA −50 V nA 5 pF Digital Output VOH High-level digital output VOL Low-level digital output CO Output capacitance CL Load capacitance VDD = 5V, IO = −5mA 4.6 V VDD = 5V, IO = −15mA 3.9 V VDD = 5V, IO = 5mA 0.4 VDD = 5V, IO = 15mA 1.1 5 V V pF 30 pF Power Supply VDD Supply voltage ICC Operating supply current Power dissipation Operating Temperature Range 4.5 5 5.5 V Mode 0 8.4 9.8 mA Mode 3 6.7 7.8 mA Mode 0 42 49 mW 39 mW +85 °C Mode 3 33.5 −40 (1) All typical values are at TA = +25°C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for VIN+ = −250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) With reduced accuracy, minimum clock can go from 1MHz up to 32MHz. 4 www.ti.com SBAS318 − JUNE 2004 EQUIVALENT INPUT CIRCUIT VDD VDD RON = 350Ω C(SAMPLE) = 5pF AIN DIN GND GND Diode Turn-on Voltage: 0.4V Equivalent Analog Input Circuit Equivalent Digital Input Circuit PIN ASSIGNMENTS Terminal Functions TERMINAL TSSOP PACKAGE (TOP VIEW) NAME M0 1 8 VDD VIN+ 2 7 MCLK ADS1203 VIN− 3 6 MDAT M1 4 5 GND NO. I/O DESCRIPTION M0 1 I VIN+ 2 AI Mode input Noninverting analog input VIN− 3 AI Inverting analog input M1 4 I Mode input GND 5 P Power supply ground MDAT 6 O Modulator data output MCLK 7 I/O Modulator clock input or output VDD 8 P Power supply: +5V nominal NOTE: AI = analog input, AO = analog output, I = input, O = output, P = power supply. 5 www.ti.com SBAS318 − JUNE 2004 PARAMETER MEASUREMENT INFORMATION tC1 MCLK tW1 tD1 MDAT Figure 1. Mode 0 Operation TIMING CHARACTERISTICS: MODE 0 over recommended operating free-air temperature range at −40°C to +85°C, and VDD = +5V, unless otherwise noted. PARAMETER MODE MIN MAX UNIT tC1 tW1 Clock period 0 91 111 ns Clock high time 0 Data delay after falling edge of clock 0 (tC1/2) + 5 2 ns tD1 (tC1/2) − 5 −2 ns t C2 MCLK tD2 t W2 tD3 MDAT Figure 2. Mode 1 Operation TIMING CHARACTERISTICS: MODE 1 over recommended operating free-air temperature range at −40°C to +85°C, and VDD = +5V, unless otherwise noted. PARAMETER MODE MIN MAX UNIT tC2 tW2 Clock period 1 182 222 ns Clock high time 1 Data delay after rising edge of clock 1 Data delay after falling edge of clock 1 (tC2/2) − 5 (tW2/2) − 2 (tW2/2) − 2 (tC2/2) + 5 (tW2/2) + 2 (tW2/2) + 2 ns tD2 tD3 6 ns ns www.ti.com SBAS318 − JUNE 2004 t C1 Internal MCLK tW1 tC3 Internal MDAT tW3 MDAT 1 0 1 1 0 0 Figure 3. Mode 2 Operation TIMING CHARACTERISTICS: MODE 2 over recommended operating free-air temperature range at −40°C to +85°C, and VDD = +5V, unless otherwise noted. PARAMETER MODE MIN MAX UNIT tC1 tW1 Clock period 2 91 111 ns Clock high time 2 Clock period 2 (tC1/2) + 5 111 ns tC3 tW3 (tC1/2) − 5 91 Clock high time 2 (tC3/2) − 5 (tC3/2) + 5 ns ns tC4 MCLK tW4 tD4 MDAT Figure 4. Mode 3 Operation TIMING CHARACTERISTICS: MODE 3 over recommended operating free-air temperature range at −40°C to +85°C, and VDD = +5V, unless otherwise noted. PARAMETER MIN MAX tC4 tW4 Clock period MODE 3 41 62 UNIT ns Clock high time 3 10 ns tD4 tR Data delay after falling edge of clock 3 0 tC4 − 10 10 Rise time of clock 3 0 10 ns tF Fall time of clock 3 0 10 ns ns NOTE: Clock signal is specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; see Figure 4. 7 www.ti.com SBAS318 − JUNE 2004 TYPICAL CHARACTERISTICS VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 3, MCLK = 20MHz) 4 4 3 3 2 2 1 1 0 INL (LSB) INL (LSB) INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 0) −40_C −1 +85_C −2 +25_C −1 +85_C −2 +25_C −3 −40_ C 0 −3 −4 −4 −5 −320 −240 −160 −80 0 80 160 240 −5 −320 320 −240 Differential Input Voltage (mV) −160 −80 0 80 160 240 320 Differential Input Voltage (mV) INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 3, MCLK = 32MHz) INTEGRAL NONLINEARITY vs TEMPERATURE 5 4 0.0076 3 Mode 3 (MCLK = 32MHz) 4 0.0061 INL (LSB) INL (LSB) 1 0 +85_C −1 −40_C −2 3 0.0046 Mode 0 2 0.0031 Mode 3 (MCLK = 20MHz) −3 1 0.0015 +25_C −4 −5 −320 0 −240 −160 −80 0 80 160 240 320 −40 −20 0 OFFSET vs TEMPERATURE 80 0 100 0 Mode 0 −100 −100 Mode 3 (MCLK = 20MHz) −200 −200 −300 Offset (µV) Offset (µV) 60 OFFSET vs POWER SUPPLY 0 Mode 3 (MCLK = 20MHz) −400 −500 −300 Mode 0 −400 −500 Mode 3 (MCLK = 32MHz) −600 −600 Mode 3 (MCLK = 32MHz) −800 −40 −20 −700 −800 0 20 40 Temperature (_C) 8 40 Temperature (_C) Differential Input Voltage (mV) −700 20 60 80 100 4.5 4.6 4.7 4.8 4.9 5 5.1 Power Supply (V) 5.2 5.3 5.4 5.5 INL (%) 2 www.ti.com SBAS318 − JUNE 2004 TYPICAL CHARACTERISTICS (continued) VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. GAIN vs TEMPERATURE RMS NOISE vs INPUT VOLTAGE LEVEL 14 0.10 Mode 0 0 12 RMS Noise (µV) Gain (%) −0.10 Mode 3 (MCLK = 20MHz) −0.20 −0.30 8 6 4 Mode 3 (MCLK = 32MHz) −0.40 −0.50 −40 10 2 −20 0 20 40 Temperature (_ C) 60 80 0 −320 100 −240 −80 0 80 160 240 320 Differential Input Voltage (mV) SIGNAL−TO−NOISE + DISTORTION vs TEMPERATURE SIGNAL−TO−NOISE RATIO vs TEMPERATURE 85.6 85.2 Mode 3 (MCLK = 32MHz) Mode 3 (MCLK = 20MHz) 84.8 85.4 84.4 84.0 85.2 Mode 3 (MCLK = 20MHz) 85.0 SINAD (dB) SNR (dB) −160 84.8 84.6 83.6 83.2 Mode 0 82.8 82.4 82.0 Mode 0 Mode 3 (MCLK = 32MHz) 81.6 84.4 81.2 84.2 −40 80.8 −20 0 20 40 60 80 100 −40 −20 0 Temperature (_C) 20 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 110 80 100 16 98 14 86 10 74 Sinc2 Filter 10 62 8 50 Current (mA) Sinc3 Filter SNR (dB) 9 ENOB (Bits) 60 POWER−SUPPLY CURRENT vs TEMPERATURE 18 12 40 Temperature (_ C) Mode 0 8 Mode 3 (MCLK = 32MHz) 7 Mode 3 (MCLK = 20MHz) 6 38 6 26 4 10 100 1k Decimation Ratio (OSR) 10k 5 −40 −20 0 20 40 60 80 100 Temperature (_C) 9 www.ti.com SBAS318 − JUNE 2004 TYPICAL CHARACTERISTICS (continued) VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. SPURIOUS−FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (Mode 0) SPURIOUS−FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (Mode 3, MCLK = 20MHz) 101 −101 101 99 −99 99 −97 95 −95 SFDR THD 89 97 −95 −93 −91 91 −91 −89 89 −87 87 85 −85 85 −20 0 20 40 Temperature (_C) 60 80 −89 0.5VPP 5kHz −40 100 −105 105 SFDR −95 93 −93 91 −91 SFDR (dB) 95 −89 89 0.5VPP 5kHz −110 SFDR −100 THD −90 80 −80 70 −70 60 −60 −85 0 20 40 Temperature (_ C) 60 80 1 20 SPURIOUS−FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Mode 3, MCLK = 32MHz) −110 SFDR SFDR −100 −100 100 THD 90 −90 80 −80 70 −70 60 50 20 90 −90 80 −80 70 −70 −60 60 −60 −50 50 SFDR (dB) THD 10 −110 110 THD (dB) 100 Frequency (kHz) 10 Frequency (kHz) 110 1 −50 50 100 SPURIOUS−FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Mode 3, MCLK = 20MHz) SFDR (dB) 100 −87 85 10 80 90 THD (dB) SFDR (dB) −97 −20 60 100 −99 THD 97 −40 20 40 Temperature (_ C) 110 −101 87 −85 0 −103 101 99 −20 −87 SPURIOUS−FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Mode 0) SPURIOUS−FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (Mode 3, MCLK = 32MHz) 103 −97 93 87 −40 −99 THD 95 −93 91 −101 THD (dB) 93 −103 SFDR −50 1 10 Frequency (kHz) 20 THD (dB) SFDR (dB) 97 −105 THD (dB) 103 SFDR (dB) 105 −103 0.5VPP 5kHz 103 THD (dB) −105 105 www.ti.com SBAS318 − JUNE 2004 TYPICAL CHARACTERISTICS (continued) VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT, fIN = 5kHz, 0.5VPP) 0 0 −20 −20 −40 −40 Magnitude (dB) Magnitude (dB) FREQUENCY SPECTRUM (4096 Point FFT, fIN = 1kHz, 0.5VPP) −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 0 5 10 15 20 0 5 Frequency (kHz) CLOCK FREQUENCY vs TEMPERATURE 15 20 CLOCK FREQUENCY vs POWER SUPPLY 10.8 10.5 10.5 10.3 MCLK (MHz) MCLK (MHz) 10 Frequency (kHz) 10.2 9.9 9.6 10.1 9.9 9.7 9.3 9.5 −40 −20 0 20 40 Temperature (_ C) 60 80 4.5 100 COMMON−MODE REJECTION RATIO vs FREQUENCY 4.7 4.9 5.1 Power Supply (V) 5.3 5.5 POWER−SUPPLY REJECTION RATIO vs FREQUENCY 110 90 105 85 100 80 PSRR (dB) CMRR (dB) 95 90 85 80 75 75 70 65 60 70 55 65 50 60 1 10 Input Frequency (kHz) 100 0.1 1 10 Frequency of Power Supply (kHz) 100 11 www.ti.com SBAS318 − JUNE 2004 TYPICAL CHARACTERISTICS (continued) VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. MCLK AND MDAT TYPICAL SINK CURRENT MCLK AND MDAT TYPICAL SOURCE CURRENT 70 80 5.5V 70 Output Current, IOH (mA) Output Current, IOL (mA) 60 50 5V 40 4.5V 30 20 10 5.5V 50 5V 40 30 4.5V 20 10 0 0 0 1 2 3 4 Output Voltage, VOL (V) 12 60 5 6 0 1 2 3 4 Output Voltage, VOH (V) 5 6 www.ti.com SBAS318 − JUNE 2004 GENERAL DESCRIPTION The ADS1203 is a single-channel, 2nd-order, CMOS delta-sigma modulator, designed for medium- to high-resolution A/D conversions from DC to 39kHz with an oversampling ratio (OSR) of 256. The output of the converter (MDAT) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage. The modulator shifts the quantization noise to high frequencies. A low-pass digital filter should be used at the output of the delta-sigma modulator. The primary purpose of the digital filter is to filter out high-frequency noise. The secondary purpose is to convert the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). A digital signal processor (DSP), microcontroller (µC), or field programmable gate array (FPGA) could be used to implement the digital filter. Figure 5 shows the ADS1203 connected to a DSP. The overall performance (speed and accuracy) depends on the selection of an appropriate OSR and filter type. A higher OSR produces greater output accuracy while operating at a lower refresh rate. Alternatively, a lower OSR produces lower output accuracy, but operates at a higher refresh rate. This system allows flexibility with the digital filter design and is capable of A/D conversion results that have a dynamic range exceeding 95dB with an OSR = 256. THEORY OF OPERATION The differential analog input of the ADS1203 is implemented with a switched-capacitor circuit. This circuit implements a 2nd-order modulator stage, which digitizes the analog input signal into a 1-bit output stream. The clock source can be internal as well as external. Different frequencies for this clock allow for a variety of solutions and signal bandwidths (however, this can only be used in mode 3). The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream, which accurately represents the analog input voltage over time, appears at the output of the converter. ANALOG INPUT STAGE Analog Input The input design topology of the ADS1203 is based on a fully differential switched-capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (92dB), and excellent power-supply rejection. The input impedance of the analog input is dependent on the modulator clock frequency (fCLK), which is also the sampling frequency of the modulator. Figure 6 shows the basic input structure of the ADS1203. The relationship between the input impedance of the ADS1203 and the modulator clock frequency is: Z IN + 28kW f CLKń10MHz (1) The input impedance becomes a consideration in designs where the source impedance of the input signal is high. This may cause a degradation in gain, linearity and THD. The importance of this effect depends on the desired system performance. There are two restrictions on the analog input signals, VIN+ and VIN−. If the input voltage exceeds the range GND – 0.4V to VDD + 0.3V, the input current must be limited to 10mA because the input protection diodes on the front end of the converter will begin to turn on. In addition, the linearity and the noise performance of the device is ensured only when the differential analog voltage resides within ±250mV; however, the FSR input voltage is ±320mV. +5V +5V VDDO M 0.1µF ADS1203 10nF 27Ω 27Ω 1nF 1nF M0 DSP VDD VIN+ MCLK SPICLK VIN− MDAT SPISIMO M1 GND VSSO Figure 5. Connection Diagram for the ADS1203 Delta-Sigma Modulator Including DSP 13 www.ti.com SBAS318 − JUNE 2004 RSW 350Ω(typ) High Impedance > 1GΩ AIN+ CINT 7pF (typ) 1.5pF Switching Frequency = CLK VCM 1.5pF CINT 7pF (typ) RSW 350Ω(typ) High Impedance > 1GΩ AIN− Figure 6. Input Impedance of the ADS1203 Modulator The ADS1203 can be operated in four modes. Modes 0, 1, and 2 use the internal clock, which is fixed at 20MHz. The modulator can also be operated with an external clock in mode 3. In all modes, the clock is divided by 2 internally and is used as the modulator clock. The frequency of the external clock can vary from 1MHz to 32MHz to adjust for the clock requirements of the application. The modulator topology is fundamentally a 2nd-order, switched-capacitor, delta-sigma modulator, such as the one conceptualized in Figure 7. The analog input voltage and the output of the 1-bit digital-to-analog converter (DAC) are differentiated, providing analog voltages at X2 and X3. The voltages at X2 and X3 are presented to their individual integrators. The output of these integrators progress in a negative or positive direction. When the value of the signal at X4 equals the comparator reference voltage, the output of the comparator switches from negative to positive, or positive to negative, depending on its original state. When the output value of the comparator switches from high to low or vice versa, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage at X6, causing the integrators to progress in the opposite direction. The feedback of the modulator to the front end of the integrators forces the value of the integrator output to track the average of the input. fCLK X(t) X2 Integrator 1 X3 Integrator 2 X4 DATA fS VREF Comparator X6 D/A Converter Figure 7. Block Diagram of the 2nd-Order Modulator 14 www.ti.com SBAS318 − JUNE 2004 DIGITAL OUTPUT A differential input signal of 0V will ideally produce a stream of ones and zeros that are high 50% of the time and low 50% of the time. A differential input of +256mV will produce a stream of ones and zeros that are high 80% of the time. A differential input of –256mV will produce a stream of ones and zeros that are high 20% of the time. The input voltage versus the output modulator signal is shown in Figure 8. DIGITAL INTERFACE INTRODUCTION The analog signal that is connected to the input of the delta-sigma modulator is converted using the clock signal applied to the modulator. The result of the conversion, or modulation, is the output signal DATA from the delta-sigma modulator. In most applications where a direct connection is realized between the delta-sigma modulator and an ASIC, FPGA, DSP, or µC (each with an implemented filter), the two standard signals (MCLK and MDAT) are provided from the modulator. To reduce the wiring (for example, for galvanic isolation), a single line is preferred. Therefore, in mode 2, the data stream is Manchester encoded. MODES OF OPERATION The system clock of the ADS1203 is 20MHz by default. The system clock can be provided either from the internal 20MHz RC oscillator or from an external clock source. For this purpose, the MCLK pin is bidirectional and controlled by the mode setting. The system clock is divided by 2 for the modulator clock. Therefore, the default clock frequency of the modulator is 10MHz. With a possible external clock range of 1MHz to 32MHz, the modulator operates between 500kHz and 16MHz. The four modes of operation for the digital data interface are shown in Table 1. Modulator Output +FS (Analog Input) −FS (Analog Input) Analog Input Figure 8. Analog Input vs Modulator Output of the ADS1203 Table 1. Digital Data Interface Modes of Operation MODE DEFINITION M1 M0 0 Internal clock, synchronous data output Low Low 1 Internal clock, synchronous data output, half output clock frequency Low High 2 Internal clock, Manchester encoded data output High Low 3 External clock, synchronous data output High High 15 www.ti.com SBAS318 − JUNE 2004 Mode 0 In mode 0, the internal RC oscillator is running. The data is provided at the MDAT output pin, and the modulator clock at the MCLK pin. The data is changing at the falling edge of MCLK; therefore, it can safely be strobed with the rising edge. See Figure 1 on page 6. Mode 1 In mode 1, the internal RC oscillator is running. The data is provided at the MDAT output pin. The MCLK pin provides the half modulator clock. The data must be strobed at both the rising and falling edges of MCLK. The data at MDAT is changing in the middle, between the rising and falling edge. In this mode the frequency of both MCLK and MDAT is only 5MHz. See Figure 2 on page 6. Mode 2 This filter provides the best output performance at the lowest hardware size (for example, count of digital gates). For oversampling ratios in the range of 16 to 256, this is a good choice. All the characterizations in the data sheet are also done using a sinc3 filter with an oversampling ratio of OSR = 256 and an output word width of 16 bits. In a sinc3 filter response (shown in Figure 9 and Figure 10), the location of the first notch occurs at the frequency of output data rate fDATA = fCLK/OSR. The –3dB point is located at half the Nyquist frequency or fDATA/4. For some applications, it may be necessary to use another filter type for better frequency response. This performance can be improved, for example, by a cascaded filter structure. The first decimation stage can be a sinc3 filter with a low OSR and the second stage a high-order filter. In mode 2, the internal RC oscillator is running. The data is Manchester encoded and is provided at the MDAT pin. The MCLK output is set to low. There is no clock output provided in this mode. The Manchester coding allows the data transfer with only a single line. See Figure 3 on page 7. In mode 3, the internal RC oscillator is disabled. The system clock must be provided externally at the input MCLK. The system clock must have twice the frequency of the chosen modulator clock. The data is provided at the MDAT output pin. Since the modulator runs with the half system clock, the data changes at every other falling edge of the external clock. The data can safely be strobed at every other rising edge of MCLK. This mode allows synchronous operation to any digital system or the use of clocks different from 10MHz. See Figure 4 on page 7. OSR = 32 f DATA = 10MHz/32 = 312.5kHz −3dB: 81.9kHz −10 −20 Gain (dB) Mode 3 0 −30 −40 −50 −60 −70 −80 0 200 400 600 800 1000 Frequency (kHz) 1200 1400 1600 Figure 9. Frequency Response of Sinc3 Filter 30k FILTER USAGE A very simple filter built with minimal effort and hardware is the sinc3 filter: ǒ Ǔ −OSR Output Code The modulator generates only a bitstream, which does not output a digital word like an analog-to-digital converter (ADC). In order to output a digital word equivalent to the analog input voltage, the bitstream must be processed by a digital filter. H(z) + 1 * z −1 1*z OSR = 32 FSR = 32768 ENOB = 9.9 Bits Settling Time = 3 × 1/f DATA = 9.6µs 25k 20k 15k 10k 5k 0 3 0 (2) 5 10 15 20 25 30 Number of Output Clocks 35 Figure 10. Pulse Response of Sinc3 Filter (fMOD = 10MHz) 16 40 www.ti.com SBAS318 − JUNE 2004 The effective number of bits (ENOB) can be used to compare the performance of ADCs and delta-sigma modulators. Figure 11 shows the ENOB of the ADS1203 with different filter types. In this data sheet, the ENOB is calculated from the SNR: SNR = 1.76dB + 6.02dB × ENOB (3) data clocks. The data clock is equal to the modulator clock divided by the OSR. For overcurrent protection, filter types other than sinc3 might be a better choice. A simple example is a sinc2 filter. Figure 12 compares the settling time of different filter types. The sincfast is a modified sinc2 filter: ǒ Ǔ 2 −OSR H(z) + 1 * z −1 ǒ1 ) z −2 1*z 16 sinc3 10 14 (4) sinc3 9 sincfast 12 8 sinc2 8 6 sinc 4 sincfast 7 10 ENOB (Bits) ENOB (Bits) Ǔ OSR sinc2 6 5 4 sinc 3 2 2 1 0 1 10 100 1000 OSR Figure 11. Measured ENOB vs OSR In motor control applications, a very fast response time for overcurrent detection is required. There is a constraint between 1µs and 5µs with 3 bits to 7 bits resolution. The time for full settling is dependent on the filter order. Therefore, the full settling of the sinc3 filter needs three data clocks and the sinc2 filter needs two 0 0 1 2 3 4 5 6 Settling Time (µs) 7 8 9 10 Figure 12. Measured ENOB vs Settling Time For more information, see application note SBAA094, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at www.ti.com. 17 www.ti.com SBAS318 − JUNE 2004 The DSP (such as a C28x or C24x) can be directly connected at the output of two channels of the optocoupler. In this configuration, the signals arriving at C28x or C24x are standard delta-sigma modulator signals and are connected directly to the SPICLK and SPISIMO pins. Being a delta-sigma converter, there is no need to have word sync on the serial data, so an SPI is ideal for connection. McBSP would work as well in SPI mode. APPLICATIONS Operating the ADS1203 in a typical application using mode 0 is shown in Figure 13. Measurement of the motor phase current is done via the shunt resistor. For better performance, both signals are filtered. R2 and C2 filter noise on the noninverting input signal, R3 and C3 filter noise on the inverting input signal, and C4 in combination with R2 and R3 filter the differential input signal. In this configuration, the shunt resistor is connected via three wires with the ADS1203. When component reduction is necessary, the ADS1203 can operate in mode 2, as shown in Figure 14. M1 is high and M0 is low. Only the noninverting input signal is filtered. R2 and C2 filter noise on the input signal. The inverting input is directly connected to the GND pin, which is simultaneously connected to the shunt resistor. The power supply is taken from the upper gate driver power supply. A decoupling capacitor of 0.1µF is recommended for filtering the power supply. If better filtering is required, an additional 1µF to 10µF capacitor can be added. The output signal from the ADS1203 is Manchester coded. In this case, only one signal is transmitted. For that reason, one optocoupler channel is used instead of two channels, as in the previous example of Figure 13. Another advantage of this configuration is that the DSP will use only one line per channel instead of two. That permits the use of smaller DSP packages in the application. The control lines M0 and M1 are both low while the part is operating in mode 0. Two output signals, MCLK and MDAT, are connected directly to the optocoupler. The optocoupler can be connected to transfer a direct or inverse signal because the output stage has the capacity to source and sink the same current. The discharge resistor is not needed in parallel with optocoupler diodes because the output driver has push-pull capability to keep the LED diode out of the charge. HV+ Floating Power Supply Gated Drive Circuit R2 27Ω RSENSE R3 27Ω R1 D1 5.1V C1 0.1µF ADS1203 C4 10nF C2 1nF C3 1nF M0 VDD VIN+ MCLK VIN− MDAT M1 R4 Optocoupler C28x or C24x SPICLK SPISIMO GND Power Supply Gated Drive Circuit HV− Figure 13. Application Diagram in Mode 0 18 R5 www.ti.com SBAS318 − JUNE 2004 HV+ Floating Power Supply Gated Drive Circuit R1 D1 5.1V R2 27Ω RSENSE C1 0.1µF ADS1203 M0 C2 0.1µF Power Supply VIN+ MCLK VIN− MDAT M1 R4 Optocoupler VDD C28x or C24x GND Gated Drive Circuit HV− Figure 14. Application Diagram in Mode 2 Floating Power Supply HV+ C28x or C24x Gate Drive Circuit CVDD ADS1203 R2 27Ω M0 + RSENSE − C2 0.1µF C1 0.1µF VDD VIN+ MCLK SPICLK VIN− MDAT SPISIMO M1 GND DVDD Figure 15. Application Diagram without Galvanic Isolation in Mode 0 19 www.ti.com SBAS318 − JUNE 2004 ADS1203 R1 27Ω + RSENSE − C1 0.1µF − VIN+ MCLK VIN− MDAT M1 GND ADS1203 R2 27Ω + RSENSE VDD M0 VDD M0 C2 0.1µF VIN+ MCLK VIN− MDAT M1 GND C4 0.1µF C5 0.1µF C28x or C24x CVDD ADS1203 R3 27Ω + RSENSE − M0 C3 0.1µF VDD C6 0.1µF SPICLK VIN+ MCLK SPISIMO VIN− MDAT SPISIMO M1 GND SPISIMO DVDD CLK Figure 16. Application Diagram without Galvanic Isolation in Mode 3 20 www.ti.com SBAS318 − JUNE 2004 LAYOUT CONSIDERATIONS Power Supplies The ADS1203 requires only one power supply (VDD). If there are separate analog and digital power supplies on the board, a good design approach is to have the ADS1203 connected to the analog power supply. Another possible approach to control noise is the use of a resistor on the power supply. The connection can be made between the ADS1203 power-supply pins via a 10Ω resistor. The combination of this resistor and the decoupling capacitors between the power-supply pins on the ADS1203 provide some filtering. The analog supply that is used must be well regulated and generate low noise. For designs requiring higher resolution from the ADS1203, power-supply rejection will be a concern. The digital power supply has high-frequency noise that can be capacitively coupled into the analog portion of the ADS1203. This noise can originate from switching power supplies, microprocessors, or DSPs. High-frequency noise will generally be rejected by the external digital filter at integer multiples of MCLK. Just below and above these frequencies, noise will alias back into the passband of the digital filter, affecting the conversion result. Inputs to the ADS1203, such as VIN+, VIN−, and MCLK should not be present before the power supply is on. Violating this condition could cause latch-up. If these signals are present before the supply is on, series resistors should be used to limit the input current. Experimentation may be the best way to determine the appropriate connection between the ADS1203 and different power supplies. Grounding Analog and digital sections of the design must be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. Do not join the ground planes; instead, connect the two with a moderate signal trace underneath the converter. For multiple converters, connect the two ground planes as close as possible to one central location for all of the converters. In some cases, experimentation may be required to find the best point to connect the two planes together. Decoupling Good decoupling practices must be used for the ADS1203 and for all components in the design. All decoupling capacitors, specifically the 0.1µF ceramic capacitors, must be placed as close as possible to the pin being decoupled. A 1µF and 10µF capacitor, in parallel with the 0.1µF ceramic capacitor, can be used to decouple VDD to GND. At least one 0.1µF ceramic capacitor must be used to decouple VDD to GND, as well as for the digital supply on each digital component. 21 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS1203IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-3-220C-168 HR ADS1203IPWT ACTIVE TSSOP PW 8 250 None CU NIPDAU Level-3-220C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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