The TRU-2500 is the latest addition to Vectron International s family of high performance timing recovery units. It extends the highly respected TRU-600 circuit topology to 2.5 Gb/s data rates with performance optimized to exceed the most stringent SONET/SDH transmission standards. VI s TRU-2500 regenerates clean clock and data signals from an incoming 2.488 Gb/s non-return to zero (NRZ) data stream. The device utilizes SAW filter clock recovery technology for superior jitter tolerance, jitter transfer and jitter generation performance, independent of the data pattern transition density. Output clock jitter is exceptionally low at typically less than 2.0 ps RMS. The clock is extracted from the NRZ data stream by first passing it through a frequency doubler to generate spectral energy at 2.488 GHz. A precision narrow-band SAW filter extracts the clock and eliminates unwanted jitter. The resulting clock is then precisely aligned at the decision circuit to retime the input data. The TRU2500 combines Vectron s SAW filter expertise with custom GaAs ASIC technology for high performance timing recovery applications. The circuit is assembled on a precision ceramic hybrid and packaged in a hermetic SMD package with industry common footprint and pinout. Precision SAW filter technology assures full Bellcore compliance over all operating conditions and eliminates the need for external tuning or compensation. High bit-rate SAW filter clock recovery was developed for and has been proven in high reliability undersea links. The timing recovery circuit must extract a clean clock signal from an input NRZ data stream and then reclock the data with the clock. A simplified block diagram of a basic timing recovery circuit is shown in Fig 1.The data retiming aspect of the design is somewhat straightforward. Recovering a clock compliant with jitter standards and maintaining acceptable clock to data alignment at the decision circuit are the most difficult aspect of the design. It is this aspect of the design which VI has mastered through many years of experience. The clock recovery process can be viewed as a bandpass filter operation, accomplished either through a SAW filter or through the composite effect of a closed loop system (PLL). Most clock recovery devices employ a phase lock loop architecture, which employs a phase detector and loop amplifier to lock a free running VCO to the input signal. At lower data rates PLL designs provide acceptable performance, but as data rate increase, the ability to control critical loop gain parameters over environmental extremes becomes exceedingly difficult. The accuracy and stability of the bandpass characteristic determines how effectively the process will comply with stringent SONET/SDH jitter requirements. The TRU2500 offers superior jitter transfer, jitter tolerance and jitter generation performance because its bandpass characteristic is prescribed by a precision quartz SAW filter which can be precisely controlled and accurately reproduced in volume production. The circuit architecture of the clock recovery path is shown in Figure 2. Figure 3. illustrates the time domain waveform and its associated frequency domain spectrum at various points in the path. Since the input NRZ data stream (A) has a null at the clock frequency, non-linear processing of the signal is required to generate spectral content at the clock rate. The circuit uses a microstrip line to delay the data 1/2 of a bit period. The data and delayed data are then fed through an exclusive or-gate to produce a pulse at each data transition. This signal then has a strong spectral peak at the desired clock rate (B) and can be viewed in the time domain as a clock signal with missing pulses. The pulse train is then filtered and shaped prior to the SAW filter to provide optimum performance. The SAW filters this signal to provide a continuous sine wave (C) with compliant jitter characteristics. This signal is amplified and becomes both the output clock and the retiming signal for the decision circuit. Due to careful attention to pre-filtering and shaping, SAW filter bandpass characteristics, and the elimination of feedback loop clock to data alignment control, the TRU2500 is able to offer output jitter performance as low as 2psRMS, a level not achieved by phase locked loop designs. Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 2 Frequency Doubler Data In B C A Precision SAW Filter Time Delay 0 1 0 1 1 1 0 1 0 0 1 A B C Accurate alignment of the clock within the data eye is required for error free data retiming in the presence of noise. The TRU-2500 uses a programmed delay line to achieve exceptional clock to data alignment. The delay is set at the factory to ensure generous margin 0 t Fclk f Fclk f Fclk f t t for system specifications over a wide power supply and temperature range for the lifetime of the product. The decision circuit also includes CML clock and data output buffers with 50 Ohm internal matching for easy interface. Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 3 Absolute maximum ratings are worst case and short duration exposure conditions. Exposure to conditions more severe may result in permanent damage. Exposure for extended periods may also affect device performance or reliability. Functional operation of the device is not implied at these conditions. Supply Voltage Range Loss of Signal Bias Voltage VSS -7 +0.5 V VDD - 7 V - 2 W VSS +0.5 V Power Dissipation Data Output Voltage Operating Temperature Range TOP -40 85 C Storage Temperature Range TS -40 125 C Maximum and minimum values are testing requirements. Typical values are characteristics of the device and are result of engineering evaluations. Typical values are for information purposes only and are not part of the testing requirements. Supply Voltage Supply Current VSS -4.75 - -5.25 ISS - - 475 mA DATAIN 100 - 900 mVpp Data Output Voltage DATAOUT 625 800 - mVpp Clock Output Voltage CLKOUT 625 800 - mVpp TR/F - 70 - ps LOS Output Signal, Low VLOSL -1 - 0.5 V LOS Output Signal, High VLOSH VDD-0.5 - VDD V Compliant with SONET/SDH Requirements UI Data Input Sensitivity (Differential) Clock/Data Output Rise/Fall Time (20/80%) V Jitter Tolerance JTOL Jitter Transfer Break Point JBW - - 2 MHz Jitter Generation JGEN - 2 3 ps 45 50 55 % Output Clock Duty Cycle D Acquisition Time TAQ - 350 500 ns Clock to Data Alignment (Figure 4) TCDA - 40 - ps Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 4 Data Out Clock Out TCDA = 40ps Typical SONET/ SDH standards specify jitter generation, jitter tolerance, and jitter transfer requirements for receiver and clock recovery elements. Jitter generation (see figure 5.) is minimized through careful design of the clock recovery path to minimize pattern dependent noise on the output clock. Jitter transfer and tolerance performance result from optimization of the SAW filter Ch. 2 Timebase Window 1 # Samples = 157.0 mVolts/div = 20.0 ps/div = -441.56 mVolts = 1024 bandpass characteristics. The SAW filter in the TRU2500 was specifically designed for clock recovery. It exhibits excellent control of the passband response and eliminates inband ripple. The filter is individually housed in a ceramic package and is measured for insertion loss, phase, and bandwidth. A typical response is shown in Fig 6. Offset Delta Window Delta T Sigma = -411.3 mVolts = 9.8125 mVolts = 2.0 ps = 1.0 ps Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 5 S21 (5dB/DIV) 2488.32 Frequency (MHz) 10 MHz/Div. Optimized jitter transfer and tolerance performance is dependent upon precise control of the filter bandwidth. The jitter transfer function is a baseband measurement of the SAW filter, or the loop filter bandwidth for a PLL device. The specifications form a jitter mask which limits inband jitter peaking to less than 0.01 UI and at 2MHz. The mask then rolls off at 20 dB/dec. Figure 7 shows the jitter transfer function for the TRU2500 at 25 C, -40 C, and +85 C.The responses show a complete absence of jitter peaking and virtually optimum bandwidth with negligible temperature variation. The jitter tolerance mask and the TRU2500 test results are shown in figure 8. At the high frequency portion of the mask, the device must run essentially error free with 0.15 UI additional sinusoidal modulation on the input data. As the modulation frequency is decreased approaching the filter bandwidth, jitter tolerance rises as the recovered clock starts to track the modulation. The breakpoint frequency for this rise in tolerance is approximately 1 MHz, this places a lower limit on the clock recovery filter bandwidth. The combined jitter tolerance and jitter transfer requirements restrict the filter bandwidth to the 1 to 2 MHz range, over all conditions. The TRU2500 typically maintains better than 0.5UI tolerance at high frequencies, due to the SAW filter response. This is virtually impossible for a PLL to meet at high data rates. Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 6 5dB/DIV 100K 1M 10M Jitter (UI p-p) 10 25C -40 85C 1 0.1 100000 1000000 10000000 100000000 Fmod (Hz) Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 7 Several parameters may be measured on a clock recovery device to characterize its response to initial start up and transient input data bursts. In conventional Phase Locked Loop designs an internal VCO functions as a clock source which must be synchronized by the loop to the input data rate. The time needed to synchronize the internal clock and provide error free data retiming after a long period without input data transitions is the acquisition time. The response time to shorter time intervals with no data transitions is sometimes referred to input blanking. A third measure of the retiming function is the maximum run length of ones or zeros with no errors. Passive filter based clock recovery depends on the selectivity or Q of the filter along with the gain of associated amplifiers to build up a clock signal derived directly from the input data. Evaluation of the TRU-2500 shows that the clock signal reaches full amplitude in about 350ns with a random data input. Further evaluation shows that error free data is available at the output after a 250ns interval, less than 1000 data transitions. This interval may be shortened through the use of a preamble. This acquisition time is three orders of magnitude shorter than a comparable PLL based design. A plot comparing the recovery time for input blanking is shown in figure 9. A clock recovery device will provide error free performance up to a specified maximum number of consecutive ones or zeros. In a PLL design, synchronization is lost briefly and errors occur for a short interval until synchronization is reestablished. As the run length increases the PLL drifts further from lock and the error interval becomes longer. Eventually a limit is reached where the device is starting from a maximum frequency offset and the recovery time is the acquisition time. A PLL will output a frequency with considerable error with no data input. The SAW filter based TRU-2500 also provides a stable output clock for a comparable time period of at least 250ns after input data is stopped. 250ns correspond to 625 bit intervals at 2.5Gbit/s. Evaluation shows the typical TRU-2500 can run error free with up to 650 zeros or ones imbedded in a 2e13 random data pattern. Recovery Time (us) 1000 100 10 TRU-2500 1 0.1 0 200 400 600 800 1000 1200 Input Blanking (us) Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 8 Pinout Information The Pinout for the TRU2500 is shown in figure 10 52 NC GND GND VFB GND GND GND GND DATAIN GND GND GND GND DATAINB GND GND GND 68 NC GND GND NC GND GND VREF GND NC GND NC GND GND LOS GND GND NC 17 VI TRU-2500 51 VTH GND GND VFBN GND GND GND GND DATAOUT GND GND GND GND DATAOUTB GND GND VSS V108 NC GND GND GND GND GND GND GND CLKOUTB GND GND GND GND CLKOUT GND GND GND 1 35 34 18 Figure 10. Pin Diagram Table 3. Pin Description Pin Symbol 7 VREF Name/Function Reference Voltage (Nominally-3.2V) 14 LOS 26 CLKOUT Loss of Signal 31 CLKOUT 35 VSS 38 DATAOUT Regenerated Data Out (-) Terminate into 50V to GND 43 DATAOUT Regenerated Data Out (+) Terminate into 50V to GND Recovered Clock Out (-). Terminate into 50V to GND Recovered Clock Out (+). Terminate into 50V to GND Supply Voltage (-5.0 V) Nominal 48 VFB DC Feedback Voltage (-), Not Used 51 VTH Input Threshold Voltage, (Not Typically Used) 55 DATAIN Data Input (-) Internally AC coupled 60 DATAIN Data Input (+) Internally AC coupled 65 VFB DC Feedback Voltage (+), Use to Adjust Decision Threshold (Not Typically Used) 1,4,9,11, 17,18,68 NC No Internal Connection 2,3,5,6,8 10,12,13,15 16,19,20,21 22,23,24,25, 27,28,29,30, 32,33,34,36, 37,39,40,41, 42,44,45,46, 47,49,50,52, 53,54,56,57, 58,59,61,62, 63,64,66,67, Case GND Case Ground Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 9 P The TRU-2500 is designed for optimum performance with a -5 Volt supply. Good high speed grounding and layout practice should be employed to assure acceptable performance at this high a data rate. The device temperature rating is specified as the case temperature. Consequently good thermal grounding will increase the useful ambient temperature capability of the device. Data inputs are differential with internal AC coupling to a 50 Ohm termination. This allows a simple interface to a variety of drive circuits, including single ended inputs. The TRU2500 design makes use of GaAs HBT technology to realize lower input offset levels than is achievable with other FET designs. The extremely low offset allows the device to operate without bias feedback and results in typical input sensitivities as low as 60 mV. Since feedback is not used, it is not necessary VTH to connect VTH to VFB. Since VFB has no internal connection, VTH and VFB may be connected with no ill effect. The bias point for each input is accessible through the VTH and VFB pins through 1kV resistors. Input offset levels can be adjusted by applying a 0V to -1V bias, to either or both of the VFB and VTH pins. This could be accomplished by individually tying the either or both of the inputs to -5 V through large variable (100kV) resistors. This could be used to optimize the switching threshold for a particular system or application. The differential outputs for clock and data are 50V CML, as shown in Figure 12. This design has true 50V output impedance for optimum reflection coefficient and reduced sensitivity to variation in interconnect and downstream terminations. The CML output can interface directly to devices with CML inputs, 50 Ohm to ground, or may be AC coupled to interface with ECL, PECL. Vss DATAOUT DATAOUT VFB NC* 1k 50 Programable Delay D D DATAIN C DATAIN C 50 CLKOUT Clock Recovery 1k CLKOUT VFB Voltage Reference Vref Transition Detector 10K LOS Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 10 50 50 Out Out In In lb VSS Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. VI employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the mode. Although no industry-wide standard has been adopted for the CDM, a standard HBM (resistance = 1500V, capacitance = 100pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters. Human-Body (HBM) 500* V min. Charged-Device 200 V min. * Mil-STD-883D, Method 3015, Class 1 Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON 11 68 Pin surface mount package Dimmensions are in inches 1.180 .590 68 52 51 1 .050 35 17 .015 34 18 1.370 1/12 .010 0.190 max T Vectron International reserves the right to make changes to the product(s) and/or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Printed in USA 1/99.