®
ADS
901
ADS901
E
10-Bit, 20MHz, +3V Supply
ANALOG-TO-DIGITAL CONVERTER
TM
FEATURES
DESCRIPTION
● LOW POWER: 48mW at +3V
● SUPPLY RANGE: +2.7V to +3.7V
● ADJUSTABLE FULL SCALE RANGE WITH
EXTERNAL REFERENCES
● NO MISSING CODES
● WIDEBAND TRACK/HOLD: 350MHz
● POWER DOWN: 15mW
● 28-LEAD SSOP PACKAGE
The ADS901 is a high-speed pipelined analog-todigital converter that operates from a +3V power
supply. This complete converter includes a wide bandwidth track/hold and a 10-bit quantizer. The full scale
input range is set by external references.
The ADS901 employs digital error correction techniques to provide excellent differential linearity for
demanding imaging applications. Its low distortion
and high SNR give the extra margin needed for
telecommunications, video and test instrumentation
applications. The ADS901 is available in a 28-lead
SSOP package.
APPLICATIONS
●
●
●
●
●
BATTERY POWERED EQUIPMENT
CAMCORDERS
DIGITAL CAMERAS
COMPUTER SCANNERS
COMMUNICATIONS
CLK
LVDD
ADS901
Timing
Circuitry
IN
T/H
Pipeline
A/D
Error
Correction
Logic
3-State
Outputs
10-Bit
Digital
Data
Reference
Ladder
REFT CM REFB
Pwrdn
OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1997 Burr-Brown Corporation
PDS-1340C
Printed in U.S.A. June, 1999
SPECIFICATIONS
At TA = +25°C, VS = LVDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.
ADS901E
PARAMETER
CONDITIONS
Resolution
Specified Temperature Range
TEMP
MIN
Ambient Air
–40
UNITS
+85
Bits
°C
1Vp-p
1.5
1
1.25 || 5
V
V
µA
MΩ || pF
CMOS Compatible
Rising Edge of Convert Clock
Start Conversion
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
Full
10k
20M
5
DYNAMIC CHARACTERISTICS
Differential Linearity Error (Largest Code Error)
f = 500kHz
f = 9MHz
No Missing Codes
Integral Nonlinearity Error, f = 500kHz
Spurious Free Dynamic Range(2)
f = 500kHz (–1dBFS(3) input)
f = 9MHz (–1dBFS input)
Signal-to-Noise Ratio (SNR)
Referred to Sinewave Input Signal
f = 500kHz (–1dBFS input)
f = 9MHz (–1dBFS input)
Maximum SNR
Referred to DC Full Scale Input Signal
f = 9MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 3.58MHz (–1dBFS input)
f = 9MHz (–1dBFS input)
Effective Number of Bits(4)
fIN = 3.58MHz
Differential Gain Error
NTSC, PAL
Differential Phase Error
NTSC, PAL
Output Noise
Input Grounded
Aperture Delay Time
Aperture Jitter
Analog Input Bandwidth
Small Signal
–20dBFS Input
Full Power
0dBFS Input
Overvoltage Recovery Time(5)
DIGITAL OUTPUTS
Logic Family
Logic Coding
High Output Voltage, VOH
Low Output Voltage, VOL
3-State Enable Time
3-State Disable Time
Internal Pull-Down to Gnd
Power-Down Enable Time
Power-Down Disable Time
Internal Pull-Down to Gnd
MAX
10
ANALOG INPUT
Specified Full Scale Input Range(1)
Common-Mode Voltage (Midscale)
Analog Input Bias Current
Input Impedance
DIGITAL INPUT
Logic Family
Convert Command (Start Conversion)
TYP
±0.8
±0.9
Guaranteed
±3.5
Full
Full
Full
Full
±1.0
Samples/s
Clk Cyc
LSB
LSB
LSB
Full
Full
45
50
49
dBFS(3)
dBFS
Full
Full
48
53
53
dB
dB
62
dB
50
50
49
8.0
2.3
1.0
0.2
3
7
dB
dB
dB
Bits
%
degrees
LSB rms
ns
ps rms
350
100
2
MHz
MHz
ns
Full
Full
Full
45
CL = 15pF
CMOS Compatible
Straight Offset Binary
+2.4
OE = L
OE = H
20
18
50
133
18
50
Pwrdn = L
Pwrdn = H
LVDD
+0.4
40
10
V
V
ns
ns
kΩ
ns
ns
kΩ
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ADS901
2
SPECIFICATIONS (CONT)
At TA = +25°C, VS = LVDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.
ADS901E
PARAMETER
CONDITIONS
ACCURACY
Gain Error
Input Offset(6)
Power Supply Rejection (Gain)
Power Supply Rejection (Offset)
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
TEMP
Full
Full
Full
Full
Full
Full
∆ VS = +10%
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation
Power Dissipation (Power Down)
Thermal Resistance, θJA
28-Lead SSOP
Operating
Operating
Operating
Operating
Full
Full
Full
Full
MIN
REFB +0.5
0.8
+2.7
TYP
2.5
0.4
56
68
2
1
4
MAX
UNITS
VS–0.8
REFT –0.5
+3.0
16
49
15
+3.7
60
%FS
%FS
dB
dB
V
V
kΩ
V
mA
mW
mW
°C/W
89
NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3)
dBFS is dB relative to full scale. (4) Based on (SINAD - 1.76)/6.02. (5) No “Rollover” of bits. (6) Offset Deviation from Ideal Negative Full Scale.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VS ....................................................................................................... +6V
Logic VDD ............................................................................................. +6V
Analog Input ............................................................................... +VS +0.3V
Logic Input ................................................................................. +VS +0.3V
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
ADS901E
ADS901E
28-Lead SSOP
28-Lead SSOP
324
324
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
–40°C to +85°C
–40°C to +85°C
ADS901E
ADS901E
ADS901E
ADS901E/1K
Rail
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “ADS901E/1K” will get a single 1000piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
3
ADS901
PIN CONFIGURATION
PIN DESCRIPTIONS
TOP VIEW
SSOP
+VS
1
28
+VS
LVDD
2
27
IN
(LSB) Bit 10
3
26
CM
Bit 9
4
25
LnBy
Bit 8
5
24
REFB
Bit 7
6
23
NC
Bit 6
7
22
REFT
PIN
DESIGNATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
+VS
LVDD
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
GND
GND
CLK
OE
Pwrdn
+VS
GND
GND
LpBy
REFT
NC
REFB
LnBy
CM
IN
+VS
ADS901
Bit 5
8
21
LpBy
Bit 4
9
20
GND
Bit 3
10
19
GND
Bit 2
11
18
+VS
(MSB) Bit 1
12
17
Pwrdn
GND
13
16
OE
GND
14
15
CLK
DESCRIPTION
Analog Supply
Output Logic Driver Supply Voltage
Data Bit 10 (D0) (LSB)
Data Bit 9 (D1)
Data Bit 8 (D2)
Data Bit 7 (D3)
Data Bit 6 (D4)
Data Bit 5 (D5)
Data Bit 4 (D6)
Data Bit 3 (D7)
Data Bit 2 (D8)
Data Bit 1 (D9) (MSB)
Analog Ground
Analog Ground
Convert Clock Input
Output Enable, Active Low
Power Down Pin
Analog Supply
Analog Ground
Analog Ground
Positive Ladder Bypass
Top Reference Input
No Connection
Bottom Reference Input
Negative Ladder Bypass
Common-Mode Voltage Output
Analog Input
Analog Supply
TIMING DIAGRAM
N+2
N+1
Analog In
N+4
N+3
N
tD
N+5
tL
tCONV
N+7
N+6
tH
Clock
5 Clock Cycles
t2
Data Out
N–5
N–4
N–3
N–2
N–1
N
Data Invalid
SYMBOL
tCONV
tL
tH
tD
t1
t2
N+2
t1
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
50
24
24
®
ADS901
N+1
4
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
25
25
3
3.9
12
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fIN = 500kHz
fIN = 3.58MHz
–20
Amplitude (dB)
Amplitude (dB)
–20
–40
–60
–40
–60
–80
–80
–100
–100
0
2
4
6
8
0
10
2
4
6
SPECTRAL PERFORMANCE
0
fIN = 9MHz
–20
f1 = 4.5MHz
f2 = 5.0MHz
Amplitude (dB)
–20
–40
–60
–40
–60
–80
–80
–100
–100
0
2
4
6
8
10
0
2.5
Frequency (MHz)
5
7.5
10
Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
2
2
fIN = 9MHz
fIN = 500kHz
1
DLE (LSB)
1
DLE (LSB)
10
TWO-TONE INTERMODULATION
0
Amplitude (dB)
8
Frequency (MHz)
Frequency (MHz)
0
0
–1
–1
–2
–2
0
256
512
768
0
1024
256
512
768
1024
Output Code
Output Code
®
5
ADS901
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.
SWEPT POWER SFDR
INTEGRAL LINEARITY ERROR
100
10
fIN = 500kHz
80
SFDR (dBc, dBFS)
ILE (LSB)
5
0
–5
dBFS
60
40
20
dBc
0
–10
0
256
512
768
–60
1024
–50
–40
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
–20
–10
0
UNDERSAMPLING
54
0
fIN = 20MHz
fS = 16MHz
–20
SNR
53
Amplitude (dB)
SFDR (dBFS), SNR (dB)
–30
Input Amplitude (dBFS)
Output Code
52
SFDR
–40
–60
–80
51
–100
50
–120
0.1
1
10
0
16.2
32.4
48.6
64.8
Frequency (MHz)
Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
SPURIOUS FREE DYNAMIC RANGE (SFDR)
vs TEMPERATURE
81.0
56
0.9
fIN = 9MHz
SFDR (dBFS)
DLE (LSB)
54
0.8
0.7
fIN = 500kHz
52
fIN = 9MHz
50
fIN = 500kHz
48
0.6
–50
–25
0
25
50
75
–50
100
®
ADS901
–25
0
25
50
Temperature (°C)
Temperature (°C)
6
75
100
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS, Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.
POWER DISSIPATION vs TEMPERATURE
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
50
Power Dissipation (mW)
55
fIN = 500kHz
SNR (dB)
54
fIN = 9MHz
53
52
49
48
47
46
45
–50
–25
0
25
50
75
–50
100
–25
0
GAIN ERROR vs TEMPERATURE
75
100
0.6
Offset Error (% FS)
2.7
Gain Error (%FS)
50
OFFSET ERROR vs TEMPERATURE
2.8
2.6
2.5
2.4
0.5
0.4
0.3
–50
–25
0
25
50
75
100
–50
Temperature (°C)
–25
0
25
50
75
100
Temperature (°C)
OUTPUT NOISE HISTOGRAM (DC Input)
POWER DISSIPATION vs SAMPLING FREQUENCY
8
Power Dissipation (mW)
55
6
Counts (x105)
25
Temperature (°C)
Temperature (°C)
4
2
0
50
45
40
35
N-2
N-1
N
N+1
N+2
1
Output Code
10
100
Frequency (MHz)
®
7
ADS901
THEORY OF OPERATION
To accommodate a bipolar signal swing, the ADS901 operates with a common-mode voltage (VCM) which is derived
from the external references. Due to the symmetric resistor
ladder inside the ADS901, the VCM is situated between the
top and bottom reference voltage. Equation (1) can be used
for calculating the common-mode voltage level.
The ADS901 is a high speed sampling analog-to-digital
converter that utilizes a pipeline architecture. The fully
differential topology and digital error correction guarantee
10-bit resolution. The differential track/hold circuit is shown
in Figure 1. The switches are controlled by an internal clock
which has a non-overlapping two phase signal, φ1 and φ2. At
the sampling time the input signal is sampled on the bottom
plates of the input capacitors. In the next clock phase, φ1, the
bottom plates of the input capacitors are connected together
and the feedback capacitors are switched to the op amp
output. At this time the charge redistributes between CI and
CH, completing one track/hold cycle. The differential output
is a held DC representation of the analog input at the sample
time. The track/hold circuit can also convert a single-ended
input signal into a fully differential signal for the quantizer.
Consequently, the input signal-to-noise performance. Other
parameters such as small-signal and full-power bandwidth,
and wideband noise are also defined in this stage.
Op Amp
Bias
φ1
IN
φ1
φ2
APPLICATIONS
SIGNAL SWING AND COMMON-MODE
CONSIDERATIONS
The ADS901 is designed to operate on a +3V single supply
voltage. The nominal input signal swing is 1Vp-p, situated
between +1V and +2V. This means that the signal swings
±0.5V around a common-mode voltage of +1.5V, which is
half the supply voltage (VCM = VS/2). In some applications
it might be advantageous to increase the input signal swing.
This will improve the achievable signal-to-noise performance. However, considerations should be made to keep the
signal swing within the linear range of operation of the
driving circuitry to avoid any excessive distortion. In extreme situations the performance of the converter will start
to degrade due to variations of the input’s switch onresistance over the input voltage. Therefore, the signal swing
should remain approximately 0.5V away from each rail
during normal operation.
φ1
CH
φ2
OUT
φ1
OUT
φ1
CI
φ2
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
(1)
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS901 can be set to a high impedance state by driving
the three-state (pin 16) with a logic “HI”. Normal operation
is achieved with pin 16 “LO” or Floating due to internal
pull-down resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
VCM
CI
IN
VCM = (REFT +REFB)/2
VCM
Internal Non-overlapping Clock
φ1
φ2
φ1
DRIVING THE ANALOG INPUTS
AC-COUPLED DRIVER
Figure 2 shows an example of an ac-coupled, single-ended
interface circuit using a high-speed op amp that operates on
FIGURE 1. Input Track/Hold Configuration with Timing
Signals.
+3V
The pipelined quantizer architecture has 9 stages with each
stage containing a two-bit quantizer and a two bit digitalto-analog converter, as shown in Figure 2. Each two-bit
quantizer stage converts on the edge of the sub-clock, which
is the same frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to
time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
provides the ADS901 with excellent differential linearity
and guarantees no missing codes at the 10-bit level.
+5V
C1
R1
50Ω 0.1µF
VIN
IN
A1
–5V
R1
1kΩ
ADS901
CM
402Ω
VCM
0.1µF
402Ω
FIGURE 2. AC-Coupled, Single-Ended Interface Circuit.
®
ADS901
8
on a +3V supply voltage. The OPA632 provides excellent
performance in this demanding application. Its wide input
and output voltage ranges, an low distortion, supports the
ADS901 well. The OPA632 is configured for a gain of +2.
The 374Ω and 2.26kΩ resistors at the input level-shift VIN
so that VOUT is within the allowed output voltage range
when VIN = 0. The input impedance of the driver circuit is
set to match to a 50Ω source impedance. The input levelshifting was designed that VIN can be between 0V and 5V,
while delivering an output voltage of 1V to 2V into the
ADS901. Both the OPA632 and ADS901 have a powerdown function pin with the same polarity for those systems
the need to conserve power.
dual supplies (OPA650, OPA658). The mid-point reference
voltage, VCM, biases the bipolar, ground-referenced input
signal. The capacitor C1 and resistor R1 form a high-pass
filter with the –3dB frequency set at
f–3dB = 1/(2 π R1 C1)
(2)
The values for C1 and R1 are not critical in most applications
and can be set freely. The values shown correspond to a
frequency of 1.6kHz.
Figure 3 depicts a circuit that can be used in single-supply
applications. The mid-reference voltage biases the op amp
up to the appropriate common-mode voltage, for example
VCM = +1.5V. With the use of capacitor CG the DC gain for
the non-inverting op amp input is set to +1V/V. As a result
the transfer function is modified to
VOUT = VIN {(1 + RF/RG) + VCM}
EXTERNAL REFERENCE
The ADS901 requires external references on pin 22 (REFT)
and 24 (REFB). Internally those pins are connected through a
resistor ladder, which has a nominal resistance of 4kΩ
(±15%). In order to establish a correct voltage drop across the
ladder the external reference circuit must be able to typically
supply 250µA of current. With this current the full-scale input
range of the ADS901 is set between +1V and +2V, or 1Vp-p.
In general, the voltage drop across REFT and REFB determines the input full-scale range (FSR) of the ADS901. Equation (4) can be used to calculate the span.
(3)
Again, the input coupling capacitor C1 and resistor R1 form
a high-pass filter. At the same time the input impedance is
defined by R1. Resistor RS isolates the op amp’s output from
the capacitive load to avoid gain peaking or even oscillation.
It can also be used to establish a defined bandwidth to reduce
the wideband noise. The recommended value is usually
between 10Ω and 100Ω.
FSR = REFT - REFB
DC-COUPLED INTERFACE CIRCUIT
Many systems are now requiring +3V single supply capability of both the A/D converter and its driver. Figure 4 shows
an example for DC-coupled configuration operating solely
(4)
Depending on the application, several options are possible to
supply the external reference voltages to the ADS901 without
degrading the typical performance.
+3V
+5V
C1
0.1µF
RS
50Ω
VIN
IN
OPA680
R1
1kΩ
ADS901
22pF
CM
VCM
RF
402Ω
0.1µF
RG
402Ω
402Ω
CG
0.1µF
FIGURE 3. Interface Circuit. Example using the voltage feedback amplifier OPA680.
+3V
Disable
2.26kΩ
374Ω
DIS
VIN
100Ω
+3V
Pwrdn
ADS901
10-Bit
20Msps
OPA632
57.6Ω
22pF
562Ω
750Ω
FIGURE 4. DC-Coupled Interface Circuit for +3V Single-Supply Operation.
®
9
ADS901
PRECISE REFERENCE SOLUTION
For those applications requiring a higher level of dc accuracy and drift, a reference circuit with a precision reference
element might be used (see Figure 6). A stable +1.2V
reference voltage is established by a two terminal bandgap
reference diode, the REF1004-1.2. Using a general-purpose
single-supply dual operational amplifier (A1), like an
OPA2237, OPA2234 or OPA2343, the two required reference voltages for the ADS901 can be generated by setting
each op amp to the appropriate gain; for example: set REFT
to +2V and REFB to +1V.
LOW-COST REFERENCE SOLUTION
The easiest way to achieve the required reference voltages is
to place the reference ladder of the ADS901 between the
supply rails, as shown in Figure 5. Two additional resistors
(RT, RB) are necessary to set the correct current through the
ladder. However depending on the desired full-scale swing
and supply voltage different resistor values might be selected.
The trade-offs, when selecting this reference circuit, are
variations in the reference voltages due to component tolerances and power supply variations. In any case, it is recommended to bypass the reference ladder with at least 0.1µF
ceramic capacitors, as shown in Figure 5. The capacitors
serve a dual purpose. They will bypass most of the high
frequency transient noise which results from feedthrough of
the clock and switching noise from the T/H stages. Secondly, they serve as a charge reservoir to supply instantaneous current to internal nodes.
SINGLE-ENDED INPUT
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
+FS (IN = +2V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +1.5V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1V)
1111111111
1111111111
1111111110
1110000000
1100000000
1010000000
1000000001
1000000000
0111111111
0110000000
0100000000
0010000000
0000000001
0000000000
CLOCK INPUT
The clock input of the ADS901 is designed to accommodate
either +5V or +3V CMOS logic levels. To drive the clock
input with a minimum amount of duty cycle variation and
support maximum sampling rates (20Msps), high speed or
advanced CMOS logic should be used (HC/HCT, AC/ACT).
When digitizing at high sampling rates, a 50% duty cycle
clock with fast rise and fall times (2ns or less) are recommended to meet the rated performance specifications. However, the ADS901 performance is tolerant to duty cycle
variations of as much as ±10% without degradation. For
applications operating with input frequencies up to Nyquist
or undersampling applications, special consideration must
be made to provide a clock with very low jitter. Clock jitter
leads to aperture jitter (tA) which can be the ultimate limitation to achieving good SNR performance. Equation (5)
shows the relationship between aperture jitter, input frequency and the signal-to-noise ratio:
SNR = 20log10 [1/(2 π fIN tA)]
For example, with a 10MHz full-scale input signal and an
aperture jitter of tA = 20ps, the SNR is clock jitter limited to
58dB.
TABLE I. Coding Table for the ADS901.
+3V
10µF
0.1µF
RT
4kΩ
+2V
0.1µF
REFT
+VS
1kΩ
0.1µF
LpBy
VIN
IN
0.1µF
1kΩ
1kΩ
ADS901
0.1µF
CM
1kΩ
LnBy
0.1µF
1kΩ
REFB
+1V
0.1µF
RB
4kΩ
FIGURE 5. Low Cost Solution to Supply External Reference Voltages and Recommended Reference Bypassing.
®
ADS901
(5)
10
+VS
10Ω
1/2 A1
+VS
+VS
+LVDD
Top
Reference
(REFT)
Digital
Output
Stage
ADS901
RF1
10kΩ
RG1
REF1004
+1.2V
5kΩ
FIGURE 7. Independent Supply Connection for Output
Stage.
3kΩ
10Ω
1/2 A1
Bottom
Reference
(REFB)
During power-down the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition the output data from the following 5 clock cycles
is invalid (data latency).
RF2
RG2
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS901 converter have several supply pins, one of
which is dedicated to supply only the output driver. The
remaining supply pins are not, as is often the case, divided
into analog and digital supply pins since they are internally
connected on the chip. For this reason it is recommended to
treat the converter as an analog component and to power it
from the analog supply only. Digital supply lines often carry
high levels of noise which can couple back into the converter
and limit the achievable performance.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 8 shows the recommended decoupling scheme for the
analog supplies. In most cases 0.1µF ceramic chip capacitors
are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore they should
be located as close to the supply pins as possible.
A1 = OPA2237 or Equivalent.
FIGURE 6. Precise Solution to Supply External Reference
Voltages.
DIGITAL OUTPUTS
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS901 can be set to a high impedance state by driving
the three-state (pin 16) with a logic “HI”. Normal operation
is achieved with pin 16 “LO” or Floating due to internal
pull-down resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
The digital outputs of the ADS901 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows
the ADS901 to directly interface to 3V-logic. The digital
outputs of the ADS901 use a dedicated digital supply pin
(pin 2, LVDD). By adjusting the voltage on LVDD, the digital
output levels will vary respectively. In any case, it is recommended to limit the fan-out to one, to keep the capacitive
loading on the data lines below the specified 15pF. If
necessary, external buffers or latches may be used to provide
the added benefit of isolating the A/D converter from any
digital activities on the bus coupling back high frequency
noise and degrading the performance.
ADS901
+VS
1
GND
13 14
0.1µF
POWER-DOWN MODE
The ADS901’s low power consumption can be further
reduced by initiating a power down mode. For this, the
Pwrdn-Pin (Pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 70%. In
normal operation the power-down mode is disabled by an
internal pull-down resistor (50kΩ).
+VS
18
GND
19 20
0.1µF
+VS
28
0.1µF
FIGURE 8. Recommended Bypassing for Analog Supply
Pins.
®
11
ADS901